0000 org 0

0000 f3 di
0001 3e 40 ld a,40h ; ICR
0003 ed 39 3f out0 (3Fh),a ; relocate i/o
0006 3e f0 ld a,0F0h ; CBR
0008 ed 39 78 out0 (78h),a ; set up MMU
000b 31 00 ff ld sp,0FF00h

000e 21 35 00 ld hl,tabl
0011 4e ilp: ld c,(hl)
0012 23 inc hl
0013 0c inc c
0014 28 07 jr z,start
0016 0d dec c
0017 7e ld a,(hl)
0018 23 inc hl
0019 ed 79 out (c),a
001b 18 f4 jr ilp

; I
; O 138
; R pin
; Q 45 32 1
; |
; 1 00.00 0.xxx 0h-7h
; 1 00.00 1.xxx 8h-fh
; 1 00.01 0.xxx 10h-17h
; 1 00.01 1.xxx 18h-1fh
; 1 00.10 0.xxx 20h-27h
; 1 00.10 1.xxx 28h-2fh
; 1 00.11 0.xxx 30h-37h
; 1 00.11 1.xxx 38h-3fh

001d 0e 00 start: ld c,0

001f 06 08 loop: ld b,8
0021 ed 78 blip: in a,(c)
0023 0c inc c
0024 10 fb djnz blip

0026 11 00 00 ld de,0
0029 1b stall: dec de
002a 7a ld a,d
002b b3 or e
002c 20 fb jr nz,stall

002e 79 ld a,c
002f fe 40 cp 40h
0031 38 ec jr c,loop

0033 18 e8 jr start

0035 3f 40 tabl: db 3Fh,40h ;ICR set internal i/o

0037 76 7f db 76h,7Fh ;RCR refresh off
0039 78 f0 db 78h,0F0h ;CBR done at RESET
003b 5e 00 db 5Eh,0 ;CMR clock = 1*xtal
003d 5f 00 db 5Fh,0 ;CCR cpu ctrl. xtal/2
003f 7a 80 db 7Ah,80h ;CBAR C0=0h, B=0h, C1=8000h
 0041 52 00 db 52h,0 ;AXC0
0043 53 00 db 53h,0 ;AXC1
0045 40 65 db 40h,65h ;CNTLA0 8/N/2
0047 41 05 db 41h,5 ;CNTLA1 no TEND0 8/N/2
0049 42 21 db 42h,21h ;CNTLB0 PS=1 (div 30) DR=0
; (div 16) SSS=001 PHI=18432k/2
; /30, /16, SSS=/2**1 = 9600
004b 71 00 db 71h,0 ;DMODE use DREQ0
004d 72 fa db 72h,0FAh ;DCNTL mem ws = 3, IO wt. = 4
; DMA1=edge, DMA0=level, DMA1=READ
004f 6d 00 db 6Dh,0 ;IAR1B defaults (use DMA ch
1)
0051 ff db 0FFh ;RCR

0052 end

0021 blip 0011 ilp 001f loop 0029 stall

001d start 0035 tabl