OS – RESOURCE USAGE &

SHARING
ACCESSING RESOURCES
If file is to printed – it cannot be done in 10ms interval
So several access attempts are required
Other processes may also be currently accessing resources
Flag/Semaphore
While the process is using the resource – semaphore set
When resource released – semaphore reset
One process
incrementing a value in a given memory location

Read value

Inc value

Write value
Two processes
2 processes are running incrementing a single, shared
memory location
Read value

Suspend
Inc value
Task1
Read value

Inc value
Restore
Write value Task1

Write value
MEMORY PROTECTION
Section of the program where the value of the variable is being
examined and changed must be protected – until tasks complete
This section of code – critical section
Memory protection technique used - mutex
USER 1 /USER2 -CS
MOV AL,01
X1: XCHG AL,SEMAPHORE
CMP AL,01
JE X1
……
MOV SEMAPHORE,00
80286,80386 &
80486
Memory Management
 Global Space

Global
Data

OS
Data
OS OS
Code Data

A OS OS C
Code Data Data Code
OS
A Data C
Data Data Task C
B B
Task A Code Data

Task B
Memory Management – why?
Size of Physical memory
Executing Tasks should not access protected memory
Memory management functions can be minimally implemented
by OS
But for completed Memory Management H/w support is
needed
MMU
Virtual memories & MMU
In Virtual Memory System
Code & Data currently used for execution are loaded from
disk into RAM
If executing program needs a segment currently not in
memory – segment is moved from disk to memory
If DRAM is full it is swapped with existing segment
Setting up of code and data blocks
for swapping
Swap segments
Fixed sized pages
Logical segments – divide into 4k spaces
80386/80486
Virtual Memory
Refers to memory space that appears to be present from the
programmer’s point of view but is not physically present in the
DRAM
Virtual memory is larger as not all logical segment are present
in memory
This works b’coz most programs need only small section of
data/code at a particular time
80286, 80386 &
80486
Memory Protection
 MMU
Handle virtual Memory
Functionally positioned between processor and actual
memory
ALP – logical address/ labels
When program assembled logical address is replaced
by segment and offset in 8086
If MMU – selector and offset – descriptor
Descriptor – physical base address of segment ,
privilege level and some control bits
Selector Offset Logical Address

Segment Base Control &

Address protection bits

Physical Address
80286 – Virtual Memory
1GB
MMU functions
Logical address received
MMU checks to see if segment is present in memory
If yes – Calculates Physical Address
If segment not present in memory it raises an int to processor
ISR – Read code from HDD and transfer into memory
Op is semi automatic – hence delay negligible
Well structured MMU hit rate 90-95 %
MMU & Memory protection
Selector – Privilege level
Descriptors – Privilege level
Segment selector ≥ Descriptor
Access Allowed
80286, 80386 &
80486
Special Registers
MSW
TS EM MP PE

Switched
EmulateCoprocessor
Tasks
–Protect
INT7 Enabled
present
 Special 80386 Registers
P 000 0000 0000 0000 0000 0000 000 E T E M P
G T S M P E
Not Used
Selects 80287 as
Pageco-processor
Fault Linear Address

Page directory Base 0000 0000

80286,80386 &
80486
Memory Protection
Special 80386 Registers
P 000 0000 0000 0000 0000 0000 000 E T E M P
G T S M P E
Not Used

Page Fault Linear Address

Page directory Base 0000 0000

Descriptor – 80286/80386
0000 0000 0000 0000 Access Rights Base
16-23
Base Limit
0-15

Base G D 0 A Limit Access Rights Base

24-31 V 16-19 16-23
Base Limit
0-15
Access rights byte format
P DPL DPL S E ED/C R/W A
Segment Descriptors
Type Purpose
0000 Invalid
0001 Available 80286 TSS
0010 LDT
0011 Busy 80286 TSS
0100 80286 Call Gate
0101 80286/ 80386 Task Gate
0110 80286 Int Gate
0111 80286 Trap Gate
1000 Invalid
1001 Available 80386 TSS
1010 Reserved
1011 Busy 80386 TSS
1100 80386 Call Gate
1101 Reserved
1110 80386 Int Gate
1111 80386 Trap Gate
Address translation - segment

Selector (15-3) TI RPL RPL

Invisible registers
CS Base Address Limit Access
DS
ES
SS
FS
GS

LDTR Base Address Limit Access

TR

GDTR
IDTR
Segment Privilege levels
Checks
1. Valid descriptor
2. Descriptor – beyond limits of DT – exception
3. Right type
Read only –SS
Execute only –DS
4. P –bit is checked
INT 11 if not
 Segment Privilege Level
5. After loading
Write CS
Write read-only data
Inst address should not cross limits defined for
segment

User Tasks can be protected – each task own –LDT

LDTR loaded at highest level – as it is task
switching
Segment privilege levels
OS
Execute only
Privilege levels- highest
 Kernel

BIOS & Sys Services

Custom Device Drivers

Privilege Levels
Descriptor
Current
Requesting
RPL & CPL ≤ DPL
Exception
Appln access of OS/BIOS
Procedure – higher Privilege level – GATE
Types
Call
Interrupt
Task
Trap
80286, 80386 &
80486
Memory Protection-Gates
 Kernel

BIOS & Sys Services

Custom Device Drivers

Privilege Levels
Descriptor
Current
Requesting
RPL & CPL ≤ DPL
Exception
Appln access of OS/BIOS
Procedure – higher Privilege level – GATE
Types
Call
Interrupt
Task
Trap
 Call Gate
Offset (31-16) P DPL 0 Type 000 Word
Count
Selector Offset (0-15)

Gate – special type of descriptor

Gate Descriptors – GDT/LDT
Call to a procedure – in another segment
Advantage – two levels of protection
Interrupt & Exception Handling
Interrupt & Exceptions – IDT
Interrupt No. x 8 – pointer to IDT
IDT have a gate descriptor
80286 ,80386 &
80486
Call Gate - Example
 Call Gate
Offset (31-16) P DPL 0 Type 000 Word
Count
Selector Offset (0-15)

Gate – special type of descriptor

Call Selector: Offset
Selector Points Call Gate
Call Gate has Selector + Offset
Segment Descriptors
Type Purpose
0000 Invalid
0001 Available 80286 TSS
0010 LDT
0011 Busy 80286 TSS
0100 80286 Call Gate
0101 80286/80386 Task Gate
0110 80286 Int Gate
0111 80286 Trap Gate
1000 Invalid
1001 Available 80386 TSS
1010 Reserved
1011 Busy 80386 TSS
1100 80386 Call Gate
1101 Reserved
1110 80386 Int Gate
1111 80386 Trap Gate
Example
Current program at PL -01
Call 2000:0000
200 0000
RPL -00
2000 – GDT entry – Call Gate
 Call Gate
0000 1 0 1 0 1110 000 00100

3000 0200

3000 – Selector – point to descriptor

Descriptor – Base address – 2400
00002400 +0000 0200 – 00002600H
80286 ,80386 &
80486
Task Switching
Invisible registers
CS Base Address Limit Access
DS
ES
SS
FS
GS

LDTR Base Address Limit Access

TR

GDTR
IDTR
 Task Switching
Each task is assigned a Task State Segment
TSS contains
Register & Flag contents
Selector for tasks LDT
Link to TSS of previously executing task(Call/INT)
 Task State Segment
Call/Jump
Directly Point
Indirectly Point via Task Gate
INT
Indirect via Task Gate

IRET
0000 0000 0000 0000 Link
ESP0
0000 0000 0000 0000 SS0
ESP1
0000 0000 0000 0000 SS1
ESP2
0000 0000 0000 0000 SS2
CR3
EIP
EFLAGS
EAX
ECX
EDX
EBX
ESP
EBP
ESI
EDI
0000 0000 0000 0000 ES
0000 0000 0000 0000 CS
0000 0000 0000 0000 SS
0000 0000 0000 0000 DS
0000 0000 0000 0000 FS
0000 0000 0000 0000 GS
0000 0000 0000 0000 LDT
Available T
Available to user
 Task Switch using TSS - direct
1. CALL/JMP – Far
Segment – Selector
2. CPL & RPL ≤ DPL
If no- exception
3. Check if TSS is in memory
If no loaded into memory by exception ISR
4. Copies Current Task’s Registers content to
Current Tasks TSS
5. Load TR with selector & descriptor of new task
TSS
6. Register values copied from TSS into registers
7. New task Begins
 Task Switch using TSS – indirect –Task gate
1. CALL/JMP – Far
Segment – Selector
2. CPL & RPL ≤ DPL
If no- exception
3. Task Gate
Selector - descriptor
3. Check if TSS is in memory
If no loaded into memory by exception ISR
4. Copies Current Task’s Registers content to
Current Tasks TSS
5. Load TR with selector & descriptor of new task
TSS
6. Register values copied from TSS into registers
7. New task Begins
80386 & 80486
Paging
Paging – 80386 onwards
Linear – physical
CR0 – CR3
Page directory – 1024 entries – 4 bytes – each point to Page
Table
Page table – 1024 entries – 4 bytes – each point to Page
Page block of 4k
CR0 -3
CR0 – MSB PG bit, CD, NWT
CR3 – BITS 12 -31- base address of Page Directory
PD/ PT ENTRY
P P
Address (31-12) D A C W U W P
D T

U W PL3 PL0-2
0 0 None Read/Write
0 1 None Read/Write
1 0 Read only Read/Write
1 1 Read/Write Read/Write
TLB – Translation Look ahead buffer
Cache
Page table entries for 32 most recently used tables
Linear Address – upper 20 –bit tags