UNIVERSITY INSTITUTE OF

ENGG.
DEPARTMENT OF ECE
Bachelor Analyze
of Engineering
and design(Electronics And
Communication Engineering)
Microprocessor and Microcontroller
21ECH–224

DISCOVER . LEARN .
Signal Description
EMPOWER
 Microprocessor
and
Microcontroller
CO
1
Understand and gain detailed knowledge about software and
hardware structure of the Microprocessor and Microcontroller.
CO
Course
2 Outcome
Apply the acquired knowledge and analyze programming proficiency
for 8086 microprocessor.
CO
3
Apply the acquired knowledge and analyze the programming skills
for 8051 microcontroller.
CO
4
Illustrate how the communication and different peripherals are
interfaced with Microcontroller.
CO
5
Design assembly language programs for microprocessor and
microcontroller to provide solution to control problems.

2
Segment: Offset Notation
• The total addressable memory size is 1MB
• Most of the processor instructions use 16-bit
pointers the processor can effectively address only
64 KB of memory
• To access memory outside of 64 KB the CPU uses
special segment registers to specify where the
code, stack and data 64 KB segments are
positioned within 1 MB of memory
Segment: Offset Notation
• A simple scheme would be to order the bytes in a
serial fashion and number them from 0 (or 1) to the
end of memory
• The scheme used in the 8086 is called segmentation
• Every address has two parts, a SEGMENT and an
OFFSET (Segmnet:Offset )
• The segment indicates the starting of a 64 kilobyte
portion of memory, in multiples of 16
• The offset indicates the position within the 64k
portion
• Absolute address = (segment * 16) + offset
Segment Registers
• The memory of 8086 is divided into 4 segments
namely
• Code segment (program memory)
• Data segment (data memory)
• Stack memory (stack segment)
• Extra memory (extra segment)
Different Areas in Memory
• Program memory – Program can be located
anywhere in memory
• Data memory – The processor can access data in
any one out of 4 available segments
• Stack memory – A stack is a section of the memory
set aside to store addresses and data while a
subprogram executes
• Extra segment – This segment is also similar to data
memory where additional data may be stored and
maintained
 Segment Registers
• Code Segment (CS) register is a 16-bit register
containing address of 64 KB segment with processor
instructions
• The processor uses CS segment for all accesses to
instructions referenced by instruction pointer (IP)
register
• Stack Segment (SS) register is a 16-bit register
containing address of 64KB segment with program
stack
• By default, the processor assumes that all data
referenced by the stack pointer (SP) and base pointer
(BP) registers is located in the stack segment
 Segment Registers
• Data Segment (DS) register is a 16-bit register
containing address of 64KB segment with program
data
• By default, the processor assumes that all data
referenced by general registers (AX, BX, CX, DX) and
index register (SI, DI) is located in the data segment
• Extra Segment (ES) register is a 16-bit register
containing address of 64KB segment, usually with
program data
• By default, the processor assumes that the DI register
references the ES segment in string manipulation
instructions
 Segment Registers

If a location 109F0 of Code Segment is to be addressed to fetch

An instruction, the physical address will be calculated as follows
CSR = 010A
IP = F950
Effective Address = 109F0
Exercise 1
Q. If EA= 0124h and [DS] = 7000h, then the physical address is
generated as :

Q. If the content of CS is [CS] = 2500h and the content of IP is

[IP] = 0002h, then the physical address is generated as:

UIE, ECE Deptt.

Practice Questions
Q.1 The contents of DS are 1000H and offset in SI register is
0500H. Calculate physical address.

Q.2 The content of CS = F000H, DS=1000H, SS=2000H, and

ES=3000H. Find the base address of different segments in
memory.

UIE, ECE Deptt.

Minimum-Mode and Maximum-
Mode System
 Minimum-Mode and Maximum-
Mode System (cont.)

Signals common to both minimum and maximum mode

Minimum-Mode and Maximum-
Mode System (cont.)

Unique minimum-mode signals

Minimum-Mode and Maximum-
Mode System (cont.)

Unique maximum-mode signals

 PIN DESCRIPTION -8086

Pin 1, 20
Ground
Pin 40
Vcc
Pin 19
CLK
Pin 17
INTR
Pin 18
NMI
AD15 –AD0 [ Pin 2- 16 &39]
The signal have dual function as in case of the 8085. They act as bus during the first part of
machine cycle and as data bus in the later part.
A19/S6 –A16/S3 [Pin 35- 38]
Contains address information in the first part and status bits in the later part. The status bits,
when decoded, indicates the type of operations (eg. Memory access) being performed and the
segment register being used.
S4 S3 SEGMENT REGISTER
0 0 ES
0 1 SS
1 0 CS
1 1 DS

S5 = IF
S6 = 0
(ALWAYS)
BHE/S7 [pin 34]

MN/MX [pin 33]

High – Minimum Mode Operation
Low – Maximum Mode Operation
RD [pin 32]
Read or receive data from M or I/O device
TEST [pin 23]
Relate to wait instruction. The instruction puts the 8086 in
idle state which ends only when the TEST input goes low
READY [Pin 22]
Ready is a signal provided by the memory or I/O devices to the
microprocesssor.When READY = High, the microprocessor proceeds
to process the data in usual manner. When READY = Low, the
micropressor goes into wait state and waits for READY to become
High.
RESET [Pin 21]
Resets the Processor
……….PIN DESCRIPTION

DEN
Data bus Enable. This signal, when low indicates that the
microprocessor address/data bus is to be used as data bus.
HOLD
HLDA
 Minimum Mode pin Functions

Pin 24 -31
INTA - Pin 24
ALE - Pin 25
Address Latch Enable. Since data and address are multiplexed
on a single bus. ALE is output high to identify a valid address.
DEN -Pin 26
Data Bus Enable. This signal, when low indicates that the
microprocessor address/data bus is to be used as data bus.
DT/R - Pin 27
Data transmission/ Receive
M/ IO – Pin 28
WR – Pin 29
HOLD – Pin 30
HLDA - Pin 31
References

1.B. Ram, “Fundamentals of Microprocessor and Microcomputers”, 6th

edition 2005, Dhanpat Rai Publications
2. http://www.intel.com/pressroom/kits/quickreffam.htm#i486
3. Senthil Kumar N; Saravanan, M; Jeevananthan, S Microprocessors and
microcontrollers, edition, Oxford University Press
4. Hall, DV; Rap, SSSP; Ye, K. Microprocessors and Interfacing, Mc Graw
Hill India

UIE, ECE Deptt.

THANK YOU