Syllabus

Syllabus
Course Outcomes
CO No. CO Statement (At the end of the course, students will be able BL
…)

1 To explain 16-bit Microprocessor architectures and fundamental concepts of 1

Microcontrollers

2 To develop programming skills for Microprocessors and Microcontrollers 2

3 To interface various devices in Microprocessor and Microcontroller systems 3

4 To design and implement Microprocessor and Microcontroller based systems 3

5 To describe the significance of various peripherals interfaced with microprocessor. 4

6 To describe the significance of various peripherals interfaced with microprocessor. 5

Difference between 8085 and 8086
Features of 8086
1.Single +5V power supply
2.Clock speed range of 5-10MHz
3.capable of executing about 0.33 MIPS (Millions instructions per second)
4.It is 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and
16-bit external data bus resulting in faster processing(Data bus decides the size).
5.It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which
improves performance.
6.Fetch stage can prefetch up to 6 bytes of instructions and stores them in the
queue.
7.It has 256 interrupts.
8.8086 has 20bit addressing lines and 16bit data lines.
Architecture
Memory segmentation
• 20 bit address bus
• Memory segmentation:
• To increase execution speed and fetching speed, 8086 segments the
memory.
• It’s 20 bit address bus can address 1MB of memory,=2^20, itcan fetch
1 MB of memory.
• 8086 works only with four 64KB segments within the whole 1MB
memory.
BIU
• 1. The Bus Interface Unit (BIU):
• It provides the interface of 8086 to external memory and I/O devices via the
System Bus. It performs various machine cycles such as memory read, I/O read
etc. to transfer data between memory and I/O devices.
• BIU performs the following functions-
• It generates the 20 bit physical address for memory access.
• It fetches instructions from the memory.
• It transfers data to and from the memory and I/O.
• Maintains the 6 byte prefetch instruction queue(supports pipelining).
• BIU mainly contains the 4 Segment registers, the Instruction Pointer, a prefetch
queue and an Address Generation Circuit.
Physical (effective) address calculation= 20
bit

Effective address= Base address of CS register X 10 H + Address of IP

= 4042H X 10H + 0580H = (40420 + 0580)H = 41000H
BIU
• Code Segment register:
CS holds the base address for the Code Segment. All programs are
stored in the Code Segment and accessed via the IP.
• Data Segment register:
DS holds the base address for the Data Segment.
• Stack Segment register:
SS holds the base address for the Stack Segment.
• Extra Segment register:
ES holds the base address for the Extra Segment.
Address Calculation
Address Generation Circuit:
•The BIU has a Physical Address Generation Circuit.
•It generates the 20 bit physical address using Segment and Offset addresses using the formula:

Physical Address = Segment Address x 10H + Offset Address

Eg= PA is 80000
Of instruction
Cs=?= 8000
IP=?= 0000
8 0 0 0= CS
+ 0 0 0 0=IP
8 0 0 0 0= PA
Example of physical address calculation
• Suppose,
• CS= Code segment holds the value 3000 (remember, this is contents of the register CS)
• This is actually a 16bit hexadecimal number(0011 0000 0000 0000)
• Let IP= instruction pointer hold the value FFFF (This is the content of register IP)
• Then 20 bit physical address is calculated as
• 3 0 0 0 (segment address/ base address)
• + F F F F (Offset address)
• =3 F F F F= 20 bit physical address
• 2)CS has 4042
• IP has 0580
• Physical address is
• 4042
• + 05 8 0
• = 4 0 9 A 0
• (Contents= data=16bit)
Queue
• 6 Byte Pre-fetch Queue:
• It is a 6 byte queue (FIFO).
• Fetching the next instruction (by BIU from CS) while executing the
current instruction is called pipelining.
• Gets flushed whenever a branch instruction occurs.
EU
• Stack Pointer:
Points to Stack top. Stack is in Stack Segment, used during
instructions like PUSH, POP, CALL, RET etc.
• Base Pointer:
BP can hold offset address of any location in the stack segment. It is
used to access random locations of the stack.
• Source Index:
It holds offset address in Data Segment during string operations.
• Destination Index:
It holds offset address in Extra Segment during string operations
Combinations of Segment and pointer
registers( produce addresses)
• CS:IP= produce 20 bit address of instruction/command
• SS:SP and SS:BP=produce 20 bit address of stack
• DS: SI= produce 20 bit address of input data
• ES: DI= produce 20 bit address to store/ display the output
• IP is in BIU, because it helps to calculate the address of the instruction
• Contents of all these registers is 16bit
• Their 16 bit contents are combined using the same formula to
produce 20 bit address.
• All these registers have addresses also, their addresses are 20 bits
EU- the below mentioned are used only for
temporary storage and arithmetic calculations.
• AX register:- Accumulator
It holds operands and results during multiplication and division operations. Also an accumulator
during String operations.

• BX register:
BX temporary storage. Especially multiplication.

• CX register:
It holds count for instructions like loop, rotate, shift and string operations, like a counter.

• DX register:
It is used with AX to hold 32 bit values during multiplication and division.
• Note: All these are 16 bit
Note
• Please note that the input data, or the output results are not stored
in any of these registers.
• The instruction, data input and output are stored somewhere in
addresses calculated by these registers.
• We just collect 16bit contents of these registers to calculate address
of instructions and data.
Flag register
Status Flags
Flag Bit Function

S After any operation if the MSB is 1, then it indicates that the number is negative. And this flag is
set to 1

Z If the total register is zero, then only the Z flag is set

AC When some arithmetic operations generates carry after the lower half and sends it to upper half,
the AC will be 1

P This is even parity flag. When result has even number of 1, it will be set to 1, otherwise 0 for odd
number of 1s

CY This is carry bit. If some operations are generating carry after the operation this flag is set to 1

O The overflow flag is set to 1 when the result of a signed operation is too large to fit.
Control Flags
Flag Bit Function

D This is directional flag. This is used in string related operations. D = 1, then

the string will be accessed from higher memory address to lower memory
address, and if D = 0, it will do the reverse.

I This is interrupt flag. If I = 1, then MPU will recognize the interrupts from
peripherals. For I = 0, the interrupts will be ignored

T This trap flag is used for on-chip debugging. When T = 1, it will work in a
single step mode. After each instruction, one internal interrupt is generated.
It helps to execute some program instruction by instruction.
Pin Diagram
Desription
• VCC – Pin number 40 – At this pin, the external power supply of + 5V is
provided to the processor.
• VSS – Pin number 1 and 20 – These two pins acts as the ground. This pin
directs the extra current of the microprocessor to ground.
• AD0 – AD15 – Pin number 2 to 16 and 39 – These are the multiplexed
address and data bus.
• We know that the 8086 microprocessor has 20-bit address bus and 16-bit
data bus. So, the 16 lines of the address and data bus are multiplexed
together so as to reduce the number of lines inside the IC.
• We are aware of the fact that at a time either address or data will be
transmitted by the bus. So, at a particular time only either the address or the
data bus will be enabled from the multiplexed buses.
• A16/S3, A17/S4, A18/S5 and A19S6 – Pin number 35 to 38 – Out of 20
address bits, 4 are present in the multiplexed form with the status
signals. In the case of memory operations, these pins act as an address
bus and contain the memory address of any particular instruction or
data.
• Basically, the signal at S3 and S4 show that which segment is currently
accessed by the microprocessor among the four segments present in it.
Status signals s3 and s4
• S5 acts as interrupt flag. S6 is always 0
• BHE’/S7 : Bus High Enable/Status. During T1 it is low. It is used to enable
data onto the most significant half of data bus, D8-D15. 8-bit device
connected to upper half of the data bus use BHE (Active Low) signal. It is
multiplexed with status signal S7. S7 signal is available during T2, T3 and T4.
• RD’: This is used for read operation. It is an output signal. It is active when
low.
• READY : This is the acknowledgement from the memory or slow device that
they have completed the data transfer. The signal made available by the
devices is synchronized by the 8284A clock generator to provide ready input
to the microprocessor. The signal is active high(1).
• INTR : Interrupt Request. This is triggered input. This is sampled during the last
clock cycles of each instruction for determining the availability of the request. If
any interrupt request is found pending, the processor enters the interrupt
acknowledge cycle. This can be internally masked after resulting the interrupt
enable flag. This signal is active high(1) and has been synchronized internally.
• NMI : Non maskable interrupt. This is an edge triggered input which results in a
type II interrupt. A subroutine is then vectored through an interrupt vector lookup
table which is located in the system memory. NMI is non-maskable internally by
software. A transition made from low(0) to high(1) initiates the interrupt at the
end of the current instruction. This input has been synchronized internally.
• MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the
processor will operate in. If high, Minimum mode, If Low, Maximum mode.
• TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes
low(0), execution will continue, else the processor remains in an idle
state. The input is internally synchronized during each of the clock
cycle on leading edge of the clock.
• CLK : Clock Input. The clock input provides the basic timing for
processing operation and bus control activity. Its an asymmetric square
wave with a 33% duty cycle.
• RESET : This pin requires the microprocessor to terminate its present
activity immediately. The signal must be active high(1) for at least
four clock cycles.
Minimum mode special signals
• INTA’ : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of
each interrupt acknowledge cycle.
• DT/R’ : Data Transmit/Receive. This pin is required in minimum systems,
that want to use an 8286 or 8287 data bus transceiver. The direction of data
flow is controlled through the transceiver.
• DEN’ : Data enable. This pin is provided as an output enable for the
8286/8287 in a minimum system which uses transceiver. DEN is active
low(0) during each memory and input-output access and for INTA cycles.
• ALE : Address Latch Enable. ALE is provided by the microprocessor to
latch the address into the 8282 or 8283 address latch. It is an active high(1)
pulse during T1 of any bus cycle.
• HOLD/HLDA : HOLD indicates that another master has been requesting
a local bus .This is an active high(1). The microprocessor receiving the
HOLD request will issue HLDA (high) as an acknowledgement in the
middle of a T4 or T1 clock cycle
• M/IO’
• This signal is used to distinguish between memory and I/O
operations. When it is low, it indicates I/O operation and when it is
high indicates the memory operation. It is available at pin 28.
• WR’ : It stands for write signal and is available at pin 29. It is used
to write the data into the memory or the output device depending
on the status of M/IO signal.
QS1 and QS0
These are queue status signals and are available at pin 24 and 25. These signals provide the status of instruction queue. Their conditions are shown in the following table −

Maximum Mode Signals

QS0 QS1 Status
0 0 No
operation
0 1 First byte of
opcode
from the
queue
1 0 Empty the
queue
1 1 Subsequent
byte from
the queue
Status signals in Maximum Mode
• LOCK’
• When this signal is active, it indicates to the other processors
not to ask the CPU to leave the system bus. It is activated using
the LOCK prefix on any instruction and is available at pin 29.
• RQ’/GT’1 and RQ’/GT’0
• These are the Request/Grant signals used by the other
processors requesting the CPU to release the system bus.
When the signal is received by CPU, then it sends
acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.
8284 Clock generator
Input-output lines
• X1,X2- provide crystal frequency= 3 times external frequency
• EFI- External freq input- freq from some other source
• OSC- output of freq from crystal
• F/C’ – if 0, select crystal. If 1, select EFI
• Clk- connected to 8086-output- crystal freq/3
• Pclk- peripheral clock output for peripherals
• Csync- Clock synchronization. If 1, clk and pclk are synchronized.
• RES’- used to generate Reset output
• Ready- output generated by 8284 when RDY1 and RDY2 are synchronized.
• AEN1’ and AEN2’- low at these two pins validates RDY1 and RDY2
• ASYNC’- This pin gives the information regarding the synchronization provided to the
inputs. When low, it provides 2 stage synchronization. If high, only 1 stage.
Interfacing 8284 with 8086
8282- 8 bit Latch
8286 – Octal Transreceiver
8288- Bus Controller(Used in maximum
mode)
8288- pin description
• S2’ , S1’ , S0’
• AEN’ – Address enable- If IOB(IO Bus) is high, AEN’ doesn’t have any
effect.
• CEN- Command Enable- If low, all 8288 command outputs, DEN and
PDEN’ outputs are forced to inactive.
• MCE/ PDEN’- MCE is high when IOB is low. Occurs during an
interrupt sequence serves to read a master slave condition.
• PDEN’- Peripheral data bus enable –Enables data bus transreceiver for
the I/O bus during I/O instructions
8086 minimum mode
Maximum Mode
Memory Segmentation in 8086
• Segmentation is the process in which the main memory of the computer
is logically divided into different segments and each segment has its
own base address. It is basically used to enhance the speed of execution
of the computer system, so that the processor is able to fetch and
execute the data from the memory easily and fast.
• Need for Segmentation –
The Bus Interface Unit (BIU) contains four 16 bit special purpose
registers (mentioned below) called as Segment Registers.
• Code segment register (CS): is used for addressing memory location in
the code segment of the memory, where the executable program is
stored.
Segmentation
• Data segment register (DS): points to the data segment of the memory where the data is stored.
• Extra Segment Register (ES): also refers to a segment in the memory which is another data segment in
the memory.
• Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack segment is
that segment of memory which is used to store stack data.
• The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to access one of the
1MB memory locations. The four segment registers actually contain the upper 16 bits of the starting
addresses of the four memory segments of 64 KB each with which the 8086 is working at that instant of
time.
• A segment is a logical unit of memory that may be up to 64 kilobytes long. Each segment is made up of
contiguous memory locations.
• It is an independent, separately addressable unit. Starting address will always be changing. It will not be
fixed.
• Note that the 8086 does not work the whole 1MB memory at any given time. However, it works only
with four 64KB segments within the whole 1MB memory.
Segmentation
Types of segmentation
• Types Of Segmentation –
1.Overlapping Segment – A segment starts at a particular address and
its maximum size can go up to 64kilobytes. But if another segment
starts along with this 64kilobytes location of the first segment, then the
two are said to be Overlapping Segment.
2.Non-Overlapped Segment – A segment starts at a particular address
and its maximum size can go up to 64kilobytes. But if another
segment starts before this 64kilobytes location of the first segment,
then the two segments are said to be Non-Overlapped Segment.
Memory segmentation
• Rules of Segmentation Segmentation process follows some rules as follows:
• The starting address of a segment should be such that it can be evenly divided by 16.
• Minimum size of a segment can be 16 bytes and the maximum can be 64 kB.
• Advantages of the Segmentation The main advantages of segmentation are as follows:
• It provides a powerful memory management mechanism.
• Data related or stack related operations can be performed in different segments.
• Code related operation can be done in separate code segments.
• It allows to processes to easily share data.
• It allows to extend the address ability of the processor, i.e. segmentation allows the use of 16 bit
registers to give an addressing capability of 1 Megabytes. Without segmentation, it would require 20
bit registers.
• It is possible to enhance the memory size of code data or stack segments beyond 64 KB by allotting
more than one segment for each area.
Memory Banking
Even nd Odd address example
• F0000- holds lower 8 bits = (AA)H= 10101010
• Upper 8 bits of the 16 bit number F0001= (BB)H= 10111011
• 16bit data is BBAA= 1011101110101010

• DS= 8000= seg address

• SI= 1000= offset address
• What is the physical address= 8 0 0 0
• + 1000
• 81000 contains 8 bits of data
• 81001 contains upper 8 bits of data
• Combine upper & lower= 16bit data-1st number
• SI= 1000- Fetch my 1st 16bit number
• To fetch the 2nd 16bit number, SI 1001 or 1002?
• The answer SI 1002 because 1st number occupied 1000 and 1001
• One 16bit number will occupy even and odd, both
• One 8 bit number for 8 bit operation, will occupy only one address location. So next 8 bit number can be fetched from the
immediate odd location.
Interrupt Vector Table
8086 interrupts
• First 1KB of memory is reserved for addresses of interrupt vector table.
• This table stores values of IP and CS of each ISR.
• Note: IVT does not store the interrupt program
• So, physical address of ISR gets calculated using CS and IP.
• Example, Consider Type 35.
• Physical Address of IVT is calculates as below
• 35*4=(140)10, ie (8C)H, or 0008C
• 0008C is IP lower, 0008D is IP higher, 0008E is CS Lower, 0008F has CS upper.
• 8 bit contents of 0008C and 0008D are combined to form 16bit IP. 8 bit contents of 0008E and 0008F
are combined to form 16 bit CS
• CS:IP calculates the 20 bit physical address of ISR of INT 35
• ISR= interrupt service routine(interrupt program)
• IRET is to be written at the end of ISR to indicate return to main program
Hardware Interrupts
• 2 Hardware Interrupts
• NMI- Non Maskable Interrupt
• INTR- Interrupt request
• NMI has highest priority- unavoidable interrupt. Positiv Edge
triggered. For NMI, processor executes Type 2 ISR.
• INTR- Maskable. If IF= interrupt Flag=1, it is unmasked and vice versa.
It is positive level triggered. When INTR is received by processor, it
sends out 2 cycles of INTA’
• Note: H/W interrupts are produced from external sources
Software Interrupts
• Represented as
• INT Type(number)- 2 byte instruction, from 0 to 255 in decimal or 0 to
FF in hexadecimal
• Eg: INT 35 (instruction)

• INT - 1 byte instruction- specifically Type 3 ISR

• INTO- 1 byte instruction. Specifically Type 4 ISR
Dedicated Interrupts
• There are 5 dedicated interrupts
• INT 0 to INT 4- software interrupts
• INT0- Type0- Divide by 0 –After performing division, if processor is unable to store the result
in destination, Type0 ISR is performed. To identify the error and rectify it.
• INT1- Type1- Single Stepping-. If Trap Flag=1, processor has to execute Type1 ISR. Processor
comes back to main program. And executes next instruction. It then executes next instruction
and again Type1 ISR. Continues till TF=0. Time consuming.
• INT2- Type2-NMI- When a request arrives at NMI, processor calculates Type2 ISR.
• INT3- Type3- Breakpoint- Used for debugging when single stepping becomes more time
consuming. After group of instructions, this INT can be used.
• INT4 – Type4-Overflow- When processor executes INTO instruction, it checks overflow flag. If
its reset, control continues sequentially. Else, it executes Type4 ISR. This ISR eliminates errors
taking place in signed arithmetic.
Interrupt Process 1
• Processor is debugging main program.
• TF=1, IF=1
• At the same time, Type35 and NMI.
• Push Flag, CS, IP[CS and IP are used , because they indicate the address of
the current instruction] of the current instruction contents to stack.
• By reducing 6 bytes(6 positions) in SP, each block in stack takes 8bytes.
• Before execution it checks NMI
• Call physical address of Type2 ISR,ie,NMI.
• After executing Type2, execute Type35.
• Pop all 6 bytes from stack.
• Return to main program
Interrupt Process 2
• Processor reaches instruction with Type35 Interrupt.
• At the same time, signal appears at INTR, ie, IF=1.
• Push Flag, CS, IP[CS and IP are used , because they indicate the address
of the current instruction] of the current instruction contents to stack.
• By reducing 6 bytes(6 positions) in SP, each block in stack takes 8bytes.

• First processor calculates PA of Type35 ISR.

• Processor checks NMI. But it is absent.
• Processor executes type35 and returns to main program by Popping the
flag, CS and IP.
• Now it reads INTR and performs the required ISR.
8086 Minimum mode write cycle
Minimum Mode read cycle
Maximum mode Write cycle
Maximum Mode Read cycle