UNIT – I

8086/8088 MICROPROCESSORS

Register Organization of 8086

In 8086 there are 14 registers. These are divides into 5 groups and each register size is 16-bit.

a. General Purpose Registers [GPRs] ---4

b. Segment Registers---4
c. Pointer Registers---3
d. Index Registers---2
e. Flag register---1

a. General Purpose Registers [GPRs]

There are 4. They are AX, BX, CX, and DX.
These registers are able to hold data, address or results on temporary basis.
After completion of any operation by CPU, the result is loaded on to GPRs in some cases.
For 8-bit operations, each 16-bit register can be divides into two 8-bit registers.
AX AH+AL BX BH+BL
CX CH+CL DX DH+DL

b. Segment Registers: -There are 4 segment registers; each register size is 16-bit.

1) CS [code segment register]

2) DS [data segment register]
3) SS [stack segment register]
4) ES [extra segment register]

These segment registers are used to hold the upper 16 bits of the Starting Address or Base
Address of their corresponding segments.  
The part of a segment starting address stored in a segment register is often called the Segment
Base.

c. Pointer Registers
There are 3 Pointer registers, with 16-bit length, those registers are
1) Instruction Pointer (IP)
2) Stack Pointer (SP)
3) Base Pointer (BP)
Instruction Pointer (IP)
It holds the address of next instruction byte to be fetched in Code Segment (CS).
It provides offset address in code segment.

Stack Pointer (SP)

It gives the offset value in Stack Segment (SS).
It holds the address of the Top of the Stack. (Or) it holds the address of the stack where the last
stack related operation is performed.

Base Pointer (BP)

It gives the offset value in Data Segment (DS) or Stack Segment (SS).
It is used primarily to access parameters passed via the stack.

d. Index Registers
There are 2 Index registers; each register size is 16-bit. Those registers are
1) Source Index register (SI)
2) Destination Index register (DI)
SI, DI are used as offset registers for data in Data Segment (DS) and Extra Segment (ES).
These are used for string related operations
If the processor executes any string related operation, the source address of the string is
provide by the combination of DS and SI registers. SI provides Offset address relative to DS.
Similarly, destination address is provided by the combination of ES and DI registers. DI provides
Offset address relative to ES
e. Flag Register
Flag means a Flip-Flop or 1-bit register.
Flag Register determines the current state of the processor.
It is also called PSW of 8086.
The bit configurations in Flag register of 8086 as follows
U U U U OV DF IF TF SF ZF U AC U PF U CY

U--- Unused
There are 9 active bit positions. Those are
OV=Overflow Flag DF=Direction Flag, TF=Trap Flag IF=Interrupt Flag SF=Sign Flag
ZF=Zero Flag AC=Auxiliary Carry Flag PF=Parity Flag CY=Carry Flag
The flags of 8086 can be divided into 2 groups.
1. Conditional flags
2. Control flags
1. Conditional Flags

These flags are also called Status Flags. These are six in number.
These flags give the conditions of the result produced by the ALU.
These flags set or reset automatically based on the conditions of the result.
These are the flags present in least significant byte of the flag register along with OV which is
present in higher order byte of the flag register. Those are CY, PF, AC, ZF, SF, and OV.

CY (Carry Flag) =1 When

In addition the carry is generated at most significant bit position (or) Cout = 1
In subtraction the minuend value is less than subtrahend (or) the first number is less than the
second number.

PF (Parity Flag) =1 When

The result least significant byte contains even no. of 1’s.

AC (Auxiliary Carry Flag) =1 When

In addition the carry is generated at the least significant nibble (or) the carry is transferred from
bit position D3 to D4.
In subtraction the borrow is being transferred from last but one nibble to last nibble (or) the
borrow is being transferred from bit position D4 to D3.
This flag is basically used for decimal adjusting nothing but BCD operations; because of this it is
also called BCD carry.
There is no conditional branching instruction based on this flag conditions.

ZF (Zero Flag) =1 When

The result of an operation is equal to zero.

SF (Sign Flag) =1 When

Most significant bit of result is equal to ‘1’. It means for signed operations the result sign is
minus.

OV (Overflow Flag) =1 When

The size of the result is greater than the size of the destination.
If any arithmetic/logic operation satisfies the overflow rule.
2. Control Flags
Control flags are set or reset deliberately to control the operations of the execution unit (or)
these flags controls the operation of the processor. These are three flags.
Control flags are as follows: These flags are set or reset by user by using instructions.

Trap Flag (TF)

TF = 1, the processor operates in single step execution mode.
TF = 0, the processor operates in normal mode.
Single step execution mode allows user to execute one instruction of a program at a time for
debugging.

2. Interrupt Flag (IF)

This flag enable/disable INTR interrupts.
IF = 1, the processor enabled INTR interrupts
IF = 0, the processor disables INTR interrupts
IF = 1 by execution of instruction STI.
IF = 0 by execution of instruction CLI

3. Direction Flag (DF)

This flag is used in string operations.
DF = 1, the processor access string bytes from higher order memory address to lower order
memory address. Processor operates in auto-decrement mode.
DF = 0, the processor access string bytes from lower order memory address to higher order
memory address. Processor operates in auto-increment mode.
Special Functions of GPRs

1. AX (Accumulator)

a) AX acts as source/destination for some arithmetic/logical operations.

b) If the processor is communicating with any input or output device, then entire
communication is done through accumulator register.
c) It acts as interface between CPU and I/O device.

2. BX (Base Register)

This register is used to hold the off-set address or the part of off-set address of an operand
in some addressing modes. Like register relative, based indexed, based indexed relative
addressing modes.

3. CX (Counter Register)
 a) This register is used as a counter to perform repeated operations by using loop
instruction.
b) If the processor performs any string related operations, count value for these
operations must be the content of CX register.

4. DX (Data Register)

a) DX register is used to hold the address of an I/O device in I/O indirect addressing.
b) Whenever the processor executes 16-bit*16-bit multiplication, the result size is 32-bit,
in that higher order 16-bits are loaded onto DX and lower order 16-bits are loaded on
AX.
c) If the processor performs 32-bit/16-bit division, in that dividend 32-bit, higher order 16-
bit are content of DX. After completion of division remainder is loaded onto DX.

Architecture of 8086
The entire architecture is divided into two independent functional parts to simplify the
operation of the processor. They are
1) BIU: Bus Interface Unit 2) EU: Execution Unit

1). Bus Interface Unit (BIU)

The functions performed by BIU are
a). Fetch the instruction or data from memory.
b). Write the data to memory.
c). Write the data to the I/O port.
d). Read data from the I/O port.

BIU has the following functional units

a). Summer circuit (or) adder circuit.
b). Segment registers & IP.
c). 6B instruction pre-fetch queue.

a) Summer Circuit

It produces a 20-bit physical address by performing the following operation.

Physical Address=Base Address * 10 + Offset Address

(OR)

First shift left the contents of base register by four times later offset address is added to the
shifted base register content to produce 20-bit physical address. Because each memory location
can be identified by using 20-bit physical address.
b) Segment Registers
The BIU contains four 16-bit segment registers. They are: the Extra Segment (ES) register, the
Code Segment (CS) register, the Data Segment (DS) register, and the Stack Segment (SS)
register.
These segment registers are used to hold the upper 16 bits of 20-bit Physical Address. It is
called the Segment Base and it is also called the Starting Address or Base Address for each of
the segment.
The part of a segment starting address stored in a segment register is often called the Segment
Base.
Instruction Pointer
Its functionality is similar to that of PC (Program Counter).
It holds the address of next instruction byte to be fetched from the code-segment. It means it
gives offset address of the instruction code bytes in the Code Segment.

c) 6B Instruction Pre-Fetch Queue

The functions of instruction Queue in BIU of 8086 are,

To increase the execution speed, BIU fetches as many as six instruction bytes ahead to time
from memory.
All six bytes are then held in first in first out 6 byte register called instruction queue.
Then all bytes have to be given to EU one by one.
This pre fetching operation of BIU may be in parallel with execution operation of EU, which
improves the speed execution of the instruction.

Why Instruction pre-fetch queue size is optimized to 6Bytes?

If the Queue size is greater than 6B then wait state period of processor is increased because any
instruction in the queue is related to Branching, or if processor receives an interrupt then
instructions in the queue must be cleared because the next instructions must be taken from the
branch specified location or from ISR (Interrupt Service routine). In this period processor must
be in wait state.

If the queue size is less than 6B then the maximum size of an instruction in the 8086 processor
is unable to execute because maximum length of instruction is 6B.

2. Execution Unit (EU)

The functions are performed by EU

a). It gives the information to BIU where to fetch instructions or data from
b). Decodes instructions, and
c). Executes instructions.
EU has the following functional parts these are
a). ALU
b). Register Set.
c). Operand & Flag Register.
d). Control System.

a). ALU (Arithmetic and Logical Unit)

It performs Arithmetic and Logical operations on 8 bits/16bits. The Bit Capacity of ALU is 16bits.
It can do the following arithmetic operations
i) Addition ii) Subtraction iii) Multiplication iv) Division v) Increment
vi) Decrement vii) Comparison

Arithmetic operations may be performed on four types of operands

Unsigned binary numbers
Signed binary numbers (Integers)
Unsigned packed decimal numbers
Unsigned unpacked decimal numbers
The ALU can also perform logical operations such as
i) NOT ii) AND iii) OR iv) EX-OR v) TEST vi) Logical Shift
vii) Arithmetic Shift viii) Circular Shift (or) Rotate

b). Register Set

The group of registers is available in Execution unit (EU).
These are used to hold the 16-bit information.
The information is address, data or result of some operation.
The registers are GPRs (AX, BX, CX, & DX), Index registers (SI & DI) and Pointer registers (SP &
BP).

c). Operand &Flag Register

Operand holds the result produced by ALU.
Flag register holds the conditions of the result.
It is called as PSW (Program Status Word) of 8086.
Each single bit in this register is called flag; it can store the conditions of the result.
Some of the flags in this register are control the operation of the processor.

d). Control System

It is divided into 2 parts. They are Decoding circuit & Timing circuit.
The EU contains the control circuitry to perform various internal operations.
A decoder in EU decodes the instruction which is fetched from memory.
Timing circuit generates different internal or external control signals required to perform the
operation.

Physical Memory Organization

8086 processor addressable maximum memory of size is 2 20 = 1MB.

The 1MB of memory logically divided into 16 segments. Each segment size is 64KB.
These 16 segments can divided into 4 groups based on type of information stored. Each group
has 4 segments.
These segments can be arranged either in overlapped or non-overlapped modes.
The four segment groups are; Data segments, Code segments, Stack segments, and Extra
segments.
Data segments are only used to store data. The Code segments are only used to store code or
instructions or programs.
Stack segments are only used to store stack information when the processor provides service
for any interrupt or subprograms.
Extra segments are used to store any information like (data, code, or stack) only after their
dedicated segments are filled.
But Extra segments are called default data segments, because the data segments are filled first
compared to other segments.
By using segmentation of the memory the following advantages are occurred.
By using only 16-bit registers, we can identify any memory location in 1MB main memory.

The efficient utilization of memory increased.

Segmented version memory supports parallel processing without any difficulty.

Segmentation gives more security.

All 4 segment registers give the base addresses of selected segments.

Segments starting address are like00000H, 10000H, 20000h, 30000H…. F0000H
Offset address range in any segment is from 0000H to FFFFH
Address range of total 1MB is from 00000H to FFFFFH

Physical Address=Base Address * 10 + Offset Address

No. of locations are getting down from segment base to desired address in the segment is
called Offset Address.
Physical Address means actual location address in the memory system.

The 1MB of memory physically organized as two memory banks. Those are Even Bank of size
512MB and Odd Bank of size 512MB.
The even memory bank is also called lower order memory bank and it only contains even
addresses. The first memory location address is 00000H and last location address is FFFFEH.
The lower order data lines (D7 – D0) of the processor are connected to this memory bank.
The odd memory bank is also called as higher order memory bank and it only contains odd
addresses. The address of the first location is 00001H and last location address is FFFFFH.
The higher order data lines (D15 – D8) of the processor are connected to this memory bank.
The enable signals for even and odd memory banks are A0 and BHE1 (Bus High Enable).

General Bus Operation of 8086

The general bus operation concept discussed about how the processor performs operation
memory read and write.
In these operations what are the different signals are involved and when they are active and
inactive with reference to clock signal.
The 8086 has a combined address and data bus commonly referred as a time multiplexed
address and data bus.
The main reason behind multiplexing address and data over the same pins is the maximum
utilization of processor pins.
The bus can be demultiplexed using a few latches and transreceivers, whenever required.
Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to
as T1, T2, T3, and T4 along with wait state Tw.
The address is transmitted by the processor during T1; it is present on the bus only for one
cycle.
The ALE signal is used to separate the address and the data or status information.
In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of operation.
Status signals S3 to S7 are multiplexed with higher order address signals A16 to A19 and the
BHE1 signal.
Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.

I/O Addressing Capability

8086 can address I/O devices either directly or indirectly.

Before discussing about direct or indirect addressing first the 8086 processor uses I/O mapped
I/ O or Isolated I/ O/ technique for addressing the I/ O devices.

In Isolated I/ O the address map of the I/O devices are same as address map of memory
locations. It same addresses is used for both memory locations and I/O devices.

In another I/ O addressing technique the processor generated addresses can be shared

between memory locations and I/O devices.

In direct addressing of I/O devices in 8086 an 8-bit addresses are used. Example instructions are

Ex: IN AL, 20H OUT 50H, AX

In this only lower order 8 address lines (A7 to A0) are used for carrying I/O device address,
remaining address lines are either operated at high impedance state or logic zero state.

In Indirect addressing an I/O devices an identified with 16-bit address, because in that case I/O
devices can address with the register DX. Its size is 16-bit.

For this case to carry address of the device lower order 16 address lines (A15 to A0) are used,
and remaining address lines (A19 to A16) are operated at high impedance state or logic zero
state. The example instructions are;

IN AX, DX OUT DX, AL

Special Purpose Activities

There are four special activities are performed by the processor 8086. Those are

1. Processor Reset and Initialization

2. Halt

3. TEST and Synchronization with External Signals

4. Deriving System Bus

1. Processor Reset and Initialization

When the processor identifies logic ‘1’ on RESET pin the processor is reset.

It remains in this state till logic’0’ is again applied to RESET pin.

When the processor is reset or reinitialize the following things are happened in the system.

The program execution is shift to initial address, i.e. FFFF0H by CS is loaded with FFFFH and IP
with 0000H.

All internal registers of processor are initialized with their initial or default values.

The internal buses are operated at tri-state or high impedance state.

The devices which are connected to 8086 also reset or re-initialized.

2. HALT

When the processor executes HLT instruction immediately the processor enter into halt state.

It remains in that state until the processor receives any hardware interrupt from external device
or the processor receives a reset signal from the external devices.

Basically HLT instruction is used as permanent termination instruction of the program, any
instruction after the HLT the processor can’t recognizes it.

3. TEST and Synchronization with External Signals

When the Processor executes a WAIT instruction, the processor preserves the contents of
registers, before execution of the WAIT instruction

And the processor waits for the TEST1 input pin to go low. If the TEST1 pin goes low, it continues
further execution; otherwise, it keeps on waiting for the TEST 1 pin to go low.

The execution of the portion of the program which appears in the program after WAIT
instruction can be synchronized with an external signal connected with the TEST 1 input.

4. Deriving System Bus

In general the processor has time-division multiplexed signals because in order to reduce the
number of pins present in the IC form of the processor.

These multiplexed signals must be demultiplexed because the system bus has dedicated signals.

We can derive the dedicated signals from multiplexed signals with help of group of latches and
buffers.

In general the latches are 74LS373 octal latches and buffers are 74LS245 octal buffers.

Pin Configuration of 8086

8086 processor has 40 pins or signals. By using these signals the processor is communicating
with the other devices present in the system.

It exists in 40 pin DIP (Dual – In line – Package). These 40 signals can be divided into three
groups. Those are

1. Common Signals

2. Minimum Mode Signals

3. Maximum Mode Signals

1. Common Signals

This group of signals is common for 8086 operations irrespective of its mode of operation.
These signals are;

AD0 - AD15

These are multiplexed address and data lines of the processor.

These signals are act as address and data signals based on different time instances.

During 1st clock cycle these lines are act as address lines A15 to A0 and in remaining clock cycles
of every machine cycle these lines are act as data lines D15 to D0.

A16/S3 – A19/S6

These are time division multiplexed address and status signals.

During 1st clock cycle these lines are act as address lines A19 to A16 and remaining clock cycles
of every machine cycle these lines are act as status lines S6 to S3.

The status signals provide different status information like the processor is communicating with
which segment and the condition of the interrupt flag.

S4 S3 Segment
0 0 Extra Segment
0 1 Stack Segment
1 0 Code Segment
1 1 Data Segment

The status of IF (Interrupt Flag) defined by status signal S5. S6 is always active low.

BHE1/S7

Bus High Enable (BHE1) is active only in the 1st clock cycle of every machine cycle. This can be
used as enable signal for odd memory bank or higher order memory bank.

If this signal is active there is a valid data is present on higher order data lines D15 to D8.

The remaining clock cycles of every machine cycle it is act as status signal S7. It is not currently
used.

MN/MX1

The logic level on this signal decides the mode operation of 8086. Basically 8086 operates in
two modes. Those are Minimum Mode and Maximum Mode.

If this signal is connected to Vcc (logic - ‘1’) the processor is operate in Minimum mode. The
same signal is connected to GND (logic – ‘0’) the processor is operating in maximum Mode.

RD1
Read signal is active the processor is performing either memory or I/O read operation. This
signal is tri-stated during the ‘hold acknowledge, .

TEST1

This signal is active the processor continues its operation otherwise the processor enter into
wait state.

READY

This signal is active the processor is ready to communicate with slowly operated peripheral
otherwise the processor operates in wait state.

This signal is used by slowly operated peripheral.

RESET

This signal is active the following things are happened in the system.

The program execution is shift to initial address, i.e. FFFF0H by CS is loaded with FFFFH and IP
with 0000H.

All internal registers of processor are initialized with their initial or default values.

The internal buses are operated at tri-state or high impedance state.

The devices which are connected to 8086 also reset or re-initialized.

NMI

The processor receives non-maskable interrupts from external devices by using this signal.

INTR

The processor receives maskable interrupts from external devices by using this signal.

CLK

By using this signal the processor send its clock information to the rest of the system and also in
receives the clock signal from external clock generator 8284.

Vcc & GND

These signals are power supply signals to 8086 processor.

2. Minimum Mode Signals

These signals are only present in minimum mode operation of 8086.

HOLD

Logic ‘1’ on this signal indicates other master wants the system. Basically this signal can be used
by DMA controller.

By using this signal DMAC send DMA request signal to processor to access system from the
processor. The processor gives highest priority to this signal compared to any other hardware
interrupts produced by peripherals.

HLDA

By using this signal the processor send its acknowledgement to bus request device along with it
release control over the system bus.

WR1

Write signal is active the processor is performing either memory or I/O write operation. This
signal is tri-stated during the ‘hold acknowledge, .

M/IO1

This is a status signal. It gives the information of the processor performing operation is related
to either memory or IO.

If logic level on this signal is ‘1’ the processor performing operation is related to memory
otherwise operation related to IO.

DEN1

This signal is act as enable signal for bi-directional buffers or transceivers. In order to derive
dedicated data bus from the processor bus bi-directional buffers are used.

DT/R1

This signal gives the direction to bi-directional buffers.

The logic level on this signal is ‘1’ it indicates the processor want to send data to other end
otherwise it ready to receive data from other end.

ALE

This signal is act as enable signal for address latches.

This signal is active only in 1st clock cycle of every machine cycle at that time there is a valid
address is present on multiplexed buses (AD15 to AD0 & A19/S6 to A16/S3).

In the remaining clock cycles of every machine cycle this signal is inactive then there is valid
data is present on multiplexed address and data lines.

Basically this signal is used to de-multiplex the multiplexed buses.

INTA1

By using this signal the processor sending its acceptance to INTR interrupt requesting devices.

3. Maximum Mode Signals

This group of signals is only present in maximum mode operation of the processor.

RQ1/GT01 & RQ1/GT11

These two signals are used for DMA operation in this mode. At a time the processor receives
two DMA requests from peripherals but it gives highest priority to the DMA request which is
coming on signal RQ1/GT01.

The same signal is act as request as well as grant signals.

S21, S11, & S01

These signals act as status signals. These signals give the following status information.

S21 S11 S01 Operation

0 0 0 Interrupt Acknowledgement
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Code Access
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive

QS1 & QS0

These two signals give the status of instruction pre-fetch queue present in the processor.

QS1 QS0 Indication

 0 0 Passive
0 1 First byte of opcode from the queue
1 0 Empty queue
1 1 Subsequent byte from queue

Minimum Mode Operation of 8086

Minimum Mode operation of 8086 is also called Single Processor Mode of operation of 8086.

In this Minimum mode based system of 8086 contains only one processor 8086 along with
Memory Elements and I/O Devices.

The processor operates in this mode when its MN/ MX1 is connected to Vcc.

In This system the system bus is in the hands of the processor. The system looks as follows

Timing Diagrams in Minimum Mode (READ Operation)

Timing Diagrams in Minimum Mode (WRITE Operation)

Maximum Mode Operation of 8086

Minimum Mode operation of 8086 is also called Multi Processor Mode of operation of 8086.

In this Maximum mode based system of 8086 contains multiple processors along with Memory
Elements and I/O Devices.

The processor operates in this mode when its MN/ MX1 is connected to GND.

In This system the system bus is in the hands of separate bus controller. Whenever a device
requires system bus they can send their request signals to bus controller 8288, then it will
assign the services.

The Maximum Mode system looks as follows

Timing Diagrams in Maximum Mode (READ Operation)

Timing Diagrams in Maximum Mode (WRITE Operation)

Addressing Modes of 8086

An Addressing mode Indicates the in which data is represent in the instruction operand filed.
The addressing mode creates flexibility to user in the implementation of a program in different
ways.
8086 processor supports 15 addressing modes.

1. Immediate Addressing Mode

In this AM instructions, the data is directly placed in the source operand field of the instruction.
The immediate data size is either 8-bit or 16-bit.
Ex: MOV BX, 2050H
2. Register Addressing Mode

In this AM, data is represented in the operand field through a register (or) the operands for an
instruction are registers.
We can use any register except IP.
Ex: MOV AX, BX

3. Direct Addressing Mode

In this AM, the address of the address of the data is directly placed in the operand fields of the
instruction.
In this addressing mode, the address of the data is nothing but the memory location address.
Ex: MOV AX, [2050H]

4. Register Indirect Addressing Mode

In this AM, the address of the address of the data indirectly represented in operand field of the
instruction by using registers.
The registers must be BX, BP, SI, DI registers.
Ex: MOV AX, [BX]

5. Register Relative Addressing Mode

In this AM instruction, the operand address is provided by the combination of base address and
an 8-bit or 16-bit displacement value.
Ex: MOV AX, 50H [BX]

6. Based Indexed Addressing Mode

In this AM, the address of data is provided by combination of base register and index register.
Ex: MOV AX, [BX][SI]

7. Based Indexed Displacement Addressing Mode

In this AM, the address of the data is provided by the combination of base register, index
register and an 8-bit or 16-bit displacement value.
Ex: MOV AX, 5000H [BX][SI]

8. Implied Addressing Mode

In this AM, the operand implicitly represented in the operation code of an instruction.
Ex: STD
9. I/O Direct Addressing Mode
In this AM, the I/O device address is directly placed in the operand field of the instruction.
Ex: IN AX, 2050H
OUT 50H, AL

10. I/O Indirect Addressing Mode

In this AM, the device address placed in operand filed of the instruction through DX register.
Ex: IN AL, [DX]

11. Indexed Addressing Mode

In this AM, the address of the data is represented in the operand field through an index register
in the instruction. It is useful when the processor executes string related operations. It is similar
to register indirect AM.
Ex: MOV AX, [SI]
12. Intra Segment Direct Addressing Mode
If the both source and destination appears in same segment then it is called intra segment.
In this AM, the destination address is directly placed in the operand field of the instruction.
Ex: JMP 2050H

13. Inter Segment Direct Addressing Mode

If the both source and destination appears in different segments then it is called inter segment.
In this AM, the destination address is directly placed in the operand field of the instruction.
Ex: JMP 3000:4050H.

14. Intra Segment Indirect Addressing Mode

In this AM, the destination address is represented in the operand filed through a register or a
memory location in an instruction.
Ex: JMP [BX]

15. Inter Segment Indirect Addressing Mode

In this AM, the destination address is represented in the operand filed through a register or a
memory location in an instruction.
Ex: JMP [2000H]

Instruction Format

There are six general formats of instructions in 8086 instruction set. The length of an instruction
may vary from one byte to six bytes.
The instruction format of 8086 has one or more number of fields associated with it. 
The first filled is called operation code field or opcode field, which indicates the type of
operation. 
The instruction format also contains other fields known as operand fields. 

One byte Instruction 

This format is only one byte long and may have the implied data or register operands.
The least significant 3 bits of the opcode are used for specifying the register operand, if any.
Otherwise, all the eight bits form an opcode and the operands are implied.
For example: 11111000 F8H  CLC: Clear Carry

D7 D0
OpCode

Register to Register 
This format is 2 bytes long.
The first byte of the code specifies the operation code and the width of the operand specifies
by w bit.
The second byte of the opcode shows the register operands and RIM field.

The register represented by the REG field is one of the operands. The RIM field specifies

another register or memory location, ie., the other operand.
The register specified by REG is a source operand if d=0, else it is a destination operand.
Register to/from memory with no displacement
This format is also 2 bytes long and similar to the register to register format except for
the MOD field.

       
The MOD field shows the MOD of addressing. In case of no displacement. MOD = 00
This format is similar to register to register transfer. The difference is in MOD field. For register
to register, MOD = 11
For register to/from memory with no displacement, MOD = 00. When MOD= 00, the r/m fields
indicates the address to memory location.
As for example r/m = 1 1 1 indicates (BX)
The instruction
1 0 0 0 1 0 1 0 0 0 0 0 0 1 1 1 indicates the instruction MOV AX, [BX]
Register to/from Memory with Displacement 
This type of instruction format contains one or two additional bytes for displacement along
with 2-byte the format of the register to/from memory without displacement.

Here a MOD field indicates the size of displacement.

MOD = 0 1 indicates displacement of 8 bytes (instruction is of size 3 bytes)
MOD = 1 0 indicates displacement of 16 bytes. (Instruction is of size 4 bytes)
Already we have seen the other two options of MOD
MOD = 1 1 indicates register to register transfer
MOD = 0 0 indicates memory without displacement
In this case, R/M fields indicates a memory when MOD is not 1 1
R/M = 1 1 1 indicates (BX)
When MOD = 0 1, the offset address is (BX) + D8
When MOD = 1 0, the offset address is (BX) + D16
Immediate operand to register
In this format, the first byte as well as the 3 bits from the second byte which are used
for REG field in case of register to register format is used for opcode.
It also contains one or two bytes of immediate data.

When w = 0, the size of immediate data is 8 bits and the size of instruction is 3 bytes.
When w = 1, the size of immediate data is 16 bits and the size of instruction is 4 bytes.
Immediate operand to memory with 16-bit displacement 
This type of instruction format requires 5 to 6 bytes for coding.
The first two bytes contain the information regarding OPCODE, MOD and R/M fields. The
remaining 4 bytes contain 2 bytes of displacement and 2 bytes of data.

Instruction Set of 8086

Instructions in the instruction set of 8086 are classified in to different types based
The number of operands in the instruction.
The type of operation
Based on Number of Operands in the Instruction

In this classification the instructions can be divided into three groups. Those are
1. Zero Operand Instructions
2. One Operand Instructions
3. Two Operand Instructions
Zero Operand Instructions
In this group of instructions there is no operand field in the instruction, only opcode part is
exist.
Ex: - NOP HLT STC WAIT
One Operand Instructions
In this group of instructions only one operand is exist in the instruction, the another operand
for the instruction are the default registers (AX or DX) these are not represented in the operand
field of the instruction.
Ex: - IN AL OUT AX DIV BX MUL CL
Two Operand Instructions
In this group of instructions two operands are exists.
Ex: - MOV AX, BX ADD AX, DX SUB AX, [BP]
Based on Type of Operation

In this instructions are classified into eight groups. Those are

1. Data Copy / Transfer Instructions

2. Arithmetic and Logical Instructions
3. Branch Instructions
4. Loop Instructions
5. Machine Control Instructions
6. Flag Manipulation Instructions
7. Shift and Rotate Instructions
8. String Instructions

1. Data Transfer Instructions

Data Transfer instructions are also called as Data Movement Instructions or Data Copying
Instructions. If the processor executes any Data Transfer Instruction there is no effect on the
Flag Register Status.
In this group of instruction execution only the Xerox copy of the source is transferred to
destination, due to this only destination content changes and the content of source is equal to
destination.
For this group of instructions the size of the source operand must be equal to destination
operand and the immediate data must be placed at source operand field.
8086 doesn’t support memory to memory data transfer.
MOV
Move a byte or word from specified source to specified destination. The source operand is
either an immediate data or a register or a memory location. The destination is either a register
or a memory location.
Ex: - MOV CX, 037A H MOV AL, BL MOV BX, [0301H]
PUSH
Move the specified operand content to top of stack. The specified operand is any 16-bit register
or any memory location.
For this instruction execution the content of SP is decrement by ‘2’.
Ex: - PUSH BX PUSH [20150H]
POP
Move a word form top of stack to specified destination. Destination can be a general purpose
register, segment register (except CS) or memory location.
For this instruction execution the content of SP is increment by ‘2’.
Ex: - POP DX POP [20150H]
XCHG
This instruction exchanges the content of Source with the content of Destination. It cannot
exchange two memory locations directly. Exchange bytes or exchange words.
Ex: - XCHG DX, AX XCHG DX, [5040H]
XLAT
Translate a byte using look-up table in the Memory.
IN
Copy a byte or word from specific Input Port to Accumulator AL or AX.
Ex: - IN AX, 0050H IN AL, DX
OUT
Copy a byte or word from accumulator AL or AX to specific Output Port.
Ex: - OUT 0050H, AX OUT DX, AL
LEA
Load effective address of operand into specified register (16-bit).
Ex: - LEA BX, label
LDS
It loads 32-bit pointer from memory source to destination register and DS. The offset is placed
in the destination register and the segment base is placed in DS.
To use this instruction the word at the lower order memory address must contain the offset
and the word at the higher order address must contain the segment base address.
Ex: - LDS BX, [0302H]
LES
It loads 32-bit pointer from memory source to destination register and ES. The offset is placed
in the destination register and the segment is placed in ES.
This instruction is very similar to LDS except that it initializes ES instead of DS.
Ex: - LES DX, [1030H]
LAHF
Load AH with the lower byte of flag register.
SAHF
Store the content of AH register to lower byte of flag register.
PUSHF
Copy flag register to top of stack.
POPF
Copy word from top of stack to flag register.

2. Arithmetic Instructions
These instructions are useful to perform Arithmetic operations, such as addition, subtraction,
multiplication, division, increment and decrement.
By execution of this group of instructions based on the result the content of flag register
modifies.
ADD
It performs addition between the contents of source and destination operands.
Ex: - ADD AL, 74H ADD DX, AX ADD AX, [BX]
ADC
It performs addition between the contents of source and destination operands along with
previous generated carry.
Ex: - ADC AL, 74H ADC DX, AX ADC AX, [BX]
SUB
It performs subtraction between the contents of source and destination operands.
The first operand is act as minuend and second operand is act as subtrahend. CF acts as borrow
flag.
Ex: - SUB AL, 74H SUB DX, AX SUB AX, [BX]
SBB
It performs subtraction between the contents of source and destination operands along with
previous generated carry.
The first operand is act as minuend and second operand is act as subtrahend. CF acts as borrow
flag.
Ex: - SBB AL, 74H SBB DX, AX SBB AX, [BX]
INC
It increment the contents of specified operand. The operand can be a register or memory
location.
It affects AF, OF, PF, SF, ZF flags. CF is not affected.
Ex: - INC AX INC [BX] INC [2050H]
DEC
It decrement the contents of specified operand. The operand can be a register or memory
location.
It affects AF, OF, PF, SF, ZF flags. CF is not affected.
Ex: - DEC AX DEC [BX] DEC [2050H]
AAA (ASCII Adjust after Addition)
The data entered from the terminal is in ASCII format. In ASCII, 0 – 9 are represented by 30H –
39H.
This instruction allows us to add the ASCII codes. This instruction does not have any operand.
Similarly the following are the ASCII related instructions.
Other ASCII Instructions are
AAS (ASCII Adjust after Subtraction)
AAM (ASCII Adjust after Multiplication)
AAD (ASCII Adjust Before Division)
DAA (Decimal Adjust after Addition)
It is used to make sure that the result of adding two BCD numbers is adjusted to be a correct
BCD number.
It only works on AL register. This Instruction is belongs to Implied addressing mode.
DAS (Decimal Adjust after Subtraction)
It is used to make sure that the result of subtracting two BCD numbers is adjusted to be a
correct BCD number.
It only works on AL register. This Instruction is belongs to Implied addressing mode.
NEG
It creates 2’s complement of a given number. That means, it changes the sign of a Number. The
source content is subtracted from the Zero. The source is a register or a memory location.
Ex: - NEG AX NEG [1250H] NEG [BX]
CMP
It compares two specified bytes or words. The Src and Des can be a constant, register or
memory location.
Both operands cannot be memory locations at the same time. And immediate data may not be
destination.
The comparison is done simply by internally subtracting the source from destination. The value
of source and destination does not change, but the flags are modified to indicate the result.
Ex: - CMP AX, BX CMP AX, [2050H] CMP BX, 3050H
MUL
It is an unsigned multiplication instruction. It multiplies two bytes to produce a word or two
words to produce a double word.
This instruction assumes one of the operand in AL or AX. Src can be a register or memory
location.
For two bytes multiplication the result size is a word (16-bit) that is default stored in the AX
register. Similarly for two words (16-bit) are multiplied the result size is 32-bit that is stored in
the combination of DX and Ax registers.
Ex: -MUL BL MUL [2050H] MUL CX
IMUL
It is a signed multiplication instruction. The conditions for this are similar to the MUL
instruction.
DIV
It is an unsigned division instruction. It divides word by byte or double word by word.
The dividend is AX, divisor is Src and the result is stored as: AH = remainder AL = quotient. It is
for word by byte division (16-bit / 8-bit).
But for double word by word division (32-bit / 16-bit) the dividend is the content of
combination of two registers DX and AX, the divisor is Src and the result is stored as: AX=
quotient and DX=remainder.
Ex: - DIV BL DIV [2050H] DIV CX
IDIV
It is a signed division instruction. The conditions for this are similar to the DIV instruction.
CBW (Convert Byte to Word)
This instruction converts byte in AL to word in AX. The conversion is done by extending the sign
bit of AL throughout AH.
This Instruction is belongs to Implied addressing mode.
CWD (Convert Word to Double Word)
This instruction converts word in AX to double word in DX: AX. The conversion is done by
extending the sign bit of AX throughout DX.
This Instruction also belongs to implied addressing mode.
3. Logical Instructions& Shift and Rotate Instructions
These instructions are used to perform Bit wise operations.
These instructions are also called as Bit-Manipulation Instructions.
The contents of flag register modifies based the result.
NOT
It complements each bit of source to produce 1’scomplement of the specified operand. The
operand can be a register or memory location.
Ex: - NOT AX NOT [2050H]
AND
It performs Logical AND operation between source and destination operands.
Source operand can be an immediate number, register or memory location. Destination
operand can be register or memory location.
Both operands cannot be memory locations at the time.
Ex: - AND AX, BX AND AX, [3050H] AND AX, 1200H AND [3040H], 1250H
OR
It performs Logical OR operation between source and destination operands.
Source operand can be an immediate number, register or memory location. Destination
operand can be register or memory location.
Both operands cannot be memory locations at the time
Ex: - OR AX, BX OR AX, [3050H] OR AX, 1200H OR [3040H], 1250H
XOR
It performs Logical XOR operation between source and destination operands.
Source operand can be an immediate number, register or memory location. Destination
operand can be register or memory location.
Both operands cannot be memory locations at the time
Ex: - XOR AX, BX XOR AX, [3050H] XOR AX, 1200H XOR [3040H], 1250H
SHL
This instruction shifts the content of the source to left side by count times.
It puts zero(s) in LSbs. MSb is shifted into carry flag.
The count value is specified by the counter register or directly mention in the instruction
operand field.
Ex: - SHL AX SHL AX, 02H
SHR
This instruction shifts the content of the source to left side by count times.
It puts zero(s) in MSbs. LSb is shifted into carry flag.
The count value is specified by the counter register or directly mention in the instruction
operand field.
Ex: - SHR AX SHR AX, 02H
ROL
It rotate left the contents of the source by count times. MSb is transferred to LSb and to CF.
If the number of bits desired to be shifted is 1, then the immediate number 1 can be written in
Count. However, if the number of bits to be shifted is more than1, then the count is put in CL
register.
Ex: - ROL AX ROL AX, 02H
ROR
It rotate left the contents of the source by count times. LSb is transferred to MSb and to CF.
If the number of bits desired to be shifted is 1, then the immediate number 1 can be written in
Count. However, if the number of bits to be shifted is more than1, then the count is put in CL
register.
Ex: - ROR AX ROR AX, 02H
NEG
It is an instruction which forms the 2’s complement (i.e., 1’s complement + 1) of an operand.
Ex: - NEG AX NEG [2002H]
TEST
This instruction performs logical AND between the contents of a source and destination operands but the result
cannot be store anywhere on the processor but the flags are changes based on the result
TEST is called as hypothetical AND.
Ex: - TEST AL, BH TEST CX, 0001H
SAL
It performs arithmetic shift left the bits of source operand by count times. It puts zero(s) in
LSbs. MSb is shifted into carry flag.
If the number of bits desired to be shifted is 1, then the immediate number 1 can be written in
Count. However, if the number of bits to be shifted is more than1, then the count is put in CL
register.
This type of operation already exists in SHL instruction, so SAL is equal to SHL.
Ex: - SAL AX SAL AX, 02H
SAR
It Arithmetic shift right the bits of source operand by count times.
It puts Sign bit as it is in the MSb position and he next vacant positions are copied with sign bit
value.
LSb is shifted into carry flag. If the number of bits desired to be shifted is 1, then the immediate
number 1 can be written in Count.
However, if the number of bits to be shifted is more than1, then the count is put in CL register.
Because of this operation SAR is not equal to SHR.
Ex: - SAR AX SAR AX, 02H

4. Program Flow Control Instructions:

These instructions cause change in the sequence of the execution of instructions. This change
can be through a condition or sometimes without condition. The conditions are represented by
flags.
These instructions are also called as Branching Instructions or Transfer of control Instructions
or Jump instructions.
These are two types of Instructions
1. Unconditional Branching Instructions
2. Conditional Branching Instructions
1. Unconditional Branching Instructions
These instructions are used to change the program execution flow control from one location to
another location unconditionally means without taking any condition from conditional flags of
8086.
By execution any instruction in this group program execution definitely modifies.
JMP
This instruction is used for unconditional jump from one place to another place. The destination
address is any location in the 1MB of addressable memory of 8086.
Generally this jump is long jump. The destination address is directly or indirectly represented in
the operand field of the instruction.
Ex: - JMP 2000H JMP [SI]
CALL
This instruction is used to call a subroutine or function or procedure into main program.
The address of next instruction (both CS & IP values) after CALL is saved onto stack. For this
instruction execution the SP content is decrement by 2 or 4.
There are two types of CALL instructions in 8086. a. NEAR CALL a. FAR CALL.
a. NEAR CALL
This CALL instruction is used when the subprogram and main program both appears in same
segment. For this instruction only offset address of subprogram placed in the operand field of
the instruction.
Ex: - CALL 2000H
b. FAR CALL
This CALL instruction is used when the subprogram and main program appears in different
segments. For this instruction both base address and offset address of subprogram placed in
the operand field of the instruction.
Ex: - CALL 2000H: 3050H
RET
It returns the control from procedure or subprogram to calling program. For this instruction
execution the SP content is increment by 2 or 4.
This instruction belongs to Implied addressing mode and its length is 1Byte. This instruction is
used as last instruction for any subprogram or procedure.
Ex: - RET
IRET
It returns the control from ISR (Interrupt Service Routine) to calling program.
For this instruction execution the SP content is increment by 6. This instruction belongs to
Implied addressing mode and its length is 1Byte.
This instruction is used as last instruction for any ISR. The SP increment by 2 for first time to get
the IP value from the stack, again SP increment by 2 for second time to get the CS value from
the stack, again SP increment by 2 for third time to get the Flag Register value from the stack.
Ex: - IRET
INT
This instruction is used to generate the software interrupts in 8086.
The value of ‘n’ is varies from 00H to 0FFH or 0 to 255d.
Ex: - INT 02H INT 21H
2. Conditional Branching Instructions
These instructions are used to change the program execution flow control from one location to
another location conditionally means with taking condition from conditional flags of 8086.
By execution any instruction in this group program execution may or may not be modifies.
It is entirely depends on the condition is satisfied or not.
The Conditional Branching Instructions are designed based on the conditions of the conditional
flags except AC.
All conditional jumps are relative jumps means operand address is 8-bit signed numbers.
Conditional Branching Instructions based conditions in the CY flag
CY = 0 JNC CY = 1 JC
Conditional Branching Instructions based conditions in the PF
PF = 0 JNP PF = 1 JP
Conditional Branching Instructions based conditions in the ZF
ZF = 0 JNZ ZF = 1 JZ
Conditional Branching Instructions based conditions in the SF
SF = 0 JNS SF = 1 JS
Conditional Branching Instructions based conditions in the OV flag
OV = 0 JNO OV = 1 JO
Some conditional branching instructions are designed based on conditions of 2 flags. Those 2
flags are CY and ZF.
JB / JNAE = Jump on Below / Jump on not Above or not Equal (CY = 1 & ZF = 0).
JNB / JAE = Jump on not Below / Jump on Above or Equal (CY = 0 & ZF = 1).
JBE / JNA = Jump on Below or Equal / Jump on not Above (CY = 1 & ZF = 1).
JNBE / JA = Jump on not Below or not Equal / Jump on Above (CY = 0 & ZF = 0).
These set of instructions are used when the comparison between two unsigned input data’s.
JL / JNGE = Jump on Lesser / Jump on not Greater or not Equal (CY = 1 & ZF = 0).
JNL / JGE = Jump on not Lesser / Jump on Greater or Equal (CY = 0 & ZF = 1).
JLE / JNG = Jump on Lesser or Equal / Jump on not Greater (CY = 1 & ZF = 1).
JNLE / JG = Jump on not Lesser or not Equal / Jump on Greater (CY = 0 & ZF = 0).
These set of instructions are used when the comparison between two signed input data’s.
JCXZ
If the processor executes this instruction the execution shifts specified destination only when
the count value in the counter register (CL or CX) is equal to zero.
Machine Control Instructions
This group of instructions is used to control the machine operation. These instructions are also
called ‘Processor Control Instructions’.
WAIT
Wait for Test input pin to go low.
HLT
Halt the process.
NOP
No operation.
ESC
Escape to external device like NDP
LOCK
Bus lock instruction prefix.

6. LOOP Related Instructions

There are two types of instructions in this group. Those are unconditional loop and conditional
loop instructions.
Unconditional LOOP
LOOP
This is a looping instruction. The number of times looping is required is placed in the CX
register.
With each iteration, the contents of CX are decremented. ZF is checked whether to loop again
or not.
If the ZF is not equal to ‘1’ then the execution goes to the specified location.
Ex: - LOOP 2040H
Conditional LOOP
LOOPZ / LOOPE Label
Loop through a sequence of instructions from label while ZF=1 and CX=0.
LOOPNZ / LOOPENE Label
Loop through a sequence of instructions from label while ZF=0 and CX=1.

7. Flag Manipulation instructions

The Flag manipulation instructions directly modify some of the Flags of 8086.
CLC
Clear Carry Flag.
CMC
Complement Carry Flag.
STC
Set Carry Flag.
CLD
Clear Direction Flag.
STD
Set Direction Flag.
CLI
Clear Interrupt Flag.
STI
Set Interrupt Flag.
8. String Manipulation Instructions

A series of data bytes or words available in memory at consecutive locations, to be referred as

Byte String or Word String.
A String of characters may be located in consecutive memory locations, where each character
may be represented by its ASCII equivalent.
The 8086 supports a set of instructions for string manipulations for referring to a string, two
parameters are required.
A. Starting and End Address of the String.
B. Length of the String.
The length of the string is usually stored as count in the CX register.
The incrementing or decrementing of the pointer, in string instructions, depends upon the
Direction Flag (DF) Status.
If it is a Byte string operation, the index registers are updated by one. On the other hand, if it is
a word string operation, the index registers are updated by two.
REP (Repeat Instruction Prefix)
This is used as a prefix to other instructions, the instruction to which the REP prefix is provided,
is executed repeatedly until the CX register becomes zero and at each iteration CX is
automatically decremented by one.
The following are the other Repeat prefixes
REPE / REPZ - repeat operation while equal / zero.
REPNE / REPNZ - repeat operation while not equal / not zero.
These are used for CMPS, SCAS instructions only, as instruction prefixes.

MOVSB / MOVSW (Move String Byte or Move String Word)

Suppose a string of bytes stored in a set of consecutive memory locations is to be moved to
another set of destination locations.
The starting byte of source string is located in the memory location whose address may be
computed using SI (Source Index) and DS (Data Segment) contents.
The starting address of the destination locations where this string has to be relocated is given
by DI (Destination Index) and ES (Extra Segment) contents.
CMPSB/CMPSW (Compare String Byte or Compare String Word)
The CMPS instruction can be used to compare two strings of byte or words.
The length of the string must be stored in the register CX. If both the byte or word strings are
equal, zero Flag is set.
The REP instruction Prefix is used to repeat the operation till CX (counter) becomes zero or the
condition specified by the REP Prefix is False.
SCANSB/SCASW (Scan String Byte or Scan String Word)
This instruction scans a string of bytes or words for an operand byte or word specified in the
register AL or AX.
The String is pointed to by ES:DI register pair.
The length of the string is stored in CX. The DF controls the mode for scanning of the string.
Whenever a match to the specified operand is found in the string, execution stops and the zero
Flag is set. If no match is found, the zero flag is reset.
LODSB/LODSW (Load String Byte or Load String Word)
The LODSB/LODSW instruction loads the AL / AX register by the content of a string pointed to
by DS:SI register pair.
The SI is modified automatically depending upon DF, if it is a byte transfer (LODSB), the SI is
modified by one and if it is a word transfer (LODSW), the SI is modified by two. There is no
prefix for this instruction.
STOSB/STOSW (Store String Byte or Store String Word)
The STOSB/STOSW instruction Stores the AL / AX register contents to a location in the string
pointer by ES:DI register pair. The DI is modified accordingly; No prefix for this instruction.
The direction Flag controls the String instruction execution, Destination Index DI is modified
after each iteration automatically.
If DF=1, then the execution follows auto-decrement mode, DI is decremented automatically
after each iteration. If DF=0, then the execution follows auto-increment mode. In this mode, DI
is incremented automatically after each iteration.
Assembler Directives

Assembler directives are nothing but statements or words which gives directions to assembler.
8086 processor has different assemblers, mainly those are TASM (Turbo Assembler), MASM
(Macro Assembler), ASM 86 (Assembler 8086). Some of the 8086 assembler directives are
ASSUME
The ASSUME directive is used to tell the assembler that the name of the logical segment should
be used for a specified segment.
The 8086 works directly with only 4 physical segments: a Code segment, a data segment, a
stack segment, and an extra segment.
Ex: - ASUME CS: CODE ASUME DS: DATA
DB
DB directive is used to declare a byte type variable or to store a byte in memory location.
Ex: - PRICE DB 49h, 98h, 29h; declare an array of 3 bytes, named as PRICE and initialize.
NAME DB ‘ABCDEF’; declare an array of 6 bytes and initialize with ASCII code for letters
TEMP DB 100 DUP (?); Set 100 bytes of storage in memory and give it the name as TEMP,
but leave the 100 bytes uninitialized. Program instructions will load values into these locations.
DW
The DW directive is used to define a variable of type word or to reserve storage location of type
word in memory.
Ex: - MULTIPLIER DW 437Ah; this declares a variable of type word and named it as MULTIPLIER.
EXP1 DW 1234h, 3456h, 5678h; this declares an array of 3 words and initialized with
specified values.
STOR1 DW 100 DUP (0); Reserve an array of 100 words of memory and initialize all words
with 0000.Array is named as STOR1.
DD
The DD directive is used to define a variable of type double word or to reserve storage location
of type double word in memory.
Ex: - MULTIPLIER DD1235437Ah; this declares a variable of type double word and named it as
MULTIPLIER. This variable is initialized with the value 437Ah when it is loaded into memory to
run.
EXP1 DD 10201234h, 20303456h, 12345678h; this declares an array of 3 double words
and initialized with specified values.
STOR1 DD 100 DUP (0); Reserve an array of 100 double words of memory and initialize all
double words with 0. Array is named as STOR1.
DQ
The DQ directive is used to define a variable of type quad word or to reserve storage location of
type quad word in memory.
Ex: - MULTIPLIER DQ 112233441235437Ah; this declares a variable of type quad word and
named it as MULTIPLIER. This variable is initialized with the value 112233441234437Ah when it
is loaded into memory to run.
STOR1 DQ 100 DUP (0); Reserve an array of 100 quad words of memory and initialize all
quad words with 0. Array is named as STOR1.
DT
The DT directive is used to define a variable of type ten bytes or to reserve storage location of
type ten bytes in memory.
Ex: - MULTIPLIER DT 112233441235437ACDh; this declares a variable of type ten bytes and
named it as MULTIPLIER. This variable is initialized with the value 112233441234437ACDh when
it is loaded into memory to run.
STOR1 DT 100 DUP (0); Reserve an array of 100 ten bytes of memory and initialize all ten
bytes with 0. Array is named as STOR1.
END
END directive is placed after the last statement of a program to tell the assembler that this is
the end of the program module.
The assembler will ignore any statement after an END directive.
ENDP
ENDP directive is used along with the name of the procedure to indicate the end of a procedure
to the assembler.
Ex: - SQUARE_NUM PROCE; It start the procedure; some steps to find the square root of a
number
SQUARE_NUM ENDP; Hear it is the End for the procedure
ENDS
This ENDS directive is used with name of the segment to indicate the end of that logic segment.
Ex: - CODE SEGMENT; hear it Start the logic
 ; Segment containing code
; Some instructions statements to perform the logical
; Operation
CODE ENDS; End of segment named as; CODE
EQU
This EQU directive is used to give a name to some value or to a symbol. Each time the
assembler finds the name in the program, it will replace the name with the value or symbol you
given to that name.
Ex: - FACTOR EQU 03H
EVEN
This EVEN directive instructs the assembler to increment the location of the counter to the next
even address if it is not already in the even address. If the word is at even address 8086 can
read a memory in 1 bus cycle.
If the word starts at an odd address, the 8086 will take 2 bus cycles to get the data. When EVEN
is used the location counter will simply incremented to next address and NOP instruction is
inserted in that incremented location.
GROUP
The GROUP directive is used to group the logical segments named after the directive into one
logical group segment.
INCLUDE
This INCLUDE directive is used to insert a block of source code from the named file into the
current source module.
PROC
The PROC directive is used to identify the start of a procedure. The term near or far is used to
specify the type of the procedure.
Ex: - SMART PROC FAR; This identifies that the start of a procedure named as SMART and
instructs the assembler that the procedure is far.
SMART ENDP
This PROC is used with ENDP to indicate the break of the procedure.
PUBLIC
The PUBLIC directive is used to instruct the assembler that a specified name or label will be
accessed from other modules.
Ex: - PUBLIC DIVISOR, DIVIDEND; these two variables are public so these are available to all
modules. If an instruction in a module refers to a variable in another assembly module, we can
access that module by declaring as EXTRN directive.
TYPE
TYPE operator instructs the assembler to determine the type of a variable and determines the
number of bytes specified to that variable.
Ex: - Byte type variable – assembler will give a value 1
Word type variable – assembler will give a value 2
Double word type variable – assembler will give a value 4