80286,80386 &

80486
Bus Pipelining
Bus Pipelining
Split Transactions supported 80386
Address
Data
 Non-Pipelined Bus
T1 T2 T1 T2

Address Address

Data Data
ADS
Pipeline
Memory Interleaving
 Memory Interleaving
0000 0001 0002 0003 0004 0005 0006 0007
0008 000C
0010 0014

Section 0 Section 1

A2
 Pipelined Bus SEC1
T1 SEC0 T2 T2P SEC1 T1P T2P SEC0 T1P T2P T1P

Address 0 Address 1 Address 2 Address 3

ADS’

DATA D0 D1 D2

Address 0 Address 2

ALE0

Address 1 Address 3
ALE1
80486
Burst Transfers
Burst Bus
T1 T2 T2 T2 T2

ADS’

DATA D0 D1 D2 D3

BRDY’
Cache
Introduction & 80486 Cache
Cache Memory
Extreme Fast Memory
Internal/External to CPU
CPU uses cache memory to store instructions that are
repeatedly required to run programs- working set
Cache hit/miss
Cache
Cntlr
L2 Cache

L1 Cache
CPU
Miss Types
Compulsory Miss/Cold Miss
Capacity Miss
Conflict Miss

Cache Organization
Direct Mapped
Set Associative
 Valid Tag Data
cache block 1
cache block 2
cache block 3
cache block 4
cache block 5
Address
Tag Index Offset

= Value

Hit
Write Through
Write Back
001 Address Data
000 0101
100 001 1111
010 010 0110
011 0000
101
100 1000
101 0001
110 1010
111 0100

00 -1 1000
-
01 -
10 0001
1111
-

10 -0 0110
-
11 - -

Block Tag Data

001 Address Data
000 0101
100 001 1111
010 010 0000
011 0110
101
100 1000
101 0001
110 1010
111 0100

0 -
10 -
1000 -01 -0000
1 -
00 -
0101 -10 -0001

Block S0 Tag S0 Data S1Tag S1Data

Set Associative Cache

 Block
Tag

bank 1 bank 2 bank n

bank select

data
Cache in 80486
Four way set associative cache
Each line – 16 bytes of data
Write Through Cache
4 ways -128 lines in each way – 16 bytes