Hardware

Components –
Memory - Cache
M1: Introduction to Embedded Systems
Cache Memory
Extreme Fast Memory
Internal/External to CPU
CPU uses cache memory to store instructions that are repeatedly required to run
programs- working set
Sequential locality of reference – spatial & temporal

Cache
Cntlr
Cache hit/miss
L2 Cache

L1 Cache

CPU

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Miss Types
 Compulsory Miss/Cold Miss
 Capacity Miss
 Conflict Miss

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Cache Organization

 Direct Mapped
 Set Associative

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Cache Architecture

MDR

Cache

MAR

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 Cache Mapping - Direct
MAIN
Page 0 Block 0 4 bytes
4k
Block1
4k
Block N Block 0 TAG
Block1
Block 0
Block1 Block N
Page 1
Block N
CACHE
Block 0
Page 2 No. of Blocks = 1K
Block1
Block N

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 Valid Tag Data

cache block 1

cache block 2

cache block 3

cache block 4

cache block 5
Address

Tag Index Offset

=

Dirty Bit Value

Hit
Write Through
Write Back

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001 Address Data
100 000 0101
010 001 1111
101 010 0110
011 0000
100 1000
101 0001
110 1010
111 0100
00 -
1 1000
-

01 -
0
1 0001
1111
-

10 -
0 0110
-

11 - -

Block Tag Data

Embedded System Design - RL1.2.4 © K.R.Anupama & Meetha.V.Shenoy 8
001 Address Data
100 000 0101
010 001 1111
101 010 0000
011 0110
100 1000
101 0001
110 1010
111 0100

0 -
10 -
1000 - -01 - -0000

1 -
00 -
0101 - -10 - -0001

Block S0 Tag S0 Data S1Tag S1Data

Set Associative Cache

Embedded System Design - RL1.2.4 © K.R.Anupama & Meetha.V.Shenoy 9
Cache Organization
 Cache
 64K x 32
 128 - 0.5 K blocks
 Two sets

 Main Memory
 256 K x 32
 512 Blocks - m
 64 Groups –n
 Group No m mod n

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 Main Memory
Organisation
Block Group
0 64 128 384 448 0
1 65 129 385 449 1
2 66 130 386 450 2

63 127 192 447 511 63

0 1 2 3 4 5 6 7

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Mapping

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 Block

Tag

bank 1 bank 2 bank n

bank select

data

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Cache – Commonly used
in systems
 Unified Cache
 Instruction/Data Cache
 Strong ARM – 16 KB, 32 way cache – each block is 32 bytes
 C5510 – 16KB instruction cache – 2 way

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