Computer Organization & Architecture (COA)

GTU # 3140707

Unit-10
Multiprocessors

Prof. Krunal D. Vyas

Computer Engineering Department
Darshan Institute of Engineering & Technology, Rajkot
krunal.vyas@darshan.ac.in
9601901005
 Outline
Looping
• Tightly coupled V/S Loosely coupled
• Interconnection Structures
• Cache Coherence
• Shared Memory Architecture
• Questions asked in GTU exam
Tightly coupled V/S Loosely
coupled
Section - 1
Tightly coupled V/S Loosely coupled

Tightly Coupled System Loosely Coupled System

Tasks and/or processors Tasks or processors do not
communicate in a highly communicate in a synchronized
synchronized fashion. fashion.
Communicates through a common Communicates by message
shared memory. passing packets.
Shared memory system. Distributed memory system.
Overhead for data exchange is Overhead for data exchange is
lower comparatively. higher comparatively.

Prof. Krunal D. Vyas #3140707 (COA)  Unit 10 – Multiprocessors 4

Interconnection Structures
Section - 2
Interconnection Structures
1. Time-shared common bus
2. Multiport memory
3. Crossbar switch
4. Multistage switching network
5. Hypercube system

Prof. Krunal D. Vyas #3140707 (COA)  Unit 10 – Multiprocessors 6

1. Time-shared common bus

Memory unit

CPU 1 CPU 2 CPU 3 IOP 1 IOP 2

Prof. Krunal D. Vyas #3140707 (COA)  Unit 10 – Multiprocessors 7

2. Multiport Memory
Memory modules

MM 1 MM 2 MM 3 MM 4

CPU 1

CPU 2

CPU 3

CPU 4

Prof. Krunal D. Vyas #3140707 (COA)  Unit 10 – Multiprocessors 8

3. Crossbar switch
Memory modules

MM 1 MM 2 MM 3 MM 4

CPU 1

CPU 2

CPU 3

CPU 4

Prof. Krunal D. Vyas #3140707 (COA)  Unit 10 – Multiprocessors 9

4. Multistage switching network

Operation of 2 X 2 interchange switch

0 0
A A
1 1
B B

A connected to 0 A connected to 1

0 0
A A
1 1
B B

B connected to 0 B connected to 1

Prof. Krunal D. Vyas #3140707 (COA)  Unit 10 – Multiprocessors 10

4. Multistage switching network

0 000
1
001
0
1
0
010
0 1 011
P1
1
P2
0
100
1
101
0
1
0 110
1 111

Prof. Krunal D. Vyas #3140707 (COA)  Unit 10 – Multiprocessors 11

5. Hypercube Interconnection

011 111

0 01 11 010 110

001 101

1 00 10 000 100

One-cube Two-cube Three-cube

010 x-or 001 = 011

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Dynamic Arbitration Algorithm
 Time Slice: The time slice algorithm allocates a fixed-length time slice of bus time that is
offered sequentially to each processor, in round-robin fashion.
 Polling: In a bus system that uses polling, the bus grant signal is replaced by a set of lines
called poll lines which are connected to all units.
 LRU: The Least Recently Used (LRU) algorithm gives the highest priority to the requesting
device that has not used the bus for the longest interval.
 FIFO: In first-come, first-serve scheme, requests are served in the order received.
 Rotating daisy-chain: The rotating daisy-chain procedure is a dynamic extension of the daisy-
chain algorithm. In this scheme there is no central bus-controller, and the priority line is
connected from the priority-out of the last device back to the priority-in of the first device in a
closed loop.

Prof. Krunal D. Vyas #3140707 (COA)  Unit 10 – Multiprocessors 13

Cache Coherence
Section - 3
Cache Coherence Problem

Main Memory X 100

230
50 Write through

Write back

Cache X 100
50 X 50 X 50
120
115
230
Processor P1 P2 P3

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Cache Coherence Solution
 Write Update
 Write Invalidate
 Software approaches
 Compiler based cache coherence mechanism
 Hardware approaches
 Directory protocols
 Snoopy protocols

Prof. Krunal D. Vyas #3140707 (COA)  Unit 10 – Multiprocessors 16

Shared Memory Architecture
Section - 4
Shared Memory Architecture
Local bus

Common System
Local
shared bus CPU IOP
memory
memory controller

System bus

System System
Local
bus CPU IOP bus CPU
memory
controller controller

Local bus Local bus

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Questions asked in GTU exam
Section - 5
Questions asked in GTU exam
1. Draw and explain shared memory architecture of multiprocessor system
2. Explain Inter-process communication
3. Explain any two interconnection structures that make it possible to form a multiprocessor
system with diagram.
4. Differentiate tightly coupled and loosely coupled systems.
5. Give the features of a multiprocessor system.
6. What is cache coherence?

Prof. Krunal D. Vyas #3140707 (COA)  Unit 10 – Multiprocessors 20