Multiprocessors

Characteristics of Multiprocessors
• Multiprocessors System = MIMD
• An interconnection of two or more CPUs with
memory and I/O equipment
• » a single CPU and one or more IOPs is usually
not included in a multiprocessor system
• „Unless the IOP has computational facilities
comparable to a CPU
• Multiprocessor system implies the existence of
multiple CPU’s although usually there will be one
or more IOP as well.
• Computers are interconnected with each other by
means of communication lines to form a
computer network. The network consists of
several autonomous computer that may or may
not communicate with each other.
• A multiprocessor system is controlled by one
operating system that provides interaction
between processors and all the components of
the system cooperate in the solution of problem
• Multiprocessing improves the reliability of the
system so that a failure or error in one part of
system, if a fault cause one processor to fail a
second processor can assign to perform the
function of the disabled processor.
• Computation can proceed in parallel in one of
two ways
• 1) Multiple independent jobs can be made to
operate in parallel
• 2) A single job can be partitioned into multiple
parallel tasks
• Classified by the memory Organization
• A multiprocessor system with common shared memory is called
Shared memory or Tightly-coupled system
• » Local memory + Shared memory
• Most commercial tightly coupled multiprocessors provides a cache
memory with CPU. There is a global common property that all CPUs
can access. Information can be shared among the CPUs by placing it
in a common global property.
• „higher degree of memory or Loosely-coupled system
• » Local memory + message passing scheme (packet or message )
• „most efficient when the interaction between tasks is minimal .
• Each system has its own local private memory. The information is
routed through message passing scheme.A packet consist of an
address ,the data content and some error detection code.
 Interconnection Structure
• T„ he interconnection between the components can have
different interconnections depending upon the number of
transfer paths that are available between the processors
and memory in a shared memory system or among the
processing elements in a loosely coupled system.
• Various interconnection structures are:
• ‹Multiprocessor System Components
• 1) Time-shared common bus
• 2) Multi-port memory •CPU, IOP,
Memory unit
• 3) Crossbar switch
• 4) Multistage switching network
• 5) Hypercube system
 Time-shared Common Bus
• Time-shared single common bus system :
• » Only one processor can communicate with the memory or
another processor at any given time
• „when one processor is communicating with the memory, all
other processors are either busy with internal operations or
must be idle waiting for the bus
• Dual common bus system :
• » System bus+ Local bus
• » Shared memory
• „the memory connected to the common system bus is shared
by all processors
• » System bus controller
• „Link each local bus to a common system bus Memory unit
• CPU 1 CPU 3 CPU 2 IOP 1 IOP 2
Time-shared single common bus system
Dual common bus system
 Interconnection Structure

MULTIPORT MEMORY
Multiport Memory Module
- Each port serves a CPU

Memory Module Control Logic

- Each memory module has control logic
- Resolve memory module conflicts Fixed priority among CPUs

Advantages
- Multiple paths -> high transfer rate
Memory Modules
Disadvantages
MM 1 MM 2 MM 3 MM 4
- Memory control logic
- Large number of cables and
connections
CPU 1

CPU 2

CPU 3

CPU 4
 Interconnection Structure

CROSSBAR SWITCH
Memory modules

MM1 MM2 MM3 MM4

CPU1

CPU2

CPU3

CPU4
Block Diagram of Crossbar Switch

} data,address, and
control from CPU 1
data

Memory
address
Multiplexers
and } data,address, and
control from CPU 2
Module arbitration
R/W
logic
memory
enable
} data,address, and
control from CPU 3

} data,address, and
control from CPU 4
 Multistage Switching Network
Control the communication between a number of sources and
destinations
• » Tightly coupled system : PU-- MM
• » Loosely coupled system : PU --PU
• Basic components of a multistage switching network :
• two-input, two-output interchange switch: Fig.
• 2 Processor(P1 and P2) are connected through switches to 8
memory
• modules (000 - 111) : Fig.
• Omega Network : Fig.
• » 2 x 2 Interchange switch ,N input x N output network
topology
 Interconnection Structure

MULTISTAGE SWITCHING NETWORK

Interstage Switch

0 0
A A

1 1
B B

A connected to 0 A connected to 1

0 0
A A

1 1
B B

B connected to 0 B connected to 1
 Interconnection Structure

MULTISTAGE INTERCONNECTION NETWORK

Binary Tree with 2 x 2 Switches 0
000
0 1
001
1
0
010
P1 0
1
1 011
P2
0
100
0
1
1 101

0
110
1
111
8x8 Omega Switching Network
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111