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8086 System Architecture Overview

The document discusses the operating modes and control signals of the Intel 8288 bus controller chip. It describes the I/O bus mode where I/O command lines are always enabled and no waiting is required to access the I/O bus. It also describes the system bus mode where both memory and I/O commands must wait for bus arbitration. The document outlines the control outputs of the 8288 including Data Enable, Data Transmit/Receive, and Master Cascade Enable/Peripheral Data Enable. It also discusses the maximum-mode memory read and write cycles of the 8086 system and memory interfacing in maximum mode.

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Aditya Kumar
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282 views17 pages

8086 System Architecture Overview

The document discusses the operating modes and control signals of the Intel 8288 bus controller chip. It describes the I/O bus mode where I/O command lines are always enabled and no waiting is required to access the I/O bus. It also describes the system bus mode where both memory and I/O commands must wait for bus arbitration. The document outlines the control outputs of the 8288 including Data Enable, Data Transmit/Receive, and Master Cascade Enable/Peripheral Data Enable. It also discusses the maximum-mode memory read and write cycles of the 8086 system and memory interfacing in maximum mode.

Uploaded by

Aditya Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

8086

BASED
SYSTEM
z

Vaibhav Nijhawan
ECE Department,
Maharaja Agrasen
Institute of
Technology
Signal Defination
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2
Vaibhav Nijhawan, ECE Department, MAIT
Minimum
z
mode Configuration
3
Vaibhav Nijhawan, ECE Department, MAIT
Demultiplexing of AD lines
z
4
Vaibhav Nijhawan, ECE Department, MAIT
Generation of Control Signals
z
5
Vaibhav Nijhawan, ECE Department, MAIT
Transceiver
z
6
Vaibhav Nijhawan, ECE Department, MAIT
7 Minimum-mode Memory-Read cycle of
8086 system
Vaibhav Nijhawan, ECE Department, MAIT
Memory interfacing in Minimum
mode
8
Vaibhav Nijhawan, ECE Department, MAIT
Maximum Mode Configuration
9
Vaibhav Nijhawan, ECE Department, MAIT
10

Operating Modes of
8288
▪ I/O Bus Mode

▪ The 8288 is in the I/O bus mode if the IOB pin is high. In
the I/O bus mode, all I/O command lines IORC¯, IOWC¯,
AIOWC¯, INTA¯) are always enabled (i.e., not dependent
Vaibhav Nijhaw an, ECE Department, MAIT

on AEN). No waiting is involved when the CPU wants to


gain access to the I/O bus It is advantageous to use the
IOB mode if I/O or peripherals dedicated to one processor
exist in a multi-processor system.
11

System Bus Mode

This mode assumes bus


arbitration logic will inform the bus
controller on the AEN line that
Operating when the bus is free for use.
Modes of 8288
Both memory and I/O commands
Vaibhav Nijhaw an, ECE Department, MAIT

wait for bus arbitration.

This mode is used when only one


bus exists. Here, both I/O and
memory are shared by more than
one processor.
12

Command Outputs

Operating
Modes of 8288
Vaibhav Nijhaw an, ECE Department, MAIT

The advanced write commands are


made available to initiate write
procedures early in the machine
cycle. This signal can be used to
prevent the processor from entering
an unnecessary wait state INTA¯
(Interrupt Acknowledge) acts as an
I/O read during an interrupt cycle.
13

The control outputs of the 8288 are


Data Enable (DEN¯), Data
Transmit/Receive (DT/R¯) and Master
Cascade Enable/Peripheral Data
Enable (MCE/PDEN¯).

The DEN¯ signal determines when


Control the external bus should be enabled
Outputs onto the local bus and the DT/R
determines the direction of data
transfer.
Vaibhav Nijhaw an, ECE Department, MAIT

The MCE/PDEN pin changes function


with the two modes of the 8288. When
the 8288 is in the IOB mode (IOB
high), the PDEN signal serves as a
dedicated data enable signal for the
I/O or Peripheral System bus
14 Maximum-mode Memory-Read cycle
of 8086
Vaibhav Nijhawan, ECE Department, MAIT
15
Maximum-mode Memory-Write cycle
of 8086
Vaibhav Nijhawan, ECE Department, MAIT
16 Memory interface of a Maximum-
mode 8086
Vaibhav Nijhawan, ECE Department, MAIT
Thank
You
z
Vaibhav Nijhaw an, ECE Department, MAIT
17

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