Instruction Set of 8086

ADDRESSING
MODES OF
8086
Vaibhav Nijhawan
Department of Electronics and
Communication Engineering
Maharaja Agrasen Institute of
Technology
Delhi
ADDRESSING MODES OF 8086
❖The addressing modes are the ways

of specifying an operand in an
instruction.
❖ Data addressing modes
❖ Address addressing modes.
2
Vaibhav Nijhawan, ECE Department, MAIT
❖ Implied
❖ Register
❖ Immediate
❖ Direct
❖ Register indirect
❖ Register indirect addressing
DATA mode works with SI, DI, BX
ADDRESSING and BP registers
❖ Base Addressing mode
MODES
❖ Index addressing mode
❖ Based Indexed Addressing mode
❖ Based Indexed with
displacement Addressing mode
❖ String Addressing Mode
3
❖ Immediate Addressing Mode
❖ MOV AX, 2500H
❖ Register Addressing Mode
❖ MOV AX, BX
❖ Direct Addressing mode or the
DATA Displacement Only Addressing
Mode
ADDRESSING ❖ MOV AX, [4321H]
MODES ❖ MOV AX, ES: [4321H]
❖ MOV AX, CS: [4321H]
❖ The Register Indirect Addressing
Modes
❖ MOV DX, [BX]
❖ MOV AX, CS:[BX]
4
DATA ADDRESSING MODES
 Base Addressing mode
MOV AL, [BX + 15]

MOV AL, DISP [BX]
 Index addressing mode
MOV AL, DISP [SI]

MOV AL, CS: DISP [SI]
5
DATA ADDRESSING MODE
❖ Based Indexed Addressing mode

❖ MOV AL, [BX][SI]
❖ Based Indexed with displacement AM

❖ MOV AL, [BX + SI + 15]
❖ String Addressing Modes
6
❖ Summary of data addressing modes
DATA ADDRESSING MODES

7
❖ These addressing modes indicate the
branch addresses in the Call and
Jump instructions.
ADDRESS ❖ In 8086 there are four types of
address addressing modes
ADDRESSING
❖ Intrasegment direct
MODES ❖ Intrasegment indirect
❖ Intersegment direct
❖ Intersegment indirect.
8
❖ADDRESS ADDRESSING MODES
❖ Intrasegment direct
2000 JMP 20H
New IP = 2020h
❖ Intrasegment indirect
2000 JMP [BX]
New IP = BX
9
ADDRESS ADDRESSING MODES
❖ Intersegment direct
❖2000 CALL 1000H: 5000H
❖ New IP = 1000H
❖ New CS = 5000H
❖ Intersegment indirect
❖ 2000 CALL [BX]
❖ New IP = Contents [BX, BX+1]

❖ New CS = Contents [BX +2, BX+3]

10
Example 1: Given that
BX = 2500H SI = 5000H, Displacement = 1000 H, IP = 2000H
Determine the effective address for the various addressing
Solution:
Immediate addressing mode effective address is the content of the IP, so EA = 2000H.
Register addressing using SI, EA = 5000H
Direct addressing using the displacement , EA = 1000H
Register indirect addressing using BX, EA = 2500H Base addressing using displacement , EA = 2500H +
1000H = 3500H
Index addressing using displacement, EA = 5000H + 1000H = 6000H
Base index addressing , EA = BX +SI = 2500H + 5000H = 7500H
Base index relative addressing, EA = BX +SI + Disp = 2500H + 5000H +1000 = 8500H
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 Example 2:
Find the branch address for the following address addressing mode
Assume the following
IP= 2500H CS = 2000H BX = 3000H DS = 4000H
Immediate value (16-bit) = 1500H
Immediate value (32-bit) = 1500:3500H [43000H] = 40FD3598H [44500H] = 05F6H
Solution:
For Intrasegment direct addressing mode the branch = 1500H + 2500H =4000H
For Intrasegment indirect addressing mode the branch address = 3000H
For Intrasegment indirect addressing using base addressing using BX register mode, branch address = [DS * 10H + BX + Disp] =
[44500H] =05F6H
or Intersegment direct addressing mode the branch address will be IP = 1500H and CS =3500H
or intersegment indirect addressing mode using BX register the branch address
= [DS * 10H + BX] = [43000H] = 40FD3598H So IP = 40FDH and CS = 3598H
12
INSTRUCTION FORMAT AND
TEMPLATES
OF 8086
INSTRUCTION FORMAT
14
 The first byte always consists of
the opcode. The OP code may
be of 8-bit or may occupy MSB
six bits of the first byte The
remaining two bits are any of
the following bits.
 Direction bit (D) defines
whether the register operand
in byte 2 is the source or
INSTRUCTION destination operand.
FORMAT D=1 To register D=0 From

register
 Data size bit (W) defines
whether the operation to be
performed is an 8 bit or 16 bit
data
W=0 8 bit operation
W=1 16 bit operation
15
 Sign Bit (S) is used for sign
extension of an 8-bit 2’s
compliment number to a 16-bit
2’s compliment number.
 V-Bit is used in shift and rotate
instruction to determine the
number of shifts.
INSTRUCTION V = 0 shift count is 1 V
FORMAT = 1 shift count is in CL
 The Z-bit is used in REP
instruction. The Z bit is matched
with the Zero flag bit. The REP
instruction goes on executing
till the Z bit does not match
with the Zero flag.
16
INSTRUCTION TEMPLATES
17
INSTRUCTION
TEMPLATES
18
Example 3:
 Construct the machine code for the instruction MOV
BL, CH
 Solution:
 The Instruction template of this instruction will be
 of two bytes only
 The 6 bit Opcode for this instruction is 100010.
 Since this instruction transfer only 8-bit hence W=0
 D=0 indicates CH is a source operand.
 In byte 2, since the second operand is a register MOD

field will be 11.
 The R/M field = 011 (BL)
 Register (REG) field = 101 (CH)
 machine code
19
The same instruction can be coded by another way by considering BL
register in REG field. In this case the D bit is defined in concern with the
BL register and now it will be D = 1 because the BL register is destination.
 The R/M field = 101 (CH)
 Register (REG) field = 011 (BL)
 Hence the machine code for MOV BL, CH will be
20
Example 4:
Construct the machine code for the instruction MOV
1234 (SI), AX
Solution:
Here REG field will specify the AX register, the D bit
must be 0, indicating the AX is the source register. The
REG field must be 000 to indicate AX register. The W bit
must be 1 to indicate it is a word operation. 1234 [SI] is
specified using MOD value of 10 and R/M value of 100
and a displacement of 1234H. The 4 byte code for this
instruction would be 89 8434 12H.
21
Example 5:
Construct the machine Code for IN AX, 35H
 Solution:
 The instruction template of the IN instruction is
 So the machine code for IN AX, 35H is 1110010100110101 i.e. E535H.
22
Example 6:
 Construct the machine Code for SUB BX, [DI]
 Solution:
 The instruction template of the SUB BX, [DI] instruction is same as that of a
two byte MOV instruction
 The 6 bit Opcode for SUB is 001010.
 D=1 so that REG field of byte 2 is the destination operand. W=1 indicates
16 bit operation.
 MOD = 00 REG = 011 R/M = 101
 The machine code is 0010 1011 0001 1101= 2 B 1 D
23
Example 7:
Construct the machine Code for MOV DS: 43 [BP], CX
Solution:
Specify BX using REG field.
D = 0, indicating that CX is the source.
The REG field = 001 indicating CX register.
W = 1 to indicate it is a 16-bit operation.
43 [BP] is specified with MOD = 01and R/M = 110 and
disp = 43 H.
Whenever BP is used to generate the EA, the default
segment
would be SS. But here in this instruction segment
override is used
the segment register DS is used. In such cases segment
override prefix byte (SOP byte) is to be used. The SOP
byte is
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INSTRUCTION SET OF
8086
DATA TRANSFER &
ARITHMETIC
INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
1. MOV Destination, Source
• MOV REG, memory
• MOV memory, REG •MOV SREG, memory
• MOV REG, REG •MOV memory, SREG
• MOV memory, immediate •MOV REG, SREG
• MOV REG, immediate •MOV SREG, REG
2. IN AL, 8-bit port address

AL, DX
3. OUT AL, 8-bit port address
AX, 8-bit port address AL, DX
AX, DX AX, 8-bit port address
AX, DX
Immediate No, cannot be transferred to SREG
26
DATA TRANSFER
INSTRUCTIONS
4. LDS Rd, M
❖ LDS AX, [BX]
❖ AX is set to [BX: BX+1] and DS is set to [BX+2: BX+3].
5. LEA Rd, M: Load Effective Address.
❖ LEA AX, 3[BX]
❖ This instruction copies the address of the memory location
3[BX] into the AX register.
6. LES Rd, M
❖ The general purpose register is loaded from the lower order
word of the memory operand and the segment register ES
from the higher order word.
LES AX, [M]
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DATA TRANSFER INSTRUCTIONS
7. XCHG Rd, M
M, Rs XLAT is something like
Rd, Rs MOV AL, [BX +AL]
8. XLAT No operands
AL = DS:[BX + unsigned AL]
9. PUSH REG
11. PUSHF No operands
SREG
12. POPF No operands
memory
13. LAHF No operands
10. POP REG
14. SAHF No operands
SREG
memory
28
ARITHMETIC INSTRUCTIONS
1. ADD REG, memory 3. SUB REG, memory
memory, REG memory, REG
REG, REG REG, REG
memory, immediate memory, immediate
REG, immediate REG, immediate
2. ADC REG, memory 4. SBB REG, memory
REG, REG REG, REG
memory, immediate memory, immediate
REG, immediate REG, immediate
The flag register is modified by these instructions

29
5. INC REG
memory
❖ In INC except the carry flag all other flag changes as that of in ADD and ADC
instructions.
6. DEC REG
memory
❖ In DEC except the carry flag all other flag changes as that of in SUB and SBB
instructions.
7. NEG REG
memory
MOV AL, 5 ; AL = 05h
NEG AL ; AL = 0FBh (-5)
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8. DIV REG
memory
9. IDIV REG
Memory
9. MUL REG
memory
10. IMUL REG
memory
One of the two operands one must be Accumulator. Result will be in

Accumulator and DX (if required) Register 31
11.CBW No operands
❖ CBW converts the signed value in the AL register into an equivalent
16 bit signed value in the AX register by duplicating the sign bit to
the left.
MOV AL, -5 ; AX = 000FBh (251)
❖ Flag remain unchanged CBW ; AX = 0FFFBh (-5)
12.CWD No operands
❖ CWD converts the 16 bit signed value in the AX register into an
equivalent 32 bit signed value in DX: AX register pair by
duplicating the sign bit to the left. 32
❖ Flag remain unchanged
MOV AX, -5 ; DX AX =00000h:0FFFBh
Vaibhav Nijhawan, ECE Department, MAIT CWD ; DX AX = 0FFFFh:0FFFBh
Example 1:
Write a program to add two 16- bit
numbers. ❖Segment defines a program segment called
Program: name (any arbitrary name)
Data Segment
num1 dw 6785h
num2 dw 1234h ❖END directive marks the end of a module
result dw 00
❖ENDS directive marks the end of a segment
Data Ends
Code Segment
assume CS:Code, DS:Data
Start:mov ax,data ❖ASSUME directive is used to tell the
mov ds,ax assembler, which segment is to be used as an
mov ax,00
active segment.
mov ax,num1
add ax,num2
mov result,ax
int 03h Data defining directives are used to define the
Code Ends type of data stored in the memory.
End start
These directives are DB, DW, DD, DQ and DT.
End
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❖DUP directive can be used to initialize several
locations and to assign values to these locations.
Example 2: Add 3 numbers of 8-bit each

Data Segment
num1 db 9fh, 05h, 45h
result db 3 dup (00h)
Data Ends
Code Segment
Assume CS: Code, DS: Data
❖The OFFSET directive is used to load the
Start: mov ax,data offset of memory location to a pointer register
mov ds,ax
mov si, offset num1
mov al, [si]
add al, [si +1]
adc al, [si+2]
mov result,al
int 03h
Code
End start
Ends 34
End Vaibhav Nijhawan, ECE Department, MAIT
INSTRUCTION SET OF 8086
LOGICAL & DATA
ADJUSTMENT INSTRUCTIONS
LOGICAL INSTRUCTIONS
15. AND REG, memory 16. OR REG, memory
REG, REG REG, REG
memory, immediate
memory, immediate
REG, immediate
REG, immediate
18. XOR REG, memory

17. CMP REG, memory memory, REG
memory, REG REG, REG
REG, REG memory, immediate
memory, immediate
REG, immediate
REG, immediate
20.TEST REG, memory

memory, REG
19. NOT REG
memory REG, REG 36
memory, immediate
REG, immediate
SHIFT AND ROTATE INSTRUCTIONS
RCL memory, immediate

• REG, immediate
• memory, CL
• REG, CL
ROL memory, immediate

• REG, immediate
• memory, CL
• REG, CL
Vaibhav Nijhawan, ECE Department, MAIT 37
 RCR memory, immediate
REG, immediate
memory, CL
REG, CL
 ROR memory, immediate
REG, immediate
memory, CL
REG, CL
SHIFT AND ROTATE

INSTRUCTIONS
38
 AAA No operands - ASCII Adjustment after addition
 It converts the result of the addition of two valid
unpacked BCD (which is also unpacked ASCII) digits to
a valid 2-digit BCD number and takes the AL register as
its implicit operand.
 The status of the CY and AC are stored in AH. The higher
Nibble of AL is always 0.
 AAA will adjust the result of the two ASCII characters
that were in the range from 30h (“0”) to 39h(“9”).This is
because the lower 4 bits of those character fall in the
range of 0-9.The result of addition is not a ASCII
character but it is a BCD digit.
39
 AAD No operands – ASCII adjustment before

Division
 AAD converts unpacked BCD digits in the AH and
AL register into a single binary number in the AX
register in preparation for a division operation.
 Before executing AAD, place the Most significant
BCD digit in the AH register and Last significant in
the AL register. When AAD is executed, the two
BCD digits are combined into a single binary
number by setting AL= (AH*10) + AL and clearing
AH to 0.
Example:
MOV AX, 0105h ; AH = 01, AL = 05 40
AAD ; AH = 00, AL = 0Fh (15)
 AAM No operands – ASCII Adjustment after

Multiplication
 AAM converts the result of the multiplication of two
valid unpacked BCD digits into a valid 2-digit unpacked
BCD number and takes AX as an implicit operand.
 To give a valid result the digits that have been multiplied
must be in the range of 0 – 9 and the result should have
been placed in the AX register. Because both operands
of multiply are required to be 9 or less, the result must be
less than 81 and thus is completely contained in AL.
 AAM unpacks the result by dividing AX by 10, placing
the quotient (MSD) in AH and the remainder (LSD) in AL.
Example:
MOV AL, 15 ; AL = 0Fh 41
AAM ; AH = 01, AL = 05
 AAS No operands – ASCII adjustment after Sub.

 It converts the result of the subtraction of two valid
unpacked BCD digits to a single valid BCD number and
takes the AL register as an implicit operand.
 The two operands of the subtraction must have its lower
4 bit contain number in the range from 0 to 9.The AAS
instruction then adjust AL so that it contain a correct
BCD digit.
 Example:
 MOV AX, 02FFh; AH = 02, AL = 0FFh
 AAS ; AH = 01, AL = 09
42
 DAA No operands - Decimal adjust After Addition.
 This instruction adjusts the result of an addition to a packed BCD
number. The previous sub instruction should place its 8-bit binary
result in AL.
 DAA converts this binary sum to packed BCD format with the least
significant decimal digit in the lower four bits and the most
significant digit in the upper four bits. If the sum is greater than 99h
after adjustment, then the carry and auxiliary carry flags are
set. Otherwise, the carry and auxiliary carry flags are cleared.
 Example:
 MOV AL, 0Fh ; AL = 0Fh (15)
 DAA ; AL = 15h
43
 DAS No operands - Decimal adjust After Sub.

 This instruction adjusts the result of a subtraction to a
packed BCD number. The
previous subtraction instruction should place its 8-bit
binary result in AL. DAS converts this binary sum to
packed BCD format with the least significant
decimal digit in the lower four bits and
the most significant digit in the upper four bits. If the
sum is greater than 99H after adjustment, then the carry
and auxiliary carry flags are set. Otherwise, carry and
auxiliary carry flags are cleared.
44
INSTRUCTION SET OF
8086
FLAG & CONTROL
TRANSFER
INSTRUCTIONS
❖ CLC No operands
❖ CLC clear the carry flag (CF) to 0
❖ CLD No operands
❖ This instruction reset the
designation flag to zero.
❖ CLI No operands
❖ This instruction resets the
interrupt flag to zero.
FLAG RELATED ❖ CMC No operands
INSTRUCTIONS ❖ STC No operands
❖ This instruction sets the Carry
flag.
❖ STD No operands
❖ This instruction sets the Direction
flag..
❖ STI No operands
❖ This instruction sets the Interrupt
enable flag.

46
❖ CALL procedure name
label
4-byte address
❖ This Instruction is used to transfer
execution to a procedure.
❖CONTROL ❖ There are two basic types of CALL’s:

Near and Far.
TRANSFER ❖ A Near CALL is a call to a procedure
INSTRUCTIONS which is in the same code segment as
the CALL instruction.
❖ A Far CALL is a call to a procedure
which is in a different segment from
that which contains the CALL
instruction.
47
RET No operands
❖ Returns from a procedure by
transferring control to an
address popped from the top of
the stack.
IRET No operands:
❖ Returns control from an
interrupt procedure to the
❖CONTROL interrupted code.
TRANSFER ❖ The IRET instruction pops IP,

CS, and the flags (in that order)
INSTRUCTIONS and resumes execution.
INT n
❖ Interrupt numbered by
immediate byte (0..255).
Generates a software interrupt.
INTO No operands
❖ Interrupt 4 if Overflow flag is 1.
48
❖ JMP label
4-byte address
❖ Unconditional Jump.
CONTROL ❖ This instruction transfers

control from one location to
TRANSFER another location of the program.
INSTRUCTIONS ❖ 4-byte address may be entered
in this form: 1234h:5678h, first
value is a segment second value
is an offset.
49
 JAE label -Jump if is Above or
Equal. Unsigned.
 if CF = 0 then jump
JB label - Jump if Below.
CONTROL

Unsigned.
TRANSFER  if CF = 1 then jump
INSTRUCTIONS  JBE label - Jump if Below or

Equal. Unsigned.
 if CF = 1 or ZF = 1 then
jump
50
 JC label - Jump if Carry
 JCXZ label - Jump if CX is 0.
CONTROL  if CX = 0 then jump

JE label - Jump if Equal.
TRANSFER

Signed/Unsigned.
INSTRUCTIONS  if ZF = 1 then jump
 JG label - Jump if is Greater.
Signed.
 if (ZF = 0) and (SF = OF)
then jump
51
 JGE label - Jump if Greater or
Equal. Signed.
 if SF = OF then jump
CONTROL  JL label - Jump if Less. Signed.
TRANSFER  if SF <> OF then jump

JLE label - Jump if Less or Equal.
INSTRUCTIONS

Signed.
 if SF <> OF or ZF = 1 then
jump
52
 JNA label - Short Jump if first
operand is Not Above second
operand. Unsigned.
 if CF = 1 or ZF = 1 then jump
 JNAE label - Short Jump if first
operand is Not Above and Not
Equal to second operand.
Unsigned.
CONTROL  JNB label - Short Jump if first
TRANSFER operand is Not Below second
operand. Unsigned.
INSTRUCTIONS  if CF = 0 then jump
 JNBE label - Short Jump if first
operand is Not Below and Not
Unsigned.
 if (CF = 0) and (ZF = 0) then
jump
53
 JNC label - Short Jump if Carry
flag is set to 0.
 JNE label - Short Jump if first
operand is Not Equal to
second operand.
Signed/Unsigned.
if ZF = 0 then jump
CONTROL 
 JNG label - Short Jump if first

TRANSFER operand is Not Greater then
second operand. Signed.
INSTRUCTIONS  if (ZF = 1) and (SF <> OF)
then jump
 JNGE label - Short Jump if first
operand is Not Greater and
Not Equal to second operand.
Signed.
 if SF <> OF then jump
54
 JNL label - Short Jump if first
operand is Not Less then
second operand. Signed.
 if SF = OF then jump
 JNLE label - Short Jump if first
operand is Not Less and Not
Signed.
CONTROL  if (SF = OF) and (ZF = 0)
TRANSFER then jump
INSTRUCTIONS  JNO label - Short Jump if Not

Overflow.
 if OF = 0 then jump
 JNP label - Short Jump if No
Parity (odd). Only 8 low bits of
result are checked.
 if PF = 0 then jump
55
 JNS label - Short Jump if Not
Signed (if positive).
 if SF = 0 then jump
 JNZ label - Short Jump if Not
Zero (not equal).
CONTROL  if ZF = 0 then jump
TRANSFER  JO label - Short Jump if

Overflow.
INSTRUCTIONS  if OF = 1 then jump
 JP label Short Jump if
Parity (even). Only 8 low bits of
result are checked.
56
 JPE label - Short Jump if Parity
Even. Only 8 low bits of result
are checked.
 JPO label - Short Jump if Parity
Odd. Only 8 low bits of result
CONTROL are checked.
TRANSFER  if PF = 0 then jump

JS label Short Jump if
INSTRUCTIONS

Signed (if negative).
 if SF = 1 then jump
 JZ label Short Jump if
Zero (equal).
 if ZF = 1 then jump
57
 LOOP label (LOOP
Unconditionally)
 Loop instruction is used to
create a loop from the Loop
instruction to a specified label.
Loop decrements CX without
changing any flags and if the
CONTROL result is not 0, transfers
TRANSFER execution to the address
specified by the operand. If CX
INSTRUCTIONS is 0 after being decremented,
execution continues at the
next instruction. The operand
must specify a short label
(between -128 and 127 bytes
from the instruction following
the LOOP instruction).
58
 LOOP conditional: Conditional
Loop instruction is used to
create a loop from the Loop
instruction to a specified label
if condition is met and if CX is
not 0.
 LOOPE label
 Decrease CX, jump to label if
CX not zero and Equal (ZF = 1).
CONTROL  LOOPNE label
TRANSFER  Decrease CX, jump to label if
CX not zero and Not Equal (ZF
INSTRUCTIONS = 0).
 LOOPNZ label
CX not zero and ZF = 0.
 LOOPZ label
CX not zero and ZF = 1.
59
 NOP
PROCESSOR-  ESC
WAIT
CONTROL

 LOCK
INSTRUCTIONS  HLT
60
INSTRUCTION SET OF
8086
STRING INSTRUCTIONS
STRING INSTRUCTIONS
 CMPSB No operands
Compare bytes: ES:[DI] from DS:[SI].
After execution DI = DI +1 and SI = SI +1 if DF = 0
Or DI = DI – 1 and SI = SI – 1 if DF = 1
 CMPSW No operands
Compare words: ES:[DI] from DS:[SI].
After execution DI = DI + 2 and SI = SI + 2 if DF = 0
A segment ov erride can be giv en for the source (but not for the
destination). CMPS and its v ariations are usually used with repeat
prefixes. REPNE (or REPNZ) is used to find the first match between two
strings. REPE (or REPZ) is used to find the first non-match.
62
STRING INSTRUCTIONS
 LODSB No operands
 Copies a byte from a string location pointed by SI to AX
After execution SI = SI +1 if DF = 0
or SI = SI – 1 if DF = 1
 LODSW No operands
 copies a word from a string location pointed to by SI to AX
After execution SI = SI + 2 if DF = 0
Or SI = SI – 2 if DF = 1
 A segment override can be given.
63
STRING INSTRUCTIONS
 MOVSB No operands
 Copy byte at DS: [SI] to ES: [DI].
 After execution DI = DI +1 and SI = SI +1 if DF = 0
 MOVSW No operands
 Copy byte at DS:[SI] to ES:[DI].
 After execution DI = DI + 2 and SI = SI + 2 if DF =
0
64
STRING INSTRUCTIONS
SCASB No operands
Compare bytes: AL from ES:[DI].
After execution DI = DI +1 if DF = 0
 Or DI = DI – 1 if DF = 1
SCASW No operands
Compare words: AX from ES:[DI].
After execution DI = DI + 2 if DF = 0
 Or DI = DI – 2 if DF = 1
No segment override is allowed
65
STRING INSTRUCTIONS
 STOSB No operands
 Store byte in AL into ES:[DI].
 After execution DI = DI +1 if DF = 0
Or DI = DI – 1 if DF = 1
 STOSW No operands
 Store word in AX into ES:[DI].
After execution DI = DI + 2 if DF = 0
Or DI = DI – 2 if DF = 1
 No segment override is allowed
66
STRING INSTRUCTIONS
 REP (Unconditionally)
 This is a prefix to a string instruction. This instruction repeats
the string instruction by the number of times indicated by
CX. For each string element, the string instruction is
performed and CX is decremented. REP is normally used
with MOVS and STOS
 REP (Conditionally)
 This prefix to a string instruction is used to repeat a string
instruction as long as condition is true and the maximum
count has not been reached not been reached.
 The conditional repeat prefixes should only be used with
SCAS and CMPS, since these are the only string
instructions that modify the zero flag.
67
STRING INSTRUCTIONS
 REPE String Instruction

 Repeat CMPSB, CMPSW, SCASB, SCASW instructions
while ZF = 1 (result is Equal), maximum CX times.
 REPE and REPZ (the names are synonyms) repeat while
the zero flag is set.
 REPNE String Instruction
 Repeat CMPSB, CMPSW, SCASB, SCASW instructions
while ZF = 0 (result is not equal), maximum CX times.
 REPNE and REPNZ (the names are synonyms) repeat
while the zero flag is cleared
68
THANK YOU

Instruction Set of 8086

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Instruction Set of 8086

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ADDRESSING

❖The addressing modes are the ways

 Base Addressing mode

MOV AL, [BX + 15]

 Index addressing mode

MOV AL, DISP [SI]

Vaibhav Nijhawan, ECE Department, MAIT

❖ Based Indexed Addressing mode

❖ Based Indexed with displacement AM

❖ String Addressing Modes

DATA ADDRESSING MODES

2000 JMP [BX]

❖ New IP = Contents [BX, BX+1]

Vaibhav Nijhawan, ECE Department, MAIT

FORMAT D=1 To register D=0 From

 In byte 2, since the second operand is a register MOD

 So the machine code for IN AX, 35H is 1110010100110101 i.e. E535H.

2. IN AL, 8-bit port address

The flag register is modified by these instructions

One of the two operands one must be Accumulator. Result will be in

Example 2: Add 3 numbers of 8-bit each

18. XOR REG, memory

20.TEST REG, memory

RCL memory, immediate

ROL memory, immediate

SHIFT AND ROTATE

 AAD No operands – ASCII adjustment before

 AAM No operands – ASCII Adjustment after

 AAS No operands – ASCII adjustment after Sub.

 DAS No operands - Decimal adjust After Sub.

Vaibhav Nijhawan, ECE Department, MAIT

❖CONTROL ❖ There are two basic types of CALL’s:

TRANSFER ❖ The IRET instruction pops IP,

CONTROL ❖ This instruction transfers

INSTRUCTIONS  JBE label - Jump if Below or

CONTROL  if CX = 0 then jump

CONTROL  JL label - Jump if Less. Signed.

TRANSFER  if SF <> OF then jump

 JNG label - Short Jump if first

INSTRUCTIONS  JNO label - Short Jump if Not

CONTROL  if ZF = 0 then jump

TRANSFER  JO label - Short Jump if

TRANSFER  if PF = 0 then jump

 REPE String Instruction

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