1.

1: Logic Signals, Logic Values, Bits and different Physical

Representation of Logic Values.
A binary logic signal can attain two different logic levels with values of either 0
(False) or 1 (True), which are termed binary digits or bits. In practice those values
can be represented by different levels of physical quantities (physical state) such as
voltage, although it could also be fluid pressure (pneumatic logic), light, etc. When
logic levels are encoded by voltage levels, a logic level of 1 can be represented, for
example, by a voltage range of near 5V (high) and a logic level of 0 can be
represented by a voltage range of near 0V (low). Such arrangement is termed
positive logic (or active-high logic). If a logic level of 1 is represented by a voltage
range of near 0V (low) and a logic level of 0 is represented by a voltage range of
near 5V (high), the logic is termed negative logic (or active-low logic). Since a
logic level of 1 can be encoded by a voltage value that it does not need to be
exactly 5V (for example) and a logic level of 0 can be encoded by a voltage level
that it does not need to be exactly 0V, these systems are inherently robust with a
high degree of immunity to noise, temperature, component variation or other
reasons that may cause the voltage level to reasonably deviate from its designated
value.

With one binary digit (n = 1) we can encode two different logic values (21 ):

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With two binary digits (n = 2) we can encode four different logic values (22), with
decimal representation from 0 to 3:

With three binary digits (n = 3) we can encode eight different logic values (23),
with decimal representation from 0 to 7:

In general, with n binary digits (n) we can encode n different logic values (2n).

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1.2:

1.3: Basic Representation of Logic Circuits: Introduction to the

Truth Table
A prime number detector: Let us assume that a combinational logic system with three inputs
(x,y,z) and one output (F) is implemented by a logic circuit within the following system black
box representation.

At any time that the binary representation of the three bits input (X,Y,Z) corresponds to a prime
number the circuit output F indicates so by producing a 1. Therefore, the output F is a function of
the input F(x,y,z). Since there are 8 possible binary combinations of the input (corresponding to
decimal numbers from 0 to 7, where 1,2,3,5 and 7 are prime) we will use a Truth Table to
describe the circuit logical operation by tabulating all eight possible input-output relationships:

1.4:

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In Combinational Circuits the output depends only on the current input (no memory needed).
The operation of these circuits is completely described by their Truth Tables, which list the
system output for all possible combinations of the input logic values.

In Sequential Circuits the output depends on past values of the input (memory is needed) and
eventually on the current input as well. The memory of a sequential circuit is termed the State of
the circuit. The operation of these circuits is completely described by their State Tables, which
list the Next State (next system memory) and the circuit output as a function of the Present State
(current system memory) and, eventually, the current input as well. Sequential circuits are
studied in the second part of the course.

1.5: Three Fundamental Logic Functions (AND, OR, NOT)

Truth Table definition of the Logic Function AND:

Note that both conditions, X AND Y, must be true (1) for the output to be true (1).

Schematic representation for the Logic Gate AND:

Note that both conditions, X AND Y, must be true (1) for the output to be true (1).

Note that x AND y = x.y it is also called Logical Multiplication. Sometimes we omit the
multiplication dot when the variable name is known and clear. The argument for using the dot
rests on the fact that, frequently, the logic variables are denoted by names with several literals. In
any case an engineering document should have a consistent notation.
Truth Table definition of the Logic Function OR:

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Note that at least one condition, X OR Y, need to be true (1) for the output to be true (1).

Schematic representation for the Logic Gate OR:

Note that x OR y = x + y it is also called Logical Addition.

Truth Table definition of the Logic Function NOT:

Schematic representation for the INVERTER gate that implements the NOT function:

The bubble at the tip of the gate is called an inverting bubble.

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1.6: Additional Logic Functions (NAND, NOR)
The NAND function is equivalent to applying an AND following by a NOT function.
Truth Table definition of the Logic Function NAND:

Schematic representation for the Logic Gate NAND.

The NAND gate is an AND gate followed by an inverter gate, therefore the NAND gate can be
represented by using just the inverting bubble at the end of the AND gate.

RECALL that the alternative notation is: X NAND Y =( X . Y )' =X . Y

The NOR function is equivalent to applying an OR following by a NOT function.

Truth Table definition of the Logic Function NOR:

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Schematic representation for the Logic Gate NOR:

The NOR gate is an OR gate followed by an inverter gate, therefore the NOR gate can be
represented by using just the inverting bubble at the end of the OR gate.

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2.1: Implementing Truth Tables through Logic Circuits
Note that a Combinational Logic Circuit can have any number of interconnected logic gates
and inverters, however, no feedback loops are allowed. In latter sections we will learn formal
procedures to synthetize a logic circuit from the system truth table. We will also learn how to
obtain a truth table by analyzing a given circuit, thus establishing its operation. At this point we
do not yet have formal techniques to establish whether a given circuit can be further simplified or
not.

The following logic circuit is one of many possible logic circuits that implements the Truth
Table for the prime number detector system presented before. Since we do not yet have formal
technique in this case we notice, by inspection, that the output F is always equal to the input Z
except in row 2 where X = 0 and Y = 1. This allows us to formulate a logic equation for F that
gives the correct result for the eight possible inputs:

Such expression can be readily implemented by the logic circuit shown in the figure below. We
can verify that it operates as required by substituting the eight possible combination of the input
logic values in the previous expression. Furthermore, we can do the same by propagating each of
the eight possible input combinations of logic values for X,Y,Z through the circuit to verify that
the correct output is always obtained.

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Logic Variables, Algebraic Operators, Algebraic Expressions and Logic Equations
*X and Y are logic variables that may change with time (logic signals).
*The “prime” or “hat” symbol for the NOT X = X’ is an algebraic operator that
“complements” X.
*X’, X’.Y, X’.Y+Y, etc. are algebraic expressions.
*F = X’.Y+Z is an equation

3.1: Combinational Circuit Analysis

From a given Logic Circuit or Diagram we determine its function or operation by finding a Truth
Table or a Logic Expression, which relates the circuit output to the circuit inputs. Formal
techniques to carry out these procedures will be established later.

3.2: Combinational Circuit Synthesis

From a functional description (Logic Expression) of the desired input-output relationship for a
combinational system or from the Truth Table that completely specifies its operation we
determine a suitable Logic Circuit consisting of interconnected discrete logic gates (or other
devices to be introduced later).

3.3: Combinational Circuit Design

Based on the specifications and needs of a real-life problem we develop a Truth Table or
functional description of a system that will operate in a manner that is consistent with the
problem needs and specifications. We can then, based on the truth table for example, synthetize a
logic circuit that may take into consideration other design constraints such as cost, size, weight,
component-type, and the like.

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4.1: Switching Algebra
History
Claude Shannon established how to use Boolean Algebra (developed by George Boole), which is
a two valued algebraic system, to describe and analyze relay circuits, thus the name Switching
Algebra. For example, an open relay is OFF, and it can be considered as x=0 while a closed relay
is ON and it can be considered as x=1. Two relays in series realize an AND function since both
need to be ON for the serial arrangement to be ON. Two relays in parallel realize an OR function
since only one them (or both) needs to be ON for the parallel arrangement to be ON

Axioms, Theorems, and the Duality Principle

Switching algebra is constructed from a set of Axioms or Postulates, which are a minimal and
non-contradictory set of definitions from which all other properties of the algebra can be derived
or proven (Theorems). Each Axiom or Theorem will have a dual statement based on the Duality
Principle of Boolean Algebra.

Duality Principle
Any statement (Axiom, Theorem, Identity) in Switching Algebra remains true if we interchange
OR by AND, AND by OR, 1 by 0 and 0 by 1, wherever they appear in the statement.

Switching Algebra Axioms

These 5 statements and their duals embody the definition of Switching Algebra. Based on these
axioms a set of theorems or properties can be proved, which will allow us to manipulate, design
and simplify logic circuits.

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Switching Algebra Properties (Theorems)

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Proving Theorems
Note that in the properties list there are single variable theorems, two variable theorems and n-
variable theorems.
All single-variable theorems can be easily proved by Perfect Induction, where the theorem is
proved for all possible values of the variable, which are only two values, 1 or 0.
All two-variable theorems can be easily proved by Perfect Induction, where the theorem is
proved for all possible combination of values for the two variables, which are four combinations
of: 00, 01, 10, 11.
All three-variable theorems can be easily proved by Perfect Induction, where the theorem is
proved for all possible combination of values for the two variables, which are eight combinations
of values: 000, 001, 010, 011,100, 101, 110, 111.
As we add more and more variables proofs by Perfect Induction become lengthy.
*NOTE 1:
Once a theorem is proved it can be used to prove further theorems in the same way axioms can
be used to prove theorems.
*NOTE 2:
Once a theorem is proved its dual theorem becomes proved as well. This is a "meta theorem" or
theorem about theorems.
*NOTE 3:
Each variable in the property list can be substituted by a group of variables. For example, P5.a
states that a.b+a.b'= a, therefore w.y'.(x+z') + w.y'.(x+z')' = w.y', where a=w.y' and b=x+z'.

For n-variables theorems, Finite Induction (or Complete Induction) can be used. This is a
technique where the statement is proved for n = 2, then if the statement is assumed true for n=k it
is proved true for n=k+1. This proves the statement for all n.
Examples:
1. Prove the single variable theorem: a'+ a = 1 (P5aa - Complement).
Using Perfect Induction, we list of all possible cases:

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As expected the result is 1 in all cases. Note that to obtain a' from a, we used axioms 2a and 2b.
To obtain the result for: a'+a = a'ORa we used axiom 5b.
2. Prove the three-variable theorem: a.(b+c) = a.b + a.c (P8a - Distributive Property)
Using Perfect Induction, we list all possible cases:

We used axioms 3a to 5a and 3b to 5b. We note that the last two columns are the same for all
cases, which proves the statement as desired.
3. Prove the two variable theorem: a.b + a.b' = a (P9a - Adjancency)
Method 1: Using axioms and previously proven theorems.
a.b + a.b' = a.(b+b') Distributive (P8a)
a.b + a.b'= a.(1) Complement (P5a)
a.b + a.b'= a Identity (P3.b)

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Method 2: Using Perfect Induction (all possible combinations are calculated)

Note that the two columns for a and for a.b+a.b' have the same value for all possible combination
of values of the variables a and b, which proves the statement.
4. Prove the two-variable theorem: (a+b)'=a'.b' (P11a - DeMorgan)

The last two columns have the same value for all possible combinations of values for the
variables involved which proves the statement to be true.
Note that the dual statement is therefore proved to be true: (a.b)'=a'+b' (P11b)
The DeMorgan theorem has important implications. P11a implies that an AND gate with its
inputs complemented is equivalent to a NOR gate, while P11b implies that an OR gate with its
inputs complemented is equivalent to a NAND gate.
P11a a'.b'= (a+b)'

P11b a'+b'= (a.b)'

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4.2 Simplification using Properties (The Algebraic Method)
Example.
Given the following expression for logic function F, find a minimal expression written as a sum
of products of the logic variables found in the expression.

*Note 1
None, some, many, or all the logic variables can potentially vanish from the final, simplified,
expression.
*Note 2
There is no single approach to select which properties to use or in which order the properties will
be applied.
F = [ w.z'.(x+y')+(x'.z+y).z.w]'

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Observation:
As we mentioned before, there is no standard technique regarding what properties to apply and in
which order. We cannot always be sure that a minimal expression was achieved. As the number
of logic variables increases the technique becomes cumbersome.

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5.1: Different Combinational Logic Function Representations
Important Definitions:
Literal, Product Term, Sum Term, SOP and POS Expressions, Normal Terms:
 A logic variable or its complement is called a Literal.
 A single literal or a logical product of two or more literals is called a Product Term.
 A single literal or a logical sum of two or more literals is called a Sum Term.
 A logical sum of product terms is called a Sum of Product (SOP) expression.
 A logical product of sum terms is called a Product of Sums (POS) expression.
 A product term or a sum term without repeated variables is called a Normal Term.
 If any variable appears more than once, then the term is a Non-Normal Term.
 Non-Normal terms can be converted to either a Constant Term or a Normal Term by
applying properties P3 to P6.
n-Variable Minterms:
 A minterm is a normal product term with n-literals, which is 1 in precisely one row, and
for that row alone, of a truth table.
The Truth Table Revisited:
We will now add to the truth table a column for the minterms and a column for the
maxterms.
We will use as an example the truth table developed for the prime number detector.

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Note that if, for example, the minterm for row #1 X'.Y'.Z is evaluated for the logical values
corresponding to such row (001) its value is 0'.0'.1 = 1. If we substitute in the minterm the
logical values of any other row its value will be 0. Therefore, the minterm X'.Y'.Z is 1 only for
exactly one row of the truth table.
Note that if, for example, the maxterm for row #1 X+Y+Z' is evaluated for the logical values
corresponding to such row (001) its value is 0+0+1' = 0. If we substitute in the maxterm the
logical values of any other row its value will be 1. Therefore, the maxterm X+Y+Z' is 0 only for
exactly one row of the truth table.
Canonical Sum of Minterms
As we mentioned, minterms can be used to give an algebraic formulation of logic functions
defined by truth tables. This is achieved by formulating the logic function as a logical sum of all
minterms that correspond to values of 1 in the truth table for the logic function. This is also
known as the canonical sum of minterms. In our example this corresponds to minterms of rows
1,2,3,5,7.
F(X,Y,Z) = X'.Y'.Z+X'.Y.Z'+X'.Y.Z.+X.Y'.Z+X.Y.Z
Note that for each combination of bits that corresponds to a prime number only one of the
product terms will be 1 and therefore the sum will be 1 as needed. This SOP algebraic expression
defines the same logic function as the truth table.
List of Minterms
The above expression can be summarized as a list of all the minterms that are to be summed.
F(X,Y,Z) = ∑m(1,2,3,5,7)
Canonical Product of MAXTERMS
As we mentioned, maxterms can be used to give an algebraic formulation of logic functions
defined by truth tables. This is achieved by formulating the logic function as a logical product of
all MAXTERMS that correspond to values of 0 in the truth table for the logic function. This is
also known as the canonical product of MAXTERMS. In our example this corresponds to
MAXTERMS of rows 0,4,6, that is, the rows that are not listed for the minterms.
F(X,Y,Z) = (X+Y+Z).(X'+Y+Z).(X'+Y'+Z)
Note that for each combination of bits that corresponds to a prime number all the sum terms in
the product will be 1 and therefore the product will be 1 as needed. Recall that the MAXTERMS
are 0 only for the combinations of bits of non-prime numbers 0, 4, 6.
This POS algebraic expression defines the same logic function as the truth table

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List of Maxterms
The above expression can be summarized as a list of all the MAXTERM that are to be
multiplied.
F(X,Y,Z) = π (0,4,6)
Relationship between minterms and MAXTERMS
The lists of minterms and MAXTERMS both describe the same logic function.
F(X,Y,Z) = ∑m(1,2,3,5,7) = π (0,4,6)
A MAXTERM can be obtained by complementing the corresponding minterm and then applying
DeMorgan.
Summary of Logic Function Representations
 Truth Table
 List of Minterms
 Canonical Sum of Minterms
 List of MAXTERMS
 Canonical Product of MAXTERMS

6.1: Combinational Circuit Analysis

From a given Logic Circuit or Diagram we determine its function or operation by finding a Truth
Table or a Logic Expression, which relates the circuit output to the circuit inputs. One of the
techniques to obtain a functional description of the circuit output based on the circuit inputs
consist in propagating the logic signals as they go through the different gates until they reach the
output. After we obtain a functional description and/or a truth table, the circuit can be further
manipulated.

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7.1: Combinational Circuit Synthesis
After a truth table or logic function is developed based on a given word problem (design stage)
we need to synthesize an actual logic circuit using either discrete gates or other components such
as, decoders, multiplexers, programmable logic arrays, FPGAs, etc. This synthesis can be done
using HDL (hardware description languages), other simulation software packages or by hand.
After a truth table or logic function is developed based on a given word problem (design stage)
we need to synthesize an actual logic circuit using either discrete gates or other components such
as, decoders, multiplexers, programmable logic arrays, FPGAs, etc. This synthesis can be done
using HDL (hardware description languages), other simulation software packages or by hand.

Example:
We continue using our example of the prime number detector for numbers between 0 and 7. We
previously did synthetize this circuit by inspection looking system truth table.
One possible formal approach to obtain a Logic Circuit from a Truth Table consist in:
Write the canonical sum of minterms or canonical product of MAXTERMS.
Minimize and/or manipulate the algebraic expression to obtain your circuit.
This can be done using properties, graphical methods (K-maps: to be seen later), software
packages or an algorithmic approach (McCluskey).
1. Canonical Sum of Minterms from Truth Table (as previously obtained)

2. Minimization using properties

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This is the “minimal” expression obtained using this particular property applied to these terms in
this order. Note that the final expression is not as thoroughly minimized as the one that we
previously obtained by inspection, which underscores the heuristic characteristic of this method.
In order to further simply this expression we can resort to an algebraic trick by adding a term that
when combined with Z gives Z again, that is: Z+X’.Y.Z = Z.(1+X’.Y) = Z.(1) = Z, therefore:
F(X,Y,Z) = Z+ X’.Y.Z +X’.Y.Z’ we now combine the last two terms using P8a
F(X,Y,Z) = Z+ X’.Y.(Z + Z’) = Z+ X’.Y.(1) = Z+ X’.Y which after P8a, P9a and P3b gives the
result
F(X,Y,Z) = Z+ X’.Y we now have the same result previously obtained by inspection.
Minimization by using properties is a heuristic technique and thus there could be many avenues
to a result, which could be, or not, a minimal expression. This calls for a more thorough, and
simpler, application of P9a, through a graphical method called Karnaugh Maps, to be introduced
in the next module.

8.1: Additional Logic Functions (XOR, XNOR)

Truth Table definition of the Logic Function XOR (exclusive-OR):

Note that exclusively one condition, X or Y, have to be true in order for the output to be true.
The algebraic definition can be based on the canonical sum of minterms:

Schematic representation for the Logic Gate XOR (exclusive-OR):

Note that both inputs must be different for the output to be a logical 1.
Truth Table definition of the Logic Function XOR (exclusive-OR):
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Note that exclusively one condition, X or Y, must be true for the output to be true.
The algebraic definition can be based on the canonical sum of minterms:

Schematic representation for the Logic Gate XOR (exclusive-OR):

Note that both inputs must be the different for the output to be a logical 1.
Truth Table definition of the Logic Function XNOR (exclusive NOR):

Note that both conditions, X and Y, must be the same for the output to be true.
The algebraic definition can be based on the canonical sum of minterms:

Schematic representation for the Logic Gate XNOR:

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Note that both inputs must be the same for the output to be a logical 1.
Properties:
 X ⊕ Y’ = (X ⊕ Y)’
 X⊕0=X
 X ⊕ 1 = X’
 X⊕Y=Y⊕X
 Z)⊕ (Y⊕Z = X ⊕ Y)⊕(X
All can be readily proven by using the algebraic definition or by perfect induction.

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9.1: Circuit Manipulations
From a two level AND-OR implementation to a NAND-NAND implementation.
Example:

Place inverting bubbles at the tip of your first level AND gates and compensate by cancelling
them out by placing inverting bubbles at the input of the OR gate. You may also substitute the
Inverters for NAND gates with the inputs tied.

Note that, due to DeMorgan, an OR gate with its inputs complemented is equivalent to a NAND
gate, therefore we obtain a circuit with all NAND gates.

Observation:
An Inverter gate can be implemented by a NAND gate with the inputs tied. This can be seen
applying DeMorgan to the output of a NAND gate with its inputs tied and then applying P6a.

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From a two level OR-AND implementation to a NOR-NOR implementation.
Example:

Place inverting bubbles at the tip of your first level OR gates and compensate by cancelling them
out by placing inverting bubbles at the input of the AND gate.

Note that, due to DeMorgan, an AND gate with its inputs complemented is equivalent to a NOR
gate, therefore we obtain a circuit with all NOR gates.

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An XOR gate can be implemented with four NAND gates
We start with the XOR gate algebraic definition with a SOP structure:

We could be tempted to use the previous developed method for converting a two level AND-OR
implementation to NAND-NAND. In this case this would require five NAND gates due to the
required Inverters.

We introduce an algebraic “trick” adding 0 valued terms to the logic sum, followed by
application of DeMorgan and finally using the previous methodology to convert AND-OR to
NAND-NAND in order to achieve an implementation with only four NAND gates.
X ⊕ Y = X’.Y + X.Y’ = X’.Y + Y’.Y + X.X’+ X.Y’ = (X’+Y’).Y+X.(X’+Y’) = (X.Y)’.Y+X.(X.Y)’

We now apply the usual procedure implementing the sum of product expression obtained above through a
AND-OR logic circuit and then converting to NAND-NAND.

We finally obtain a four NAND gate implementation of an XOR gate.

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