/**

* lib.sv
*
* RISC-V 32-bit Processor
*
* ECE 18-447
* Carnegie Mellon University
*
* This is the library of standard components used by the RISC-V processor,
* which includes both synchronous and combinational components.
**/

/*----------------------------------------------------------------------------*
* You may edit this file and add or change any files in the src directory. *
*----------------------------------------------------------------------------*/

// Force the compiler to throw an error if any variables are undeclared

`default_nettype none

/
*----------------------------------------------------------------------------------
----------------------------------
* Combinational Components

*----------------------------------------------------------------------------------
----------------------------------*/

module counter
#(parameter WIDTH=32)
(input logic [WIDTH-1:0] D,
input logic reset_n, clk, up, en, load,
output logic [WIDTH-1:0] Q);

always_ff @(posedge clk, negedge reset_n) begin

if(!reset_n) Q <= 0;
else if(load) Q <= D;
else if (en) begin
if(up) Q <= Q + 1;
else Q <= Q - 1;
end
else Q <= Q;
end

endmodule: counter

/**
* Selects on input from INPUTS inputs to output, each of WIDTH bits.
*
* Parameters:
* - INPUTS The number of values from which the mux can select.
* - WIDTH The number of bits each value contains.
*
* Inputs:
* - in The values from which to select, packed together as a single
* bit-vector.
* - sel The value from the inputs to output.
*
* Outputs:
* - out The selected output from the inputs.
 **/
module mux
#(parameter INPUTS=0, WIDTH=0)
(input logic [INPUTS-1:0][WIDTH-1:0] in,
input logic [$clog2(INPUTS)-1:0] sel,
output logic [WIDTH-1:0] out);

assign out = in[sel];

endmodule: mux

/**
* Shifts input 1 by input 2, can be left or right
*
* Parameters:
* - WIDTH The number of bits each value contains.
*
* Inputs:
* - in1 The value to be shifted
* - in2 Number to shift by
*
* Outputs:
*
* - leftShift value shifted left
* - rightShift value shifted right
* - leftShiftArith value shifted left arith
* - rightShiftArith value shifted right arith
**/
module shifter
#(parameter WIDTH=0)
(input logic [WIDTH-1:0] in1,
input logic [WIDTH-1:0] in2,
output logic [WIDTH-1:0] leftShift,
output logic [WIDTH-1:0] rightShift,
output logic [WIDTH-1:0] rightShiftArith
);
assign leftShift = in1 << (in2 & 'b11111);
assign rightShift = in1 >> (in2 & 'b11111);
assign rightShiftArith = (in1[31]) ? ((in1 >> (in2 & 'b11111)) | ('hFFFFFFFF <<
('d32 - (in2 & 'b11111)))) :
in1 >> (in2 & 'b11111);
//assign rightShiftArith = (in2&'b11111);
//assign rightShiftArith = ('hFFFFFFFF << ('d1056 - in2));
endmodule: shifter

/**
* Adds two numbers of WIDTH bits, with a carry in bit, producing a sum and a
* carry out bit.
*
* Parameters:
* - WIDTH The number of bits of the numbers being summed together.
*
* Inputs:
* - cin The carry in to the addition.
* - A The first number to add.
* - B The second number to add.
*
* Outputs:
* - cout The carry out from the addition.
 * - sum The result of the addition.
**/
module adder
#(parameter WIDTH=0)
(input logic cin,
input logic [WIDTH-1:0] A, B,
output logic cout,
output logic [WIDTH-1:0] sum);

assign {cout, sum} = A + B + cin;

endmodule: adder

/
*----------------------------------------------------------------------------------
----------------------------------
* Synchronous Components

*----------------------------------------------------------------------------------
----------------------------------*/

/**
* Latches and stores values of WIDTH bits and initializes to RESET_VAL.
*
* This register uses an asynchronous active-low reset and a synchronous
* active-high clear. Upon clear or reset, the value of the register becomes
* RESET_VAL.
*
* Parameters:
* - WIDTH The number of bits that the register holds.
* - RESET_VAL The value that the register holds after a reset.
*
* Inputs:
* - clk The clock to use for the register.
* - rst_l An active-low asynchronous reset.
* - clear An active-high synchronous reset.
* - en Indicates whether or not to load the register.
* - D The input to the register.
*
* Outputs:
* - Q The latched output from the register.
**/
module register
#(parameter WIDTH=0,
parameter logic [WIDTH-1:0] RESET_VAL='b0)
(input logic clk, en, rst_l, clear,
input logic [WIDTH-1:0] D,
output logic [WIDTH-1:0] Q);

always_ff @(posedge clk, negedge rst_l) begin

if (!rst_l)
Q <= RESET_VAL;
else if (clear)
Q <= RESET_VAL;
else if (en)
Q <= D;
end

endmodule:register