Electronics Quantum 1st Year

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1-2J (Sem-1& 2) Semiconductor Diode
PART-1
1UNIT
Semiconductor Diode
Semiconductor Diode: Depletion Layer, V-I Characteristics,
Ideal and Practieal Diodes, Diode Equivalent Cireuits.
Questions-Answers
Long Answer Type and Medium Answer Type Questions
Que1.1.Explain semiconductor diode and also draw its

CONTENTS equivalent circuit.
Answer
Part-1 Semiconductor Diode : Depletion... 1-2J to 1-6J
Layer, V-I Characteristics, 1. A diode is an electrical device allowing current to flow only in one direction
Ideal and Practical Diodes, (forward bias) with far greater ease than in the other direction
Diode Equivalent Circuits (reverse bias).
2. The most common type of diode in modern circuit design is the
Part-2 Zener Diodes Breakdown ************************* 1-6J to 1-8J semiconductor diode (p-n junction).
Mechanism (Zener and Avalanche)
3. Adiode is a two-layer semiconductor consisting ofp-type semiconductor
************************
1-8J to 1-21J material and n-type semiconductor material the equivalent circuit of
Part-3 Diode Application : Diode.. diode is shown in Fig. 1.1.1.
Configuration, Half and Full
Wave Rectification
Switch
Part-4 Clippers, Clampers. . 1-22J to 1-31J
A -oB 4- OB
Part-5 Zener Diode as Shunt Regulator, Diode aymbol Equivalent circuit
Voltage-Multiplier Circuits.********** 1-31J to 1-37J
Fig. 1.1.1
Part-6 Special Purpose Two Terminal ***********
1-37J to 1-40J 4 In an equilibrium, p-n junction, the free electrons from the n-type region
Devices: Light Emitting Diodes, will diffuse across the junction to the p-type side where they will
Photodiodes recombine with some of the holes in the p-type material. Similarly,
holes will diffuse across the junction in the opposite direction and
Part-7 : Varacter Diodes, Tunnel Diodes, recombine.
.... 140J to 1-463
Liquid-Crystal Displays 5. The recombination of free electrons and holes in the vicinity of the
Junction leaves a narrow region on either side of the junction that
contains no mobile charge. This narrow region which has been depleted
of mobile charge is called the depletion layer.
Diffusioninofthe
(donors)
electrons into the p-region will leave positively charged ions
n-region.
7
Similarly, diffusion of holes near the p-n interface in the n-type region
leaves fixed ions (acceptors) with negative charge.
1-1J (Sem-1& 2)
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1-3 J (Sem-1& 2) 14J (Sem-1 &2)
Eerg Dome an Semiconductor Dode
their neutraity and become In practical, small current ofthe
The regwtas Teary
the p-n interlaces lose 3 a
order of pA lows in the circuit due
cer get ormng thte epace charge region or depletion layer. minority carriers. This is known as revere current. The revere current
is shown in Fig. 1.2.1.
D-1YpE
mA)
30
25 Forward bias reyion
Migrated 201 Ge Si
holes
fron p-type
15
10
Potentiel barrier / Contact
51 0.3/0.7
potentia IVkGe) VKSi)
V_Si) 5pA
10 pA
Reverse bias region I (Si)
Fig L12.p junction semiconductor.
vGe) lA
.Ge
TYos seer ztion od charyes causes en electric fielid extend across to the
sepietne leyer A preztial iferezce must therefore exist across the Fig. 1.2.1.Volt-ampere characteristies ofp-n junction.
cepiveice ayer.
As the reverse bias is increased from zero, the reverse current quickly
ue 12. Explain the V.I characteristic of p-n junction diode. rises to its maximum or saturation value. The slight increase is due to
impurities on the surface, which behaves as a resistor and hence obeys
Draw well iabelled tharacteristie.
ohm's law. This gives rise to a current called surface leakage current.
AKTU 2016-17, (Sem-I) Marks 05 5. fthe reverse voltage is further increased, the kinetic energy of electrons
becomes so high that they knock out from the semiconductor atoms. At
Anewer this stage, breakdown of junction occurs and there is a sudden rise of
Forward hias: reverse current. Now the junction is destroyed completely.
o e torward ias dapa junction,p-type is connected to the positive 6. Thus, p-n junction diode is one-way device which offers a low resistance
e r i t s w e the rtype w gaive terminal of battery. when forward biased and behaves like an insulator when reverse biased.
Thus, it can be used as a rectifier i.e., for converting alternating current
Tre yoraiz. e tn vared wi penia divider. At some forward voltage
into direct current.
V hs i n u7
YSor Si
the povential harrier is eliminated and
urrtars This vuitage is known as threshold or knee
fwir4 Que 1.3. Sketch and explain ideal and practical V-I
characteristics of ap-n junction diode.
The eorard vwiage applied inereases beyond
urwart r e t s rises expnentially as shown in Fig. 1.2.1.
threshold voltage, the
Answer
eyy a erain zie vaiue. 1 produces an extrernely large current
A Ideal V-I characteristic
wu 1y tesry the junsoion due to overheating.
1. An ideal diode is perfect conductor in forward bias and a perfect resistor
everse krias:
in reverse bias.
ia terminal while n-type is
T y vwaueed the teyative
The current-voltage characteristic of the ideal diode is shown in
mtserss v tis yreitive terninal of a battery. Fig. 1.3.1.
tea a, a
jutsan retistae becomes very
2 r t . fywe thrv the cireuit.
high and practicaly
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Electronics Engineering 1-5 J (Sem-1&
Emerging
Domain in 1-6J (Sem-1& 2) Semiconductor Diode
4. The ability of diode to withstand reverse-bias voltage is limited. If the

applied reverse-bias voltage becomes too large diode will experience a
heavy conduction known as breakdown, which is usually destructive.
5. The current versus voltage curve for a real diode looks like as shown in
Fig. 1.3.2.
VR PART-2
Zener Diodes Breakdown Mechanism (Zener and Avalanehe).
Questions-Answers
Fig. 1.3.1. V-I characteristics of an ideal diode.
3. A diode acts as a short circuit when it is forward biased. When it is
reverse biased, it acts as an open circuit.
4. Therefore, an ideal diode acts as unilateral switch. No poweris dissipated
in an ideal diode biased in either direction. Since in forward direction,
ue 14. | Explain the VI characteristic ofp-njunction diode. How
the voltage across the diode is zero and in the reverse direction, the
current through the diode is zero as shown in Fig. 1.3.1.
it is differ
from zener diode? AKTU 2016-17, (Sem-D Marks 07
OR
B. Practical: Explain input and output characteristics of zener diode.
1. In practical, the battery introduced a small offset voltage (V) in forward
biased. The value of the offset voltage is determined by the typeo AKTU 2016-16, (Sem-1 Marks 05
semiconductor used in ap-n junction but cannot be measured direcuy:
AnsweT
A VI characteristic of p-n junction diode : Refer Q. 1.2, Page 1-3J,
Unit-1.
B. Zener diode:
Slope =Rr reverse-biased heavily doped p-n-junction diode which
Zener diode is a of
VB is operated in the breakdown region. Fig. 1.4.1 shows the symbol
zener diode.
V
Slope O Cathode
Anode
Fig. 14.1.Zener diode
2 When a zener diode is forward biased, its characteristics are just same
as the ordinary diode and it is shown in Fig. 1.4.2.
Fig. 1.3.2. current up to
2. The resistor 8. When zener diode is reverse biased then it gives constant
ON/OFF or approximates the semiconductor resistance w h e n diode.
a certain voltage. When the reverse

bias voltage is increased beyond
3
forward bias / reverse bias.
Areverse biased diode o fcurrentcaled
that voltage, the current inereased rapidly as shown in Fig.
1.4.2.
conducts a very small amount or

leakage current.
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4. Zener current is independent of the appied votage. t tepetie vnty

the external resistance.
5. This breakdown is called as zener breakduwn a sauw i Li

This breakdown occurs at low voltage.
+V
Zener breakdown
Avalanche breakdown
Fig. 1.42. V-I characteristic of zener diode. V

VA
The rutT value of voltage beyond which zener diode reverse current
reases rapidy is called zener voltage Vz or breakdown voltage.
The kreakdown or zener voltage depends upon the amount of doping.
A zeDer diode can be used ss a voltage regulator to provide a constant
Tae to a load.
C Difference:
Fig. 1.5.1. The I-V characteristice comparism
P junction diode Zener diode between zener and avalanche brealkdov
The elecricity flows in one The electricity flows in both the i Avalanche breakdown:
denon direction.
Avalanche breakdown takes place in sightly thic~ junctioz zhar t e
Tee reverse bias The bias makes the
reverse zener breakdown case. It means both sides of junction are igimiy àopetL
permanently damages the electricity flow in both the 2. In this case, the electric field across the deplerion region (laver ie um st
Sepletion region direction.
strong to produce zener breakdown for the same appied voltap- D
The width of depletion The width of depletion region is zener breakdown case.
the p narrow because the p and n
e o n is large because 3.
Here, the minority carriers accelerated by the 5eid colide witi he
and reon is lightly doped. | region is heavily doped.
semiconductor atoms in the depletion regon
This is used for rectifcation. | This is used for voltage 4. During collision the kinetic energy of electrozns is transíerred o ozhe
regulation. covalent bonds, thus the energy transferred to covalent bonds increases
Che band energy, hence covalent bonds are broken and elecroz-hole
Qae 15. Explain reverse breakdown of a diode.
pairs are generated.
ABSwer 5. The newly generated carriers transfer their energr o other covalen
bonds and break more bonds and thus extremely large numbers of carriers
Zererse breakdown occur by two
can
breakdowa and avalanche breakdown.
mechanisms that are zener are generated due to cumulative process of avalanche multipicarion
This breakdown is called avalanche breakdown as shown in Fig 1.9.1
Zener breakdown: This breakdown occurs at higher voltages.
i takes place in very thin junction (i.e., depletion layer is narrow due to
eæry doped junctions on both sides).
WDeD a all
reverse bias voltage is applied, a very strong electric field PART3
appruimately 10 Vin) is set up across the thin depletion layer.
Teis seld is esough to break the covalent bonds. This
Diode Application: Diode Configuration, Halfand Full
bonds prouces large number
breaking of covalent Wave Rectification.
of electrons
and holes which constitute the
rerersë saturation curent (i.e.. zener current).
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Electronics Engineering 1-9 J (Sem-1& 2) 1-10 J (Sem-1 & 2) Semiconductor Dide
Questions-Answers
Si
Que 1.6. Explain the series diode configuration.
Answer Fig. 1.6.3. Reversing the diode.

1. The series circuit of diode is shown in Fig. 1.6.1. 5. The diode is in the *OFFP state, resuting in the equivalent cireuit of
The state of the diode is first determined by
Fig. 1.6.4(b).
2 replacing the diode with a
resistive element as shown in Fig. 1.6.2(a). The
resulting direction ofI is 7 Due to open cireuit, the diode current is 0 A and the voltage
resistor R is the following:
across the
a match with the arrow in the diode
symbol and since E> the diode
VR
is in the "ON" state.
R R1, R (0 A)R =0V
=
3. The Vp E
network is then redrawn as shown in Fig. 1.6.206) with the
appropriate equivalent model for the forward biased silicon diode.
K
W
Ip = 0A
Si
E
(a)
Fig. 1.6.1. Series diode configuration.
Fig. 1.64.
4. The resulting voltage and current level are the following:
V=Vx Que 1.7.Determine Vo, and draw the output waveform of the
given network of Fig. 1.7.1.
VR=E-Vx
V 5V Ideal
20 V
DH
V 6.8 k Vo
+V
- - 20 V
0.7
R E Fig1.7.1
RVR AKTU 2015169em-0,Marks0
(a) (b) Answer
Fig. 1.6.2. For V, s5V, the 5V battery will ensure the diode is forward-bissed and
5. In 2. oV-5v.
Fig. 1.6.3 the diode is reversed. Replacing the diode with a resistor 5V
element as shown in Fig. 1.6.4 (a) will reveal that the V5V 5 V= 0V
direction does not match the arrow in the diode resulting current 3. At
symbol. -20 V
-20 V - 5 V= - 25 V
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(Sem-1& 2) 1-12J (Sem-1
& 2) Semiconductor Diode
For V,>5 V, the díode is reverse-biased and Vo = 0.

4
Si
0V 10 V si 6 k Vo
8 kQ
WW
25 V
No Fig. 1.9.1.
Fig. 1.7.2.
Que 1.8. Sketch Vo for given eircuit configuration (Fig. 1.8.1).

AKTU 2016-17(Sem-D,Marks 05
4 V Answer
VO-ww-H -oVo 0.7 V

2.2 kQ
V Si
Si
Fig. 1.8.1. o.7v kn Vo
10 V L
AKTU 2017-18 (Sem-II), Marks 3.5
8 k2
Answer
1. Assume input waveform,
Fig. 1.9.2.
AV
0.7 V 0.1167 mnA
5 V
Fig. 1.8.2.
I6kn
Vo 0.7V
2. For positive half cycle. Diode is in ON state. Voltage across 8 k2, applying KVL in loop L
Vo = 0.7 V -V+10 V-0.7 V- 0.7 V=0
3. For negative half cycle. Diode is in OFF state. V = 8.6 V
Vo -4+ V, =-4 -5=-9V We have, 8.6 1.075 mAA
4. Output waveform as shown in Fig. 1.8.3.
AVo
IR8k
I=11 = 1.075 mA
0.7VA Apply KCL at node A, I, =1, -1, =

1.075 mA-0.1167 mA
9 V I= 0.96 mA
Fig. 18.93. ue 1.10,
Explain the working of half wave and full wave bridge
Que 19. For the circuit shown in Fig. 1.9.1, determine 7,12, 1, rectifier.
Vo
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OR
rectifier with elear diagram. . Center-tap rectifier:
plain the bridge
AKTU 2017-18(Sem-D, Marks 3.5 D
OR
Draw the cirvuit and diseuss the working of ull wave bridge reetifier
with suitable input-utput waveform.
Input O-
AKTU 2016-17(Sem-D, Marks 05 AC voltage Vo

220 V O
50Hz
Answer
Half wave rortifier: It is shown in Fig. 1.10.1. As the name
signifies
ny halt portion of input is rwctifiwd teither positive half or negative hald.
Only single diode and a stop down transtormer are required for this
cinruit
Da
Fig. 1.10.3. Full wave rectifler.
1. In center-tap full wave rectifier cireuit, diode D, will be ON for positive
AC
input o- half eyele (ie., Oto n) and the diode D, will be OFF during this cycle.
220 V v-VsinotR 2. The diode D, will be ON for negative half cycle (i.e., n to 2r) while the
diode D, will be OFF during this cycle.
3. The input and output waveforms are shown in
Fg. 1.10.1. Half wave rectifiercireuit Fig. 1.10.4.
ot (a)
(a) A2T 4
2
DC (V
output
voltage (V
N.
(V
Vpc (b)
ot
(b) 2T
2n ot Fig 1.10.4. (a) Input waveform (6) Output waveform.

Fig 110.2. () Input voltago (6) Output voltage
Bridge rectifier: As shown in Fig.1.10.5(b) only diodes D, and D, are
B. Full wave roctifier : This circuit gives the output for full cycle (i.e., for cve during positive half cycle while diodes D, and D, are active for
both positive and negative half eycles). "There are two types of circuits egative half cycle as shown in Fig. 1.10.5(c) and Fig. 2.10.5(d) shows
used for it the total
output with the active diodes for a particular cycle.
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Electronics Engineering 1-15J (Sem-1&2 1-16J (9em-1 & 2) Semiconductor Diode
OR
Explain the operation of full wave hridge rectifier with the help of a
circuit diagram.Also sketoch the input and output waveforma. Define
AC
its PIV. Also derive its ripple factor and rectification efficiency.
No
Input
voltage
220 V
50 Hz
D
a) ,A OR
AKTU 2017-18 Bem-1D,Marke 07
Draw the circuit and discuss the working of full wave bridge rectifier
with suitable input-output waveforms. What is PIV of bridge
A rectifier ?
AKTU2016-17(Sem-D, Marko07
D A Answer
Half wave rectifier:
A
b)
. Operation: Refer Q. 1.10, Page 1-12J, Unit-1.
No Vo i. PIV
L
D
LA 1.
2.
Aswe
know during negative half cycle, diode will be reverse biased and
there will be no output voltage.
In the negative half cycle the voltage across diode will be maximum
D3 when input reaches to its maximum value Vm This maximum voltage
(c) during negative halfcycle is called as the peak inverse voltage (PIV).
3. PrV for half wave rectifier is given by
PIV= V,"
N ii. DC voltageand DC current:
Suppose current in load
Da
sin øt 0S t ST ...(1.11.1)
DA TS ot s 2n
2T ot Here, Peak value of current iz
Fig. 1.10.5. (a) Basic bridge rectifier circuit V
(6) Output of bridge rectifier for positive half cycle.
(c) Output of bridge rectifier for negative half cycle. DC voltage for half wave rectifier,
(d) Output for full cycle,
Vpc=Ipc x
RL
Vc x R,
Que 1.11.|Explain the following terms in context with half wa
rectifier and full waverectifier: VIC= 7 .1.11.2)
DC voltage and DC current
ii. RMS value of current .(1.11.3)
iv. RMS value of
OR
For a half wave rectifier, derive an expression for ripple factor. The currenat:
value
rms
of the current flowing through the load is given as
AKTU 2015-16(Sem-1D, Marks15 I ms

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Electronics
Engineering 1-17.J (Nom-1& 2)
Domain in
Emerging
. MN value of ourronti
ofi, from eq.

(1.11,1D
value
2. Replacing the
cos2
2
ofdint) ot)- t i n 2
2 2 2
sin 2»|
2n x 2 2la
2 .1.114) Hi. PIV (Poak Inverse Voltage)i lt in namo aa the hult wave rectifier, but
Eq. (1.11.4) gives total current (AC and DC). the value of PIV in difforont for contor-tap (ypo fiull wave rectifier.
3.
4. Thus instantaneous value of AC in output is, In centre-tap full rectifiera, PIV
wave
2V,,
Inbridge 4ypo full wnve roetifiorn, PIV V,
1
Ac IneY dot) iv. DCvoltago und DC ourront:
' duot) win ot dtot)

2,
+ e 2 1e
ac .- 1.11.6)
v.Ripple factor: The ripple factor is given as

V 2 R 2
r =acme = v. Ripplo faotor:
Since, rms 2 and Ipc=I,/n. So, r =1.21 r ACcme

vi. Rectification efficiency: The efficiency is given as
n= Output DC power Ppc r0.482

Input AC power PaC (R, +r) vi. Rootification ofricionoy:
where, R,> load resistance, r-> diode resistance
(21,/ R,
P A /V2¥r, +
R,)
x 100 %
/2 +R,)
= 81.2 %
n = 0.406 (ra«R)
(r«R,)
40.6 % Que 1.12. Diforontiute botweon hulf wave and full
B. Full wave rectifiers: wave rectifiers.
Operation and waveforms of full wave bridge reotifieri
AKTU 2015-16(Sem-D, Marks 05
Refer Q. 1.10, Page 1-12J, Unit-1
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AnswerT 2.2 koV,ms

Full wave rectifier
ca 2.2k 2.2 ka
S.No. Half wave rectifier
1. Full wave rectifier is an AHalfwave rectifier is an electronic
electronic circuit which circuit which converts only one-half F'or negative
half eyele of V, :
converts entire eycle of AC of the AC cycle into

intopulsating DC.
pulsating DC.
ON diode
2 Full wave rectifier, is bi- The Half wave rectifier is
directional, it conducts for unidirectional; it means it will allow
positive half a s well as the conduction in one
direction only. 2.2 k
negative half of the cycle.
Pig1.18.8
3. Peak inverse voltage (PIV) Peak inverse voltage (PIV
is the
the 2.2 k) resistor acting aN a load in tlhe wame
is twice of the maximum maximum value of supplied input. Polarity of V,across
value ofsupplied input. Using voltage divider rule.

2.2 k2(,A
Ripple factor is high.
4. Ripple factor is low. chmax 2.2 k 2.2 ko
100 2 V)-0V
for the network of Fig. 1.13.1, and
Que1.13.| Sketch Vo» Vpc I
0.636 Va= 0.636 (B0 V)
=
31.8V
determine the peak inverse voltage of each diode.

AVo
50 V
311.8 V
100 V
V Ideal diodes * V Pig1.18.4
100 V
2.2 k
2.2 k
ofeach diode V,,
=
2.2 k Peak inverse voltage

waveform for the given network
- 100 V Que 1.14.Determine the output
DC level and compute
Fig. 1.13.1. 1.14.1. Determine the output
asshown in Fig.
2015-16(Sem-I),
Marks 05 PIV for ench diode.
AKTU
10 V
Answer 2ks
For positive
half-cycle of V,:
2k 2k
ON diode
Vo2.2k 2 . 2 ka P L14.
N Marks 07
2.2k AKTU2017-18(em 11),
Fig. 1.13.2
rule and
we get,
divider
Using voltage
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Answer
For positive half-cycle of V,: PART-4
ON diode Clippers, Clampers.
Vo 2 kQ Questions-Answers
2 ko
Que 1.15. Draw a simple clipping cireuit with suitable waveform
O
Fig. 1.14.2. and explain types of clippers.
Using voltage divider rule, Answer
A Clipping circuit:
VOmax 22k0+2k2
k2Vm-! ' (10v) =5V A wave shaping circuit which controls the
shape of output waveform
by removing (clipping) a portion of the applied wave is known as
For negative half-cycle of V,: circuit. For
a clipping circuit at least one
clipping
resistance and one diode are
ON diode required.
B. Types of clippers: There are mainly two types of clippers i.e., positive
and negative clippers.
They are further divided into two categories:
2k Series clippers (for ideal diode):
2 ka a.
Simple series clippers:
2 k2 Positive
K
Vo
Fig. 1.14.3.
Using voltage divider rule,

t R
Omax2 kn
2 kQ+2k2
vma
2
=(10)=6V (a)
3.18V Negative
DC0.636 VOmax 0.636 (5 V)
= =
No
Vo
5 V V R Vo
- - Vpc
3.18
(6)
Fig.1.16.1.
Fig 1.144.
Peak inverse voltage of each diode = Vm 10 V
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a d series clippers:
Positive b. Biased parallel clippers :
Wo Positive
W-
R So
o
(a
o
R
- V-
o
Negative
Vot U
R o Negative
(c)
Vot V
RS Vo W-
(d o
Vo
Fig. 1.15.2
Parallel clippers (for ideal diodes): Fig. 116.4
Simple parallel clippers: C.
Combination clipper (Positive
Positive and Negative):
No R
AM
Vo
Wegative
a)
VTT
Fig. 1.15.5.
ue 1.16. What do you
different types
mean by clamper circuit ? What are the
of clamper ciruits?
6)
Pi-113.3
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Answer
Nogative clnmper with bias
A (lampercirvuit:
A elamping circuit ix a deviee that 'elampe' n nignal to a ditforont
level A clanmpingeirruit must huve a diordo, n rosintance andn caphe.
AVo
an independent 1Mi supply is nlso required to introduee an udditiou
shi. onal
B.Types of clampor cirouit: Thoro are Lwo
typon of elumpor cireuitu
1. POsitive Clamper: lt shilts the original nignul in vortienl upwurd
direction.
Vo
fin: V
Qutput ine ()
Fig. 1.16.4. (a) Negative clamper with positive bias,

Fig. 1.16.1. Positiveo clampor. (b) Negntivo clamper with negative bias.
Output voltage Vo V+ V. =Vm + V =2V,
Positive clamper with bia8 Que 1.17. Sketch V, for each network of Fig. 1.17.1, for the input
shown.
A Vi C
120 V
Si
20 V
ER Vo
() Fig. 1.17.1.
Fig. 1.16.2. (a) Positive clamper with positive biused,
6) Positive clamper with negative biased.
Negative clamper: It shifls the original signal in vortical downwon
direction. OR
Bketch the output for
given clamper circuit with shown
Fig. 1.17.1. input in
V.
o AKTU 2017-18(Sem-1D, Marks 3.5
Answer
Fig. 1.16.3.
-o
UE F'or positive
half
120 V 20 V 0.7 cycle capacitor charges to peak value of
V =99.3 V with
Vo 20 V+ 0.7 V polarity (+ 4E -). The output
=
20.7 V.
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2. For next negativehalfeycle VoV,-99.3 V with negative peakvalue
Vo -
120 V- 99.3 V=-219.3 V.

Vo + 10- 0.1 F Si
20.7 V
1 R56 k vo
2V
0 -99.3 V
-10 f1 kHz
Fig. 1.19.1
-219.3 V-
AKTU 2017-18 (Sem-D, Marks 3.5
Fig. 1.17.2.
Answer
Que 1.18. Design a clamper to perform the funetion indicatedi
Fig. 1.18.1.
t RC (56 k2) (0.1 F) =
5.6 ms
Vo 30V 5t 28 ms
20 V . 5t 28 ms >> =0.5 ms,
V Vo
T2 0 . 5 T 5 6 : 1
- 10 V ii. Positive pulse of V
- 20 V Diode ON' and Vo-2V+0.7 V= -1.3 V
Fig. 1.18.1
AKTU 2016-17(Sem-ID), Marks 6.2 Capacitor charge to 10 V+2V-0.7 V= 11.3 V
Negative pulse of V
Answer Diode OFF' and
V= -10 V-11.3 V= -21.3 V
C
+0 -O+
R Vo -1.3 V
10 V
-21.3 V
Ng. 118.2.
During positive half cycle: Fig. 1.192
Vo=V,+Vc+(-10) = Vm+Vm -10 = 20+ 20-10 =30 V
Que
During negative half cycle:
the
120.Define clipper circuit. Sketch the output waveform
circuit shown below for
Vo-10V given input.
Que 1.19.Determine v, for the circuit shown in Fig. 1.19.1
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Emerging Domain
in Electronics Engineering 1-29 J (Sem-1& 2) & 2) Semiconductor Diode
1-30 J (Sem-1
10 kQ
+0 wM- I=n0.7-5.3 10-6 0.4 mA (Peak).
Vi 10 kQ 10 k2
ii. During negative half cycle of V,:
10 V 1. When 7V< V, <0, both diodes will be reverse biased so output will
V follow input voltage i.e., Vo=V
Vo 2. When V <-8 V, then D, will be reverse biased and D, will be forward
-10 v
5.3 V 7.3 v biased
So, Vo-(0.7 + 6.3) = -8 V (constant)
For Vin-10 V
-o-
,=in0.7+ 7.3 -10+8
Fig. 1.20.1 10 k2
10 k2
-0.2 mA.
AKTU 2017-18(Sem-ID, Marks 07 3. The waveforms for V and I are shown in Fig. 1.20.2.
Answer Que 1.21. Explain the function of the cireuit of Fig. 1.21.1 and draw
A Clipper: Refer Q. 1.15, Page 1-22J, Unit-1. the output waveform.
B. Numerial: R
During positive half
cycle of V;: ww
1 When 0< V, <6V, then both diode 2.
D,
output will follow input voltage.
and D, will be reverse biased and 9
ie., VinD 15 sin (oL)

Vo)
Z. When V>6V, then D, will be forward biased and D, will
be reverse biased.
So, Vo 0.7+ 5.3 = 6 V (constant)
3. Fig. 1.21.1.
The current i
forward biased.
will flow only when either of the two diodes will be
4V
AKTU 2015-16(Sem-I), Marks 7.5
+10 v
Answer
1. During positive half cycle:
-10 V- Case-1: When Vin6 V
Diode A and B, both are reverse biased
Vo
+10
ii Case-2: When Vo
V>6
Diode A is forward biased, diode B is reverse biased
2.
Vo 6V
During negative half cycle:
LO- Case-1: When Vin-9V
Diode A and B, both are reverse biased
.
0.4 mA- Case-2:
Diode
When
A is reverse
biased, diode B is forward biased
0.2 mA Vo-9V
Que 1.22.For the given clamper cireuit shown
Fig. 1.20.2 Fig. 1.22.1, in
4. For Vn 10 VV determine
signal.
the output voltage and also
draw the waveform of
output
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Engineering 1-31 J (Sem-1&2 Semiconductor Diode
1-32J (Sem-1& 2)
in Electronics
Emerging Domain
2. The zener diode is selected with V, equal to the voltage desired across
+ 10 the load.
a. Under reverse biased condition, voltage across zener diode practically
remains constant, even if the current through it changes by a large
Ysi5V SR Vo extent.
Under normal conditions, the input current I, = 1, +I, flows through
-15 resistor R. The input voltage V, can be written as
V=1,R+V, = 7 +1)R + V,
Fig. 1.22.1.
R
WWw-
AKTU 2016-17(Sem-1), Marks 05
T
Answer
1. During positive pulse of V, the diode is short circuited. The voltae

across R will be the same as across the battery (parallel).
R
So,
Vo 5V
2. The voltage that charge up the capacitor, applying KVL Fig. 1.23.1. Zener voltage regulator.
+10V- V.-5V 0, then V. 5V= =
5. When the input voltage V, increases, as the voltage across zener diode
3. During negative pulse of V, the diode is open circuited. Applying kVL remains constant, the drop across R will increase with a correspondingg
Vo-15-5=-20V increase inI, +I,.
Vo 6. As Vis a constant, the voltage across the load will also remains constant
and hence,I, will be a constant.
5V 7. Therefore, an increase in I, +I, will result in an increase inI, which will
not alter the voltage across load.
Thus, zener diode is used as a voltage
regulator.
8. To operate zener diode as
voltage regulator, the reverse voltage applied
to zener diode never exceeds PIV of the
diode and at the same time, the
-20 V applied input voltage must be greater than the breakdown
the zener diode. voltage of
Fig. 1.22.2.
Que 1.24
PART-S . Find the range
of R, andI, that will maintain a constant output
Zener Diode as Shunt Regulator, Voltage-Multiplier Circuits of 10 V
(Fig. 1.24.1).
ii. Also determine the maximum
for given circuit.
wattage rating of the zener diode
Questions-Answers
R
Long Answer Type and Medium Answer Type Questions V50 V V,-10 v
o-
Maad32 mA
Que 123. How zener diode is used as shunt regulator? Explat Fig. 1.24.l.
Answer
AKTU 2017-18(Sem-ID, Marks 07
1. The circuit diagram for hown
zener
voltage/shunt regulator circuit 1s s
Fig. 1.23.1.
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Frnyitz *main in Electronica Engineering 1-33 J (Sem-1&
1-34J (Sem-1&2) Semiconductor Diode
Answer
20
1. We have I 16.67 mA
iven:1,ma32 mA, V, -10V 1.2 1 0
To Pind:Rarge tf1, and R, mazimum wattage.
2. So, n
Vi min = (R+R).V-220+120020
1200 x 20
P r o n the tirauit,
I=1,+I V.min 23.67 V
where,
V, 50-10 4 0 mA 3. Now, current through Rg
1kn 60 + 16.67 76.67 inA
ma: +L
=
When Iis mininurth, 1, ia maximum and viceversa. 4. So, V maxIRs +Vz =76.67 x 10-3 x220 + 20
Therefur, =iz ma +1,an in+L,max Vmaz 36.87 V
4 1n =2
mA
17, Hence, the range ofV, lies between 23.67 V and 36.87 V
V 10
Que 1.26. For the network of Fig. 1.26.1, determine the range ofV,
Hece FL.mas -1810-
0 *1.25 kn that will maintain V, at 8V and not exceed the maximum power
rating of the zener diode.
R
Therefore, L 40 mA -
5 mA =
35 mA VO WW
82
10
5 mA
285.72 Q V=8V R0.22 k
5 Hente, the range of 1 is between 8 mA and 35 nA while range ofk Zmax400 mW
tetweer 572 a n d 1.25 k.
Mazimum wattaze of zener diode ia,
ara
A 10 =320 10r =0.32 W Fig. 1.26.1
Que 125. Determine the range of V,for the Fig. 1.25.1, that AKTU 2015-16(Sem-D, Marks 05
maintain the zener diode in "ON" state. AnswerI
The procedure is same as Q.
1.25,
Ans. Range is 10.98 V to 15.08 V. Page 1-33J, Unit-1.
220
Que 127.| Describe with the help of circuit diagram
V, 20 V R12ka V working of
voltage tripler.
OR
Fig 1.25. Explain with suitable circuit that how diode acts
multiplier ? as a
voltage
AKTU 2017-18(Sem-), Mar Draw and discuss OR
voltage tripler circuit.
Answer
y- AKTU 2016-17(Sem-I), Marks 05
Given : R, = 2 0 a , V, = 2V, 60 mA, K = 12 n
Answer
ToFind Range f V Fig. 1.27.1 shows a circuit
of
used as a
doubler, tripler and general multiplier i.e., this circuit can be
quadrupler.
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Electronics Engineering 1-35 J (Sem-1&2 1-36J (Sem-1& 2) Ssrmitondutr Dind
in
Emerging Domain
2 Circuit-1 is a Doubler (2V,)

Circuit-2 is a Tripler (3V,) 10. Voltage quadrupler: Taking output across C, and C,
Vo Vc+ V 2Vm + 2V,, = 4V,
Circuit-3 is a Quadrupler (4V).
During positive half cycle, the diode D, is ON and it charges capacitorc voltage multiplier using p-n junction
What is diode 7
3
Lo V
Que 1.28.|
Explain the operation of voltage doublers
4. In the first negative half cycle, the diode D, is ON and it charges C. OR
(V2 V + Vei = 2 V . In this eycle the charge on capacitor ar diagram.
Explain full wave voltage doubler with
starts discharging.
AKTU 2017-18(9em-I), Marks 3.5
5. In the second positive halfcycle
the diode D, and D, are ON, the
C will be charged to V,, and the capacitor C, will be charged to
capaci
Answer
Vca V+-V¢)+Vc2 VV+ 2V 1. The circuit which produces a greater DCoutput voltage than AC input
Vc2Voltageacross C) voltage using a roctifier circuit is called as voltage multiplier.
2. The output of voltage doubler is twice the peak input voltage.
Tpler TBV 2m
Circuit3
3. There are two types ofvoltage doubler eircuits:
.
1
Half wave voltage doubler
Thecircuit diagram is shown in Fig. 1.28.1.
C
Input
from D D, D D,
mains
L Circuit 1 2V,
Ca
2 m
Input Vn D,Y C2 2V Vy= 2V,
Doubler (2V, Fig. 1.28.1. Half wave voltage doubler

2. During positive half-cycle of the input voltage, diode D, is forward biaed
. Circuit 2 i (ON) and diode D, is reverse biased (OFF).
Capacitor (C, chargeä to th:
peak value of secondary voltage V, with polarity.
---Quadrupler
- - - - - -(4V,
-- .
3.
During negative half-cycle, diode is ON while diode
Fig. 1.27.1. General circuit diagram of multiplier. Capacitor C, is charged up to a D, voltage i.e., the
D, is OFF.
of
voltage and the voltage C.
across
sum
peak-supply
6. second are ON.
During negative half-cycle,
voltage across capacitor is given as:
the diode D, and diode D, 4.
During positive half-cycle: Vci Vn =
cVe 2V (V+ Vca Vc V -2V * = +2V,*" VCi VCI Vm

7. Now
C
Voltage across C, -
Vci= V,
Vollage across C Vc2= 2V
>
Voltage C->Ves= 2V,

across
Voltage across C Vca=

8.
2V
>
Fig. 1.28.2
Voltage doubler: Taking output across 5.
C2 During negative half cycle
Vo Vc 2V -
V-Ves Vez= 0
9 Voltage tripler: Taking output across C and C
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Domain in Electronics Engincering 1-37 J (Som-1&2
(Sem-1& 2) Semiconductor Diode
Emerging 1-38 J
-V - V + Ve 0
Ve2 2m Answer
C A LED: LED is a special type of semiconductor p-n junction that under
forward bias emits external radiations in ultraviolet, visible and infrared
regions of electromagnetic spectrum.
D C2 Vo B. Construetion of LED:
1. LED is just not an ordinary p-n junction diode where silicon is used.
Fig. 1.28.3.
Here we use compound having elements like gallium, arsenic and
phosphorus which are semitransparent unlike silicon which is opaque.
ii. Full wave voltage doubler
3. In all semiconductor p-njunctions, some of its energy will be given off as
1 The circuit diagram is shown in Fig. 1.28.4.
heat and some in the form of
2.
During positive half cycle, D, is ON and D, is OFF. Capacitor C, will be photons.
4 In the materials, such as gallium arsenide
charged to a peak value V phosphide (GaAsP) or
gallium
phosphide (GaP), the number of photons of light energy emitted is
D sufficient to createa visible light source.
Recombination Light O/P
C
Vo 2V,m
P
F Depletion Symbol
D CT R
region
Fig. 1.28.4. Full wave voltage doubler.

VcI Vm Vcc
3. During negative half eycle, D, is OFF and D, is ON. Capacitor C,s Fig. 1.29.1
charged to peak value V Thus output voltage with no load connected C. Principle of LED:
The process involves:
Vo VCt Vca Generation of electron-hole pair (EHP)
by excitation of semiconductor.
V2 ii.
Recombination of EHP.
Extraction of photons from the
2. semiconductor.
The characteristic for
|PART-6 LED is given in Fig. 1.29.2.
Special Purpose Two Terminal Devices : Light Emitting Diodes 2
Photodiodes. 10
Questions-Answers
Long Answer Type and Medium
Answer Type Question 0
20 40 60 80 100(mA)
Fig. 1.29.2. Characteristics.
Que 1.29. What is LED? Give its truction
and applications. principle of working, con

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Electronics Engineering 1-39J (Sem-1&z Seniconductor Diode
Emerging
Domain in
1-40J (Sem-1& 2)
D. Working:
the electrona from n-type rnater 6. This dide is designd in auch a m a n n e r that the rays are allowed to fall
forward bias condition, restricd
1 When ILELD is in holeH in thep-type mate unly on ons Eurfare arYAs thEjunction The remaining sides are
and recormbines with eria
cross the p-n junction for the light to penetrate.
takes place, the recombining electrons rel
2. When recombination 1. A the tenperature due t
illumination increases, more and more
the form of heat and light.
energy in
the type of material, i.e.,
electron-hole pairs are generated and resuits in increasing the reverse
3. The emission depends upon aturation current.
(invisible)
GaAs- infrared radiation When light rays fall on depletion wiith 'W,it creastes electron-hole pair
CaP- red or green light(visible) and slectrons are Fwept ints n-region and holes ints p-reion very rapidly.
GaAsP r e d or yellow light (visible). This gives rise to a phuto current. This is the basic principle ofoperation
E Applications: of photodiode.
clocks etc.
Display LEDs like calculator, digital B. Photodiode characteristies
s o u r c e in optical fibre
communication.
2. Light
Light in a source detector package like smnoke detectu
3 source
tachometers, proximity detectors etc.
Que 130.| What is photodiode ? What a r e its different types -Va

Describe the construction of a photodiode with its operation. Increasing light | 10.000 Ln/n|
intensity
Answer 25,00 Lm/n
A
1.
Photodiodes:
Two terminal devices designed to respond to photon absorption Pig. 130.2.
1A
called photodiodes. The Fig. 1.30.2 shows the V-I characteristics
ofp-n junction photodiode
Photodiode is a semiconductor p-n junction device whose operatirn with different illumination level.
2.
limited to reverse bias region. When no light ray is incident, the diode has a small reverse current
3. The types of photodiode are: known as dark current.
3. The dark current is that current which exists
p-n diode only writh
illumination.
no applied
. p-i-n diode
4 The increase in reverse
ii. Avalanche diode voltage does not increase the reverse
significantly because all available charge carriers have alreadycurrent
4. The output current of a reverse biasp-n junction changes wDen a swept across the junction. being
is exposed to illunination. 5. The photodiode can also be
used as a variable
resistor controiled by
5. The variation in the output current is linear with respect to Iun light intensity.
flux. The construction and symbol is shown in Fig. 1.30.1. 6.
Photodiode operates in quadrants, ie., in third
hu
are
negative and power is being delivered to thequadrant, bothI and V
circuit. device from external
7 In fourth quadrant, Vis positive and I is
P from the junction to the
negative and power is delivered
external circuit. In
quadrant operation is preferred. applications, usually third
R
(a) E b) Varacter Diodes, Tunnel Diodes,

PART-7|
Pig. 1.30.I.
Liquid-Crystal Displays
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Semiconductor Diode
Emerging Domain in
Electronics Engineering 1-41J (Sem-1&2) 1-42J (Sem-1& 2)
Varicap characteristics:
Fig. 1.32.3 shows the characteristics of a typical commercially available
Questions-Answers 1.
varicap diode.
We see that there is the initial sharp decline in C with increase in

Long Answer Type and Medium Answer Type Questions 2.
reverse bias.
about 20 V.
3. The normal range of Vp for varactor diodes is limited to
In terms of the applied reverse bias, the transition capacitance is given
Que 131. Explain input and output characteristics of varactor approximately by
k
diode.
AKTU2015-16(Sem-), Marks 06 C V+VR
where k = Constant determined by the semiconductor material and
Answer
construction technique
1. This is also called as varicap, VVC (voltage variable capacitance),or Knee potential
tuning diode. Magnitude of the applied reverse bias potential
2 This isconstructed from semiconductor materials. It is simply a voltage n = 1/2 for alloy junction = 1/3 for diffused junction
dependent variable capacitor. CHpF)
100
s0
e 60
W 40
Depletion region K
20
holes electrons - 10 - 12
Fig. 131.1. Fig.1.31.3

In terms of the
3 Fig. 1.31.1 shows the varactor diode in reverse-bias condition and symbol capacitance at the zero-bias condition C10), the capacitance
as a function of V is given by:
of varactor diodes.
CC0)
If V larger, then W-> wider
V-> smaller, then W-> narrower CR -V/Vr
4. The depletion region Win this case acts like an insulator preventing the
conduction between the n and p region of the diode, just like a dielectr Que 132.Explain working and characteristics of Tunnel diode
which separates the two plates of a
capacitor. with the help of neat diagram.AKTU 2015-16(Sem-D,
5. Let area of plates = A
If distance between two OR
Marks 05
capacitor plates W =
Discuss the construction and

then A its 1-V working of tunnel diode. Also sketch
capacitance, C 6.
W
=
characteristics and explain.
where Permittivity of the semiconductor materials.
e =
AKTU 2017-18(Sem-ID, Marks 07

OR
xplain principle of operation and construction of tunnel diode.
Draw its v.I
characteristic. AKTU 2016-17(Sem-D, Marks 5.25
Fig. 1.31.2.
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Enmergng Domain in Elect ronics lEngineering 1-43J (Sem-1& 2) (Sem-1& 2)
Semiconductor Diode
1-44J
OR then the conduction band of
. If the forward bias is inereased further,
characteristic of tunnel diode. and there
Explain the V.I n-side would move away lrom the valence band of the p side,
to the filled states
AKTU 2016-17(Sem-D, Marks 05 would be no empty states on the p-side corresponding
on n-side
OR would go to zeroand the normal diffusion
6. Hence, tunneling current
This results in normai p
n
Explain tunnel diode. AKTU 2017-18(Sem-ID, Marks 3.5 component of current would dominate
junctwn diode eharacteristics.
ii. In reverse bins condition:
Answer
n-side, thus
When negative voltage is applied to the p-side with respect to
A P'rinciple of Operation of tunnel Diode: wouldpush Ep, alwve with their separation beng equal to the
. In forward biun condition
pphed voltage.
A small forwnrd biae is npplied neross the junet ion.
The filled states of the p side are directly opposite to the empty states on
Sinee, the potentinl of the p side under this condition is highorthan the
the n side across a very narrow barrier
potentul of n side, , will move below E,, 1s shown in Fig. 1.32.1 (a
thus thurn
and the oectrons in ihe conduetion band on the n-sicde fuces emply 3. Thus, the electrons fromp side would easily tunnel through
burrier by the process of quantum mechancal tunneling and appear on
stutes in the valencoe band on the p side, nt same energy level.
the n sid
1 Since, electrons travel from p side to n sde, the actual direction of
current is from n top side and is negative
As the amount of reverse bas s increased, more nunber ot filled statea
FEpty atem E in the valenee band ofthep sde would appear ofPposite to the numbr ot
yty nta y nply t u t a
mply slates illd tntn mpty st ates n the conducton bxn«d ofthe n sde and the reverne current
Filld atatas would keep on nereasng with reverse voltage.
3. Churacteristies: Due to heavy dopug, the current u negative
resistanee regon is suddenly ineroaed with a nmall appled voltage
De to ths reduced depleton rogion the atiulden inerease n curreni (at
law Forward Bi i h orwand Binn
nall applied voltage) is called "earrier punching through" etlect
(mA)
mdy ntal Enpty eates

-
Filld tnlew" illed atatea Negative resistane

TOgto
Neve bias v
3 The thin barrier acrosu
the
FL32.1
junetion would pernmit tunnelingg or
lectr
from nside
to p-sitde, with tho consequent curront flowig h
p-side ton vide Thus, 1,, poaitivein
for this case. As the
increased, more nuch illed lorw y Nupwrnuposed somoonduter
the empty nlaton ntates on the n-Bide would come opr diodo characterintw
With further
ineresu te in
renchod when the maxin forward biaN, a specific condition
vould
band on number of flled etates in he

the
n side
the valence band on
would fare the maximum cotes Vy
number of
peak
the p side. The tunneling eurrent enpye rene
Pla. 1.38.
wou
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Emerging Domain in
Electronics Engineering 1-45 J
(Sem-1& 2 1-46J (Sem-1 & 2) Somiconductor Diodo
Que 1.33.Explain principle

of operation of LCD. V. When the cell is energised, no twisting of light takos place and the cell
appears dull.
AKTU 2016-17(Sem-D, Marks05 3 Liquid crystal cells are oftwo types
a. Transmittive type:
Answer
used in similar applications where i In the transmittive type cell, both glass sheets are transparent, so that
Liquid crystal cell displays (LCDs)
are
1.
a r e display of numeric and light froma rear source is scattered in the forward direction when the
LEDs are used. These applications
in dot matrix and segmental displays. cell is activated.
alphanumeric characters
The LCDs are of two types: b. Reflective type

2.
i The reflective type cell has a reflecting surface on one side of gluss
Dynamie scattering:
sheets.
The construction ofa dynamic scattering liquid crystal cell is shownin
Fig. 1.33.1
i.
The incident light on the front surface of the cell is dynamically scattored
by an activated cel.
Ir ent
Liquid. ii. Both types of cells appear quite bright when activated even under ambient
Spacer crystal electrodes
light conditions.
4. liquid erystals light reflectors transmitters and therefore
Glass The are or
they consume small amounts of energy (unlike light generators).
5.
Mirror surface in Considering the
25 uA for dynamic
case
of seven segment display the current is about
reflective type cell
scattering cells and 300 uA for field effect cells.
B. Unlike LEDs which can work on DC the LCDs require AC
Fig. 1.33.1. voltage
supply.
. The liquid erystal material may be one ofthe
several organic
which exhibit optical properties of a crystal though they remain in liqu
compouns 7. Atypical voltage supply to dynamic scattering LCD is 30 V peak to peak
with 50 Hz.
form
. Liquid crystal is layered between glass sheets with transparent electrods
deposited on the inside faces. VERY IMPORTANT QUESTIONS
iv. Whena potential is applied across the cell, charge carriers flowing throu
the liquid disrupt the molecular alignment and produce Following questions are very important. These questions
turbulence may be asked in your SESSIONALS as well as
When the liquid
v.
is not activated, itis transparent. UNIVERSITY EXAMINATION.
vi When the liquid is activated the molecular turbulence causes light to
scattered in all directions and the cell appears to be brign
phenomenon is called dynamic Q.1.Explain the V-I characteristic
scattering. well labelled characteristic.
of p-n junction diode. Draw
b. Field effect type:
i
Ans Refer Q. 1.2.
The construction of field effect liquid crystal display is
a
thatd
thedynamic scattering type, withthe exception similararii

that two thinpo 2. Explain the v-I characteristic ofp-n junction diode. How
optical filters are placed at the inside of each is
differ from it
i. glass sheet. zener diode ?
The liquid crystal material in the field effect cell is also rent P ABs Refer Q. 1.4.
from that employed in the
dynamic scattering cell.
of difie
ii. The material used s thei 8. Explain the
is twisted nematic working of half wave and full wave
bridge
type and
passing through the cell when the latter is not actually twi rectifier.
iv. This
allows the light to pass through the energized. AaRefer Q. 1.10.
appears bright. optical filters a
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Emerging Domain in Electronics Engineering 1-47 J (Sem-1&2|

Q.4. For a half wave rectifier, derive an expression for rippl
factor.
Ans. Refer Q. 1.11.
Q.5. Differentiate between halfwave and full wave rectifiers

Ans. Refer Q. 1.12.
Q.6. Sketch V, for each network of Fig. 1, for the input shown.
Vi C
120 V
Si
R
Vi + Vo
E 20v
Fig. 1.
Ans Refer Q. 1.17.
Q.7. Describe with the help of circuit diagram

tripler. working of voltage
Ans. Refer Q. 1.27.
Q.8. What is voltage

the
multiplier usingp-njunetion
operation of voltage doublers.
diode? Explain
Ans Refer Q. 1.28.
Q.9. Explain input and output characteristics of

Ans Refer Q. 1.31. varactor diode.
Q.10. Explain the V-I characteristic of tunnel diode.
An Refer Q. 1.32.
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Emerging Domnin in Eloctronicn Enginuering
2-4J (Mem-1 & 2)
3.JT and lFr
2 - 2 J(Sem-1& 2) a. Emitter:
This in thw loft hand neclion of the trannintor.

PART1
. he main function of thin region in Lo nupply majority charge carriors
(oither holen or oloctronn) to thue bae and henee it in more heavily
Transistor Construction, (Operation
Bipolar Junetion Transistor:
Amplification Action.
dopod in compurinon Lo other rogiona
b. Bano:
The middle section of the tranwintor in known an bAne

Questions-Answers
Thin in very lightly doped and in very thin (10 " m) an compared to
.
eilhor omitter or colleclor no Lhut it may pann most »f the
Long Answer Type and Medium Answer Type Questions injected
charge enrriora Lo the collector.
e. Collector:
i. The right hand neclion of transintor in known an colloctor
Que2.1. Explain BJT.
The min function of the collector in Lo colleet majorily charge
Answer through the base. "Thin in moderately doped.
currier
. A junction tran»istor is a three-layer semiconductor device, nundwich 8. The urrow hend direction indicates the convontional
ofone type of semiconductor mulerial between two layers of theother low i . , in case ofnpn il in from buse to emitter while
direction of current
type. in from emitter to bnso.
in cane
of prnp it
2. There
two Lypes of
are
transintors: 9. In most of the can the collector region in nade large due to thr fact
that collector han to
npn tranwistor and dinnipute much greater power.
b. pnp transistor. 10. The junction between emitler and base
may he called an emilLer-bane
3 When a layer of jp-lype material is sandwiched
junclion and junction between ban and collector may he called an
between two luyers of collector-bune junetion.
n-4ype material, the transistor is known as
npn as shown in 1 The emitter-buse junction is nlway» forward binned while the
Fig. 2.1.1a).
collector- base junetion is reversed bianed.
4.
Similarly, when layer of n-type material is sandwiched between LWO
a
12. The resistance of emitter-ban
layers of p-lype material, the transistor i« known aN junctionin very xmall an conpared t
shown in Fig. 2.1.16). pnp trunsistor as
collector-base junction.
5. The trunsintors are made .
So, forward bias applied to emitter-buse junction
either from silicon or in generally very
6 The nymbols for
npn and pnp transistorn are
germanium crystal. Hmall and reverse bian on
collector-bae junetion in much higher.
alo shown in Fig. 2.l.l.
ue 2.2.
Emitter Collertor Deneribe the operation of pnp transistor.
Base
Anwwer
u) Structure of lransintor with emitter bane junclion as forward biaH and collector
npn tranistor DANe Junetion an reversed biased is
B nhown in Fig. 2.2. 1.
Emitter Collector T h o holen of
p region are repelled by ponitive terminal
Lowards the buse. of baltery Vg
Base epotential burrier at emitter bae juncuon in reduced as il in forward
(b) Structure of Dli and holen erons thie junction and penetrate inton-region, contitute
pup trannlor B the emitler
current g
7 A
Lransistor has three Fig.2.1.. e width of bse in very thin and only 5% of holes recombine wilh the
doped region Tree
olectrons of n-region which constituten the
current
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ging Dounin in Flortronies Engineering
2-5J(Sem-1 &2)
2 4em-1&9
avvx
( he a r e
and ontor
ta the polontinl baurier al tho
junetion is redueed due to forward
alle iirafd bia and mae rogion veory thin and
ia
The naning h av lightly deopel, olertronae ryas the

y baae rogion
Age Thia conat it
aw aleetronn (onbna Wilh the holes in

p region and ar lost as
Rae llevtor rharge e1rrior,
Naaw olotroun in rogion HWl.

up by poailiv
collertor voltnge
ls thid way elocLron conduetion tukea plnco, continuoualy s long as
V
he two junetionn
ure properly binsed
No the curront conduction in npn lranaintor in carriod out by the
oloctro,
ollertar junction
Emitter Buse Collector
2.21.0eration of pnp transistor

As hoies ach the vllarter, elrtons are emitted trom the negative
ternai ot ettery and neutralice these holes,
VEE Vcc
Now s wvalent bend near the emitter electrode breaks down. The
iberated elrtnn enters the pasitive terminal of battery VgR. This Fig. 2.3.1.
Y S IS npatai agin and again.
Applying Kirehhoff's eurrent law,
A the wth ofthe base ngion is very smal, the ratio of hole current 9
to electwn curnnt is
very larye so the electron current may be
negiected 10. The collector current has two components the majority and minority
0 Thus ouly the hole current current
plays the inportant role in the operationo0 carriers. The minority current component is called leakage
pp tranSistor.
co.
Que 23Explain the operation of npn transistor. So,
c Cmajority*cominority
OR Que 2.4. Describe the biasing of BJT circuit.
Explain various eurrent components
suitable diagram.
in npn
transistor with help Answer
AKTU 2016-17(Sem-D, Marks05 Biasing is necessary to establish the proper region of operation
for AC
Answer amplification.
The bias1ng of 2. base is lightly doped and collector is
npn transistor is shown in The emitter layer is heavily doped,
The emitter base Fig. 2.3.1.
junction is forward biased moderately doped.
lled fromthe because electro the conduetivity and hence increases
negative terminal of This low doping level decreases
The collector base battery
junetion is reversed VxE towa
EE towards the jun
he resistance of the material by limiting
the number of free" carriers.
flowing away from the biased becaus
use electrons are
battery terminal Voc- colector junction towards the collector
The electrons in poSIEI

of the emitter region are
battery towards the emitter repelled from the negau
gative termina
junction.
BIT and F Emerging Donialn in Electronies ngineering
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Signal
C 10utput
B
EE V¢c
Fig. 2.5.1. Transistor as an
ampliier
A Small change in signal voltage produces an appreciable change in
5.
emitter current because the input circuit has low resistance.
VEE (b)
Vcc Due to transistor action, the change in emitter current causes almost
6.
Fig. 2.4.1. the same change in collector current.
When the collector current flows through the load resistanece R, a
7.
transistor:
large voltage is developed across it.
A For pnp junction as forwaard bias and.collecte 8.
In this way, a weak signal applied in the input circuit appears in the
transistor with
emitter
base amplified form across the output circuit
pnp
r e v e r s e biased.
base junction as 9. Let, small voltage change AV, causes large emitter current change Alg
junction is reduced as it is fomuwarl
emitter-base We define it by the symbol a that fraction of this current change is
The potential barrier at this junction.
biased and holes pass through collected and pass through R
voltageat collector, the holes a r e easily drit.
i By applying negative
a
across the
collector-base junction to
constitute a current 1. ,
transistor: 10. The change in output voltage across load resistor
B. For npn AVo= R, x A¢
The emitter-base junction of npn is forward bias and the electron i
repelled by a negative forward junction.
=
R, x a x
Al
11. The voltage amplification
i The collector-base function is bias because electrons flow
reverse
toward positive collector battery terminal Vcc to constitute a curret A = AVO

AV
will be greater than unity and transistor acts as an amplifier.
Que2.5. Explain transistor as an amplifier in detail
Answer
PART-22|
Common Base, Common Emitter, Common Collector Configuration.
The transistor has two p-n junctions i.e., it is like two diodes. 1
Junction between emitter and base may be called emitter-base dioue
Simply emitter diode. The junction between base and collector
may
called as
collector-base diode or collector diode. The basic Questions-Answers
transistor amplifier is shown in circu
2. The weak
Fig. 2.5.1. Long Answer Type and Medium Answer Type Questions
signal to be amplified is emitter-base cireu
and the
output is taken applied betweer
across the
ed ir the
collector-base circuit load resistor ",,
CO Que 2.6. Draw the basic structure of CB BJT and explain its
let us assume for
instant Vg is principle of operation with in neat diagram along with its input
4. Now for
negative disconnected.
reversed bias, whichpeak of signal,
the emitter base
base junction
will and output characteristics. AKTU 2017-18(Sem-ID, Marks 07
the input circuit is not
desirahle, Ju*
because to acHieve amplificati
should remain OR
forward bias.
BJT and FET
2-8J(Sem-1& 2)
cireuit with
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its circnis
Emerging Donain in Electronics
neering 2-9J (Sem-1& 2)
of a common base
it
nlain the working I (1-a)= algt cBo
diagram.
AKTU 2015-16(Sem-II,Marks 05
Answer
The relation between d and B is given by
configuration:
A Common-base (CB) 7.
the input signal is applied between emitter and a or 1-a- 1
ln this configuration,
is collected from collector and base as shown in
base. The output
Fig. 2.6.1. I BI+ (1+p)ICBO
=
B) ca0
B.
B.
Characteristics
of CB circuit:
I (mA)
clmA)
VCB 20 V
Saturation Active region
B
8
YCB 10V region
I=5 mA
CB 1V
B 4 mA
Vcc 3 mA
Fig. 2.6.1. Common-base npn transistor amplifier. 2 mA
1 mA
Current amplification factor (a)
T0.2 0.4 0.6 0.8 1.0 VBE (V) -0.250 1 2 3 45
It is defined as the ratio of the collector current to the emitter current of
(a) Input characteristies
Cut off region
a transistor when no signal is applied and is called DC alpha (b) Output characteristics
(apc).
Fig. 2.6.2
a. Input characteristics:
i There exists a cut in, offset or threshold voltage VpE below which the
2. Simply pc1S current is very small
Then i increases rapidly with small increase in V»g i.e., input resistance is
very small.
3. Higher the value of a better is the transistor in the sense that collector b. Output characteristics:
current approaches the emitter current. In active region, the collector current is independent of collector voltagee
=
al and Ip =Ig-Ic and depends upon emitter current but if Vc increases beyond a certain
value, Ic increases rapidly due to avalanche breakdown.
I=I-alp=1, (1-a) In this region, the base emitter function is forward biased whereas
4. Now, when signal is applied, the ratio of change in collector to emitter
collector base function is reversed biased.
current at constant collector base voltage is defined as current
amplification factor. n cut offregion, a small amount of collector current flows even when
=0, i.e. leakage current IcBo
Here emitter base and collector base junctions both are reversed biased.
smant
n saturation region, current Ic flows even if VcB 0 .
Practically Gpc= AC = a = 0.9 tn 0.99 Here collector and emitter junctions both are forward biased.
Total collector current l , = z * Jco
5.
Mayornty Minonty ue 2.7. Draw and explain the input and output characteristics
or
6. The collector eurrent can also be expressed as common emitter configuration.
u+p+ co AKTU 2015-16(Sem-D, Marks 05
OR
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BJT and FET
(Sem-1 & 2)
J erging Domain in Electronics Engineering
2-10
OR -
2-11 J (Sem-1& 2)
sketch the
input and o u
c o m m o n emitter circuit and utput
Draw the
characteristics. Also explain active region, cut-off region
saturation region by indicating them on the characteristics curve,
AKTU 2017-18(Sem-D, Marks 0 i s generally greater than 20 and ranges from 20 to 500. Hence, this
OR configuration 1s trequently used when current gain as well as voltage
circuit of BJT and explain its input
Draw the CE configuration gain is required.
and
output characteristics. AKTU 2015-16(Sem-II), Marks 7.5 5.

Total collector c u r r e n t
OR Ic= Blp +cEo

Draw the circuit diagram of BJT in CE configuration. Draw output 6. We know that
characteristic curves and indicate the different regions of operation. Ic = a l + lcBo = a (g +Ic)+ lceo
AKTU 2016-17(Sem-D, Marks 05 I(1 a) = a lg +lCBO
OR
Why is transistor biasing required ? Deseribe collector to base
biasing in CE n-p-n transistor circuit.
7. On solving we get ß =
-a
and lcEo 1-a Tceo
AKTU 2016-17 (Sem-I), Marks 05
B. Characteristics of common emitter circuit:
Answer a. Input characteristic:
The forward biased diode curve is expected because the base emitter
A CE configuration section of transistor is a diode and it is forward biased.
1. In CE configuration, the input signal is applied between base and emitter
In this case, Ig increases less rapidly with VBE as compared to common
and the output is taken from collector and emitter. base configuration i.e., input resist ance of common emitter is higher
2. As emitter is common to input and output circuits, hence the name than base
common emitter configuration and is shown in Fig. 2.7. 1.
common
circuit
Ip(A) VCE 1 V
8mA
B Ic 100
CE 10 V A
80 uA
90 C E = 20V 0 A
60 A
80 (Saturation 5 50 uA
70 region) -40 A
Signal 60 30 uA
Ig 50
Active region'20 A
40
10 A
30
A
BB Vcc 20
Fig. 2.7.1. Common-emitter npn transistor amplifier. 10F 0
5 10
VCEV)
5 20
0.20.4 0.60RO BE V VCEsat Cut-off region)
3. The base current amplification factor is the ratio of collector current
the base crrent and is also called DC beta (Ppc) of a transistor, when
to ICEO = BIcBO
(a) Input characteristics (6) Output characteristics
no signal is applied.
Fi. 2.72
I Output characteristics:
of collector
4. When signal is applied, the ratio of change in collector current to tne active region, for small values of base current, the effect
otage over collector current is snall while for large base curTent
change in base current is defined as current amplification factor is
alues effect increases. Thus, the current gain of this configuration
greater than unity.
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BJT and FE Domain in Elect ronics Engineorino
Fmerging 2-13 (Sem-1& 2)
When Vhas very low value. the transistor
The said to is be
in
change !,
n
produce corresponding change saturated
does not a
in I
I mA)
cut off repon. small amount of i- flows even when
a
6
and the transuster said to be =0. ie.. i
s
cut-oft.
C- Transistor biasing Refer Q 24. Page 2-5J.
: 100 A
Unit-2 Ip 80 uA
e 28 Explain the operation of common
Ip60 A
collecte
ofiguration with suitable characteristics in detail I 40 A
B 20 uA
Ig = 0 uA
The diagran for determining the static characteristics of an n
carcat
0i 2 3 4 5 6 V
ramsistor in the common collector
configuration is showni Fig. 2.83.Output charaeteristics.
Fig 261
Que 2.9. Derive the relation between a, B and y.

VEE
Answer
1. We know, a= a n d B =
2.
ig 28.1.
Input characteristices: 3. Now
To determine the input characteristics, Vec is kept at a suitable fixe
vaiue B(1- a) a or ß -ßa
= = a
The base-colector votage Vgc is increased in equal steps and t B a(1+B)

corresponding increase in l is noted.
This is repeated for different fixed values of VEc. Plot of Vpc versus,
for different values of Vec is shown in Fig. 2.8.2.
1+P
or 1 =1+P
eA4 1-a
100 4.
VEC 4 Vv
Yanda-
5. Also
= 2 V 1 .2.9.1)
40
-U,71, "1-a
...(2.9.2)
7. We have,
12 3 4 5
VscV) 1-a1+8
8 Put values of eq. (2.9.2) in eq. (2.9.1)
Pig 282.1nput characteristice
Output characteristics:
The output characteristics shown in Fig. 2.8.3 are the plots ot
versus I for different values of Ig
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2-14J (Sem-1& 2) BJT and FET nerging Domain in Electronics Engineering
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Que 2.10.| An npn transistor with ß =98 is operated in the CB 80

configuration, if the emitter current is 2 mA and reverse saturation 2. Now B+1 80+0.98
current is 12 uA. What are the base and collector current ? I =Ida=2 mA and 1 =1/80 = 0.025 mA
So,
AKTU 2016-17(Sem-D, Marks 08 R==
E 2 mA
=1.2 ko
Answer 3. Now Vcc VCE +1cRc +pRg
12 5.2+ 2R+1.2 x 2
Given: =
98, 1g =2 mA, gat =12 uA Rc = 2.2 k2
To Find:1p, lc and VccpRg+ VBE +1R
12 = 0.025 mA x R,+0.7 V + 1.2 x 2
a= 98
1+B 1+98
0.989 R 356 k2
Now, V =
Vs + VBE =24 +0.7 = 3.1 V
BC B-Vc
I 3.1-7.6= -4.5 V
Ic = a = 0.989 x 2 = 1.978 mA
Que 2.12. For the voltage divider configuration of Fig. 2.12.1,
g l-le =2-1.978 =0.022 mA determine r, A,, Z;, and Zo
22 V
Que 2.11.For the network of Fig. 2.11.1
Determine Rg and Rg
Find V VCE and VBc
6.8 k2
12 V
5 6 kQ 10 F
2 mA 10 F
B 90 2
Rc
- 7.6 V
8.2 ko
VB
VCE B 80 2 1.5 k
20F
2.4 V
R Fig. 2.12.1
AKTU 2015-16(Sem-), Marks 10
Fig. 211.1
Answer
AKTU 2017-18(Sem-1), Marks07 Using approximate approach,
Answer 8.2 x 103 x 22
2.81 V
2. (56+8.2)x 103
Given: Voc 12 V, Vc= 7.6 V, V =2.4 V, B
=
80
V V-VRE =2.81 0.7
= 2.11 V
To Find:R, R Vp VCE VBc 3.
V 2.11
= 1.41 mA
1 We have,
VCE Vc- V =7.6 V- 2.4 V 5.2 V R1.5 10
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BJT and FE Emerging.
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(Sem-1
2-16J
_ 2 6 x 103
1 . 4 1 x 1 0 18.44Q
R
R'= (56 ks0) || (8.2 ks) 324 x10
56x 8.2x 10 2x 10-3 4+18x103-0.7
(56+8.2) 7.15 ka 1.2 x10

Z= R° |I Br.= (7.15 k ) || (90) (18.44 Q) R 86.5 kQ
7.15 kS||1.659 k2
7.15 x 1.659 x
10
VCECclcR¢+R)
= 1.35 kQ2 10 18-2x 10-d (R+1.2x 10)
(7.15+1.66)
R 2.8 kQ
4,= - 6.8 x10
1. -368.76
Te 18.44 Oue 2.14.|For the circuit shown in Fig. 2.14.1, determine VpI Vc
8.
2 Re6.8kQ Given thatß = 80, VBE =0.7 V.
Que 2.13. Given that I co 2 mA and
Vczg =
10V, determine R, and +V=20v
Rfor the network of Fig. 2.13.1.
R = 20 K
18.V R =2K
Vs
Rc 10 F R 5K R=1K
10 uF
AKTU 2016-17(Sem-), Marks 7.5
Answer
18 k 12 k 20x54K
Rh Rlk220-5+n
Vh=Vg * 4
20+5
Fig.2.13.1. V,-Va 4-0.7 0.0388 mA.

AKTU 2016-17(Sem-), Marks pR++)R
= B. =80 x 0.0388
4+81
=3.11 mA
V Ve-IR,
= = 20-(3.11 x 2) =
13.8 V
Answer
Given:co = 2 mA, VcBQ = 10 V, R, = 1.2ka,R,=18 ka PART-3
ToFind:R, R eld Effect Trunsistor : Construction and Characteristics of JFETs

Transfer Characteristics.
18 kQ 324 x 10 V..(2.13.1
V R+18 kQ
x 18 V =
R +18 x 10
m-1I & 2)
BJT and FE
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Emerging
2-19 J (Sem-1& 2)
ntacts are
Long Answer Type
Questions-Answers 1.
made at the two
Ohmie called source ends n-type
terminal S and theofother
as
semiconductor bar.
and On aDotential difference is established drain terminal D.
as
Medium Answer Type between source
Questions rent flows one end from to the
other end in and drain, a
Que 2.15. Sort of channel. This current
consists of
n-type material which
| Explain the in this case a r e electrons. majority carriers which
transconductance curve of a JFET. B. Operation of n-channel FET
AKTU The operation of n-channel FET can
be
Draw the OR 2015-16(Sem-ID, Marks 0 1 Fig. 2.15.2.
understood with the help of
circuit and
explain drain characteristic
the 2. irst,suppose that the gate has been reversed biased by gate
N-channel JFET. fo rain battery is not connected. o that space batteryVcc and
charge region or depletion region
AKTU 2016-17(Sem-I), Marks on either side of a reverse biased
p-n junction are formed
Draw and OR 3. Prther consider effect of drain battery VDo while
explain the The voltage VpD 15
dropped across the
Vccis removed.
n-channel JFET and draw n-channel resistance (say
its
transfe giving rise to a drain current. Ras)
characteristics. AKTU 2016-17(Sem-ID, Marks 5.2 p= VDD'Rps
OR
Explain the formation of depletion Depletion D
region in JFET.
n-channel
region
OR
AKTU
2016-17(Sem-D, Marks 75
Explain the construction and
working of N-channel JFET. I 0V
the drain characteristics and Dra
transfer curve
AKIU 2017-18(Sem-D, Marks 3.5
AnsweT
JFET (Junction Field
A Baaic construction : Effect Transistor):
The strzcture of n-charnei feld effect
tranaistor is shown in Fig. 216á1
ran
Pig. 2.15.2 Operation of PET

Coneider points A and B in n-chanzel as showe in Fig. 2.15.3.
two
Le
Piuion rgnn and Ve be potential drog at these points. Certainly V,> Ve so
nanne ae
tprogresaive voltage drop, the reverse biasing efet is stronger
e a r dran
Fig 2.15.1.Janction fieid-efle

Fo
traneistor JFET)
e zczo f n-chantal JFET, a narrow bar of n-tgE
isnusr ia
m2zra. 2ken. Nm on
oppssite idea of ita mGEE
a 2 11
Pig 2153. Votage drop a s chaanel

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Emerging Domaini
2-21 J (Sem-1& 2)
2-20 J (Sem-1& 2) BJT and FET Transfer characteristics:
7 This racteristics is a plot of drain current Ip, versus voltage

ne transfer c h a r a
explains why the depletion regions extend farther into the channel
at point A than at e 1or a constant value
etween gate and source csshown of voltage between
8.
point B. in Fig. 2.15.5.
This gate bias increases the depletion regions and thereDy decreases drain and source Vps This is
the cross-section of n-channel due to which Ip
decreases. Since negativa When Vos0,p=lpss
gate voltage controls the drain current, FET is called voltage controllei
a 2 I = 0, Vos = Vp
and
device. characteristic follows the equation
C. Static Characteristics The transfer
Static means I, versus

of FET (V-D: 3.
2.
Vps for different values of Vas
Let usconsider the characteristics for VGs 0, the curve is shown in
Fig. 2.15.4.
3. When Vps = 0, there is no attracting potential at the drain and hence
I Ipss
drain current 1p 0, although the channel between the gates is fully
=
Va (off)
open as VGs =0.
ID
4 As Vps increased,
is the electrons flow source to from
channel between depletion layers and the drain current 1, increases
drain through
ps
linearly up to a point A (knee point).
Vps
Ohmic region constannt
Pinch off point

Ip Saturation level C
Breakdown
region
Ipss VGs 0V
Increasing resistance due Vas Vp -4V- 2V 0
Knee point to narrowing channel
Fig. 2.15.5. Transfer characteristics.
with respect to
the various FET parameters
I D-channel resistance
Que 2.16.| Discuss
Vps common source configuration.
2.15.4. Drain characteristies of n-channel FET when Vcs 0.

Fig. Answer
od the static or ohmic resistance of the
With the increase of Ip, the ohmic resistance drop in the material ii DC drain resistance Rps: This is
5
semiconductor bar. So as the voltage Vps is progressively increased channel.
rate
the drain current Ip, from point A, increases at reverse square law It is given by:
The corresponding voltage
up to point B which is called pinch-off point.
6.
is called pinch-off voltage and is denoted by Vp
As Vps is further increased, the channel resistance also increases
AC drain resistance
Rps1pD
such a way, that 1D remains constant up to point C. The region
BC
known as saturation region or amplifer region. =ps Vas held constant
in the pinch-off
Va This is evaluated at VGS = 0 ie., when FET is operating
region. drain
where Ipss = Drain current when gate is shorted to source, and 1. Transconductance: The control that
the gate voltage has over
similar to
by forward
transconductance g, and is
Vas Voltage between gate and source. current is measured
transfer characteristics.
conductancegm. It is simply the slope of
With continued increase of Vs corresponding to point C (cal mutual
avalanche breakdown voltage V), eventually breakdown across
gae junction takes place and current 1, shoots to a high value
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BJT and FET
E m e rn G Domain in Electronics Engineeringg
2-23 J (Sem-1& 2)
he input signal is amplified by amplifier.
The unit of
Vas
AVas VDs held constant
Itis
then rectified and filtered to
produce DC
iv.
g is siemens (mho). 9. Tt. signal level. This voltage is applied to thevoltage
outp
proportion to
gate of the FET that
Amplification factor: The amplification factor 4 is defined as #he AC resistance Detween drain and source changes.
so
nacitor C'isolates the transistor from FET so that

(AVDs held constant
Ca
10. the bias conditions
AVs)
Que 2.17. | Explain with the
1 of transistor are
not affected.
Thus, when output increases, VGs also increases and Rps changes so
help of necessary diagrams, how FET that the gain of the transistor decreases. Thus automatically the is gain
can be used a s
(Voltage Controlled Resistor) VVR. controlled.
Answer Oue 2.18. Show that the transconductance g of JFET is related

1. In most of the linear current
Ips by
applications, JFET is operated in constant current to drain
portion of its output characteristics i.e.,
in saturation region.
2. FET can also be used in the
region before pinch-off where Vpp is small.
3. FET when used in region before
pinch-off, it works as variable resistance
device i.e., the channel resistance is controlled Answer
by the bias
gate voltage 1. As we know, the saturation drain current, Ins is given by
(Vas)
In suchapplications, the FET is referred as voltage variable resistor
(VVR) voltage dependent resistor (VDR).
or
'nspss 1Y ..(2.18.1)
5. The VVR can be used to vary the where Vp is pinch-off voltage and
voltage gain of a multistage amplifier. Ipss is the value of Ips when
This action is referred as automatic gain control (AGC). Vas0.
6. Ifthe signal is low then voltage gain 2. Differentiating eq. (2.18.1) with respect to Vcs, we get
of the stages can be increased and
when becomes high, the gain can be reduced
the general level of amplification is maintainedautomatically. In this way,
fairly constant. Vs
7. The circuit arrangement of AGC
amplifier
variable resistor is shown in Fig. 2.17.1.
using the FET as voltage
3. We know that, ol ps
8m ,Va is constant
VpD
8m ...(2.18.2)
4 From eq. (2.18.1), we have
R
Amplifier stage
C oVo
| pss
.Substituting this value in eq. (2.18.2), we get
Rg2 Rectifier
Rg Em V Lpss
BmV,2 Ipssps
2
Fig. 2.17.1. PET as VVR.

Vp may be positive or negativel
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(Sem-1& 2) B.JT and FET Emerging Domair lectronics Engineering
2-24 J 2-25J (Sem-1& 2)
t there be an increase in the drain current. This will

increase the
Que 2.19. tage drop across resistor Rs and this results in decrease of channel
Draw the schematie diagram of self-biasing JFFT amplifier
i width. So, the drain current is reduced.
Explain the CMOS inverter circuit working operation,
For DC analysis, the capacitors can be replaced by open circuit and the
AKTU 2015-16(Sem-I1), Marks10 8.
resistor RG replaced by short-circuit equivalent. Since I =0 A The
OR shown in Fig. 2.19.1(6).
equivalent circit is
Draw the CE n-p-n BJT characteristics. Also explain the self bias indicated loop, we have
9. For the
configuration in DC bias configuration.
- VGs-VRS =0
AKTU 2016-17(Sem-11), Marks 105 Vcs-VRS

VGs-Rs
Answer 10. The gate
is kept at this much negative potential with respect to ground.
A. CE characteristics : Refer Q. 2.7, Page 2-9J, Unit-2. but
B. Self bias configuration: and VDsVpD-lp (Rs +R)
1. The self bias configuration eliminates the need of two DC supplies ie, In addition Vs Rg Vo =OV
only drain supply is used and no gate supply is connected.
VVDS+Vs=VpD-VRp
2. Fig. 2.19.1 shows the arrangement, a resistor Rg is connected in the
source leg of the configuration. This is known as bias resistor.
C. CMOs Inverter
1 An inverter is a logic element that "inverts" the applied signal. That is, if
3. The DC component of drain current 1, flowing through Rs makes a the logic level of operation are 0V (0-state) and 5 V (1-state), an input
voltage drop across resistor Rs. level of 0 V will result in an output level 5 V, and vice versa.
4 The capacitor Cs bypasses the AC component of drain current. 2 InFig. 2.19.2, both gates are connected to the applied signal and both
drain to the output Vo
+VpD +VpD to the
3. The source of the p-channel MOSFET (Q) is connected directly
applied voltage Vss. whereas the source of the n-channel MOSFET (Q)
is connected to ground. For the logic levels defined above, the application
Ip of 5 V at the input should result in approximately OV at the output.

G 4. With 5 V at V, (with respect to ground), Vcs, = V;, and Q, is ON,
G
Signal in a relatively low resistance between drain and source as
resulting
shown in Fig. 2.19.2.
VGS Since V, and Vss are at 5 V, Vos, = 0V, which is less that the required
RG VRSRs rfor the device, resulting in an OFF state.
RsCs and is quite high for
OThe resulting resistance level between drain
source
2 as shown in Fig. 2.19.2. is very

Vowill reveal that
(a) (6) Asimple application of the voltage-dividertherule
desired inversion process.
Fig. 2.19.1. Self bias configuration. close to 0V, or the 0-state, establishing
The addition of Rc in circuit does not upset the DC bias, but avo1a t 0V, and , will be OFF
6.
short-circuiting of the AC input voltage. Otherwise, the leakage cur
8. For an applied voltage V, of0V (0-state), Vas, =
would build up static charge at the gate which could change the Dia MOSFET.
wth
Vss =
V, turning on the p-channel
-5
6. Rg also help to prevent any variation in FET drain current. 9. small resistance level, Q, a high
The result is that , will present a
5 V(the 1-state).
resistance, and Vo Vss = =
2-26 J (Sem-1& 2)
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BIT and FET main in ectronics Eng
10. Since the drain
current that flows for
Emerging
gineering
2-27 J (Sem-1& 2)
transistor to the either case is limited by the
either state is veryleakage value, the power OFp yoltage between gate and source is
low. dissipated by the device in zero
2,201., significant current lows for a given(Vs 0), shown in the
=
as
Vpg, like FET a
ss 5 V
p-channe
MOSFET
2
V, Vo 0V
(0-state) G
5V V
(1-state) n-channel VGs 0 V
MOSFET
VG$-
Fig. 2.19.2. CMOS inverter.
PART-4 Pig. 2.20.1. Depletion mode MOSFET

MOSFET (Depletion and 3. Let negative potential is applied at the gate. In such case positive charges
Enhancement Type, Transfer are induced in n-channel through
Characteristic. Si0, as shown in Fig. 2.20.2.
SiO layer n-channei
Questions-Answers
Long Answer Type and Medium Answer Type Questions Recombination
present
Que 2.20.| Draw the circuit of n-channel depletion type MOSFET

P material
and explain its operation. Also draw its drain and transfer G subtrate
characteristies. AKTU 2017-18(Sem-IID, Marks 07
OR Holes attached
Describe the construction and basie connection of
depletion to negative
Metal potential at gate
MOSYET. AKTU 2016-17(Sem-), Marks 05 contact
OR Electrons repelled
Explain eonstruetion and working of depletion MOSFET. by negative potential at gate
Fig. 2.20.2. Reduetion in free earriers in a channel due to

AKTU 2017-18(Sem-), Marks 3.5 a negative potential at the gate terminal
Answer 4
his mechanism depletes the channel from majority carriers ie.
P o r the depletion mode, the gate in ntial
whule the drain w maintained at
maintained at negative potenu electrons, and hence conductivity decreases
poitive potential.
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BJT and FET
5 Here it should be remembered that
Emerging
ing Doi Domain in Electronics Engineering 2-29 J (Sem-1& 2)
drain current Ip, the channel because of the voltage
region near the drain end drop due t nel
interconnects the p*-type source and
Since the p-channe
than the region near the is more
source. depleted ain-to-source current ilows even though the gate voltage
p"-type drain,
6. Here too much negative is equal to
a MOSFET
gate voltage can
pinch-off channel. Hence
the
zero.
behaves like a FET. he depletion states that the channel exists even at zero gate
Characteristics curves of T6 positive gate voltage 1s applied between gate voltage.
Fig. 2.20.3 shows the drain MOSFET:
a
5. to source of the
1.
characteristics and transfer m-channel depletion type MOSFET, the device will be turned OFF.
for n-channel MOSFET characteristics VGs 0
respectively. VDs
Source (S) Gate (G) Drain (D) Al
A ID (mA)
Ip (mA)
10.9 SiO2
Depletion VGs +1V
mode Enhancemen
mode
VGS 0V
Ipss
n-type
substrate p-channel
-VGs=-1 v
-Vas = -2v
DSS Fig. 2.21.1. Cross-section of a p-channel depletion MOSFET with Ves
-3V 6.
0
Ap-channel depletion type MOSFET with positive gate voltage is shown
in Fig. 2.21.2.
V43-2 V/2 101 Vos
o.3Vp Vos.V,6v Vcs>0 Vps
Fig. 2.20.3. Drain and transfer characteristics for an Source (S) Gate (G) Drain (D) Al
n-channel depletion-type MOSFET.
2. The two modes, namely

depletion mode and enhancement mode siO2
correspond to negative and positive gate voltages respectively.
It is obvious, that for Vas 0, the drain current
3 =
I, is not zero, but it has

appreciable value.
The gate voltage at which I, reduces at a recommended drain P-channel Depletion
voltage region
Vs is called gate source cut-off voltage. This is denoted by Vss (OFF n-type substrate
and corresponds to pinch-off voltage
Vp
Que 221.| Draw and explain the construction and working o
Fig. 2.21.2. Cross-section of a p-channel depletion type
p-channel depletion type MOSFET. Also draw the characteristicso
p-channel depletion type MOSFET. 7.u e
to
MOSFETwith Vas0.
positive gate voltage, a space charge region is induced under the
AKTU 2016-17(Sem-D, Marks 0 X1de. Consequently, the thickness of the p-channel region will be
reduced.
nwer Since the channel thickness is reduced, the channel
conductance is also
1 Fig. 2.21.1 shows ap-channel de pletion type MOSFET. reduced and in turn drain current
reduces
2 When zeto voltagz is applied to the gate, a p-channel or an inver positive gate voitage is equal to the threshold voltage, the induced
layer of holes ezist under the ozide. pace charge region extends completely through the p-channel region
and dueiti
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BJT and FET Emerging Domain in Electronics Engine
10. When a negative gate voltage is applied between gate to
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2-31 (Sem-1& 2)
soure.
negative gate voltage creates a hole accumulation layer as sh ig
as shownin
for s,: efer Q.2.18, age 2-23J, Unit-2.
E x p r e s s i o r
B.
Fig. 2.21.3. C. nhancement oSFET:
21 shows the
VGs0 DS 1
Fig. 2.22.1
cross-sectional view of n-channel
MOSFET
enhancement
Source (S) Gate (G) Drain (D)
Al D
SiO
n-doped region
Si0 no-channel
Metallic
contacts
Hole accumulation
G o p-type Substrate
n-type substrate layer
substrate SS
Fig. 2.21.3. Cross-section of a p-channel depletion

MOSFET with Vas <0. n-doped region
Fig. 2.22.1. Enhancement MOSFET.
11. Due to accumulation of holes in the p-type channel, drain current I t consists of a lightly doped p-type substrate into which two
increases.
12. The drain and transfer characteristics are shown
doped nt-regions are diffused. This n*-regions act as source andheavily
drain
in Fig. 2.21.4. respectively.
A (mA) 3. A thin layer of insulating
A (mA) SiO, is grown over the entire surface and
holes are cut into the oxide layer through which metal contacts
are to be
made for source and drain terminals.
Vos-1V
4 On SiO, layer, a
conducting layer of aluminium overlaid, covering entire
channel length from source to drain, constitute the
-Vss = 0V
gate.
Working of Enhancement MOSFET:
VGs+1 Vv 1. The
channel, the insulating dielectric SiO, and metal layer of gate forms
Vcs+2V parallel plate capacitor.
a
s+3V When a positive

Gs+4 V potential is applied at the gate with respect to substrate,
Vcs+5V negative charges are induced on semiconductor side.
-io i24s 6 Vs 3.
(a) Transfer characteristics Vs=V=+ 6v nese negative charges, induced onp-type substrate consist of electrons
b) Drain characteristics wnichforms an inversion layer as shown in Fig. 2.22.2.
Fig. 2.21.44 h e inversion layer forms an effectiven-type channel.
Que 2.22.Deseribe the working h e n the positive potential at the gate is increased, the magnitude of
and operation of enhancement mou e induced negative charges in semiconductor increases.
depletion mode MOSFET. Also derive of
.
JFET configuration. expression for Bm

an s , the conductivity of induced n-channel increases and results in
increased drain current.
AKTU 2015-16(Sem-ID, Marks 1 oraconstant drain voltage, the drain current increases as the positive
Answer n voltage increases ie., the drain current has been enhanced by the
A
Depletion mode MOSFET: Refer epieation of positive gate voltage. Such MOSFET is termed as an
Q, 2.20, Page 2-26J, Unit-% enhancement MOSFET.
Domain in Electronics
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BJT and F Emerging gineering 2-33 J (Sem-1& 2)
attracted to positive gate
o
threshold voltage is defined as the gate voltage at which channel is
Electrons
tinduced n-channel)
3 ced to produce
induced the flow of current
In of
FETis very useful inprescribed
oted by V
V. Such type of value and is
,Region depleted of p-type switching
carries (holes) since no gate voltage 1s required to hold it off. applications,
( Explain
Que 2.23.Ex
p-channe enhancement MOSFET.
construction, working and characteristics of
AKTU 2015-16(Sem-D, Marks 05|

Answer
0A
A Construction:
G
P 1. The construction of ap-channel enhancement type MOoSFET is exactly
the reverse of that n-channel enhancement type MOSFET. It is shown
in Fig. 2.23.1(a).
There is an n-type substrate and p-doped regions under the drain and
2 source connections.
The terminal remains as identified, but all the polarities and the current
directions are reversed.
Hoies repelled
Insulating layer B. Operation:
br positive gate
When VsG < |V»l:
Channel formation in the
Fig. 2222. no channel and transistor operates in cut-off mode i.e., ip
There is
= 0.
n-channel enhancement type MOSFET.
MOSFETT: When VpG> |Vpl or VSD < |Vovl:
Characteristies curves
of enhancement in triode
222.3 shows the static drain and transfer characteristics ofn-charn The continuous channel is created and transistor operates
1 Fig
enhancement MOSFET. region.
2 Fron ig. 222.3. as Vos is made positive, the drain current first
increax
When VDeS |V»| or VeD |Vovl
slowly and then at relatively fast rate with increase of Vas The channel is pinched-off and the transistor operates in saturation
region.
Vos+8 VV C. Characteristics
in Fig 2.23.16), with
1 The drain characteristics will appear as shown
vaues
increasinglevels of current resulting from increasingly negative
Vas+7V of Vas
D pmA)4
-Vas =6V
Vas5V P
-Vas=+4V
Go SS
Ycs*
5 10 15 20 25 Vcs
Vas=V2V
Fig. 2.22.3. Drain and transfer characteristics for an b)

(a)
n-channel enhancement-type MOSFET.
BJT and FE
EmergingDomain in ectronics Engineering
2-34J(Sem-1&2)
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where, R 82 2-35 J (Sem-1& 2)
-Vas-6V 11 MQ
2 Z,= Rg = 82 MO || 11 MQ = 2x11x 10
-Vcs-5V
82 11 9.698 M
as-4V
_100x 10 x2x 10
(100 2) x 10 1.96 kO
-3V 20x11
4 For Vas
VosV2v VGs 82 11'p x610
c
Ip 3.880 mA
Fig. 2.23.1. p-channel enhancement-type MOSFET
2
(about the l,
The transfer characteristics will be the mirror image (about the
of the transfer curve of n-channel enhancement MOSFET axis) 5. ps 1
3 The transfer curve is shown in ig. 2.23.1e), with Ip increasing wit V
increasingiy negative values of VGs beyond VT
Que 2.24. Determine Z, Z Vo for the network of Fig. 2.24.1

3.88x
10 12x 103 1- Yc-3
L
V=20mV. 3.88x10
+20 V 19
12 x 103 1. 3
Gs-1.294
82 MO
2k 6. We know that
DSs 1 2 mA -2x12x 10 1294|

Vp=-3V 3
=
4.55 ms
7.
Ta 100 kQ Vgs V = 20 V
8. We know,
11Mo
610
Vo-8Vg,Tal|R)
Vo=-4.55 x 103 100x2 x103
100+2 =-8.92 V
Fig. 2.24.1.
Que
Answer
as
2.25.Determine Ip, Vas V» Vs and Vpns for the given network
1. shown in Fig. 2.25.1.
Converting Fig. 2.24.1 as given in
Fig. 2.24.2. 16V
20 v
2 k 2.1 MQ 2.4 k
Vo
DSS = 8 mA
V V,=-4V
Vo 270 ka
610 0 s 1.5 kQ
Fig. 2.24.2 Fig. 2.25.1.

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2-36J (Sem-1& 2) PJT and P Domain in Eleetr Lngneer
ing 7 J Sem-1é2
Z 12
Answer
Given: pss8 mA, V, = -4 V

To Find: Vas VpVg V 2 12 10
1.
V R+RVR
RR
270 16
2100+ 270
1.82 V
2. Vs Va-Rs = 1.82-1.5/p 410r 1- =3m5
3 As,
ass 1
4 On solving A-3 5 15k2 25 k
Dg = 2.41 mA
Ay=-3 nS x 168
5.
Gs 1.82-2.41 x 1.5 =- 1.795V
6 VD VDD-1,R, = 16 -2.41x 2.4 = 10.216 V A=-5.04
7.
8.
VsR=3.615V Pue 2.27. For the voltage divider network shown in Fig. 227.1.
VDs -Vs= 6.601 V mA, Vp -3.5 V, determine V po
9 VDG VD-Va = 8.396 V
Givenpss=10 =
V V, and Vose
Vpse
Que 2.26.Determine
Z, Z, and A, for the network of Fig. 2.26.1, ift
22 k
IDss 12 mA, Vp =-6V, and Yos = 40 micro siemens.
910 k 1P
+18 V
18 ka
1F V=-6V
220 k 1.2 k
1 MQ
1.5 V+T Fig. 2.27.1.
Fig. 2.26.1. AKTU 2017-18(Sem-ID, Marks 07
AKTU 2015-16(Sem-D, Marks 05 Answer

Answer The procedure is same as Q. 2.25, Page 2-35J, Unit-2.
Given:1pss 12 mA, Vp=-6V, Yos = 40 uS, R=1 MQ, R, = 1.8k ns. V 3.33 V, Vas =Vcsa = -
1.662 V, Vpso = 3.188 V, V =8.188 V,
Z R 1 MQ s 5V.Ipo = 4.16 mAA
To Find:Z, 2,A,
1. We have,
Z- R lla
2. 1 25 k
40S
os
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VERY IMPORTANT qUESTIONs
Pollowing questions are very important. These questin
may be asked in your SESSIONALS as well as
UNIVERSITY EXAMINATION.
Q1. Explain the operation of npn transistor.

Ans Refer Q. 2.3
Q2. Draw the basic structure ofC3 BJT and explain ita
prinapie
of operation with in neat diagram along with its input and
output characteristics.
Ans Refer Q 2.6.
3 . Draw and explain the input and output characteristics of

common emitter configuration.
Ans Refer .2.7.
Q.4. An
9.4. An npn
npn transistor with p = 98 is operated in the CB
transistor witn p currenti is 22 mA and
configuration, if the emitter and reverse
reverse
saturation current is 12 uA. What are the base and collector
current?
Ans Refer Q. 2.10.
Q.5. Explain the transconductance curve of a JFET.

Ans. Refer Q. 2.15.
Q.6. Draw the circuit of n-channel depletion type MOSFET and

explain its operation. Also draw its drain and transfer
characteristics.
Ans Refer Q. 2.20.
Q.7. Describe the working operation ofenhancement mode and

depletion mode MOSFET. Also derive an expression for g
of JFET configuration.
Ans Refer Q. 2.22
Q.8. Explain construction, working and characteristics o

p-channel enhancement MOSFET.
Ans. Refer Q. 2.23.
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3 UNIT Operational Amplifiers

and IoT
CONTENTS
Part-1 Operational Amplitier 3-2J to 3-4J
Introduction. Op-Amp Basic
Part-2 Practieal Op-Amp Circuits. 3-4J to 3-13J

(Inverting Amplitier,
Nou-inverting Amplitier,
Unit Follower, Summing Amplitie
Integrator. Differentiator)
Part-3 Differential and 3-13J to 3-19.J
Common-Mode
Operation, Comparators
Part.4 : Introduction of loT. 3-19J to 3-23J
System, Components
of loT System Microprocessor
and Microcontroller
Part-5 Bluetooth Technology, 3-23J to S-29J

Wi-Fi Technology,
Concept of Networking.
Sensor Nodes,
Concept of Cloud
Operational Amplifiers and Domain in Electronics neering 3-3J (Sem-1& 2)
2J
(Sem-1
& 2) www.aktutor.in
ingEmerg
PART1
Op-Amp Bas
V
Introduction, Sasic.
Amplifier: OP
Operational ViaR W-
AVi Vo= AV id
Questions-Answers
V
Medium
Answer Type Questin-
ions
Answer Type and Fig.3.1.2. Equivalent circuit
Long
resistance which is Thevenin's equivalent.
a R.is the output
Op-Amp with
the help ofblock diagram. Also d The voltage source AVa is an equivalent Thevenin's voltage source.
Que &1. Define proportional to the difference between

its equivalent circuit. The output voltage is directly
voltages.
the two input
open-loop voltage gain of 1,00,000, input impedance of 2 M2
Answer
various mathematical operations 13 It has
of 75 2.
to perform
1 Op-Amp is designed and output impedance
2 The Fig. 3.1.1 represents
the block diagram approach of an operational 14, Fig.3.1.3 shows popular package style
and the pin diagram.
amplifer. Emitter follower with

Differential NC
amplifier
constant current source
Offset null1
Invering Level Output Output 2
Input Intermediate Inverting input
stage
shifting stage 3 Output
stage stage Non-inverting input
Non- - Offset null
inverting Differential Complementary symmetry
amplifier push-pull amplifier
Fig. 3.1.1. Block diagram of Op-Amp. Fig. 3.1.3. Dual in ine package.
3. It consists of two differential amplifiers followed by level shifter and an
of block diagram. Also
output stage. Que3.2. Define Op-Amp with the help
with its ideal and practical
The input stage is a dual input differential amplifier which
most of the voltage gain to operational amplifier. It also provides high
provides describe the equivalent circuit along
characteristics.
resistance to operational amplifier. OR
Also draw its
5. with the help of block diagram.
he intermediate stage is also dual input. This is driven by the
ot irst stage and is used to provide some additional gain. The DC leve
outpur Define Op-Amp
quivalent circuit. List the ideal characteristics of Op-Amp.
ar the output of intermediate stage is well above the groundleve Marks
AKTU 2017-18(Sem-I, 07
6.
The level shifter is emitter follower using constant current soutof
an
OR
The function of level shißter is to shift DC level at the outpu and equivalent circuit
of a n Op-Amp. Explain
intermediate stage downwards to id the block diagram
zero volt with respect to grou aeal characteristics of an Op-Amp
7. The output
stage is generally push-pull mplifier. Its function is to
Marks 1.5
Dcrease large output voltage swing capability and to provide l0w output AKTU 2016-16(Sem-D,
resistance.
8. Fig. 3.1.2 shows the
equivalent circuit of
Answer
9.
1S the difference of two input voltagesoperational ampune
ie., (V,-V). R, is t
input
A Op-Amp: Refer Q.3.1, Page 3-2J, Unit-3.
resistance
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Operational Amplifiersa EnergingDomnin in Electronies Engineering 3-5 J (Sem-1 & 2)
s4Jem-1& )
in ideal a n d pra.
cases
Characteristies
ofOp-Amp
8 Ideal Practical wW
Characteristic
R
No
10 or 120 dB 2
CMRR W
80 V sec V1
Slew rate
Input resistance
102
Output resistance 100 2
Fig. 3.3.1. 1Inverting amplifer.
Voltage gain A 106
is given
,The current i, flowing through R, by,
Bandwidth 10 Hz
i,= =(:: V, =O due to virtualground)
Offset voltage Negligible R
Offset current Negligible and i
PART-2 3 At pointA,
Practical Op-Amp Circuits (Inverting Amplifier, Non-inverting
Amplifer, Unity Gain Amplifier, Summing Amplifier, Integrator
Differentiator). 4,
B. Non-inverting amplifier:
3.3.2.
L The circuit for non-inverting amplifier is shown in Fig.
Questions-Answers R
W-
Long Answer Type and Medium Answer Type Questions R i
V Vo
ue 33.
Draw the circuit of an Op-Amp as voltage follower V2
find an
expression for its voltage gain. Fig. 3.3.2. Non-inverting amplifier
OR T h e currents i, and i, are given as:
Draw and derive loop
relationship for Op-Amp as
Co
non-inverting amplifier circuit. AKTU i V, andi,= ( V =
V, due to virtual ground)
2016-17(Seml;
OR 3Applying KCL at point A,
Derive enpression for voltage gain of inverting and
an non-inverting
ideal
operational amplifier no 4)i0, R
configurations. arks
AKTU2017-18(Sem-D, Mar
Answer
A iaverting OpAmp
Fi 331 harwa V R
and the baic inverting mplifier with input ress
leedtark resistance
R
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Operatior Amplifiers and Fmerging Domain in Electronics Engineer
3-6J (Sem-1& 2) 3-7J (Sem-1& 2)
Follower)
VV,V,
Op-Amp
(Voltage
4. IfR, =
R, R,
= =
R, then
Amp where R, ->o
C. Unity gain unity gain
Op-A
reprosents
. Pig. 3,.3.3 A=1
V-IV,V, V,
1 b.
Thus the output voltage is proportional to the algebraic surn of three
input voltages.
Again, if R= R,
is unity and the output voltage
follows the innt V-IV+V,+ VJ
2 1 h e voltage gain voltage
Que3.6. Calculate the output voltage for the cireuit of Fig. 3.5.1
with inputs of V, = 40 mV rms and V, = 20 mV rms.
in 470 k
Fig. 3.8.3. 47 kQ w
+15 Ve
V W
Quue 34 Explain summing amplifier using Op-Amp. V2 wW
121k2
AKTU2015-16(Sem-D,Marks
- 15 V
Answer
1 Fig. 3.4.1 shows the three input summer circuit. This circuit provides
Fig. 35.1
means ofalgebraically summing three input voltages, each multipie
by a constant gain factor.
AKTU 2016-17(Sem-),Marks 07
R R Answer
wW
Given: V,=40 mV rms, V,=20mVrms,R, 47 k, R, = = 12 k,
WW R 470 k.
To Find:Vo
R
N
W
V-VV24740 20
= - [400 +783.3] = - 1183.33 mV rms
Fig. 3.4.1. Summer cireuit.
2 = -1.18 V rms
At
point A(virtual ground), the different currents are givenas:
Que 36 Explain zero crossing detector using Op-Amp.
3. ii.-andi--R
Applying KCL at point A, we AKTU 2015-16(Sem-1D, Marks 03
get,
itig-i =0 Answe
The basic comparator can be used as a zero crossing detector when ref
is set to zero.
Operational. www.aktutor.in
Amplifiersaand IoT
3-8J(Sem-1& 2) Emerging Domain in Electronics Engines
neering
in Fig. 3.6.1 and 3-9 J (Sem-1& 2)
the output
an
shown
detector is
zero-crossing
2. An inverting wn in
signal is showni Fig. 3.6.2. The OR
waveform for a
sinusoidal input
wave generator.
circuit Explain the operation of Op-Amp
integrator.
a sine-to-square
is also called
AKTU 2017-18(Sem-ID, Marks 3.5
OR
Draw the circuit diagram of an integrator
R using Op-Amp and explain
W Vo its working. AKTU 2016-17(Sem-), Marks 05
OR
Write a short note on differentiator.
Answer
R A Integrator:
rer=0V 1. The cireuit of integrator is shown in Fig. 3.7.1.
2.
This circuitproduces an output voltage which is proportional to the time
integral of the input voltage. Due to this reason it is known as integrator.
Fig. 3.6.1.
N
3. The integrator is an inverting Op-Amp in which feedback resistor R,has
been replaced by a capacitor C.
Feedback through capacitor forces a virtual ground to exist at the
inverting input terminal.
5. The capacitive reactance X. can be expressed as:
OV
and ,-g-cd dt
R
V
+sat
0V
Fig. 3.7.1.
-V sat
6. At point A :
ii
Fig. 3.6.2.Input and
output waveforms. -c%
Que 3.7Explain
integrator circuit using Op-Amp d V, Rd
AKTU 2015-16(Sem Marks04
Explain how Op-Amp can be OR V0)=RCV,)dt
i. Integrator used as is the integral of the input
1. Th that the output
iii. Voltage follower. Inverting summer and e above equation shows
a n inversion and scale multiplier of 1VR,C.
Marks 07
AKTU 2017-18(Sem-D, Mar
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(Sem-1 & 2)
Operational Amplifiers andnd ulot Cmerging Domain in Electronies Engineering
3-10J 3-11J (Sem-1& 2)
B. Differentiator:
tiator is to give an output voltaga

difforentiator
V.=1
Let
V and V2 at ground, so output due to V,, Vo, will be due to
is
2.
1 T h e The
function of a
rate of
change
ch of input voltage. vhich is input at non-inverting terminal,
to the
proportional
d i f f e r e n t i a t o r is
shown in Fig. 3.7.2
2 The circuit of a R Vo 1 15010.1, 450 3

(10+ 10) 2 1502 1.5 V
2V andV, is at
L e t V, =
ground, so
input at inverting terminal,
output due to V, Vy will be due to
Vo
Vo2 x2 -4 V
Plg. 3.1.2 4. Now total output, V% = Vo1 + Vay

feed linearly increasing voltage to the differentiator- V + 1.5-4 = - 2.5 V
3. When we
constant DC output. So it is an inverse mathematical operationto that
of an integrator.
Oue 3.9.Find out the voltage V2 and V, of the given network of
Fig. 3.9.1.
4. At pointA,
VC 200 ko
20 k2 W
dC whe da . 3.7.1)
dt
Vo- iR .3.7.2) N
5. Put the value of i from eq. (3.7.1) in eq. (3.7.2)
V-CR dt
3.7.3)
V =
0.2 v
6. The eq. (3.7.3) shows that the
output voltage equal V is to a constant
-CR) times the time derivative
C. of the input voltage V1 200 kQ
Unity
Unit-3.
gain amplifier (voltage follower) : Refer Q. 3.3, Page W
D.
Inverting summer : Refer . 3.3, Page 3-4J, Unit-3. 20 ko
ue 3.8.
in Fig. 3.8.1.
Determine the output voltage for the given circuit show"
Fig. 3.9.1.
300 ka AKTU 2015-16(Sem-D, Marks 05

150 k
Va=2VoWM Anewer
10 kQ
741
No Let
2
V be the output of It Op-Amp.
Thus,
V-1Vo-W 3
VA 0.2V ( Unity gain follower)
10 ko 20 ko -10 x 0.2 =
-2v
Fig. 3.8.1 V,-(1)V. =11 x02=-221
Answer AKTU 2017-18(Sem-ID, Mark 0 Design and draw an inverting amplifier using Op-Amp
1 We can withaaigain
n
get V, by of5 and R, = 10 ka. AKTU 2016-17(Sem-D, Marks 05
superposition method,
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Operational Amplifer Domain in Electronics Engineering
3-13 J (Sem-1& 2)
ndbn
Answer
A = -5
47-120) 18
Gain.
= -
-1200 + 180) =
1020 mV
10 kQ
R, =
V% = 1.02 V
=-5 R 330 k2
R= 470 k
W- W-
R, 5 10 50 kQ
R= 5 x = x =
R 33 k
V W R =47 ko
12 mV
R=47 kQ
W
VW
No v 18 m
Fig. 3.10.1
Fig. 3.11.2
Que 3.11. Caleulate the output voltage V, of the circuit.
PART-3
330 k2 470 kQ Differential and Common-Mode Operation, Comparators.
WW w-
33 k
12 mVWW Questions-Answers
47 kQ
ww- Long Answer Type and Medium Answer Type Questions
47 kQ
W-
ge 3.12. Explain with the help
V=18 mV of necessary diagram:
Inverting amplifier
Integrator
3.11.1.
Differential amplifier in two modes of operation.
AKTU 2015-16(Sem-D, Marks10

OR
AKTU2017-18(Sem-D, Mark Analyse the
of operation.differential amplifier with suitable circuit in two modes
Angwer
Answer
330 x 12 mV =- 120 mV 8 tng amplifier : Refer Q. 3.3, Page 3-4J, Unit-3.
33 S r a t o r : Refer Q. 3.7, Page 3-8J, Unit-3.
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3-14J(Sem-1&2) Operational Amplifiers and Lt nerging Engineering 3-15J (Sem-1& 2)
(in two modes of operation

(i
C.
Differential
amplifier
ircuit
circ has two separate VeVca Vcc-,Re= Vcc-R
connected inputs and
amplifier
1.
The
differential
outputs
and that itters are
the emit
together. " +cc
separate
separate voltage supplies,
2 It also
consists oftwo signal
amplifier circuit, input
the es both transistors
operates he
3. In differential t h e common emitter
single-ended operation due to VC
in from both collectors.
resulting in output
of the inputs
double-ended operation, the difference resulting in
,
4. In
outputs from both collectors due to the ifference of the signals applied Vg 0V. VB=0V
to both inputs.
5. In common-mode operation,
the
common input signal resulte
anposite signals at each collector; these signals cancel each other
is zero.
that the resulting output signal
is the very
6. The main feature of the differential amplifier large gain
when opposite signals is applied to the inputs as compared to the very
small gain resulting from cormon inputs.
Fig. 3.12.2.
7. Let's consider DC bias operation of the differential amplifier circuit
With each base voltage at 0v, the common emitter DC bias voltageis the basic parameters of Op-Amp.
Que 3.13.|Explain
=0V- VBE 0.7 V
VE = -
OR
Explain the following

characteristics of an Op-Amp:
+cc i. CMRR
ii. Slew rate AKTU 2017-18(Sem-D, Marks 3.5

Rc OR
Draw and explain the differential amplifier.
Define CMRR and slew
Vo1 V 02 Vi rate in Op-Amp. AKTU 2016-17(Sem-I), Marks 5.25
Answer
3-13J, Unit-3.
A Differential amplifier: Refer Q.3.12, Page
Basic parameters of Op-Amp:bias currents lg1 and g2 are
the base
1. input
nput bias current: The transistors in the input differential amplifier
c u r r e n t s of the two
D1as I is defined as the average
-VEE Fig. 3.12.1. stage of the Op-Amp. An input and
bias current
8. The emitter DC bias

current is ot the two input bias currentsIg1 Ig2 that is
then,
.Vu-0.7 2
flowing into the inverting
input,
9. ASsuming the transistors areRwell R where, I = DC bias current
input.
matched, we
ge current flowing into the non-inverting
g2 DC bias =
nput offset current and voltage: offset current, I is

defined as the
Collector voltage, 2
I
put offset c u r r e n t : The input
bias currentsg
and p2
between two input
agebraic difference
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Operational Amplifiers and loT
indicates the
maximum amount by which tho
The value of , bias
current may differ.
voltage: Input
offset voltage, Vi, is the differential
tial input
ii voltageoffset
Input that exists between two input terminals of an O-Am mp without
In other words, it is the amount of the
external inputs applied.
any betvween two input terminals in ord
voltage that should be applied to
force the output voltage to zero.
3 Slew rate (SR):It is defined as the maximum rate of change of output

voltage per unit of time and is expressed in volts per micro-second
SR d V/usec
Le dt mar
Slew rate indicates how rapidly the output of Op-Amp can change in
response to change in input frequency.
4 CMRR (common-mode rejection ratio) : It is an ability to reject the
common mode noise which is present at both the inverting and
non-inverting terminal.
CMRR 20 log
Acx
Que 3.14. Determine the output voltage of an Op-Amp for input
voltages of V = 200 V and V = 140 V. The amplifier has a differential
gain of A = 6000 and the value of CMRR is:
200
i 105
Answer
Given:
V,=200 V, V= 140 V, A =
6000
To Find: V
For CMRR 200
AACM
=
V AVa+Acu Vcu A,(V, -V,)*

CMRR2
6000K200-140) +5000 200 +140 365100V
200 2
36.51 kV
For CMRR 10 =
V AVa+ACM VCM
A4lACM
6000200-140)+ 5000 200+140360010.2
2
360 kV
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Operational Amplifieru and lft dou Domain in Pleronies Enginesering
Energin, 3-17J (em-1& 2)
(Sem-1
3-16J
16.For an input of V, « 0 mV in the eireuit Pig 3.15.1,

maximum
amount by which the in..
indicates the
The value of/ determ
ne the maximum frequeney that may he uaed. The Op-Amp
current may differ. = 04 V/s.
rate SN
offset voltage:
Input offet voltage, V, is the differentill input s
slew
i. Input between two input Ís of an Op-Amp with
terminal
voltagethat exints In other words, it isthe amount 2
external inputs applied.
i of the
any two input terminals in
should be applied between der tw
voltage that
to z e r o .
force the output voltage
3 Slew rate (SR): Itin defined an the

mazimum rate of change outod of
and i8 exprenBed in volts per micro-eend,
voltage unit
per of time
SR du, V/uee Pig 3.15.1.
dt
Slew rate indicaten how rapidly the output of Op-Amp can chanye in AKTU 2015-16Sem, Marks
respone to change in input frequeney.
4. CMRR (common-mode rejection ratio) :It in an ability to reject the Answer
common mode noise which i» present at both the inverting and
GAven: R= 200 k, R, =2 k2, V,= 50mV, SR =94 Vs
non-inverting terminal.
CMRR 20log A ToFind:

\AcM
Que 3.14. Determine the output voltage of an Op-Amp for input
A R 2k
2 utput gain factor, K =A V, = 10) 50 10 -5 V
voltages of V =200 V and V= 140 V. The amplifier has a differential
gain of A= 6000 and the value of CMRR is Maximum signal frequeney SR94 -0.012 Hz
200 2K215)
ii. 10 AKTU 2015-16(Sem-1), Marks 05 e 3.16. Write a short note on comparator and enlist its
Answer pplications
Given: Answer
V,= 200 V, V =
140 V, A, = 6000
A Comparator:
ToFind:V ignal voitayt
comparator is a circuit that is used for conparing
a
For CMRR= referenEe voitage at h e r

200 =A,IACM Ed at one input ofOp-Amp with a knuwn
input.
,AVa *Acau VcM A,V,
-V,)*CMRR2 10
=6000 200-140)+5000 (200 +140=365100V
200 2
For CMRR 36.51
10'
kV
=
A4ACM V-Vyzr)
V,A4V+Acu CM -V - 10
6000%200-140),5000 200+140360010.2 a) Ideal com
parator
(b Practical cwmparator.
360 kV 10 2 characteristics
Fig. 3.16.1. The transfer
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Operational Amplifiers and l ng Domain in Electronics Engineering
Emerg 3-19J (Sem-1& 2)
an open-loop
Op-Amp
with output +V
Vn=Vccas shown Inverting comparator:
In inverting comparator, fixed reference voltage V,...is applied to (+ ve)
2 It is basically characteristics Fig.3.16.1(a).
of
in ideal transfer input and a time varying signal u, is applied to (-ve) input.
comparator:
two types of
There are basically R
3.
i. Non-inverting comparator: W-
3.16.2a) is called non-inverting comparator. AG.
a
1.The cireuit of Fig. to (-ve) input and a time varyinu

reference voltage Vrofis applied signal
to (+ve) input.
, is applied R
2 The output voltage is at
-
Vnt 1or u, <ro And u, Koes to + V (Vref

v,>ref for a sinusoidal input signal applied to the (s w
3. The output waveform ve)
and Pig. 3.16.2c) for positive and negative
input is shown in Fig. 3.16.2(6) (a)
Ve Pespectively.
R Vi V
N
Vref
Vrof oV ov
(a)
V,«
Vper
OV +V sat H
+sat
OV OV
-Vsat
ren
V>Vre V-Vref
V<Vref (c)
(b)
V. g . 3.16.3. (a) Inverting comparator. Input
and output waveforms
. 0.
for (b) Vref> 0 (c) V<
+Hat
OV Applications of comparator:
OV Zero crossing detector
+Vgut Window detector
ii. Phase meter.
V,>Vref
(b) V,<Vre
(c)
PART-4
Fig. 3.16.2. (a) Components of loT System
Non-inverting
waveforme Input and
(A) g comparator. Input
for6 a
output ntroduction ofloT System,
M i c r o p r o c e s s o r a n d Microcontroller
Vref positive (c) Vrnegatve.
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Smart devices and sensors Device connectivity

Questions-Answers
Devices and sensors are the components of the device
connectivity
layer. These smart sensors are continuously collecting data from the
Medium Answer Type Questions
Long Answer
Type and environment and transmit the information to the next layer.
ii. Gateway:
1lOT Gateway manages the bidirectional data traffic between different

Write short note
on Internet of Things (loTs). networks and protocols. Another function of gateway is to translate
Que 3.17.
different network protocols and make sure interoperability of the
connected devices and sensors.
Answer
is a system of interrelated computing 2. Gateways can be configured to perform pre-processing of the collected
1 The Internet of Things (loTs)
mechanical and digital machines, objects, animals or people data from thousands of sensors locally before transmitting it to the
devices,
that are provided with Unique Identifiers (UIDs) and the toability next stage. In some scenarios, it would be necessary due to compatibility
transfer data overnetwork without
a requiring human-to-human or ofTCP/IP protocol.
human-to-computer interaction.
i . Cloud:
The Internet of Things (IoTs) is the network of devices such as vehicles,
2 1. Internet of things creates massive data from devices, applications and
and home appliances that contain electronics, software, sensors, users which has to be managed in an efficient way. loT cloud offers
actuators, and connectivity which allows these things to connect,
tools to collect, process, manage and store huge amount of data in real
interact and exchange data. time. Industries and services can easily access these data remotely and
3. The Internet of Thirgs (loTs) is also a natural extension of SCADA make critical decisions when necessary.
(Supervisory Control and Data Acquisition), a category of software
2 Basically, IoT cloud is a sophisticated high performance network of
applieation program for process control, the gathering of data in real servers optimized to perform high speed data processing of billions of
time from remote locations to control equipment and conditions. Distributed
4. SCADA 8ystems include hardware and software components.
devices, traffic management and deliver accurate analytics.
database management systems are one of the most important
6. components of loT cloud.
The hardware gathers and feeds data into a computer that has SCADA
sollware installed, where it is then processed and presented 1u n a
iv. Analytics:
timely manner. of smart
1.
Analytics is the process of converting analog data from billions
devices and into useful insights which can beinterpreted and
Que 3.18. What are the major components of lol
sensors
solutions are inevitable for
for
used detailed analysis. Smart analyties
of the entire system.
Answer 1OT'system for management and improvement
2. Big collected from IoT devices and
Components of IoT: D1g enterprises use the massive databusiness opportunities. Careful
utilize the insights for their future
trends in the market and
analysis will help organizations to predict
Thing or User
plan ahead for a successful implementation.
device Cloud V. User interface:
interface 1. of the lo'T system which
ser interfaces are the visible, tangible part
will have to make sure a well
Designers
an accessible by
be users.
eftort for users and encourage
aesigned user interface for minimum
more interactions.
Gateway Analytics significance in today's competitive
Ser interface design has higher
the user whether to cho0se a particular
arket, it often determines interested to buy new devices or
will be
Fig. 3.18.1. uevice or appliance. Users
friendly and compatible with
Major com
omponents of loT. Snart gadgets if it is very user
common
wireless standards.
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ng Dom 3-23J (Sem-1& 2
These processors are a rapid movement of the code and

concerned with
and microprocess
ane ota from external addresses to the chip. It also has one or two ypes of
What is
microcontroller
Why
Que&19. preferred forcontrolling operation? bit-handling instructions
are
Aficroprocessors are more expensive than mierocontrolers because

microcontrollers
Answer
addition of external RAM. ROM and IO ports makes these system bube
and more expensive.
A Microcontroller:
of RAM, ROM, VO Dorte aand Microcontrollers are preferred over microprocessors

fixed amount for
contains a
1.
Amicrocontroller controlling operations because:
timer all on a single chip.
a needs of the tass eficiently and
shown in Fig. 3.19.1. :They meet the computing
cast
The block diagram of

microcontroller is
2 effectively.
Timer/Counter IO assemdiers and debuggers
ALU
port i Software development tools such as complers
are available for operations.
Accumulator IO
i Wide availability and reliable sourres the microcwntrvler.
Register(s) port
ir. The power consumption
of this device is also very low.
Internal
Internal
ROM
Interrupt PART-5
circuits
RAM
Bluetooth Technology, WiRi Technology. Concept of Netwerkings
Clock Sensor Nodes, Coneept of Cloud
Stack pointer circuit
Program counter
Questions-Answers
Fig. 3.19.1. Block diagram of a microcontroller.
3. Microcontrollers are intended to be special purpose digital computers
Microcontroller is concerned with rapid movement of bits within
the
4
chip. It also consists of many bit-handling instructions.
e 3.20. Explain in detail about the bluetooth and its application.
Mierocontrollers are normally less expensive than microprocessor
B. Microprocessor
Answer
hcroprocessors contain no RAM, no ROM, and no VO ports on thecu
itself *Dluetooth was designed to be low powered,
operate over a short range.
nd support both data and voice services.
T h e block of
diagram of a microprocessor is shown in Fig. 3.19.4. 2 communieations among all
sorts
etooth enables peer-to-peer

Arithmetic devices.
devices to exchange
and Logie unit| and communication
ystem enables computing the benetit of the user.
for
Accumulator ntornation and work together in common: Both aim to
much
Bluet computing have convenient, and
Working register(s) t h and pervasive communications ensier, more
Computing and
nmore personal.
Program counter Stack pointer small mobile
5. Both enab devices, especially
the of a myriad of evident that
Clock circuit dev ble use
accomplish these
objectives. Thus, it appears
Interrupt circuits| O match with and key
a element of pervasive
Fig. 3.19.2.Block Blueto can be an
Comth
excellent
3. diagram of a microprocesso computing.
Microprocessors are intended to be
general purpose digital compute
Eeneral purpose
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Electronics Engineering 3-25J (Sem-1& 2)
Operationa Ampli and lo
3 - 2 4J (Sem-1&2) EE
E
S02.11b/g standards use the 2.4 GHz frequency band, whereas
has applications in at least three The
11ses the 5 GHz band, and 802.1ln uses a multiple input multiple
networking, automobileimportant
S02.11a u s
has to utilhze both the 2.4 GHz and 5 GHz bands
Specifically,
bluetooth
domains:
home netwo t (MIM0) mechanism
output
6. computing
e-business.
pervasive
mobile
and
solutions,
standard
aims to
hieve interconnectivit
achie
As
between
a resnle
any
bluetooth manutacturer.
or
7. The regardless of brand any
bluetooth
device
anywhere in
the world can connect to ther similar
bluetooth device
within its range. ESS AP
devices such as pervasive . AP
usages,
other
bluetooth
Wireless
8 There are many bluetooth
uses radio frequency-based da Wireless
Wireless client Wireless
ethernet,
Tike wireless client
BSS Chent BSS
client
transmission.
between
etooth and wireless ethernet is th
bluetoo
difference
The major WLAN.
9 the piconet. Fig. 3.21.1.
Infrastructure
concept of within close ranothat
idea that devices are
modes, ad-hoc mode
10. Bluetooth
is based on the them to access each othe wireless LAN standard operates in two
small network, allowing The 802.11 i n f r a s t r u c t u r e mode (peer-to-AP).
should establish a (peer-to-peer)
or
or
stations (STAs) c o n n e c t to,
resources.
which is based on more or less static P
setup, wireless
infrastructure
wireless ethernet, In an
(AP).
11. In contrast to bluetooth enables a less restrictive, associate with an
a c c e s s point
addresses, basic service set (BSS)
(internet protocol) of such as bluetooth enabled (STA(s) + AP) is called a
6 This grouping of devices
the usage
low-level communication; also, an outside
network
to
(the internet) via its
connect
referred to as BTnodes. where each STA can
active tags
standard for associated AP.
bluetooth as a communication be
12. The main r e a s o n for using in an identify itself. Multiple APs c a n
modules are being integrated service set ID (SSID) to
the active tags is that
bluetooth ABSS BSSs
(DS) where different
. uses a
PDAs,
such as mobile phones, connected via a wired
distribution system
increasing number of c o n s u m e r devices, (ESS).
extended service set
and digital cameras. are referred to as an
different SSIDs, a STA may change
a scenario where BSSs
use AP
Bluetooth applicationa: n
its association to a different
however it must change
1 Mobile e-business association of connection.
which causes a temporary loss
a c c e s s control
(MAC) address
pager (BSSID) is the media
i communicator ADasic service set ID a unique
BSS AP in an ESS. This
0 an AP; this allows a STA to identify BSS.
infrastructure
WLAN within one
ii. mobile phone. is carried out on an
Eearch must go through
a three-phase
2 Home networking8 10 rder a STA
to associate with an AP,
in 3.21.2.
i Fax Setup process as illustrated Fig. phases. Unn
authentication, and association
i Bluetooth passive
S e phases are the scan, must discover nearby APs by using a
i. Head phone. or power on, a STA
3.
0ns an active scan. broadcast beacons
Automobile network solution. 12. Apas on each
channel for
broadcast
involves listening sends out a
e e Scan
Sentfrom APs. In an active STA 'actively
lol. ctive scan, the from an
Give an overview of Wi-Fi network in probe reque frame channel and
then
for response
waits a
one
Answer s t othe
AP
APon that channel. the STA
the starts
1. 13. After APs one AP

is selected,
discovered and the AP
02.11 standard extends the 802 T
area
wireless medium by specifying the operation ot wireless local are itself with
authentication
authenticate
toprocess which the

chosen
network (WLAN communication within the.SM radio bands. 14. The frame, to
authentication
medis
an
sends out frames.
2. First AP reo rst
version was
and authentication
(PHY).
sponds with additional
published1997.are
access control (MAC) networkinlayers ThedefinedI
physical 802.11.
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Response timei is the elapsed time between an
3
Probe request The performance of anetwork inquiry and
response. a
number of users, the type ofdepends

on anumber
4 offactors, including
Probe response the
transmission
of the connected hardware, and the efficiencymedium,
of the
the
capabilities
Authentication request i. Reliability: software.
Authentication Response
In addition to accuracy of delivery, network
the frequency of falure, the time it takes reliability is measured by
a link to recover from
Association request failure, and the network's robustness in a catastrophe.
a
ii. Security:
Association response
1 Network security issues include
protecting data from unauthorized
Acknowledgment access.
Protecting data from damage and development.
Fig. 3.21.2. Request-response process. Implementing policies and procedures for recovery from breaches and
data losses.
15. The authentication phase controls what nodes
can access the AP.
network access control mechanism. Itisa Que 3.23.Explain the components of sensor node.
16. After successful
authentication, the STA mov es to associate with
the
by sending an association/re-association request frame to which AP Answer
the AP
responds with an association/re-association response frame.
17. Finally, the STA sends an
acknowledgement (ACK) frame to the AP. Location finding unit|| SensingUnit
Once the AP receives this
ACKframe, the STA is associated with the AP
and a valid connection is established between Transciever ADC
the STA and the AF.
18. The infrastructure topology is sometime
called an AP topology since t
wireless network consists of at least an AP and a set of Processor
wireless devices.
19. In this topology, the
system is divided into basic cells, where each cellis
controlled by an AP. To extend the
coverage area, multiple basic cells
Storage
can be used.
Power
Que 3.22. What is network? What are the criteria to be meet bya
network? Fig. 3.23.1. Architecture of a sensor node.
Answer Components of sensors node are:

.Location finding unit:
A Network a.
transceiver which transmits or receives
Ocation finding unit contains a
1 A network is a set of devices (often referred to data.
as nodes) connecteu
communication links. b Ensor node often makes use of ISM band, which gives free radio,
2. A node can be The possible choices of wireless
computer, printer, or any other device capable
a din
ectrum allocation and global availability.
and/or receiving data or se are Radio Frequency (RF),
optical communication
B. Network criteria:
generated by other nodes on the networK. nsmission media
A network must be
daser) and infrared.
C.
line-of-sight for communication
able to meet ser requires less energy, but need
most
a certain number of criteria. 1e
important of these are
Performance:
performance, reliability, and security nd is sensitive to atmospheric conditions.
Performance can be measured in and
Sensing unit:
a Sen
sensor nodes to capture data from their
response time. many ways, including transit ANrsare used by wireless
2. Transit time is the amount environment. a measurable response to a
of time required for message to tra e lfrom
that produce
one device to
another.
a a r e hardware devices like temperature of pressure.
g e in a physical condition
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2 Operational Amplifiers and loT Emerging Domain in
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-29J (Sem-1& 2)
Sensors measure physicaldata of the chnology merges virtualization,
have specifñc parameter to be monitored and
characteristics such as accuracy, 3 grid functionalities and web standards
ingle utility model which is delivered
Transceiver: sensitivity etc.
rnet, whereas the business intelligence to the
customers over the
defines the best cost schemes
The
functionality of both transmitter and receiver are combined ading to win-win situation for both the cloud service
single device known as a transceiver. into a as the cloud service consumer. provider as well
.
Transceivers often lack unique identifiers. Cloud brokers negotiate the best deals and
The cloud consumers and cloud providers. relationships between the
operational states are transmit, receive, idle, and
generation transceivers have built-in state machines thatsleep. Current They can use speciahzed tools to identify the most
operations automatically. perform some wesOurce and map the requirements of the applicationappropriate
to it.
cloud
Most transceivers Cloud broker services are mainly categorized into three
operating in idle mode have a
power consumption groups:
Service intermediation broker provides a service to a consumer
almost equal to the power consumed in receive mode.
2. that
Processor: enhances a given service by adding some value on top to increase some
specific capability.
The processor
processes data and controls the functionality of other hService aggregation brokerage service combines and integrates into
components in the sensor node. one or more services and ensures that data are modelled across all
D. While the most common
processor is a microcontroller, other alternatives component services and movement, security of data between the service
that can be used as a controller are a general purpose consumer and multiple providers.
desktop
microprocessor, digital signal processors etc. C. Service arbitrage is similar to cloud service aggregation but services
C. A microcontroller is often used in being aggregated are not fixed. In addition, these services provide
many embedded system such as sensor
node because of its low cost, flexibility to connect to other flexibility and opportunity for the service aggregator.
devices, ease
of programming and low power consumption.
5. Que 3.25.|What are the components of cloud?
Storage o r External memory
a. Flash memories are used due to their cost and storage capacity.
Memory Answer
requirements are very much application dependent.
b. Two categories of memory based on the purpose of storage are: user Components of cloud:
memory and program memory where user memory is used for storing Cloud service consumer (or end user):
1. Cloud service consumers are the end users known as clients, which
application relatedor personal data and program memory is used for
programming the device. interact with the system and demand for services as per their
6. requirement.
Power source: The client can be categorized into the following three categories
a. A wireless sensor node is a popular solution when it is dificult or
impossible to run a mains supply to the sensor node.
Mobile clients : Mobile clients run the application from laptops, PDAs
and smart phones. This category of clients demands for higher speed
b. An important aspect in the development of a wireless sensor node is
and hig) level of security.
ensuring that there is always adequate energy available to power the DVD
: Thin clients neither have hard drives nor have
system. DThin clients
ROM drives, and largely depend on the server.
The sensor node consumes power for sensing, communicating and data
clients are self-sufficient in terms of accessories.
C.
hick clients:Thick
processing. Cloud service provider:
d. Power is stored either in batteries which host the servers in the
or capacitors. loud service providers are the agents
cloud and deliver service to the end users.
Que 3.24. Explain briefly the term cloud. Sales Force, IBM,
are Gongle, Amazon,
n e major cloud providers
Answer Microsoft and Rackspace. the comnmunication channel
is
nternet medium : Internet medium
where services are
redirected.
Cloud is an extension ofthe internet with some level of inherent discipline and provider
and ethics. Eween the consumer
Datacentre: where the applications

subscribed
atacentre is the collection of servers

2. Cloud can be thought of unification of information technology w
business intelligence. are housed.
and server.
t consists of storage, network,
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VERY IMPORTANT QUESTIONS
questions a r e very
important, Thee
Following
may be asked in your SESSIONALS
a esti
questiona
Q.1. Define Op-Ampwith the help ofblock diagram
Al o deseribe
the equivalent circuit along with its ideal
and
Ana
characteristics.
Refer Q. 3.2.
practieal
Q.2. Draw the circuit of an Op-Amp as voltage
find an expression for its voltage gain. followe
Ans. Refer Q. 3.3.
Q.3. Caleulate the output voltage for the
circuit
inputs of V, 40 mV rms and V2 20 mV rms, of
=
=
Fig. 1l with
470 kQ
47 k2 W
V W +15 Vo
V2
12 kQ 741 Vo
- 15 V
Ans Refer Q. 3.5. Fig. 1.

Q.4. Explain integrator circuit
Ans Refer Q. 3.7. using Op-Amp.
.5. Design and draw
a
gain of -5 and an inverting amplifier using
A Refer Q.3.10. R, 10 kQ.=
Op-Amp w
Q.6. Explain
the basic
Ans Refer
Q. 3.13. parameters of Op-Amp.
Q.7. What arethe
A Refer Q.3.18. components
parameters of Op-Amp.
mponents of IoT ?
Exp
Explain basie
Q.8. What is
network ? What
network?
An a r are
e the
the criteria to be by
Refer Q. 3.22. criteria meet
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4UNIT
Digital Electronics
and ICT
CONTENTS
Part-1 :
Digital Electronics: ... 4-2J to 4-6J
Number System and ..
Representation,
of
Introduction
Basic and Universal Gates
Part-2 :
Using Boolean Algebra. 4-6J to 4-13J
Simplification of Boolean
Function, K-map
Minimization up to 6 Variable
Part-3 Introduction to 4-13J to 4-14J

IC Technology SSI,
MSI, LSI, VLSI
Integrated Circuit
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Electronics
4-2J
(Sem-1
Ic Engineering 4-3 J (Sem-1 & 2)
PART1 Answer
Number System and (62.7= (1g =(Da

Digital
Electronics : kepresentation 110 010 .111 »
DiETntroduction of Basic
ana Universal
Gates 0011 0010 .1110
6 2 7 (32.E)16
Questions-Answers
(62.7)= (32.E) =
(00110010.1110)
i. (BC6),16=10 (0
Long Answer Type and Medium Answer Type Questions BC6)16 11 162 + 12x 16
x
+6 x 16° =
(3014)10
(3014)0= (101111000110)
Que 4.3. The solution to the quadratic equation 2 11 + 22 = 0
Que 4.1. Define number system and also define signed
are = 3 and x = 6. What is the base of the number system used ?
and
unsigned binary number?
Answer
Suppose the
Answer 1. base of the number is b. The given quadratic equation i
Number system:It is a language of digital systems consisting of aset (x2-11x+22), = 0 .4.3.1)
of symbols called digits with rules defined for their addition, multiplication 2. The solution of quadratic equation is,
and other mathematical operations. X = 3 andx = 6
follows: 3 The quadratic equation formed with these roots is

The classification of number system is as
(x -3) (x -6) = x*-(6 +3) x + (6 x 3) ..(4.3.2)
1. Decimal number system: It has 10 symbols, so the base or radix of
4. Comparing eq. (4.3.2) with the given quadratic eq. (4.3.1)
thisnumber system is 10. The 10 symbols are 0, 1, 2, 3, 4,5, 6, 7,8,9.
2 Binarynumber system: It is a base 2 number system. The two binary
(910 (11),
b1x 1+b° x 1= 9
digits are 1 and 0.
b+1 9, b=8
3. Octal number system: It has a base of 8, it has eight possible digits0, also, (18)10- (22,
1,2,3,4, 5,6 and 7. bx 2+60x 2 18
4 Hexadecimal number system:It is a base 16 number system. Ithas 2(6 +1) = 18, b=8
digits from 0 to 9,A, B, C, D, E and F. Hence, the base of the number system is 8.
5. Complements : These are used in digital computers to simplify the
Que 4.4.. What are the logic gates ? Explain each of them.
subtraction operation and for logical manipulation.
gned binary number: Binary number that carry identificationas Answer
to their polarity is called signed binary number. Plus (+) and minusl
1 0postive and negative numbers can be represented in a digntu There are three logic gates:
notthe three major signed binary notations are :Sign magnt AND gate
notation, 1's complement notation and 2's complement notabtion. 1. An AND gate will produce a HIGH output when all inputs are HIGH,
otherwise the output of AND gate is LOW. Fig. 4.4.1 shows the symbol
ned binary number: In these type of numbersw
o r 9 sign and concentrate only on the magnnitude (absolute
of AND gate.
value) of numbers.
A
Que 4.2, Convert the B
i. following: Fig. 4.4.1.
ii.
(62.7),=
(BC ()h= 0 2. Table 4.4.1 gives truth table for the two input
AND gate. The inputs of
6)6 =(10=(2 AND gate is A and B, the output
of gate is Y.
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Do Elerta
Tabile 452 +73 Se-1&
Outpat
-uy-i-
-A-B ij-w- - - AB -
=
- -Ew-
= - - F w-?
E-u-7
PART-2 = -1- I1-A =1
-1 I1
Using Briean Algebrc Sirmplification ofBoclean Function,
K-Map Minimization Upto 6 Variable.
Using NAND ge Using NOR gate

Questions-Answers Fig 47.1
Long Answer Type and Medium Answer Type Questions Que 4.8. Simplify the following boolean expression to a minimum
number of literals.
AC + ABC+ A AB
Que 46.State De Morgan's theorem. ( +z) +z+ry+uz
Answer
Answer
First De Morgan theorem : It saes, complement of two or ma

i A +ABC+ A +AB: A A ABC
variabies and then AND operation on these is equivalent to NOE Let Y A -
- -
operaion on these variables. NOR means complement of two or mie = CA-A)- AB-BC)
varables OR I: A A = 1}
Second De Morgan theorem : It states that complement of T

=
C-AC-AB : -
AC = - A) -C}
o r e variables ard then OR operation on these is equivalent to
a NA
operatin on these variables NAND means complement of two or D = C- A1-
variabies AND.
ue 4.7. ssible:
Simplifty the following expression as much as possit
+2)+2** *
Let
2 +y+z
Flu, x,y, z) = j~ - kzz - kzy~ + wy~
and implement your result Oy+2 I:1=

using universal gates only. Fj ++2 =r
canonical SOP form
Answer into
Que94.9C o n v e r tthe given espression

Fu, z, y, z = y~ - kIz k zy - uyã Y=A+ABBC
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& 2)
4-8 J (Sem-1
The K-map drawn in Fig. 4.11.2,
for
numbers in each row and each column tothree variables is marked wi th
show the relationship betw
Answer the squares and the three variables.
AB(C +C)+ BC(A - A)
Y =A(B +BXC+C)+ BC BC BC BC A00
Y= (AB+ ABXC +C)+ ABC+ ABC + ABC+ ABC 01 11 10
A mo mi| ma m2| o000 001 011 010o
= ABC+ ABC+ ABC+
ABC +ABC+ ABC+ ABC+ ABC OR 2 3
= ABC+ABC + ABC ABC+ABC 1 1004 101| 111 110
A +A
=A] Fig 4.11.2.
into canonical POS form
Que 4.10.| Convert the given expression 3. For example, the square assigned to m, which corresponds to row l
and column 01. When these two numbers reconsidered, they give the
Y =AlA+ B A +B +C) binary number 101, whose decimal equivalent is 5.
AnsweT For four variables:
1. The map for boolean function of variables require sixteen
four binary
Y (A+ BB+CCXA+B+ CCXA+B +C) minterms, hence the map consists of sixteen squares.
= (A+ BB+CXA+B B +TXA+B +CXA+B +C) (A +B+C) 2. The listed terms are from 0to 15, i.e., 16 minterms. The map shows the
relationship with the four variables.
= (A + B +CXA +B +CXA + B + CXA +B +C) that
3. In every square the numbers are written. The number denotes
(A +B+ CXA + B +CXA + B+C) this square corresponds to that number's minterm.
Y= (A + B +CXA+B+CXA + B +CXA + B +C) Al CD D CDCD CD AB 00 01 11 10
AB mo m ma 00 0000 0001 0011 0010

Que 4.11. Write a short note on Karnaugh map. Also show the
3 2
reduetion of boolean expression and how to mark pairs. How gate
level minimization is implemented1? AB m4 m5 6
01 0100 0101 0111 0110|
OR 5 7
AnswerT AB m12 Dm13 m15 m14 11 1100 1101 1111 1110
14
1. Karnaugh map is another way of presenting the information given by a 12 13 15|
truth These maps are also known by the name K-map. Let us
table.
consider the map for two variables. There may be four possible AB 10 1000 1001 1011 1010
combinations within four squares.
9
11 10
2. Each square represents unique minterms as shown in Fig. 4.11.1: Fig. 4.11.3.
B Simplify the
boolean function.
Que4.12
A AB AB 00 01 F (u, x, , z)
Em(1,3, 7, 11, 15)
=
conditions
OR wnich has the don't care
d (uw, z, y, z) Ed(0,
2, 5)
AAB AB
=
10
Fig. 4.11.1 Answer conditions

Zm(l, 3,7, 11, 15) and don't care
For three variables: 1. Given, Flw, x,y,2) =
1. There eight minterms for three binary variables. Hence the K-may
are z) = Ed(0, 2, 5)
dw, x, y,
consists of eight squares.
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combinations that make the function 2.
POS form vwe will take
for
of F are the variable
complement
= 1 MO,
1,2,3, 4,5,6, 8, 10, 14)function,
2. The minterms the don't care minterms that may be
minterms of d are
equalto 1. The
either 0 or 1.
3. inimization through K-nap is shown in Fig. 4.13.1.
The K-map simplification
is shown in Fig. 4.12.1.
3 yz B
00 01 11 1 0 wx 00 01 11 10
w
AI
o 00
A+LO 2
01 o1
11 14 AE
IZ
14
1 1 U
yz + WZ yZ+ z
(a) Fig. 4.12.1 b) Fig 4.13.1.
The minterms of Fare marked by 1's, those of d are marked by x's and
4 Y =(A + B) (A + C + D) (B + D)
the remaining is filled with 0's.
5. To get the simplified expression in SOP form, we must include all five 1's i AC +CD + AB +ABCD
in the map, but we may or may not include any of the x's, depending on 1. Let, Y= AC +D+ Aß+ABCD
the way the function is simplified.
6. In Fig. 4.12.1(a), don't care minterms 0 and 2 are included with the 1s,
=A(B+)ch-(A+ AB c-õD++ ABCD
resulting as
= A(B+BC-(A+ -ABC-ÕID-D)+ABCD
F=yz + w = ABCD+ ABCD+ ABD+ ABD+
7. In Fig. 4.12.1b), don't care minterm 5 is included with the 1's, resulting +ABCD+ABCD + AB D+ ABCD
as
F yz + kz Y= Zm(1, 5, 8, 9, 10, 11, 13, 14, 15)

8. The K-map in Fig. 4.12.1(b) is more feasible because, we have to use the have to take complement function,
2. Now for POS form, we
minimum don't care.
Y =I MO, 2, 3, 4, 6, 7, 12)
Que 4.13. Simplify the following expression into product of sum 3. Minimization through K-map is shown
in Fig. 4.13.2.
(POS) form CD C>D

i. ABC+ ABD+ BCD AB C+D C+D C+D
ii. ACD + CD + AB +ABCD A+B
Answer
A+ B O
i ABC+ ABD + BCD AB|0
1. Let Y ABC+ ABD + BCD A+B
=
AB (D+ D)+ AB (C+C)D +(A+ A) BCDD F i g 4.13.2.
ABCD+ ABD + ABCD+ ABCD+ ABCD + C)(B +C+D)

7 A +D)(A +
Y Em(7, 9, 11, 12, 13, 15)

4-12J (Sem-1 & 2)
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Emerging Domain in
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Que 4.14. Simplify the following
Boolean function using AB Group 2
Y= Em(0, 1,3, 5, 6,
Kmap E 00
01 11ÍABCDF)
10
7,9, 11, 16, 18, 19, 20,21, 22, 24, 26) CD NEF AB
Answer
ooi CD00 01 11 10
00
K-map: 01 1 16 7 19 18
Group1 01
ABCDE 000 001 011 010 110 111 101 100
2123 22
11
00 1 1onF EL Group 4 3130
01
Z
24 0
16
8 9i_10
Group 3
CACE) 10A2527
13 25 Group 5 Group 6
7
(BCDF)
11 (BCE) (BCDEF)
15 27 31 cD00o1A 1110 AB
10
00
EO001
CD00_01
32 3335 00
48 49 51 0
Fig. 4.14.1
3637 3938 01
52 5355 54
Y =DEAB+CDB+ +CAB +DB +CDB +CDE + CDA 1 15 1 so 61
DB +CA) +CBD + D) + DEA + AC)+ CD
6362
+DA)
=
=
DBEA +CA) + B(D+)+ DEA ®C)+ CD + DA)
104041
Group 7
4322 1011
56 5759 58
Que 4.15. Simplify the Boolean funetion ABCF

The expression is,
FA, B, C,D, E, F) =
Em(0,5, 7, 8, 9, 12, 13, 23, 24, 25, 28, 29, 37, 40, 42, 44,
46, 55,56, 57, 60, 61) F ABDEF + ABCDF +BCDEF + ACE + BCE +BCDEF+ ABCF
Answer
1. Group 1 and group 2 are two
pairs of l's in the first 16-cell map. PART-3
Introduction to IC Technology: SSI, MSI, LSI, VLSI
2. Group 3 is formed by two isolated l's from first 16-cell
16-cell map. map and third Integrated Circuits.
3. Group 4 is a combination of two quads from first 16-cell and second

16-cell map.
Questions-Answers
4.
Similarly group 5 is a combination of two quads from second 16-cell may
and fourth 16-cell
map. Long Answer Type and Medium Answer Type Questions
5.
Group 6 is again a combination is isolated
16-cell maps. 1's from second and
1ou
6 Finally group 7 is a quad within the third
16-cell map.
ue 4.16.DDefine the term:SSI, MSI, LSI and VLSI.
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Answer
VERY IMPORTANT QUESTIONS
the number of active devices per chip, tha llowing questions are very
Depending upon are
different levels integration:
of may be asked in your important. These question"
SESSIONALS as well as
sSI:
less than
When the active devices per chip
are 100, then it is T
(SS). Most of the SSI chips use inteoec
as small scale integration
transistors.
resistors, diodes and bipolar
.1. Define number system
ii. MSI:
binary number ? and also define signed and unsigned
When the count of active devices per chip is betvween 100 and 1000
Ans Refer Q. 4.1.
then it is referred as medium scale integration (MSI). In most of the
MSI chips, BJTs and enhancement mode MOSPETs are integrated.
9.2. Explain universal gates.
ii. LSI Ans Refer Q. 4.5.
In large scale integration (LS), the number of active devices per chip
ranges between and 100,000. In general, LSI chips use MOS Q.3. Simplify the following expression as much
transistors; as it requires less number of steps for integration. Thus
as
possible:
Flw, x, y, z) j~ + TZ + üxy~ + uwy~
=
more
number of components can be produced on the chip with MOS
transistors than with the bipolar transistors. and implement your result using universal gates only.
Ans Refer Q. 4.7.
iv. VLSI:
When the active devices per chip are over hundreds of Q.4. Simplify the following boolean expression to a minimum
then it is referred as very large scale
thousands,
integration (VLS). Almost all number of literals.
modern chips employ VLSI technique.
i. AC +ABC+ A + AB
v. ULSI:
ii. (+ y +z) +2 + *y + wz
Recently a new level of
integration has been introduced which is known Ans Refer Q. 4.8.
asultra large scale integration (ULSI). In ULSI
one million active
technique, more than
devices are integrated on a single chip. Pentium Q5. Simplify the boolean function.
microprocessors use ULSI technology. F (u, x, y, z) = Em(1,3, 7, 11, 15)
Table 4.16.1. which has the don't care conditions
d (w, a, y, 2) = Ed(0,2, 5)
S. No. Level of integrationa Number of active Ans Refer Q. 4.12.
devices per chip
Small seale
integration (SSI) less than 100
2. Medium scale
integration (MSI) 100 10000
3.
Large scale integration (LSI)
1000 100000
4. Very large scale
integration (VLSI) Over 100000
5. Ultra large scale
integration (ULSI) Over 1 million
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Long Answer Type and Medium Answer Type Questions

Que1.1.Explain semiconductor diode and also draw its

4. The ability of diode to withstand reverse-bias voltage is limited. If the

a certain voltage. When the reverse

conducts a very small amount or

4. Zener current is independent of the appied votage. t tepetie vnty

5. This breakdown is called as zener breakduwn a sauw i Li

Fig. 1.42. V-I characteristic of zener diode. V

Que 1.6. Explain the series diode configuration.

Answer Fig. 1.6.3. Reversing the diode.

For V,>5 V, the díode is reverse-biased and Vo = 0.

Que 1.8. Sketch Vo for given eircuit configuration (Fig. 1.8.1).

VO-ww-H -oVo 0.7 V

0.7VA Apply KCL at node A, I, =1, -1, =

AKTU 2016-17(Sem-D, Marks 05 AC voltage Vo

2n ot Fig 1.10.4. (a) Input waveform (6) Output waveform.

AKTU 2015-16(Sem-1D, Marks15 I ms

ofi, from eq.

' duot) win ot dtot)

v.Ripple factor: The ripple factor is given as

Since, rms 2 and Ipc=I,/n. So, r =1.21 r ACcme

n= Output DC power Ppc r0.482

AnswerT 2.2 koV,ms

converts entire eycle of AC of the AC cycle into

is twice of the maximum maximum value of supplied input. Polarity of V,across

value ofsupplied input. Using voltage divider rule.

determine the peak inverse voltage of each diode.

2.2 k Peak inverse voltage

Using voltage divider rule,

Fig. 1.16.4. (a) Negative clamper with positive bias,

120 V- 99.3 V=-219.3 V.

20 V . 5t 28 ms >> =0.5 ms,

ie., VinD 15 sin (oL)

1. During positive pulse of V, the diode is short circuited. The voltae

2 Circuit-1 is a Doubler (2V,)

Doubler (2V, Fig. 1.28.1. Half wave voltage doubler

cVe 2V (V+ Vca Vc V -2V * = +2V,*" VCi VCI Vm

Voltage C->Ves= 2V,

Voltage across C Vca=

Fig. 1.28.4. Full wave voltage doubler.

and applications. principle of working, con

tachometers, proximity detectors etc.

Que 130.| What is photodiode ? What a r e its different types -Va

(a) E b) Varacter Diodes, Tunnel Diodes,

We see that there is the initial sharp decline in C with increase in

Fig. 131.1. Fig.1.31.3

Discuss the construction and

AKTU 2017-18(Sem-ID, Marks 07

mdy ntal Enpty eates

Filld tnlew" illed atatea Negative resistane

band on number of flled etates in he

Que 1.33.Explain principle

The LCDs are of two types: b. Reflective type

thedynamic scattering type, withthe exception similararii

Emerging Domain in Electronics Engineering 1-47 J (Sem-1&2|

Q.5. Differentiate between halfwave and full wave rectifiers

Q.7. Describe with the help of circuit diagram

Q.8. What is voltage

Q.9. Explain input and output characteristics of

This in thw loft hand neclion of the trannintor.

The middle section of the tranwintor in known an bAne

The naning h av lightly deopel, olertronae ryas the

aw aleetronn (onbna Wilh the holes in