UGRD-CS6201A Architecture and Organization

Final Exam
From: Mark Angelo Carcillar
Score: 50/50

1. Which is NOT TRUE with CISC

- none of the above
2. The actual operand is specified in the instruction itself.
- Immediate mode
3. The two major phase of instruction execution
- instruction fetch phase and execute phase
4. In RISC `,Few addressing mode, and most instructions have register to register
addressing mode
- True
5. Which of the following is NOT a computer operation cycle?
- coding
6. Data manipulation instructions use no address.
- stack architecture
7. in RISC instructions are executed by hardwired control unit
- True
8. Set of complete instructions that the microprocessor executes is termed as
________________
- instruction set
9. Indicates the operand data is stored in the register itself
- Register addressing mode
10. In RISC, not pipelined or less pipelined
- False
11. Program lengths and # of memory accesses tend to be intermediate between the
above two architectures
- register-to-memory architecture
12. Clock speeds are generally measured in
- MHz and GHz
13. Single accumulator architecture, have no register profile
- True
14. A version of displacement addressing
- Relative Addressing
15. Which is not TRUE about Register Addressing
- none of the above
16. Does the opposite, reducing the cycles per instruction at the cost of the
number of instructions per program.
- RISC
17. Which of the following is NOT an Addressing Mode?
- Indirect Addressing
18. In CISC, single register set
- True
19. In RISC simple instructions taking one cycle
- True
20. The effective address of the operand is the contents of a register specified in
the instruction.
- Auto Increment mode
21. CISC
- Complex Instruction Set Computer
22. Which is NOT True about RISC
- Addressing modes are unlimited in number
23. Determines how fast a single instruction can be executed in a processor. The
microprocessor’s pace is controlled by the System Clock. Clock speeds are generally
measured in million of cycles per second (MHz) and thousand million of cycles per
second (GHz).
- system clock speed
24. The effective address of the operand is the output of a register specified in
the instruction.
- False
25. Allow only one memory address
- Register-to-register Architecture
26. Have only control registers such PC
- Memory-to-memory architecture
27. If fetching and executing of instructions is carried out one by one from
successive addresses of memory
- Straight line sequencing
28. In indirect addressing, large address space.
- True
29. In CISC complex instructions taking single cycle
- False
30. The setback of this design is that the computer has to repeatedly perform
simple operations to execute a larger program having a large number of processing
operations.
- RISC
31. The contents of a register specified in the instruction are first automatically
incremented and are then used as the effective address of the operand
- False
32. In RISC, many instructions
- False
33. Memory-to-Memory architecture, all of the access of addressing -> Memory
- True
34. Operand is in memory cell pointed to by contents of register R
- Register Indirect Addressing
35. Memory accesses are restricted to load and store instruction, and data
manipulation instructions are register to register
- RISC
36. In CISC, few instruction
- False
37. Have no register profile
- single accumulator architecture
38. Approach attempts to minimize the number of instructions per program,
sacrificing the number of cycles per instruction.
- CISC
39. Has a constant value or an expression.
- immediate
40. The number of bits processed in a single instruction
- word length
41. Which of the following is NOT the characteristic of microprocessor?
- none of the above
42. Operand is held in register named in address field
- Register Addressing
43. Which is TRUE about Register-to-Register architecture?
- Allow only one memory address
44. Operand is held in register named in address field
- Register Addressing
45. Processors reduce the program size and hence lesser number of memory cycles are
required to execute the programs.
- CISC
46. Stack architecture, data manipulation instructions use one address.
- False
47. Register file: smaller than in a RISC. Control unit: often micro-programmed
- CISC
48. Which is TRUE about implied mode
- The operand is specified implicitly in the definition of the mode
49. RISC
- Reduce Set Instruction
50. Program lengths and # of memory accesses tend to be _______________ between the
above two architectures
- Intermediate

Sources:
https://www.geeksforgeeks.org/difference-between-risc-and-cisc-processor-set-2/
https://study2online.com/question/17152.html
https://study.com/academy/lesson/addressing-modes-definition-types-examples.html