Instruction set architecture defines the abstraction model of a computer.

Classification
of instruction set through architectural complexity. This form of classification
narrows down to two(2) types, thus : Complex instruction set computer (CISC) and
Reduced instruction set computer (RISC).

The Reduced Instruction Set Computer

RISC as the name suggests, is a smaller number of computer given instruction more
than a (CISC), therefore giving it the ability to operate at a higher speed and
performing numerous amount of instructions per second.
In the late 1970s, reduced instruction set computers relied on simple computational
elements to execute most of it’s operations in a single cycle. All computation except
load and store take place in the data path. In line subroutines can be called up for
complex functions and assist processors operates when required for floating point
arithmetic and graphics.
The first popular prototype computer made to use a reduced instruction set computer
architecture was outlined by John Cocke an IBM researcher accompanied by his team
in the late 1970s. Through his work and efforts John Cocke received the Turing award
in 1987.
Due to the ability of each instruction processed in the same amount of time, achieving
pipelining. Through pipelining, set of instructions can be set up line an assembly line
where multiple instructions executes at the same time.

The Complex Instruction Set Computer

Complex instruction set computer is mostly termed as a computing device in

comparison to a reduced instruction set computer may undertake many operations and
take many cycles to execute.
One of the major goal of a complex instructions computer architecture is to be able to
complete a particular task in just a few lines of assembling.
This operation is attained by building a processor that can be able to execute and
understand multiple set of operations. The cisc architecture pays special attention to
hardware. Small code sizes but high cycles execution per second.