Q1.

Write down the algorithm for Booth Multiplication and show the steps
for multiplication of two numbers n1=10 and n2=6.

Ans:

• Booth Multiplication of two numbers n1=10 and n2=6.

Multiplicand(M)=10=(1010)2, Multiplier(Q)=6=(0110)2

Result= 60 = (111100)
Q2. Explain Non-Restoring division algorithm for integer division. Show
the steps for division of two numbers n1=14 and n2=3.

Ans:

⚫ Non-Restoring division algorithm for integer division of two numbers

n1=14 and n2=3.

Divident(Q)=14=(1110)2 , Divisor(M)=3=(0011)2

Quotient 4 and Remainder 2

Q3.A non-pipeline system takes 50ns to process a task. The same task can be processed
in a 6-segment pipeline with a clock cycle of 10ns. Determine the speed up ratio of pipeline
system for 100 tasks. What is the maximum speed up that can be achieved?

Ans:
Time taken by non-pipeline to process a task t n = 50ns
Total time taken by non-pipeline to process 100 task = n t n
= 100 ×
50= 5000ns
For
Pipeline:
Number of segment pipeline k = 6
Time period of 1 clock cycle t p = 10ns
Total time required to complete n tasks in k segment pipeline with tp clock cycle time:
= ( k + n − 1 )t p = ( 6 + 100 − 1 )10 = 1050ns
Speed up Ratio:
When total time taken by the pipeline to process 100 tasks is divided by the total
time required to complete n tasks in k segment pipeline with t p clock cycle time
then speed up ratio is obtained. S =5000/1050
= 4 .76
Q4.A digital computer has a memory unit of 64K×16 and a Cache memory of 1K words.
The Cache uses direct mapping with a block-size of 4 words. Then show how many bits
are there in the tag, index, block and word fields of the address format.

Ans: Main memory has 64K = 64 x 1024 = 2^6 x 2^10 =

2^16 words Cache memory has 1K = 1024 = 2^10
words

The Size of index field of check =10 bits

Tag field use=(16-10)=6 bits

The number of bit required to select each block=8 bit

Word in a block = 10-8 =2 bit
Q5. How many 128×8 RAM chips are needed to provide a memory capacity of 2048
bytes? How many lines of the address bus must be used to access 2048 bytes of memory?

16 ram chips are needed provide a memory capacity of 2048 bytes.

11 bits lines of the address bus must be used to access 2048 bytes of memory.
Q6. Draw the circuit diagram of control unit and explain its operation principle.

Ans:

A control unit works by receiving input information to which it converts into control signals,
which are then sent to the central processor. The computer’s processor then tells the attached
hardware what operations to perform.

Functions of the Control Unit –

➢ It coordinates the sequence of data movements into, out of, and between a processor’s
many sub-units.

➢ It interprets instructions.

➢ It controls data flow inside the processor.

➢ It receives external instructions or commands to which it converts to sequence of control

signals.

➢ It controls many execution units(i.e. ALU, data buffers and registers) contained within a
CPU.

➢ It also handles multiple tasks, such as fetching, decoding, execution handling and
storing results
Q7. Draw the flowchart for instruction cycle and show the register transfer operations
that takes place to execute an instruction.

Ans:

Q8.What is DMA and what is DMA controller? Write down the steps of how CPU
initiates DMA transfer through DMA controller.

Ans: DMA: DMA is a feature of computer systems. It allows input/output (I/O) devices to
access the main system memory (random-access memory), independent of the central
processing unit (CPU), which speeds up memory operations.

DMA controller: The term DMA stands for direct memory access. The hardware device used for direct
memory access is called the DMA controller. DMA controller is a control unit, part of I/O device’s interface
circuit, which can transfer blocks of data between I/O devices and main memory with minimal intervention
from the processor.

The Steps of CPU initiates DMA transfer through DMA controller:

o Primarily, when any device requires to send data between the device
and the memory, the device need to send DMA request (DRQ) to DMA
controller.

o The DMA controller sends Hold request (HRQ) to the CPU and waits
for the CPU to assert the HLDA signal.
 o Then the microprocessor tri-states all the data bus, address bus, and
control bus. The CPU leaves the control over bus and acknowledges
the HOLD request through HLDA signal.

o When the CPU is in HOLD state with the HOLD request, the DMA
controller has to control the operations over buses between the CPU,
memory, and I/O devices.

Q9. Write down the differences between Isolated I/O method and Memory mapped I/O
method.

Ans:

Isolated I/O Memory Mapped I/O

Both have same address space

Memory and I/O have separate
address space

All address can be used by the Due to addition of I/O addressable

memory memory become less for memory

Same instructions can control both

Separate instruction control read I/O and Memory
and write operation in I/O and
Memory

In this I/O address are called ports.

Normal memory address are for
both

More efficient due to separate buses Lesser efficient

Larger in size due to more buses Smaller in size

Simpler logic is used as I/O is also

It is complex due to separate treated as memory only.
separate logic is used to control both.
 Q10. Let X and Y be two successive digits in a certain number system. When written
as (XY), it is equal to (25)D and when written as (YX), it is equal to (31)D. Find the
value of X, Y and the base of the number system.

Ans: Call the base b.

Then we know that bx+y=25, and by+x=31.
Thus (b-1)(y-x)=6.
Since b>0 and |y-x|=1, we now have that y-x=1 and b=7Taking this back into the
simultaneous equations from before, we get 7x+y=25 and 7y+x=31. Solving this, we get
x=3. Hence y=4,base b=7.

Q11. An eight-bit register R contains the binary value 10011101. What will be the
content of the register for (i) arithmetic shift right operation and (ii) arithmetic shift
left operation? State how the overflow is detected during arithmetic shift operation.

Ans: The value in R = 10011101

(i)Arithmetic shift left operation:

1 0 0 1 1 1 0 1

1 1 0 0 1 1 1 0

(ii)Arithmetic shift left operation:

1 0 0 1 1 1 0 1

0 0 1 1 1 0 1 0

Overflow is detected during arithmetic shift operation

An overflow occurs after an arithmetic shift left if initially, before the shift, Rn-1 is not
equal to Rn-2. An overflow flip-flop Vs can be used to detect an arithmetic shift-left
overflow.
Vs = Rn-1 + Rn-2
If Vs = 0, there is no overflow, but if Vs = I, there is an overflow and a sign reversal after
the shift.
Q12.An address space is specified by 24 bits and the corresponding memory space by 16
bits.
Determine the following:(i) How many words are there in the address space and
memory space? (ii) If a page consists of 2K words, how many pages and blocks are
there in the system?

Ans: Address space bits=24bit

Memory space bits= 16 bit

The number of word in memory space is 4096 words.

Q13.Consider the arithmetic expression [Ai+(Bi*Ci)+Di]. Define the pipeline

configuration to carry
out this task. List the content of each register for i=1 to 5.

Ans: I= 1 to 5

Ai Bi CI DI

R1 R2

Multiplier

R4 R3 R5

adder

R6