APARNA PATWAL

Email: aparna.skp@gmail.com
Mob. No.: +91 8510045229 | +91 6392179945

PROFILE SUMMARY
Validation Engineer (Contractual employee)
NXP Semiconductors, Bengaluru
Current Parent Company: Hays Specialist Recruitment Pvt. Ltd., Mumbai
(January 2021 to Present)
Older Parent Company: Randstad India Pvt. Ltd., New Delhi
(August 2020 to December 2020)

• Functional Validation of SPI Interface & protocol

• Power and Performance KPI
• Validation Board Bring-Up
• Pre-Silicon Validation of an I2C Module with FPGA Proto typing and Post Silicon Validation using
Python and RTOS Test Content
• I2C Electrical Characterization and Specification compliance checks
• PVT validation
• Automation for various Clock measurement, boot timing analysis & Power mode timings

INTERNSHIP EXPERIENCE
Worked as Design Engineer Intern at NXP Semiconductors, Bengaluru
(August 2019 to July 2020)
• Developed an automatic I2C bus timing Analyzer tool using Python
• Automation of lab equipment’s using Python (Keysight & Teledyne LeCroy oscilloscope)
• Automation for low power mode timing measurements using Python & performed PVT analysis

EDUCATION
M. Tech. (VLSI & ES) | Defence Institute of Advanced Technology, Pune, Maharashtra | 2020
In association with NIELIT, Calicut (KL) with 7.932 CGPA
B. Tech.(EE) | Dr. APJ Abdul Kalam Technical University, Lucknow, U.P.| 2016 with 76.70%
Senior School Examination (CBSE) | Kendriya Vidyalaya, Mau, U.P.| 2011 with 70.80%
Secondary School Examination (CBSE) | Kendriya Vidyalaya, Bharatpur, Rajasthan | 2009 with 72.20%
SKILLS
Communication Protocols I2C, SPI
Hardware description language Basics of VHDL & Verilog
Programming Languages Python, basics of C, LADDER LOGIC
Layout Tools Cadence EDA Tools (nclaunch, Genus, Innovus), Mentor Graphics-
pyxis, ModelSim-Altera 10.1d, Microwind
HDL Tool Xilinx Ise Design Suite 14.7, VIVADO
FPGA development board Xilinx Spartan 3E
Other Tools Microsoft visual Basic 2010, Nunit, Allen Bradley MicroLogix 1000 PLC
Instruments Proficiency Digital oscilloscope (Keysight & Teledyne LeCroy), Thermostream,
Keithley SMU, Keysight Power supply, Keysight Power Analyzer
Protocol Analyzer Saleae Logic Pro16 Analyzer, Telos I2C Analyser and Interface Tracii XL
2.0 & Telos I2C Negative Tester
Debugger Tool J-link

ACADEMIC PROJECTS
➢ M. Tech Major Project : I2C Bus Timing Parameters Analysis for Master device using Python in Soc
Validation
• Measure all I2C bus timing parameters for all modes (SM, FM, FM+, HSM) automatically using python.
 • Generate reports in excel file format which will show whether timing parameters are satisfying to standard
value for that particular mode or not.

➢ M. Tech. 1st Semester Mini Project : ADC0804 Implementation On FPGA SPARTAN 3E- Board
• Implementation of ADC0804 is 8-bit successive approximation converter in VHDL on Xilinx Ise Design
Suite 14.7
• Done simulation for the same on ModelSim-Altera

➢ B. Tech. Major Project : PLC Based Railway Crossing Barrier and Traffic Light Control
• Objective : To avoid accidents at unmanned railway crossings by making railway crossing system
automatic
• This project is using Allen Bradley MicroLogix 1000 PLC and Sensors

CERTIFICATIONS
• Electronic Board Design & Bring Up | NIELIT, Calicut (IEEE Kerala Section), 2 Days (April 27, 2019 &
April 28, 2019)

• Nuclear Electromagnetic Pulse Course | Defence Institute of Advanced Technology, Pune, 11 Days (Feb.11,
2019 to Feb. 22, 2019)

• Construction Of Turbo Generator | Bharat Heavy Electricals Ltd., Haridwar, 4 weeks (June 16,2015 to July
16 July,2015)

• PLC SCADA (Module 1) | Sofcon India Pvt. Ltd., Lucknow, 4 weeks (June 10,2014 to July 10,2014)

• PLC based railway barrier and traffic light control (Review Paper Pres.) | SSVGI , Bareilly (National
Conference)
ACHIEVEMENTS AND CO-CURRICULAR ACTIVITIES
• Secured First position in B. Tech. with Electrical Engineering & Class Representative of B. Tech. EE Batch
• Awarded with Merit Scholarship by SRMS Trust (2015 & 2016)
• Participated in one day Workshop cum Training Program on Industrial Automation organized by Finetech
Institute of Industrial Automation, Noida
• Organizer in Synergy club during Techvyom (Technical Fest 2014) of SRMSCET, Bareilly.

HOBBIES
Sketching, Painting

PERSONAL DETAILS
Father’s Name : Dr. Shrawan Kumar Patwal Marital Status : Unmarried
Mother’s Name : Mrs. Poonam Patwal Blood group : A +ve
Birthday : August 21, 1994 Nationality : Indian
Gender : Female Language(s) : English, Hindi
Permanent Add. : Katuapura Pashchim, Ganga Pandey Marg, Maunath Bhanjan, U.P. 275101

DECLARATION
I hereby declare that the above-mentioned information is true to the best of my knowledge and belief.

Place: Bangalore, Karnataka APARNA P