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DYPCOE, Akurdi

D. Y. Patil College of Engineering, Akurdi.


Department of Electronics & Telecommunication
Date:

Experiment No: 05
Study of QPSK Transmitter and Receiver.

Aim : To study QPSK Transmitter and Receiver.

Apparatus:- Experiment kit, DSO, Connecting Wires, Probes

Theory:

To transmit digital data on analog lines or even into space, modulation of analog signal is
required. BPSK is a system in which carrier is transmitted for ‘1’ and inverted carrier is
transmitted for digital ‘0’. Here if bit rate is ‘Tb’ then bandwidth required is ‘2Tb’.To reduce this
bandwidth requirement QPSK can be used. For QPSK, bandwidth requirement is ‘Tb’ i.e. half
that of BPSK.

Block Diagram:

Transmitter:

TE E&TC (2019 Pattern) Digital Communication


DYPCOE, Akurdi

Receiver:

In QPSK two consecutive bits are combined to form a symbol and for resulting 4 combinations,
4 different phases of carrier is transmitted. By using D flip-flop type arrangement type, incoming
bit pattern is divided into different bit pattern viz odd pattern and even pattern. Each symbol is
having bit duration of 2Tb seconds.

Odd bit pattern is converted into PSK using sine wave as a carrier. Even bit pattern is converted
into PSK using cosine wave as a carrier. Both the bit patterns are added to give QPSK signal.
Here active edges of odd or even clocks are separated by time Tb. After each ‘Tb’ period but
every bit is there for 2Tb period. So in offset QPSK system the phase changes by 90 degree only.

At receiver, carrier is recovered from QPSK signal itself. This is synchronous reception. To
recover carrier, QPSK signal is passed through band pass filters whose centre frequency is
adjusted to 4 times carrier frequency. In this kit IC1496 is used as analog multiplier.

Then QPSK signal is multiplied by sine wave and cosine waves. As a result we get odd and even
pattern after filtering and integrating multipliers outputs. Now these two patterns are combined to
get original bit pattern. This is done by using analog switch.

TE E&TC (2019 Pattern) Digital Communication


DYPCOE, Akurdi

Procedure:

1. Switch on power supply.

2. Connect clock to input of even and odd clock generator

3. Connect pattern to input of the O & E generator.

4. Connect O.data & E.data to their respective inputs at 1496 multipler.

5. Observe QPSK output.

6. Connect sine and cosine inputs to their respective pins at the receiver end.

7. Observe the regenerated output.

Observation:

Draw the following Waveforms on a graph paper:

1. Input bit pattern


2. Odd and Even data.
3. Sine Wave & Cos Wave
4. BPSK1 and BPSK2.
5. QPSK output.
6. Recovered bit pattern.

Conclusion:

TE E&TC (2019 Pattern) Digital Communication

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