Microprocessors: Microcontrollers

OXFORD
"ICHII tDVCATION
Microprocessors
and
Microcontrollers
Microprocessors
and
Microcontrollers
N Senthil Kumar
Professor
Department of Electrical and Electronics Engineering
Mepco Schlenk Engineering College
Sivakasi, Virudhunagar Dt.
Tamil Nadu
N\ Saravanan
Professor
Thiagarajar College of Engineering
Madurai
Tamil Nadu
S Jeevananthan
Assistant Professor
Pondicherry Engineering College
Puducherry
OXFORD
UNIVERSITY PRESS
OXFORD
UNIVERSITY PRESS
Oxford University Press is a department of the University of Oxford.

It furthers the University’s objective of excellence in research, scholarship,
and education by publishing worldwide. Oxford is a registered trademark of
Oxford University Press in the UK and in certain other countries
Published in India by
Oxford University Press
YMCA Library Building, 1 Jai Singh Road, New Delhi 110001, India
© Oxford University Press 2010
The moral rights of the author have been asserted
First Edition published in 2010

Eighth impression 2013
All rights reserved. No part of this publication may be reproduced, stored in

a retrieval system, or transmitted, in any form or by any means, without the
prior permission in writing of Oxford University Press, or as expressly permitted
by law, by licence, or under terms agreed with the appropriate reprographics
rights organization. Enquiries concerning reproduction outside the scope of the
above should be sent to the Rights Department, Oxford University Press, at the
address above
You must not circulate this book in any other form

and you must impose this same condition on any acquirer
ISBN-13: 978-0-19-806647-7
ISBN-10: 0-19-806647-3
Typeset in Times New Roman

by Trinity Designers & Typesetters, Chennai
Printed in India by Raj Kamal Electric Press, Kundli
To
our parents, teachers
and
to our institutions
N. Senthil Kumar
M. Saravanan
I dedicate this work

to my father Late Mr S. Seenithangam.
S. JEEVANANTHAN
PREFACE
A microprocessor is technically a miniaturized central processing unit (CPU)

of a computer. While it plays a pivotal role in the functioning of a computer, it
requires the support of external components, such as memory and I/O devices, to
perform meaningful tasks. Microprocessors are general-purpose devices that can
be programmed and reprogrammed to perform different sets of tasks. Conversely,
a microcontroller is a chip that not only performs the desired tasks but also has
integrated components, such as memory and I/O ports, as part of its design. Since
it acts as a tiny computer with all its integrated features, a microcontroller is also
termed as ‘computer-on-a-chip’ or ‘system-on-a-chip’. Microcontrollers are used in
applications to perform specific tasks and hence do not require reprogramming.
Advancements in the semiconductor industry led to the introduction of very
fast, high power, and miniaturized integrated circuits (ICs). It also paved way
for the growth of advanced microprocessors and microcontrollers that serve to
perform enviable tasks with unimaginable precision and accuracy. The evolution
of these high speed entities fuelled the growth of many innovative applications,
virtually in every sphere of our lives.
The first microprocessor, 4004, was introduced by Intel in 1971. This 4-bit
microprocessor was developed to be used in a calculator. This first-generation
microprocessor has developed over the years and seen about five generations within
four decades. Technological advancement has taken place in terms of increase in
the size of the data handled, speed of execution, amount of memory interfaced, and
reduction in physical size. Today, there are several processors in the market, from
which designers can select the one that best suits their requirements. It can be said
that the number of personal computers in a developed country is greater than its
human population. In addition, recent statistical reports point out that every house
in a developed country has an average of about 30 processors working hidden in
various domestic appliances.
Microprocessors and microcontrollers have facilitated the execution of
complicated tasks such as automation, precision measurement, and control, in a
simple and effecti ve manner. They are popular today because of their unprecedented
use in almost all areas. Applications of microprocessors and microcontrollers
can be found equally in both complex industrial processes and simple domestic
appliances.
VI PREFACE
ABOUT THE BOOK

This book is the result of the author team’s endeavour to bring forth a comprehensive
learning resource to cater to this extremely important subject in the engineering
curricula. The book covers the important features and applications of different
microprocessors and microcontrollers. The book is written with a view to present
to the readers the internal architecture, programming, system design, and select
interfacing aspects of Intel’s 8085 and 8086 microprocessors, and Intel’s 8051 and
8096 microcontrollers in a student-friendly manner. Since almost all universities
in India offer this subject as an introductory and interdisciplinary course, the
contents of this book have been written in a simple way assuming that the students
have no prior knowledge of this topic. The book would be useful to undergraduate
engineering students of electrical and electronics, electronics and communication,
instrumentation and control, information technology, and computer science and
also to practising engineers.
The book addresses the basic architecture of the microprocessors and
microcontrollers and explains the related hardware and software models of the
selected chips. It covers the programming of Intel microprocessors (8085 and
8086) and microcontrollers (8051 and 8096) and then proceeds to the interfacing
of specific devices with selected processors. The strength of the book lies in the
discussion of a large number of examples on programming and interfacing, which
would offer a vivid understanding of the applications of these chips.
KEY FEATURES
• One-text resource covering the 8085, 8086, and 8051 and an introduction to the
8096 processors
• Exhaustive programming examples (assembly language codes), which would
not only help students hone their programming skills but also allow faculty
members to use select portions for their laboratory
• A section on C programming applied to the 8051 processor
• Application examples (case studies) on traffic light control, thermometer,
elevator control, and washing machine control to appreciate the general design
process
• Simple theoretical questions, programming questions, and application sets
(‘Think and answer’ type questions) at the end of all the relevant chapters
• Extensive coverage of advanced Intel processors including the Pentium
processors, PowerPC, and PIC16F877 microcontroller
• Accompanied by a CD containing ALP codes and simulation-based learning
for select examples discussed in the book
CONTENT AND ORGANIZATION

This book consists of six parts. After a general introduction to microprocessors, the
first part of the book covers the basic hardware details of the 8085 processor with
the related signals and their implications. The second part details the instruction set
PREFACE Vil
and programming of the 8085. The third part explains the hardware and software
details of Intel’s 8-bit 8051 microcontroller series. The hardware and software
details of Intel’s 16-bit microprocessor, the 8086, form the fourth part. The fifth
part includes the details of Intel’s 16-bit microcontroller, the 8096. The last part
covers the recent developments in microprocessor-based systems, other advanced
microprocessors, and the PIC16F877 microcontroller.
Chapter 1 of the book contains an introduction to microprocessors, a list
of various terms related to microprocessor technology, and the evolution of
microprocessors.
Chapter 2 introduces and explains the details of Intel’s 8085 microprocessor,
along with its basic architecture and pin details.
Chapter 3 details the complete instruction set of the 8085 processor and the
related instruction format, addressing modes, and classification.
Chapter 4 discusses numerous 8085 example programs.
Chapter 5 explains the basic data transfer mechanism between the processor
and the peripheral, along with the interrupt structure of the 8085 processor.
Chapter 6 covers the methods of interfacing the memory and input/output
devices with the 8085 processor.
Chapter 7 handles the interfacing of some of the programmable peripheral
devices manufactured by Intel with the 8085 processor.
Chapter 8 gives an overview of a complete 8085-based system, including the
address map, a general microcomputer system, and other supporting devices.
Chapter 9 introduces Intel’s 8-bit microcontroller, the 8051, with details of its
internal architecture and memory organization.
Chapters 10 and 11 cover the software and internal hardware details of the
8051 microcontroller.
Chapter 12 explains the interfacing of the 8051 with a few basic peripherals
and includes numerous solved examples. This chapter also covers RTC interfacing
using the I2C standard.
Chapter 13 introduces the architecture, memory locations, and pin details of
Intel’s 16-bit processor, the 8086.
Chapter 14 discusses the addressing modes, instruction set, and programming
of the 8086.
Chapters 15 and 16 cover the interrupt structure of the 8086 and memory and
I/O interfacing (inclusive of printer and CRT terminal) with the 8086.
Chapters 17 deals with multiprocessor configuration, its advantages, need, bus
arbitration, and interconnection topologies.
Chapter 18 describes complete 8086-based systems.
Chapter 19 presents the basic features of Intel’s 16-bit 8096 microcontroller
series.
Chapter 20 addresses the programming of the 8096 microcontroller.
Chapter 21 details the internal hardware of the 8096.
Chapter 22 discusses the recent trends and developments in microprocessor
technology and the use of high-level language programming with the 8051
microcontroller, along with a few examples in C language.
Vijj PREFACE
Chapter 23 offers a preview of Intel's advanced processors (80186, 80286,

80386, 80486, and Pentium), PowerPC, and the features, architecture, and
programming of the PIC16F877 microcontroller.
Appendices A-E contain the instruction sets of the 8085, 8051, 8086, and
8096 processors, for ready reference. They also contain case studies on washing
machine and elevator control.
IN CHE CD
• Simulator for the 8085 processor, from http://gnusim8085.org. Students can
execute in this simulator the 8085 assembly language codes given in the book.
They can execute each instruction and see how it affects the various registers,
the memory, and the flags. This will help in understanding the instruction sets
and algorithms used in the programming examples.
• Assembly language codes for 8085 from Chapter 4, which can be readily
executed in the simulator
• Assembly language codes for 8051 and 8086, from Chapters 10 and 14,
respectively, which can be run in any executable environment
Students and faculty members are requested to go through the readme.mht file
(autorun enabled), which provides guidelines for installation and utilization of the
simulator.
ACKNOWLEDGEMENTS
The authors acknowledge the authorities of their respective institutions for having
permitted them to embark on this mission and also for providing the necessary
support. Special thanks to Mr Sridhar Ratnakumar, Activestate Software Inc.,
Canada, for having permitted us to use the 8085 simulator developed by him in
the CD accompanying the book. During the course of development of this book,
we were hardly able to spare any time for our families. Their support has made this
book possible. The support rendered by the editorial team of Oxford University
Press is gratefully acknowledged. We would also like to thank all the reviewers
who gave their valuable comments on the manuscript at its draft stage,It is with
devotion that we recall the blessings of the Almighty for having been with us in
our efforts to come out with this book.
While we have tried our best to make the book error-free, readers are encouraged
to write to us with feedback, suggestions, and comments for improving the contents
of the book.
N. Senthil Kumar
M. Saravanan
S.Jeevananthan
BRIEF CONTENTS
Preface v
1. Microprocessors—Introduction and Evolution 1
PART 1: INTEL 8085 ARCHITECTURE AND PROGRAMMING

2. Intel 8085 Microprocessor Architecture 19
3. Instruction Set and Execution in 8085 33
4. Assembly Language Programming of 8085 63
PART 2: HARDWARE INTERFACING WITH INTEL 8085

5. Methods of Data Transfer and Interrupt Structure in 8085 155
6. Interfacing Memory and I/O Devices with 8085 175
7. Features and Interfacing of Programmable Devices
for 8085-based Systems 197
8. A Complete 8085-based System 292
PART 3: INTEL 8051 MICROCONTROLLERS

9. Introduction to 8051 Microcontrollers 303
10. 8051 Instruction Set and Programming 314
11. Hardware Features of 8051 329
12. 8051 Interface Examples 366
PART 4: INTEL 8086—16-BIT MICROPROCESSORS

13. Intel 8086 Microprocessor Architecture, Features, and Signals 419
14. Addressing Modes, Instruction Set, and Programming of 8086 432
15. 8086 Interrupts 485
16. Memory and I/O Interfacing 507
X BRIEF CONTENTS
17. Multiprocessor Configuration 537

18. 8086-based Systems 566
PART 5: INTEL 8096—16-BIT MICROCONTROLLERS

19. Overview of Intel 8096 Microcontrollers 585
20. 8096 Instruction Set and Programming 598
21. Hardware Features of 8096 616
PART 6: ADVANCED TRENDS

22. Microprocessor System Developments and Recent Trends 659
23. Advanced Microprocessors and Microcontrollers 672
Appendix A: 8085 Instruction Set 731
Appendix B: 8051 Instruction Set 735
Appendix C: 8086 Instruction Set 743
Appendix D: 8096 Instruction Set 749
Appendix E: Case Studies 752
Bibliography 760
Index 761
DETAILED CONTENTS
Preface v
1. MICROPROCESSORS—INTRODUCTION AND EVOLUTION 1

1.1 Introduction 1
1.2 Explanation of Basic Terms 2
1.3 Microprocessors and Microcontrollers 5
1.4 Microprocessor-based System 6
1.5 Origin of Microprocessors 7
1.5.1 First generation (1971-1973) 8
1.5.2 Second generation (1974-1978) 8
1.5.3 Third generation (1978-1980) 8
1.5.4 Fourth generation (1981-1995) 8
1.5.5 Fifth generation (1995—till date) 9
1.5.6 Timeline of microprocessor evolution 9
1.6 Classification of Microprocessors 10
1.7 Types of Memory 11
1.8 Input and Output Devices 13
1.9 Technology Improvements Adapted to Microprocessors
and Computers 14
PART 1: INTEL 8085 ARCHITECTURE AND PROGRAMMING
2. INTEL 8085 MICROPROCESSOR ARCHITECTURE 19

2.1 Introduction 19
2.2 Architecture of 8085 20
2.2.1 Arithmetic and logic unit 20
2.2.2 General-purpose registers 21
2.2.3 Special-purpose registers 22
2.2.4 Instruction register and decoder 24
2.2.5 Timing and control unit 24
2.3 Pin Layout and Description of Signals 27
2.3.1 Address and data buses 28
2.3.2 Control and status signals 28
2.3.3 Externally initiated signals 28
2.3.4 Serial I/O signals 29
2.3.5 Power supply and system clock 30
Xl'i DETAILED CONTENTS
2.4 Microcomputer System based on 8085 30

3. INSTRUCTION SET AND EXECUTION IN 8085 33
3.1 Microprocessor Instructions 33
3.2 Classification of Instructions 34
3.2.1 Instruction classification based onfunctionality 34
3.2.2 Instruction classification based on length 35
3.2.3 Addressing modes in instructions 37
3.3 Instruction Set of 8085 40
3.3.1 Format of assembly language instructions and programs 40
3.3.2 Data transfer instructions 41
3.3.3 Arithmetic instructions 44
3.3.4 Logical instructions 46
3.3.5 Branching instructions 48
3.3.6 Machine control instructions 49
3.4 Sample Programs 50
3.5 Instruction Execution and Timing Diagrams 51
3.5.1 Opcode fetch machine cycle 52
3.5.2 Memory read machine cycle 54
3.5.3 Memory write machine cycle 54
3.5.4 I/O read cycle 55
3.5.5 I/O write cycle 56
3.5.6 Timing diagrams for select instructions 56
3.6 De-multiplexing AD0-AD7 59
4. ASSEMBLY LANGUAGE PROGRAMMING OF 8085 63

4.1 Assembler 63
4.1.1 Need and advantages 64
4.1.2 Assembler directives 65
4.2 Assembly Language Programs 66
4.2.1 Programming examples based on simple arithmetic
and logical operations 67
4.2.2 Programming examples based on looping and branching 85
4.2.3 Code conversion, decimal arithmetic, and bit manipulation 123
4.2.4 Programming examples based on subroutine concepts 131
4.2.5 Programming examples based on counters and time delays 136
PART 2: HARDWARE INTERFACING WITH INTEL 8085
5. METHODS OF DATA TRANSFER AND INTERRUPT STRUCTURE IN 8085 155

5.1 Data Transfer Mechanisms 155
5.2 Memory-mapped and I/O-mapped Data Transfer 156
5.3 Programmed Data Transfer 156
5.4 Direct Memory Access 157
5.5 Parallel Data Transfer 158
5.6 Serial Data Transfer 159
DETAILED CONTENTS xiij
5.6.1 Introduction to RS-232 standard 160

5.6.2 Introduction to RS-485 standard 162
5.6.3 GPIB/IEEE 488 standards 163
5.7 Interrupt Structure 165
5.8 Types of Interrupts 165
5.8.1 Vectored and non-vectored interrupts 165
5.8.2 Maskable and non-maskable interrupts 166
5.8.3 Software and hardware interrupts 166
5.9 Interrupt Handling Procedure 166
5.10 Interrupt Sources and Vector Addresses in 8085 167
5.10.1 Software interrupts 167
5.10.2 Hardware interrupts and priorities 168
5.11 Masking of Interrupts 169
5.11.1 SIM instruction 170
5.11.2 RIM instruction 170
5.12 Timing of Interrupts 171
5.13 Interfacing of INTR Interrupt with 8085 172
6. INTERFACING MEMORY AND I/O DEVICES WITH 8085 175
6.1 Introduction 175
6.2 Interfacing Memory Chips with 8085 176
6.2.1 Generation of control signals (MEMR and MEMW)
for memory 176
6.2.2 Interfacing EPROM chip with 8085 177
6.2.3 Interfacing RAM chip with 8085 183
6.2.4 Partial address decoding for memory 186
6.3 I/O- or Peripheral-mapped I/O Interfacing 187
6.4 Memory-mapped I/O Interfacing 190
6.5 Partial Address Decoding for I/O Devices 193
7. FEATURES AND INTERFACING OF PROGRAMMABLE DEVICES
FOR 8085-BASED SYSTEMS 197
7.1 Intel 8255 Programmable Peripheral Interface 197
7.1.1 Features of 8255 197
7.1.2 Block diagram of Intel 8255 198
7.1.3 Operating modes and control words of 8255 199
7.1.4 Programming examples 204
7.2 Interfacing Switches and LEDs 205
7.3 Interfacing Seven-segment Displays 209
7.4 Traffic Light Control 211
7.5 Interfacing Analog-to-digital Converters 214
7.6 Interfacing Digital-to-analog Converters 218
7.6.1 Square wave generation 219
7.6.2 Staircase waveform generation 220
7.6.3 Ramp waveform generation 221
7.6.4 Waveform generation usingstored data 222
XIV DETAILED CONTENTS
7.7 Interfacing Stepper Motors 223

7.8 Interfacing Intelligent LCDs 228
7.9 Keyboard and Display Interface IC 8279 233
7.9.1 Matrix keyboard 234
7.9.2 Multiplexed display 238
7.9.3 Features, block diagram, and pin details of 8279 241
7.9.4 Programming of 8279 242
7.9.5 Display interface using 8279 247
7.9.6 Keyboard interface using 8279 248
7.10 Intel Timer IC 8253 250
7.10.1 Features of IC 8253 250
7.10.2 Block diagram of IC 825*3 and pin details 250
7.10.3 Operating modes and control word of IC 8253 252
7.10.4 Interfacing IC 8253 with 8085 257
7.10.5 Application examples 257
7.11 Introduction to Serial Communication 261
7.11.1 Features and details of 8251 US ART 263
7.11.2 Control words 265
7.11.3 Interfacing 8251 with 8085 267
7.12 8259 Programmable Interrupt Controller 268
7.12.1 Features and architecture of 8259 268
7.12.2 Pin diagram and details of 8259 270
7.12.3 Initialization of 8259 270
7.12.4 Operation of 8259 274
7.12.5 Interfacing 8259 with 8085 275
7.13 8237 DMA Controller 275
7.13.1 Features, pin details, and architecture of 8237 276
7.13.2 DMA initialization and operation 283
7.13.3 Operation of 8237 with 8085 285
8. A COMPLETE 8085-BASED SYSTEM 292

8.2 System Overview 292
8.3 Address Map of General 8085 System 293
8.4 General Microcomputer Systemusing 8085 294
8.5 Other Supporting Devices 298
PART 3: INTEL 8051 MICROCONTROLLERS
9. INTRODUCTION TO 8051 MICROCONTROLLERS 303

9.2 Intel’s MCS-51 Series Microcontrollers 304
9.3 Intel 8051 Architecture 304
9.4 Memory Organization 306
9.5 Internal RAM Structure 307
DETAILED CONTENTS XV
9.5.1 Special function registers 308

9.5.2 Processor status word 309
9.6 Power Control in 8051 311
9.6.1 Idle mode 311
9.6.2 Power down mode 312
9.7 Stack Operation 312
10. 8051 INSTRUCTION SET AND PROGRAMMING 314

10.2 Addressing Modes of 8051 314
10.2.1 Immediate addressing 314
10.2.2 Register direct addressing 314
10,2.3 Memory direct addressing 315
10.2.4 Memory indirect addressing 315
10.2.5 Indexed addressing 315
10.3.5 Bit manipulation instructions 320
10.4 Some Assembler Directives 322
10.5 Programming Examples using 8051 Instruction Set 322
11. HARDWARE FEATURES OF 8051 329
11.2 Parallel Ports in 8051 329
11.2.1 Structure of port 1 330
11.2.2 Structure of ports 0 and 2 331
11.2.3 Structure of port 3 332
11.3 External Memory Interfacing in 8051 334
11.3.1 Program memory interfacing 334
11.3.2 Data memory interfacing 336
11.3.3 Timing diagram for external program and data memory access 337
11.4 8051 Timers 339
11.4.1 Timer SFRs 339
11.4.2 Timer operating modes 341
11.4.3 Timer control and operation 344
11.4.4 Using timers as counters 345
11.5 8051 Interrupts 347
11.5.1 Interrupt sources and interrupt vector addresses 347
11.5.2 Enabling and disabling of interrupts 348
11.5.3 Interrupt priorities and polling sequence 349
11.5.4 Timing of interrupts 350
XVI DETAILED CONTENTS
11.6 8051 Serial Ports

11.6.1 Serial port control SFRs 3$$
11.6.2 Operating modes ^57
11.6.3 Programming serial port 359
12. 8051 INTERFACE EXAMPLES 366

12.1 Interfacing 8255 with 8051 366
12.2 Interfacing of Push Button Switches and LEDs 367
12.3 Interfacing of Seven-segment Displays 369
12.4 Interfacing ADC Chip 371
12.5 Interfacing DAC Chip 373
12.5.1 Square wave generation 374
12.5.2 Staircase wave generation 374
12.5.3 Ramp wave generation 375
12.5.4 Sine wave generation 376
12.6 Interfacing Matrix Keypad 377
12.7 Interfacing Stepper Motor with 8051 380
12.8 Interfacing LCD with 8051 384
12.9 Interfacing DC Motors/Servomotors 388
12.10 Microcontroller Application Example—Stopwatch 391
12.11 Microcontroller Application Example—Traffic light control 393
12.12 Microcontroller Application Example—Thermometer 397
12.13 RTC Interfacing using FC Standard 400
12.13.1 Details of FC bus 401
12.13.2 8051 Subroutines used to implement FC bus 405
12.13.3 DS1307—Serial FC real-time clock IC 407
PART 4: INTEL 8086—16-BIT MICROPROCESSORS
13. INTEL 8086 MICROPROCESSOR ARCHITECTURE, FEATURES,

AND SIGNALS 419
13.2 Architecture of 8086 419
13.2.1 Execution unit 419
13.2.2 Bus interface unit 422
13.3 Accessing Memory Locations 423
13.4 Pin Details of 8086 426
13.4.1 Function of pins common to minimum and maximum modes 426
13.4.2 Function of pins used inminimum mode 428
13.4.3 Function of pins used in maximum mode 428
14. ADDRESSING MODES, INSTRUCTION SET, AND PROGRAMMING OF 8086 432
14.1 Addressing Modes in 8086 432
14.1.1 Register addressing mode 432
14.1.2 Immediate addressing mode 433
14.1.3 Data memory addressing modes 433
DETAILED CONTENTS XVii
14.1.4 Program memory addressing modes 435

14.1.5 Stack memory addressing mode 437
14.2 Segment Override Prefix 438
14.3.4 Flag manipulation instructions 450
14.3.5 Control transfer instructions 451
14.3.6 Shift/rotate instructions 454
14.3.7 String instructions 456
14.3.8 Machine or processor control instructions 457
14.4 8086 Assembly Language Programming 458
14.4.1 Writing 8086 programs using line assembler 459
14.4.2 8086 Assembler directives 465
14.4.3 Writing assembly language programs using MASM 474
15. 8086 INTERRUPTS 485
15.2 Interrupt Types in 8086 485
15.3 Processing of Interrupts by 8086 486
15.4 Dedicated Interrupt Types in8086 488
15.4.1 Type OOH or divide-by-zero interrupt 488
15.4.2 Type 01H, single step, or trap interrupt 488
15.4.3 Type 02H or NMI interrupt 488
15.4.4 Type 03H or one-byte INT interrupt 489
15.4.5 Type 04H or overflow interrupt 489
15.5 Software Interrupts—Types 00H-FFH 489
15.6 INTR Interrupts—Types 00H-FFH 490
15.7 Priority Among 8086 Interrupts 492
15.8 Interrupt Service Routines 492
15.9 Bios Interrupts or Function Calls 499
15.9.1 INT 10H 499
15.9.2 INT 11H 501
15.9.3 INT 12H 502
15.9.4 INT 13H 502
15.9.5 INT 14H 502
15.9.6 INT 15H 502
15.9.7 INT 16H 502
15.9.8 INT 17H 502
16. MEMORY AND I/O INTERFACING 507
16.1 Physical Memory Organization in 8086 507
16.2 Formation of System Bus 508
16.3 Interfacing RAM and EPROM Chips using only Logic Gates 510
XVill DETAILED CONTENTS
16.4 Interfacing RAM/EPROM Chips using Decoder IC and Logic

Gates 514
16.5 I/O Interfacing 517
16.5.1 I/O instructions in 8086 517
16.5.2 I/O-mapped and memory-mapped VO 518
16.6 Interfacing 8-bit input device with 8086 519
16.6.1 Assigning 8-bit address to 8-bit input device using address
decoder having only logic gates 519
16.6.2 Assigning 8-bit address to 8-bit input device using address
decoder IC 74LS138 520
16.6.3 Assigning 16-bit address to 8-bit DIP switch using address
decoder having only logic gates 521
16.7 Interfacing 8-bit Output Device with 8086 521
16.8 Interfacing Printer with 8086 523
16.9 Interfacing 8-bit and 16-bit VO Devicesor Ports with 8086 528
16.10 Interfacing CRT Terminal with 8086 529
17. MULTIPROCESSOR CONFIGURATION 537
17.2 Multiprocessor System—Need and Advantages 538
17.3 Different Configurations of Multiprocessor System 539
17.3.1 Coprocessor and closely-coupled configurations 539
17.3.2 Loosely-coupled configuration 539
17.4 Bus Arbitration in Loosely-coupled Multiprocessor System 540
17.4.1 Daisy chaining 541
17.4.2 Polling 541
17.4.3 Independent requesting 542
17.5 Interconnection Topologies in a Multiprocessor System 543
17.5.1 Shared bus architecture 543
17.5.2 Multi-port memory 543
17.5.3 Linked input/output 544
17.5.4 Crossbar switching 544
17.6 Physical Interconnections Between Processors in
a Multiprocessor System 545
17.6.1 Star configuration 545
17.6.2 Ring or loop configuration 545
17.6.3 Completely-connectedconfiguration 546
17.6.4 Regular topology 546
17.6.5 Irregular topology 546
^•7 Operating System Used in a Multiprocessor System $47
17.8 Typical Multiprocessor System having 8086 and 8087
17.8.1 Architecture of 8087 548
17.8.2 Pin details of 8087 548
17.8.3 Interconnection of 8087 with 8086 550
17.8.4 Data types of 8087
DETAILED CONTENTS XIX
17.9 Typical Multiprocessor System having 8086 and 8089 553

17.9.1 Pin details of 8089 554
17.9.2 Local and remote operation of 8089 556
17.9.3 8089 (IOP) architecture 557
17.9.4 Communication between CPU (8086) and IOP (8089) 561
18. 8086-BASED SYSTEMS 566
18.2 8086 in Minimum Mode Configuration 566
18.2.1 Formation of separate address bus and data bus in 8086 566
18.2.2 Formation of buffered address bus and data bus in 8086 568
18.2.3 Connection of 8284A with 8086 569
18.3 8086 in Maximum Mode Configuration 570
18.4 8086 System Bus Timings 572
18.4.1 Timing diagrams for general bus operation in minimum mode 572
18.4.2 Timing diagrams for general bus operation in maximum mode 576
18.4.3 Interrupt acknowledgement (INTA) timing 577
18.4.4 Bus request and bus grant timing 578
18.5 Design of Minimum Mode 8086-based System 579
PART 5: INTEL 8096—16-BIT MICROCONTROLLERS
19. OVERVIEW OF INTEL 8096 MICROCONTROLLERS 585

19.2 Features of Intel 8096 Microcontroller 587
19.3 Functional Block Diagram of Intel 8096 Microcontroller 587
19.3.1 CPU section 587
19.3.2 8096 CPU buses 589
19.3.3 Register arithmetic and logical unit 589
19.3.4 Temporary register 589
19.3.5 Register file 590
19.3.6 Program status word 591
19.3.7 Memory controller 591
19.3.8 Internal timing 591
19.3.9 I/O section 592
19.4 Memory Structure of 8096 593
19.5 Power Down Mode of CPU 596
20. 8096 INSTRUCTION SET AND PROGRAMMING 598

20.1 8096 Operand Types 598
20.2 Addressing Modes 599
20.2.1 Register direct addressing 599
20.2.2 Indirect addressing 599
20.2.3 Indirect addressing with auto increment 600
20.2.4 Immediate addressing 600
20.2.5 Short-indexed addressing 600
XX DETAILED CONTENTS
20.2.6 Long-indexed addressing 600

20.2.7 Zero register addressing 600
20.2.8 Stack pointer register addressing 601
20.3 Classification of Instructions 601
20.3.2 Arithmetic and logical instructions 601
20.3.3 Shift/rotate instructions 602
20.4 Complete 8096 Instruction Set 604
20.5 Programming Examples using 8096 Instruction Set 608
21. HARDWARE FEATURES OF 8096 616

21.1 Parallel Ports in 8096 and their Structure 616
21.1.1 PortO 616
21.1.2 Port 1 617
21.1.3 Port 2 617
21.1.4 Ports 3 and 4 618
21.2 Control and Status Registers 618
21.2.1 Input/output control register 0 619
21.2.2 Input/output control register 1 619
21.2.3 Input/output status register 0 619
21.2.4 Input/output status register 1 620
21.3 Timers 620
21.3.1 Timer 1 620
21.3.2 Timer 2 621
21.4 Interrupts 623
21.4.1 Interrupt sources 623
21.4.2 Polling routine 624
21.4.3 Vectored interrupt 624
21.4.4 Interrupt control 626
21.4.5 Interrupt pending register 627
21.4.6 Interrupt mask register 628
21.4.7 Global disable 628
21.4.8 Program status word 628
21.5 Serial Ports 629
21.5.1 Operating modes of serial port 630
21.5.2 Serial port control/status registers
631
21.5.3 Determining baud rale
631
21.5.4 Program for serial port data reception
632
21.6 Analog-to-digital Converter
633
21.7 Digital-to-analog Converter
636
21.8 High Speed Input Unit
637
21.8.1 HSI interrupts
640
21.8.2 Programming HSI A/1O
O4v
21.9 High Speed Output Unit
642
DETAILED CONTENTS XXi
21.9.1 HSO status 645

21.10 Memory Expansion 645
21.10.1 Single-chip mode 646
21.10.2 Expanded mode 646
21.10.3 Choice of bus width 647
21.10.4 Bus control 648
21.10.5 ROM/EPROM lock 650
PART 6: ADVANCED TRENDS
22. MICROPROCESSOR SYSTEM DEVELOPMENTS AND RECENT TRENDS 659

22.2 Microcontroller Features and Developments 660
22.3 Microprocessor Development Systems 661
22.3.1 In-system programming 662
22.3.2 Debugger 662
22.3.3 Emulator 662
22.4 Cross Compiler for 8051 663
22.5 Programming 8051 in CLanguage 664
23. ADVANCED MICROPROCESSORS AND MICROCONTROLLERS 672
23.2 80186 Microprocessor 673
23.2.1 Architecture 673
23.2.2 Instruction set of 80186 674
23.3.1 Architecture 675
23.3.2 Register organization and real or protected addressing in 80286 676
23.3.3 Privilege levels in protected mode of operation 679
23.3.4 Descriptor cache or program-invisible registers 681
23.3.5 Accessing memory using GDT and LDT 681
23.3.6 Multitasking in 80286 683
23.3.7 Addressing modes and new instructions in 80286 684
23.3.8 Flag register 685
23.4.1 Architecture of 80386 686
23.4.2 Register organization in 80386 688
23.4.3 Instruction set of 80386 691
23.4.4 Addressing memory in protected mode 692
23.4.5 Physical memory organization in 80386 693
23.4.6 Paging mechanism in 80386 694
23.6 Pentium Microprocessor 700
23.6.1 Architecture of Pentium 700
XXii DETAILED CONTENTS
23.6.2 Protected mode operation of Pentium '05

23.6.3 Addressing modes in Pentium 705
23.6.4 Paging mechanism in Pentium 705
23.7 Other Versions of Pentium 705
23.7.1 Pentium pro processor 705
23.7.2 Pentium 11 processor 706
23.7.3 Pentium III processor 706
23.7.4 Pentium 4 processor 706
23.8 Power PC Architecture 706
23.8.1 Overview of PowerPC 708
23.8.2 PowerPC family members 708
23.8.3 Features of PowerPC 601 (MPC601) 708
23.9 PIC16F877 Microcontroller 710
23.9.1 Features of PIC16F877 710
23.9.2 Pin diagram and block diagram of PIC 16F877 711
23.9.3 Instruction set of PIC16F877 713
23.9.4 Memory organization in PIC16F877 715
23.9.5 Assembly language programming of PIC16F877 718
Appendix A: 8085 Instruction Set 731
Appendix B: 8051 Instruction Set 735
Appendix C: 8086 Instruction Set 743
Appendix D: 8096 Instruction Set 749
Appendix E: Case Studies 752
Bibliography 759
Index 7^1
CHAPTER 1 |
MICROPROCESSORS—
INTRODUCTION AND EVOLUTION
LEARNING OUTCOMES
After studying this chapter, you will be able to understand the following:
• Importance of microprocessors
• Origin and evolution of microprocessors
• Classification of microprocessors and memories
• Common input and output devices for computers
• Bus structures used in computers and technology improvements
1.1 INTRODUCTION
The microprocessor is an electronic chip that functions as the central processing
unit (CPU) of a computer. In other words, the microprocessor is the heart of any
computer system. Microprocessor-based systems with limited resources are called
microcomputers. Today, microprocessors can be found in almost all consumer
electronic devices such as computer printers, washing machines, microwave ovens,
mobile phones, fax machines, and photocopiers and in advanced applications such
as radars, satellites, and flights. Any middle-class household will have about a
dozen microprocessors in different forms inside various appliances. The recent
developments in the electronics industry and the large-scale integration of devices
have led to rapid cost reduction and increased application of microprocessors and
their derivatives.
Typically, basic microprocessor chips have arithmetic and logic functional units
along with the associated control logic to process the instruction execution. Almost
all microprocessors use the basic concept of stored-program execution. Programs
or instructions to be executed by the microprocessor are stored sequentially in
memory locations. The microprocessor, or the processor in general, fetches the
instructions one after another and executes them in its arithmetic and logic unit. So
all microprocessors have a built-in memory access and management part as well
as some amount of memory.
A microprocessor can be programmed to perform any task that can be written
and programmed by the user. Without a'program, the microprocessor unit is
a piece of useless electronic circuit. The programmer must take care of all the
resources of the microprocessor and use them efficiently for implementing the
required functionality. So to work with the microprocessor, it is necessary for the
programmer to know about its internal resources and features. The programmer
2 MICROPROCESSORS AND MICROCONTROLLERS
must also understand the instructions that a microprocessor can support. Every
microprocessor has its own associated set of instructions; this list is given by all
microprocessor manufacturers. The instruction set for microprocessors is in two
forms—one in mnemonic, which is comparatively easy to understand and the other
in binary machine code, which the microprocessor works with and is difficult
for us to understand. Generally, programs are written using mnemonics called
assembly-level language and then converted into binary machine-level language.
This conversion can be done manually or using an application called assembler.
In general, programs are written by the user for the microprocessor to work with
real world data. Data are available in many forms and from many sources. To input
these data to the microprocessor, the microprocessor-based systems need some
input interfacing circuits and some electronic processing circuits. These circuits
include data converters and ports. After processing the real world data, the output
from the microprocessor must be taken out to give to the output devices or circuits.
This again needs interfacing circuits and ports. So a microprocessor-based system
will need a set of memory units and interfacing circuits for inputs and outputs.
The circuits, together with the microprocessor, make the microcomputer system.
The physical components of the microcomputer system are called hardware. The
program that makes this hardware useful is called software.
The semiconductor manufacturing technology for chips has developed from
transistor-transistor logic (TTL) to complementary metal-oxide-semiconductor
(CMOS). Microprocessor manufacturing also has gone through these technological
changes. The other semiconductor manufacturing technology available is emitter-
coupled logic (ECL). TTL technology is most commonly used for basic digital
integrated circuits; CMOS is favoured for portable computers and other battery-
powered devices because of its low power consumption.
1.2 EXPLANATION OF BASIC TERMS

The terms relevant to the use of microprocessors are explained in this section. These
explanations will give the reader an understanding of various microprocessor-
related terms, technologies, and topics.
Chip A chip or an integrated circuit is a small, thin piece of silicon with the
required circuits and transistors etched on it to perform a particular function.
Simpler processors may consist of a few thousand transistors etched onto a silicon
base just a few millimeters square.
Bit A bit means a single binary digit. The bit is also the fundamental storage
unit of computer memory. In binary form, a bit can have only two values, 0 or 1,
whereas a decimal digit can have 10 values, represented by symbols 0 through 9.
Bit size The bit size of a microprocessor refers to the number of bits that can be
processed simultaneously by the basic arithmetic circuits of the microprocessor.
Word A word is a number of bits grouped together for processing. In
microprocessors, a word refers to the basic data size or bit size that can be processed
MICROPROCESSORS—INTRODUCTION AND EVOLUTION 3
by the arithmetic and logic unit (ALU) of the processor. A 16-bit binary number is
called a word in a 16-bit processor.
Memory word The number of bits that can be stored in a register or memory
element is called memory word. Mostly, all memory units use eight bits for their
memory word.
Byte An 8-bit word is referred to as a byte.
Nibble A 4-bit word is referred to as a nibble.
Kilobyte A collection of 1024 bytes is called a kilobyte (210 bytes).
Megabyte A collection of 1024 kilobytes is called a megabyte (220 bytes).
RAM or R/W memory Random access memory or read/write memory is a type
of semiconductor memory in which a particular memory location can be erased
and written with new data at any time. These memory units are volatile, which
means that the contents of the memory are erased when the power to the chip is
disrupted. The access of the individual memory location can be done randomly. In
microprocessors, the RAM is used to store data.
DRAM Dynamic random access memory is a semiconductor memory in which
the stored contents need to be refreshed repeatedly at about thousands of times per
second. Without refreshing, the stored data will be lost. These memory chips are
preferred in a computer system as these are slower but economical.
SRAM Static random access memory chips keep the data stored in it as long as
power is available. There is no need for refreshing. In terms of speed, SRAM is
faster.
ROM Read only memory devices are memory devices whose contents are
retained even after removing the power supply.
Arithmetic and logic unit ALU is a digital circuit present in the microprocessor
to perform arithmetic and logic operations on digital data. The typical operations
performed by the ALU are addition, subtraction, logical AND, logical OR, and
comparison of binary data. Generally, the functions of the ALU of a microprocessor
will decide the processor’s functionality.
Microcontroller A microcontroller is a chip that includes microprocessor,

memory, and input/output signal ports. Microcontrollers can be called single-chip
microcomputers.
Microcomputer The system formed by interfacing the microprocessor
with the memory and I/O devices to execute the required programs is called
microcomputer.
Bus A bus is a group of wires/lines that carry similar information.
System bus The system bus is a group of wires/lines used for communication
between the microprocessor and peripherals.
Firmware Software written for a microprocessor application without provision

for changes is called firmware. These are stored in the permanent storage or ROM
of the computer system.
Input device The devices that are used for providing data and instructions to the
microprocessor or microcomputer system are called input devices. Keyboard and
mouse are the common input devices.
Output device The devices that are used for transferring data out of the
microprocessor or microcomputer system are called output devices. Display
screen, printer, and other forms of display are the common output devices.
Floppy disk A removable-type magnetic disk used for storing programs and
data for transferring from and to the computer is called floppy disk.
Disk drive The hardware component that is used to read or write data to devices
such as floppy disks is called disk drive.
Computer architecture The design, internal configuration, and accesses in a
digital computer are together called computer architecture.
Von-Neumann architecture The architecture in which the same memory is
used for storing programs as well as data.
Harvard architecture The architecture in which programs and data are stored
in two separate memory units.
CISC processor Complex instruction set computer is a processor architecture
that supports many machine language instructions.
RISC processor Reduced instruction set computer is a processor architecture
that supports limited machine language instructions. RISC processors are expected
to execute the programs faster than CISC processors.
High-level language A computer programming language in which programs
are written without the knowledge of the processor in which the program will
be executed. BASIC, Fortran, C, Pascal, and Java are examples of high-level
languages.
Assembly language A programming language written using the mnemonics
or the instruction set of a particular microprocessor is called assembly language.
Assembly language programming is microprocessor-specific. It is not as easily
understood as a high-level language program, but is easier than a machine language
program.
Machine language Machine language refers to binary code programs that are
specific to the processor and can be directly executed by the processor. Machine
language is the lowest level language and cannot be easily understood.
Assembler A computer application program that converts the assembly language
program into machine-level language program.
Compiler A computer program that converts the high-level language program
into machine-level language program.
Interpreter A computer program that reads the high-level or assembly-level

program one line at a time and converts it into machine-level program. Compiler
and assembler can function only on the entire program in a file.
Algorithm A sequence of operations or instructions that defines how to solve a
problem using a computer or microcomputer. An algorithm must be definite, must
follow a clear instruction flow without ambiguity, and must have definite start and
end points.
BIOS Basic input/output system is a set of programs that handles the input
and output functions and interacts with the hardware directly. A new hardware
installed must be provided with the corresponding BIOS routines.
Clock The circuit in the computer that generates the sequence of evenly spaced
pulses to synchronize the activities of the processor and its peripherals is called
clock. The clock speed determines the speed of the operation of the computer. The
computer with a high frequency clock works faster. Normally the clock frequency
is in the range of megahertz (MHz) or gigahertz (GHz).
MIPS Million instructions per second is a measure of the speed at which the
instructions are executed in a processor.
Tri-state logic It is the logic used by digital circuits. The three logic levels used
are high (1), low (0), and high impedance state (Z). The logic high state of a digital
circuit can source current and the logic low can sink current in a computer system,
but the high impedance state neither sources nor sinks current and so the other
devices connected to it are not affected.
Operating system The program that controls the entire computer and its
resources and enables users to access the computer and its resources is called
operating system. It is required for any computer system to become operational and
user friendly. Under the control of the operating system, the computer recognizes
and obeys commands typed by the user. In addition, the operating system provides
built-in routines that allow the user’s program to perform input/output operations
without specifying the exact hardware configuration of the computer. In low-level
microprocessor-based systems, the program that controls the hardware is called
monitor routine or monitor software.
1.3 MICROPROCESSORS AND MICROCONTROLLERS

The microprocessor (also called CPU) is the principal element of a computer
as it executes lists of instructions. These instruction lists are commonly called
programs. This programming language is complex to use since it is machine- or
processor-specific and coded into hexadecimal and binary.
Two types of processors are manufactured—the microprocessor and the
microcontroller. At the data processing level, the two are practically equivalent.
The distinction comes from the established functionalities.
The general-purpose microprocessors give the computers all the necessary
computing power. These microprocessors need additional circuitry elements such
as memory devices and I/O ports to connect the input and output devices. All
microprocessor-based systems need two types of memories—RAM and ROM.
RAM is used for storage of data while ROM is used for storage of programs,
especially the start-up program that runs when the microprocessor is powered on.
There are numerous microprocessors developed by many companies. The
evolution of microprocessors, from4-bit microprocessors to 64-bit microprocessors,
has been discussed later in this chapter. This book is devoted to the discussion
of two groups of microprocessors— Intel’s 8-bit 8085 microprocessor series and
16-bit 8086 series.
Microcontrollers are microprocessors designed specially for control applications.
Microcontrollers contain memory units and I/O ports inside a chip, in addition to
the CPU. Microcontrollers are otherwise called embedded controllers; they are
generally used to control and operate smart machines. Some of the machines using
microcontrollers are microwave ovens, washing machines, sewing machines,
automobile ignition systems, computer printers, and fax machines. You will be
amazed to know that out of 100 processor chips manufactured, 99 are embedded
processors; only one goes into a general computer! A plethora of semiconductor
companies are in the microcontroller market and any application development
engineer is flooded with a variety of microcontrollers to choose from. This book
is confined to Intel’s 8-bit 8051 series and 16-bit 8096 series microcontroller
families.
1.4 MICROPROCESSOR-BASED SYSTEM

A computer system developed using a basic general-purpose microprocessor is
called a microcomputer system. The system consists of CPU, memory, and I/O
ports as shown in Fig. 1.1.
' ■ ■ ’ ■ ■- ■■ ■■ ■ -
Fig. 1.1 Microcomputer system (Von-Neumann model)
Figure 1.2 shows a typical personal computer system. The interfacing of the
processor with the other parts of the microcomputer system needs a three-bus
architecture. The three buses are data bus, address bus, and control bus.
Each memory location or I/O port is identified by a specific address similar to
a postal address. In microprocessor systems, the addresses are all in binary, and in
general, represented in hexadecimal number format. The address is a unique pattern
used to identify a location in the memory

or an I/O port. The address bus consists of
many lines that transport the digital data
sent by the processor. An address bus of
eight bits corresponds to eight lines of
addresses and can thus address 28 different
memory locations. These addresses are
written in hexadecimal number format
as OOH-FFH and can be used to for 256
different locations. Similarly, the 16-
bit address bus can address 2'6 different
addresses. Its address range is 0000H-
FFFFH. The greater the number of lines in the address bus, the greater the number
of locations the processor is able to manage.
The address on the address bus can locate a specific memory or VO location.
After selecting the location, the data transfer between the memory and processor
or between the I/O device and the processor is done through the data bus. The
width of the data bus determines the data size that can be transferred. An 8-bit
processor will generally have an 8-bit data bus and a 16-bit processor will have
a 16-bit data bus. The memory locations in microprocessors are accessed as
8-bit or one-byte units only. So the transfer of a 16-bit data from memory needs two
memory addresses. A 1 KB memory chip will have 1024 bytes of memory locations.
A control bus is needed for proper data transfer between the processor and
the peripherals. The control bus basically consists of signals for selection of the
correct memory or VO device from the address, indication of the direction of data
transfer, and synchronization of data transfer between slow devices. Many of
the control signals are given by the processor itself because the processor is the
master of the control system. Some control signals such as selection of the correct
memory chip can be generated externally by the logic circuits. The timing of the
control signal is very important; the entire timing of the operation is controlled by
the microprocessor in synchronization with the clock signal input.
1.5 ORIGIN OF MICROPROCESSORS

The microprocessor is the greatest invention of the 20th century. Its evolution started
from the earlier mechanical calculating devices, in the 1930s. These devices used
mechanical relays. Later, in the 1950s, these devices were replaced by vacuum
tubes. The vacuum tubes were quickly replaced by transistors. The breakthrough
in transistor technology led to the introduction of minicomputers in the 1960s and
the personal computer revolution in the 1970s.
The transistor technology led to the development of complex devices called
integrated circuits (ICs). The microprocessor, or microprocessing unit (MPU),
later evolved as an IC and was designed to fetch instructions and execute the
predefined arithmetic and logic functions. Intel was the first MPU producer and
has been holding a large share of the world market for this product. The evolution
ol microprocessors is categorized into five generations: first, second, third, fourth,

and fifth.
1.5.1 First Generation (1971-1973)

The microprocessors that were introduced from 1971 to 1973 were referred to
as the first-generation systems. First-generation microprocessors processed
their instructions serially—they fetched the instruction, decoded it, and then
executed it. The first microprocessor, the 4004, was introduced in 1971. It was
co-developed by Busicom, a Japanese manufacturer of calculators, and Intel, a US
manufacturer of semiconductors. The 4-bit 4004 microprocessors ran at 108 kHz
and contained 2300 transistors. They were fabricated using p-channel metal -
oxide-semiconductor (PMOS) technology, which provided low cost, slow speed,
and low output currents. They were not compatible with TTL. In 1972, Intel made
the 8-bit 8008 and 8080 microprocessors.
1.5.2 Second Generation (1974-1978)

As the technology evolved, the number of circuits that could be fabricated on a
chip grew. Very large-scale integration (VLSI) led to chips that had speeds up to
hundreds of millions of switchings per second. The second generation marked the
beginning of very efficient 8-bit microprocessors. Some of the popular processors
were Motorola’s 6800 and 6809, Intel’s 8085, and Zilog’s Z80. The second-
generation devices marked a sharp contrast with the use of newer semiconductor
technology to fabricate chips. They were manufactured using n-channel metal-
oxide-semiconductor (NMOS) technology. This technology offered faster speed
and higher density than PMOS. It resulted in a five-fold increase in instruction
execution speed and higher chip densities.
1.5.3 Third Generation (1978-1980)

The third generation, introduced in 1978, was dominated by Intel’s 8086 and
Zilog’s Z8000, which were 16-bit processors with minicomputer-like performance.
These processors had the technology of 16-bit arithmetic and pipelined instruction
processing. The third generation came with IC transistor counts of about 250,000.
In Motorola’s MC68020, for example, an on-chip cache was incorporated for the
first time and the depth of the pipeline was increased to five or more stages. It was
designed using high density metal-oxide-semiconductor (HMOS) technology.
HMOS provides some advantages over NMOS: Its speed-power product is four
times belter than that of NMOS; it can accommodate twice the circuit density of
NMOS.
1.5.4 Fourth Generation (1981-1995)

The microprocessors entered their fourth generation with designs containing more
than a million transistors in a single package. This era marked the beginning of 32-
bit microprocessors. Intel introduced 80386 and Motorola introduced 68020/68030.
They were fabricated using high density/high speed complementary metal-oxide-
semiconductor (HCMOS), a low-power version of the HMOS technology.
1.5.5 Fifth Generation (1995—till date)

The fifth generation microprocessors employ decoupled super scalar processing
and their design contains more than 10 million transistors. This generation marks
the introduction of devices that carry on-chip functionalities. It has also paved
the way for high speed memory I/O devices along with the introduction of 64-
bit microprocessors. Intel leads the show here with Pentium, Celeron, and very
recently, dual- and quad-core processors working with up to 3.5 GHz speed. This
generation is characterized by a low-margin single-microprocessor PC business,
which is complemented by high-volume sales. Table 1.1 gives the comparison of
the major processors based on specific parameters such as clock speed and data
word size.
Table 1.1 Comparison of general-purpose processors
General-purpose processors Transistors CPU speed Data length (bits)
8080 6,000 2 MHz 8

8085 6,500 3 MHz 8
8088 29,000 3 MHz 16
8086 30,000 4 MHz 16
80286 1,34,000 6 MHz 16
80386 2,75,000 16 MHz 16/32
80486 12,00,000 33 MHz 16/32
Athalon XP 37,00,000 2.8 GHz 16/32/64
Celeron 75,00,000 1.06-2 GHz 32
Pentium II 75,00,000 233^150 MHz 32
Pentium III 95,00,000 450 MHz-1 GHz 32
Pentium III Xeon 2,81,00,000 500 MHz-1 GHz 32
Pentium 4 5,50,00,000 1.4-2.2 GHz 32
IBM PowerPC G3 65,00,000 233-333 MHz 32
PowerPC G4 1,05,00,000 400-800 MHz 32
1.5.6 Timeline of Microprocessor Evolution

(i) 1971—Intel 4004 microprocessor with 2300 transistors, working at a speed
of 108 kHz
(ii) 1971—Intel 8008, twice as powerful as the 4004, with 3500 transistors and
speed of 200 kHz
(iii) 1974—Intel 8080 processor with 6000 transistors and speed up to 2 MHz
(iv) 1976—Intel 8085 processor with about 6500 transistors and speed of
3-5 MHz came into existence. There were multiple versions of 8085
microprocessors. The original version of the 8085 microprocessor without
suffix A was manufactured by Intel. It was quickly replaced with the 8085A,
which had a bug-fixer. A few years later, in the 1980s, Intel introduced
the 8085AH, the HMOS version of 8085A followed by the 80C85A, the
CMOS version of the 8085A.
(v) 1978—Intel 80X86 families of microprocessors. The first generation of the

80X86 families included the 8086 and the 8088. It was followed by the
80186, 80286, 80386, and 80486.
(vi) 1979—Intel 8088, which was similar in architecture to the 8086; the
difference was in the available number of data bits of the data bus. Number
of transistors: 29,000; speed: 5 MHz, 8MHz, 10 MHz
(vii) 1985—Intel 80386, the first 32-bit chip that contained 275,000 transistors,
processing five million instructions per second, and running all popular
operating systems, including Windows.
(viii) 1989—Intel 486 with an 8 KB cache memory (shared for data and
instructions), operating at clock frequencies from 25 to 100 MHz
(ix) 1993—Intel Pentium processor retains the 32-bit address bus of the 80486
but doubles the data bus to 64 bits. It includes two 8 KB cache memories—
one for instructions and the other for data. It was based on dual pipeline
method known as superscalar architecture and currently operates with
frequencies up to 1.75 GHz, 20-stage pipeline, and three-level cache
memory architectures.
(x) 1997—Intel Pentium II processor was designed specifically to process video,
MMX audio, and graphics data efficiently with speeds of200 MHz, 233 MHz,
266 MHz, and 300 MHz.
(xi) 1999—Intel Celeron processor and Intel Pentium III processor
(xii) 2000—Intel Pentium 4 processor
Various other companies such as Motorola, NEC, Mitsubishi, Siemens,
AMD, Toshiba, and Texas Instruments also manufacture processor chips. These
companies have their own chips and architectures in addition to the regular Intel
based architectures.
1.6 CLASSIFICATION OF MICROPROCESSORS

Microprocessors can be classified based on their specifications, applications, and
architecture.
Based on the size of the data that the microprocessors can handle, they are
classified as 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit microprocessors.
Based on the application of the processors, they are classified as follows:
(i) General-purpose processors
(ii) Microcontrollers
(iii) Special-purpose processors
General-purpose processors are those that are used in general computer system
integration and can be used by the programmer for any application. Common
microprocessors from Intel 8085 to Intel Pentium are examples of general-purpose
processors. Microcontrollers are microprocessor chips with built-in hardware
for the memory and ports. These chips can be programmed by the user for any
generic control application. Special-purpose processors are designed specifically
to handle special functions required for an application. Digital signal processors

are examples of special-purpose processors; these have special instructions to
handle signal processing. Application-specific integrated circuit (ASIC) chips are
also examples of this category of microprocessors.
Based on the architecture and hardware of the processors, they are classified as
follows:
(i) RISC processors
(ii) CISC processors
(iii) VLIW processors
(iv) Superscalar processors
RISC is a processor architecture that supports limited machine language

instructions. RISC processors can execute programs faster than CISC processors.
CISC processors have about 70 to a few hundred instructions and are easier to
program. However, CISC processors are slower and more expensive than RISC
processors. Very long instruction word (VLIW) processors have instructions
composed of many machine operations. These instructions can be executed in
parallel. This parallel execution is called instruction-level parallelism. VLIW
processors also have a large number of registers. Superscalar processors use
complex hardware to achieve parallelism. It is possible to have overlapping of
instruction execution to increase the speed of execution.
1.7 TYPES OF MEMORY

Memory unit is an integral part of any microcomputer system. Its primary purpose is
to hold program and data. The main objective of the memory unit design is to enable
it to operate at a speed close to that of the processor. Although technology is available
to design such a high speed memory, cost is the major limiting factor. To strike a
balance between cost and operating speed, a memory system is usually designed
using different materials such as solid state, magnetic, and optical materials.
A microcomputer memory can be logically divided into four groups:
(i) Processor memory/register
(ii) Cache memory
(iii) Primary or main memory
(iv) Secondary memory
Processor memory refers to a set of CPU registers. Processor registers are the
first set of storage devices available for the programmers to store any data, but
they are generally few in number—up to a few tens or hundreds. As these registers
are available within the processor, they are the fastest memory registers. The main
disadvantage is the cost involved, which restricts the number of registers and their
bytes.
Cache memory is the fastest external memory; it is placed close to the processor.
The instructions to be executed are placed in the cache memory for access by
the processor. These are a few kilobytes in size. Cache memory contains volatile
semiconductor RAMs. The processor fetches instructions from the cache memory
and if an instruction is not in cache, it refers to the primary memory.
Primary memory is the storage area from which all the programs are executed.
All the programs and corresponding data for execution must be within the primary
memory. The primary memory is much larger than the processor memory and the
cache memory but its operating speed is slower. The primary memory in a system
varies from few KB to a few MB.
Secondary memory refers to the storage medium for huge files such as program
source codes, compilers, operating systems, etc. These are not accessed directly or
very frequently by the microprocessor in a computer system. Secondary memory
consists of slow devices such as magnetic tapes and optical disks. Sometimes, they
are referred to as auxiliary or backup store. Stored information in a magnetic tape
or magnetic disk is not lost when power is turned off. Therefore, these storage
devices are called non-volatile memories.
Classification of primary memory Primary memory normally includes ROM
and RAM, which are further classified as shown in Fig. 1.3. Microprocessor-based
systems have at least one RAM and one ROM chip.
Primary memory
Semiconductor RAM ROM
Static Dynamic Mask OTP EPROM EEPROM Flash

PROM ROM memory
Fig. 1.3 Classification of primary memories
RAM devices allow both reading and writing to their memory cells. In static
RAM devices, bits are stored as the status of on/off switches. There are no charges
involved and hence, no charges to leak. However, static RAM devices have complex
construction and hence larger size per unit storage. So they are more expensive.
Static RAMs are comparatively faster and are used in cache memories.
In dynamic RAM devices, the data bits are stored as charge in capacitors. Since
capacitor charge has a tendency to leak, these devices need refreshing even when
they are powered. However, they have simpler construction and smaller size per
unit storage. These devices are less expensive and comparatively slower.
As the name implies, a ROM permits only read access. There are many kinds
of ROMs:
(i) Mask programmable ROMs (MPROMs) are custom-made for the customer;
their contents are programmed by the manufacturer. Since they are mass
produced, they are inexpensive. The customer cannot erase or program it
afterwards.
(ii) Programmable ROMs (PROMs) or one-time programmable (OTP) ROMs

are devices that can be programmed by the user in his/her place using
special equipments. The main disadvantage of PROMs is that they cannot
be erased and reprogrammed.
(iii) Erasable and programmable ROMs (EPROMs) allow the erasure and
reprogramming of the content by the user. In an EPROM, programs are
entered using electrical impulses and the stored information is erased using
ultraviolet rays.
(iv) Electrically erasable PROMs (EEPROMs) or electrically alterable ROMs
(EAROMs) allow the users to electrically erase and reprogram its contents.
EEPROMs are different from RAMs in that electrical signals are required
to erase and program them. EEPROMs require a higher voltage for erasing
and programming than the normal 5 V supply.
(v) Flash memory devices are a group of single transistor cell EPPROMs. Cell
sizes are about half the size of a two-transistor EEPROM. The operation
requires bulk erasure of a large portion of the memory array.
1.8 INPUT AND OUTPUT DEVICES

Input and output devices permit the user to feed data to the computer and retrieve
the computed result from it. Sometimes, the input and output devices can
communicate among themselves. In general, computer systems have I/O ports;
I/O devices are connected to these ports for data transfer. Basically, the ports are
digital registers that allow the computer to transfer data between the I/O devices
using additional control signals. These control signals allow error-free transfer of
data.
The common input device used in almost all systems is the keypad.
Microprocessor-based basic microcomputer systems use simple numeric keypads.
However, advanced computer systems use keyboards with a large number of keys
involving alphabets, numbers, and special characters. Nowadays, a number of
optical devices and scanners such as mouse, joystick, and bar code scanners are
also being used as input devices. Microcomputer systems also use different types
of sensors for data input. These sensors need data converters such as analog to
digital converters. Any introductory course on microprocessors should cover the
interfacing of data converters, keypads, and switches.
An output device is a device through which the user can receive the results from
the computer. The output can be a rapidly changing display or printed material.
Other forms of output are sounds and alarms. The simplest output devices, used in
almost all microprocessor-based systems and computer systems, are LEDs, seven
segment LED displays, and LCD displays. The advanced video display terminals
(either cathode-ray tubes or LCDs) and ink-jet and laser printers are the common
output devices nowadays. Some output devices can be used to directly control
machineries. Some devices, such as display terminals with touch screen, may
provide both input and output. Modems and other network interface cards can
also be called output devices as they enable the transmission and reception of data
between computers.
1.9 TECHNOLOGY IMPROVEMENTS ADAPTED TO MICROPROCESSORS

AND COMPUTERS
Technological improvements are taking place rapidly in microprocessor,
microcomputer, and personal computer systems. Some of these improvements are
listed here:
(i) Increase in data bus/address bus width: The processing capability of the
microprocessor can be drastically improved by increasing data size. This
development can be seen clearly from the advancements in microprocessors
(Section 1.5).
(ii) Increase in speed: As the data to be processed by the microprocessors and
computers increased in volume, it became necessary to increase the speed of
the processor. With high speed processors, the user can get results quickly,
even with large data volumes.
(iii) Reduction in size and increase in capability: The trend in microprocessor
technology is to include a large number of peripherals such as memory and
I/O ports within a single chip. Microcontrollers are manufactured in this
fashion. In addition, developments in large scale integration have led to the
manufacture of small microprocessor chips with large built-in peripherals.
Processors with a large amount of flash memory are now available in the
market.
(iv) Development of external peripherals: The use of computers in all fields have
resulted in the development of many fast and advanced peripheral devices.
For example, the application of microprocessors in medicine has resulted
in the development of many handheld electronic devices with specialized
input sensors, output printers, etc. Faster peripherals can increase the speed
of processor execution and provide a good user interface.
(v) Increase in memory unit size and speed: The developments in IC technology
have led to a reduction in the size of the memory units and an increase in
memory speed. This reduces the memory access time of the processor and
results in higher speed of execution. More amount of memory per unit area
is possible.
(vi) Microprocessors are largely used in handheld devices operated from a
battery source. This has resulted in research on the reduction of power
consumption in microprocessor chips. As power consumption is reduced,
these devices work for more time once the batteries are fully charged. There
are many devices operating at 3.3 V or even lower voltages and have low
power consumption.
POINTSTOREMEMBER’
• The microprocessor is an electronic circuit that functions as the central processing unit
(CPU) of a computer, providing computational control.
• The microprocessor is the controlling element in a computer system. The microprocessor
performs data transfers, does simple arithmetic and logical operations, and makes simple
decisions.
• The basic operation of the microprocessor is to fetch instructions stored in the memory
and execute them one by one in sequence.
• Microprocessors are used in almost all advanced electronic systems.
• Microcontrollers are advanced forms of microprocessors, with memory and ports
present within the chip.
• A microcomputer system is made by interfacing memory and I/O devices to a
microprocessor.
• Microprocessor evolution is classified into five generations. The processors that are
currently in use belong to the fifth generation.
REVIEW QUESTIONS/
1. What is the main function of a computer?

2. Name any three input devices of a computer.
3. Name any two output devices of a computer.
4. Name any three storage devices of a computer.
5. Name any three places where computers can be used.
6. Draw a block diagram of a computer and label its components.
7. Who developed the world’s first microprocessor?
8. What is the data bus width of the 8085 microprocessor?
9. When did Intel introduce the Pentium 4 microprocessor?
10. What is the amount of memory that the Pentium 4 processor can address?
11. What are the basic units of a microprocessor?
12. What is the function of microprocessor in a system?
13. How many memory locations can be addressed by a microprocessor with 14 address
lines?
14. Name any two types of memories that are used in a computer.
15. Define computer hardware.
16. Define computer software.
17. What is the role of CPU in a computer?
18. What are input and output devices?
19. Describe and draw the diagram of Von-Neumann model.
20. Define the following abbreviations: CPU, RAM, and ROM
Part 1
---------------------- ---------------------------------
INTEL 8085
ARCHITECTURE AND
PROGRAMMING
Chapter 2: Intel 8085 Microprocessor Architecture
Chapter 3: Instruction Set and Execution in 8085
Chapter 4: Assembly Language Programming

of 8085
CHAPTER 2
INTEL 8085 MICROPROCESSOR

ARCHITECTURE
LEARNING OUTCOMES
♦ Pin details and layout of the 8085 microprocessor
• Internal functional operation of the 8085 microprocessor
• Flag register and the purpose of each flag bit
• Purpose of the registers, accumulator, and system bus used in the 8085 microprocessor
2.1 INTRODUCTION
The microprocessor is a semiconductor device consisting of electronic logic
circuits manufactured using either large-scale integration (LSI) or very large-scale
integration (VLSI) technique. It basically contains registers, an arithmetic and
logic unit, flip-flops, and timing and control circuits. All microprocessors work
using Von-Neumann architecture. In this architecture, the CPU or the processor
fetches instructions from the memory, decodes it (i.e., interprets the nature of
the instruction/command and develops clock-synchronized steps for execution),
generates appropriate control signals, and finally executes it. The program is
stored in consecutive memory locations. The execution steps are repeated for all
the instructions of the program until the execution is terminated by hardware or
software. The data required may be taken either from memory or from input ports;
the results of the program may be either stored in the memory or transferred out
through output ports.
A program is a list of instructions for the microprocessor to execute. Before
the start of execution, the complete program must be stored in the memory. Let us
assume that the starting address of the stored program is 88OOH. While running
the program, the microprocessor must be directed to ‘go’ from 88OOH. Once it has
executed the instruction in 88OOH, it goes to the next address 8801H (assuming
single-byte instructions) and so on until it reaches the end of the program.
Intel 8085 is an 8-bit microprocessor manufactured by Intel Corporation and
is usually called a general-purpose 8-bit processor. It is upward compatible with
microprocessor 8080, which was Intel’s earlier product. There are several faster
versions of the 8085 microprocessor such as 8085AH, 8085AH-1, and 8085AH-2.
A microprocessor system consists of three functional blocks—central
processing unit (CPU), input and output units, and memory units, as shown in
Fig. 2.1. The CPU contains several registers, an arithmetic and logic unit (ALU),
Memory
Processor
Fig. 2.1 A microprocessor system
and a control unit. The function of ALU, as the name implies, is to perform
arithmetic and logical operations. The control unit translates the instructions and
executes the desired task.
2.2 ARCHITECTURE OF 8085

The block diagram explaining the architecture of Intel 8085 microprocessor is
shown in Fig. 2.2. It is generally available as a40-pin IC package and uses +5 V.
for power. It can run at a maximum frequency of 3 MHz. The modified versions
of the 8085 processor have these minimum common features and functional
similarities.
The 8085 is called an 8-bit processor since its data length and data bps width is
eight bits. It has an addressing capability of 16 bits, i.e., it can address 216= 64 KB
of memory (1 KB = 1024 bytes). The processor contains five functional units:
'(f) Arithmetic and logic unit (li) General-purpose registers
(iii) Special-purpose registers (Tv) Instruction register and decoder
(v) Timing and control unit
2.2.1 Arithmetic and Logic Unit

ALU is the circuitry that performs the actual numerical and logical operations.
Addition (ADD), subtraction (SUB), increment (INR), decrement (DCR),
INTEL 8085 MICROPROCESSOR ARCHITECTURE 21
Fig. 2.2 Functional block diagram of Intel 8085
and comparison (CMP) are the arithmetic operations possible in the 8085
microprocessor. The possible logical operations are AND (AND), OR (OR),
exclusive OR (EXOR), complement (CMA), etc.
The ALU of the 8085 processor is called accumulator-oriented ALU as one of
the data used in arithmetic and logic operations must be stored in the accumulator.
The other data is taken from a memory location or register. The results of the
arithmetic and logical operations are stored in the accumulator. If the operation
needs only one data, that data must be stored in the accumulator.
2.2.2 General-purpose Registers

A register is a collection of eight D-type flip-flops with parallel-in and parallel-
ouLoperaiion. A flip-flop can only store one bit at a time. Therefore, to handle
eight bits at a time, eight flip-flops are required and hence the term 8-bit register.
Though the registers are all storage areas inside the microprocessor, they differ in
the purpose of storage. The general-purpose registers are used to store only the
data that is being used by the program under execution and the Jesuits obtained
from it. These general-purpose registerTare user accessible through programs.
Registers B, C, D, E, H, and L are the general-purpose registers in the 8085,
as shown in Fig. 2.3. They can also be called scratchpad registers. In almost all
arithmetic and logical operations, these registers are used as the second operands,
the first operand being the accumulator (A). The general-purpose registers are
all 8-bit registers but they can be handled as 16-bit registers as well. This can be
achieved by combining the

register pairs B and C,
D and E, and H and L to
perform 16-bit operations.
They are then named
register pairs BC, DE, and
HL, respectively.
Among these pairs, HL
has a special significance.
A few memory-related
instructions of the 8085
(refer instruction set) use
the HL pair as a memory Fig. 2.3 Registers of Intel 8085
pointer. For example, the
instruction MOV A, M transfers the content of the memory location to which
the HL pair is pointing, to the accumulator. The HL pair is pre-loaded with the
memory address in which data is available.
2.2.3 Special-purpose Registers

There are also special-purpose registers that are dedicated to a specific function.
The accumulator, flag register, program counter (PC), and stack pointer (SP)
constitute the special registers in the 8085 microprocessor.
2.2.3.1 Accumulator
The accumulator is an 8-bit register; it is a part of the ALU and is the most
important register. It is used to store 8-bit data and to perform arithmetic and
logical operations. The output of an operation is also stored in the accumulator.
The accumulator is identified as register A in the instruction set of the 8085. The
programmer can use it at any time to store an 8-bit binary number. Being only
eight bits long, it can only hold one byte at a time. Any previous data stored in this
register will be overwritten as soon as new data is stored. The 8085 microprocessor
communicates with input/output devices only through the accumulator,?
2.2.3.2 Flag register
This is a special 8-bit register. Each bit of the flag register is quite independent of the
others. In all other registers, each bit impart of a single binary byte value and hence
each bit would have a numerical value. The flag is an 8-bit register used to indicate
the status of a recent arithmetic or logical operation. It may be set or reset after an
arithmetic or logical operation according to the condition of the processed data. The
five flag bits are zero (Z), carry (CY), sjgn (S), parity (P), and auxiliary carry (AC);
their bit positions in the flag register are shown in Fig. 2.4. The remaining three bits
(DI, D3, and D5) of the flag
register remain unassigned; s z X AC X P X CY
they are marked with an X to D7 D6 D5 D4 D3 D2 D1 DO

show that they are not used and
are don ’t cares. Fig. 2.4 Flag register
Any flag register bit is said to be ‘set’ when its value is 1 and ‘cleared’ when its
value is 0. The most commonly used flags are zero, carry, and sign. AC flag cannot
be accessed externally.
Sign flag (S) The sign flag is just a copy of the bit D7 (most significant bit—
MSB) of the accumulator. A negative number has a 1 in bit 7 and a positive
number has a 0 in 2’s complement representation. This flag indicates the sign of
the number. (It may be recalled that signed magnitude numbers use 1 to indicate
a negative number and 0 to indicate a positive number.) This flag can be used in
signed arithmetic operations.
Zero flag (Z) The zero flag is set if an arithmetic operation results in a zero. It
sets^Le-, it changes to binary 1 if the result in the accumulator is zero; if not, it
remains reset, i.e., at binary 0.
y.
Carry flag (C) The carry flag is set when a carry is generated in the process
of an arithmetic operation in the accumulator. When addition is carried out, it
sometimes results in a ninth bit being carried over to the next byte. The C flag
copies the value of the carry, which is an extra bit, from D7. It also reflects the
value of the borrow in subtractions.
Auxiliary carry flag (AC) The auxiliary carry flag is set when an auxiliary
carry is generated in the process of an arithmetic operation in the accumulator,
i.e., when a carry results from bit D3 and passes on to D4 (from the lower nibble ( >
to theJiigher.nibble). This carry is also called half-carry. It may also occur in the
process of a subtraction operation. In other words, this flag is set if the subtraction
operation results in borrow.
.
Parity flag (P) The parity flag is set if the content of the accumulator after an
arithmetic operation has an even number of Is. Otherwise, the parity flag is reset.
It is set for operation in the even parity mode.
2.2.3.3 Program Counter (PC)
PC is a register that always points to the address of the next instruction
to be executed. In other words, this register is used to sequence the execution of
the instructions. After execution of every instruction, the content of the memory
location indicated by the PC is moved to the instruction register and the PC is
loaded with the next address. It keeps track of a program by counting the memory
address from which the next byte is to be fetched, and hence the name program
counter.
2.2.3.4 Stack Pointer (SP)
Stack is an array of memory locations organized in last-in, first-out (LIFO) or first-
in, last-out (FILO) fashion. It is accessed using a 16-bit pointer register called stack
pointer, which holds the address of the memory location of the top of the stack.
The programmer can reserve and allocate a series of RAM locations to be used
as a stack and accordingly initialize the stack pointer. The range of stack memory
locations must be chosen carefully so that it does not affect the program space.
In all microprocessor-based systems, the stack is mainly used to store the return
address of the main program when a subroutine is called. While the programmer
uses the stack for storage and retrieval of data, the microprocessor uses the stack
during subroutine calls. Care must be taken by the programmer to ensure that the
data stored in the stack is retrieved properly, so that the data stored in the stack by
the processor is not affected.
2.2.4 Instruction Register and Decoder

It is an 8-bit register that usually temporarily stores the instructions drawn from
memory locations, before their actual execution. The content of the register is
decoded by the decoder circuitry, where the nature of the operation to be performed
is decided (interpreted). In addition, there are two temporary registers W and Z,
which are controlled internally and not available for user access.
2.2.5 Timing and Control Unit

The timing and control unit gets commands from the instruction decoder and
issues signals on the data bus, address bus, and control bus. The following sections
explain the operation of the various buses and the timing.
2.2.5.1 Data Bus
The microprocessor performs its functions using wires or lines called buses. For
example, an 8-bit microprocessor normally uses eight wires to carry data between
the microprocessor and the memory. To make their representation simple, the data
wires with common functions are grouped together and referred to as the data bus.
A typical microprocessor communicates with memory and iriput/output devices
using buses. There are three types of buses—the address bus, the data bus, and the
control bus.
The data bus (D0-D7) is a two-way bus carrying data around the system.
Information going into the microprocessor and results coming out of the
microprocessor are through this data bus. It is used for transfer of binary information
between the microprocessor, memory, and peripherals. The lower group of eight
address lines A0-A7 is multiplexed with the data bus in order to reduce the pin
count. Therefore, the multiplexed lower group of address lines and data lines is
more generally denoted as AD0-AD7.
2.2.5.2 Address Bus
The address bus carries addresses and is aone^waybus from the microprocessor to
the memory or other devices. It is a group of sixteen unidirectional lines that allows
flow of address from the processor to its peripheral devices. Each peripheral and
memory location is identified by a 16-bit binary number called address. It follows
that the maximum number of memory locations that can be addressed by the 8085
processor is 216 bytes = 64 KB. Its basic function is to identify a peripheral or
memory location.
The address bus lines are generally identified as A0-A15. The address bus has
eight higher-order address lines (A8-A15), which are unidirectional. The lower-
order eight lines (A0-A7) are multiplexed (time-shared) with the eight data bits
(D0-D7) and hence, they are bidirectional. When the instruction is executed, these
lines carry the address bits during the early part, and the eight data bits during the
later part. To separate the address from the data, a latch is used externally to save
the address before the function of the bits changes.
2.2.5.3 Control Bus
The control bus carries control signals_that are partly unidirectional and partly
bidirectional. For a microprocessor to function correctly, these control signals are
vital. The control bus typically consists of a number of single lines that coordinate
and control microprocessor operations. For example, a read/write control signal
will indicate whether memory is being written into or read from. Thus, they are
individual lines that provide a pulse to indicate the operation of the microprocessor.
In fact, the microprocessor generates specific control signals for every operation,
which in turn are used to identify the type of device the processor intends to
communicate with. The following points describe the control and status signals
of the 8085 processor:
(i) ALE (output): Address Latch Enable is a pulse that is provided when an
address appears on the AD0-AD7 lines, after which it becomes 0. This
signal can be used to enable a latch to save the address bits from the AD
lines, thereby de-multiplexing the address bus and data bus.
(ii) RD (active low output): The Read signal indicates that data are being read
from the selectedj/Q or memory device and that they are available on the
data bus.
(iii) WR (active low output): The Write signal indicates that the data on the data
bus are to be written into a selected memory or I/O location.
(iv) IO/M (output): It is a signal that distinguishes between a memory operation
and an I/O operation. An active low on this signal shows it is ajnemory
operation (IO/M = 0) and a high on this line indicates an I/O operation (IO/
M=l). Table 2.1 Status signals and
(v) SI and SO (output): These are status associatedoperations
signals used to specify the kind of S1 so States
operation being performed. The status
signals combine with I/O signals to 0 0 Halt
govern various operations; they are \ 0 1 Write
1 0 Read
listed in Table 2.1. If both SO and SI 11 11 retcn
are low, the operation of the processor _
tends to halt. If SO is low and S1 is high, the processor reads data. If SO is
high and SI is low, the processor writes data onto a memory or I/O device.
If both SO and SI are high, the fetch operation is performed.
The schematic representation of the 8085 bus structure, shown in Fig. 2.5, explains
how the movement of data within the computer is accomplished by a series of
buses. Address information, data, and control signals have to be carried around
inside the microprocessor as well as in the external system. Hence, the buses are
present both internally and externally.
(vi) Interrupts: These signals are used to make the microprocessor respond to high
priority externally initiated signals. When an interrupt signal is detected by the
processor, it suspends the execution of the current program and executes the
Fig. 2.5 Schematic representation of the 8085 bus structure
program corresponding to the interrupt signal instead. Five interrupt signals

(INTR, RST 5.5, RST 6.5, RST 7.5, and Trap) are available to facilitate the
processor to receive and acknowledge the interrupt call of peripherals. The
8085 processor accepts three more externally initiated signals—RESET IN,
Hold, and Ready as inputs. The following points explain these signals in
brief:
(a) INTR (input): It is a general-purpose interrupt request signal. It is an
active high signal.
(b) INTA (output): It is used to acknowledge an interrupt. It is an active low
signal.
(c) Restart interrupts (input): These are vectored interrupts that transfer the
program control to specific memory locations. They have higher priority
than INTR interrupts. The priority order is RST 7.5, RST 6.5, and RST
(d) Trap (input): It is a non-maskable interrupt, i.e., it cannot be stopped or

overridden by any command. It has the highest priority among all 8085
interrupts.
(e) RESET IN (input): When the signal on this pin goes Ipjy the program
counter is. sel lo zero and the processor is reset. It is an activejpw
signal.
(f) RESET OUT (output): This signal can be used to reset other devices that
are connected to the processor. It is an active high signal.
(g) Hold (input): This signal indicates that a peripheral such as a direct
memory access (DMA) controller is requesting the use of the address
and data buses.
(h) HLDA (output): It is ^ acknowledge signal that is sent in response to
the Hold request. During the Hold state, the peripheral (I/O) devices
get control over the data and address buses for data transfer to and from
memory. This operation is called direct memory access (DMA). DMA
is useful when high-speed peripherals want to transfer data to and from
memory. The processor does not intervene during this period.
(i) Ready (input): It is a signal that serves to delay the microprocessor
read/write signals until a slow-responding peripheral is ready to send or
accept data. If this signal goes low, then the processor is allowed to wait
for an integral number of clock cycles until Ready becomes high. The
Ready signal must be synchronized with the processor clock.
2.3 PIN LAYOUT AND DESCRIPTION OF SIGNALS

A microprocessor is a very small electronic circuit, typically 1/2 an inch (12 mm)
across. Since it is susceptible to damage due to moisture and abrasion, it is
encapsulated in plastic or ceramic, as shown
in Fig. 2.6. The size of the microprocessor
makes it impractical to give electrical
connections directly to the circuit. Hence,
the case is moulded with connecting pins,
which in turn connect to the main circuit
board. The size, shape, and number of pins
on the microprocessor are dependent on the Fig. 2.6 Microprocessor IC package
amount of data it is designed to handle.
The typical pin layout and signal groups of the 8085 microprocessor are shown
in Figs 2.7 (a) and 2.7 (b), respectively. The 8085 is available with 40 pins as a
dual in-line package (DIP).
Intel 8085 has 40 pins, operates at 3 MHz clock frequency, and requires +5V
for power supply. The signals can be classified into six groups:
(i) Address bus (ii) Data bus
(iii) Control and status signals (iv) Power supply and system clock
(v) Externally initiated signals (vi) Serial I/O signals
X1 E1 40 ^Vcc
X2 E 2 39 2 HOLD
RESET OUT C 3 38 3 HLDA
SODE4 37 3CLK(OUT)
signals SID E5 36 3 RESET IN
+5V
TRAP E6 35 J READY
RST7.5 d7 34 3 io/m XTAL Higher-order
"X1 X2 address bus.
RST6.5 E8 33 3S1
A15
RST5.5 E9 32 3RD SID — A8
8085 Multiplexed'
INTR C 10 31 3 WR SOD <-
TRAP — lower-order
INTA E 11 30 3 ALE address/data bus
RST7.5 —
AD7
ADO E12 29 3 SO RST6.5 —
AD1 RST5.5 — ADO
E13 28 3A15 -►ALE
INTR — 8085
AD2 E14 27 3A14
AD3 Ej15 26 3A13 READY —
HOLD — ■> I0/M
AD4 C16 25 3A12 HLDA <■
AD5 C 17 24 3A11 ÊTin-
AD6 C 18 23 3A10
AD7 C 19 22 3 A9
C. 21 3A8 RESET OUT CLK(OUT)
(a) (b)
Fig. 2.7 (a) Pin diagram of the 8085 (b) Signal groups of the 8085
The functions of each pin are described in Sections 2.3.1-2.3.5.
2.3.1 Address and Data Buses

The 16-bit address bus and 8-bit data bus are split into the following two groups:
(i) A8-A15 (output; three-state higher-order address bus): The most significant
eight bits of memory addresses and the eight bits of the I/O addresses are
transported on these lines. These lines enter into tri-stated high impedance
state during hold and halt modes.
(ii) AD0-AD7 (input/output; three-state multiplexed address/data bus): The
lower-order eight bits of a memory address or an I/O address appears on
these lines during the first clock cycle of a machine state. They then become
the data bus during the second and third clock cycles. Like the higher-order
address bus, these lines also enter high impedance state during hold and halt
modes.
2.3.2 Control and Status Signals

The 8085 uses various control signals for fetching and executing instructions. The
operations that take place upon execution are indicated by the status signals. The
following points explain the control and status signals of the 8085:
(i) Address Latch Enable (output): This output signal indicates the availability
of a valid address on the multiplexed address/data lines. It occurs during the
first clock cycle of a machine state and enables the address to be stored in
a latch or a register. ALE can also be used to strobe the status information.
ALE is never tri-stated.
(ii) SO, SI (output): These signals are used to indicate the kind of operation
being performed, as given in Table 2.1.
(iii) IO/M (output; three-state): IO/M indicates whether the read/write operation
is being done with respect to the memory or an I/O device. Logic 1 indicates
I/O device access and logic 0 indicates memory access. This signal is tri-
stated during hold and halt modes.
(iv) RD (output; three-state): Read is an active low signal that indicates that data
is to be read from the selected memory or I/O device through the data bus.
(v) WR (output; three-state): Write is an active low signal that indicates that the
data on the data bus is to be written into the selected memory or I/O location.
Data is placed on the data bus at the trailing edge of the WR signal.
2.3.3 Externally Initiated Signals

The operation of the microprocessor is affected by the signals it receives from
peripheral devices. The following points explain these externally initiated
signals:
(i) RESET IN (input): This signal sets the program counter to zero (0000H)
and resets the interrupt enable and HLDA flip-flops. It is an essential signal
for any microprocessor system because it determines the address at which
program execution begins. In most microprocessor-based systems, RESET
IN signal is applied as soon as the power is turned on. A power-on reset
circuit is used to do this.
(ii) RESET OUT (output): This output signal indicates that the CPU is being
reset. It can be used as a reset signal for peripheral chips. The signal is
synchronized to the processor clock.
(iii) Ready (input): This signal is used to interface slow peripheral devices with
the fast microprocessor. If Ready is high during a read or write cycle, it
indicates that the memory or peripheral is ready to send or receive data. If
Ready is low, the CPU waits for it to go high before completing the read or
write cycle.
(iv) Hold (input): Hold is an active high signal used in the direct transfer of
data between a peripheral device and memory locations. This type of data
transfer is called as direct memory access (DMA). During this transfer,
the microprocessor loses control over the address and data buses and these
buses are tri-stated. Logic 1 on the Hold pin indicates that another controller,
generally the DMA controller, is requesting the use of the address and data
buses. The CPU, upon receiving the hold request, will relinquish the use of
the buses after completing the current instruction. An acknowledge signal
is sent out by the processor and the address, data, RD, WR, and IO/M lines
are tri-stated. The processor can regain control over the buses only after the
Hold signal is removed.
(v) HLDA (output): Hold acknowledge, an active high signal, indicates that
the CPU has received the hold request and that it will relinquish the buses
in the next clock cycle. HLDA goes low after the hold request is removed.
The CPU takes the buses half a clock cycle after HLDA goes low.
(vi) INTR (input): Interrupt request is a general-purpose interrupt. It is sampled
only during the last clock cycle of the instruction. If INTR is high, the
program counter (PC) will not be allowed to increment and an INTA will be
issued. Program execution can be shifted to the interrupt service routine by
inserting an RST or CALL instruction on the data lines during this cycle.
(vii) INTA (output): Interrupt acknowledge is an active low signal used instead
of RD, after an interrupt request has been accepted. This signal is used to
read the opcode from the data bus and execute it.
(viii) RST 7.5, RST 6.5, RST 5.5—restart interrupts (input): These three inputs
are hardware interrupt signals similar to INTR. They are used to make the
processor execute a subroutine at a predefined address. However, these
interrupts do not have an acknowledgement signal.
(ix) Trap (input): Trap interrupt is a non-maskable restart interrupt. It is
unaffected by any mask or interrupt enable signal. It is the highest priority
interrupt. Interrupts, and their masking and enabling, are discussed in detail
in Chapter 5.
2.3.4 Serial I/O Signals

There are two signals to implement serial transmission. They are serial input data
(SID) and serial output data (SOD). The data bits are sent over a single line, one
bit at a time, in serial transmission.
(i) SID (input): The bit data on this line is loaded in the seventh bit of the
accumulator whenever a RIM instruction is executed.

(ii) SOD (output): The output SOD is set or reset as specified by the SIM
instruction.
RIM and SIM instructions have been explained in detail in Chapter 5.
2.3.5 Power Supply and System Clock

The following pins are available in the 8085 chip to provide power and clock
signal to the processor:
(i) XI, X2 (input): A microprocessor needs a square wave (clock) signal
to ensure that all internal operations are synchronized. A crystal or R-C
or L-C network is connected to these two pins. The crystal frequency is
internally divided by two to give the operating system frequency. There
are three advantages in increasing the frequency of a crystal—as frequency
increases, the crystal size becomes smaller, and the crystal becomes lighter
and cheaper. Therefore, clock circuits include a divide-by-two circuit so that
a double-frequency crystal can be used. So, to run the microprocessor at
3 MHz. a 6 MHz crystal should be connected to the XI and X2 pins. The
crystal is preferred as a clock source because of its high stability, large Q
(quality factor), and absence of frequency drifting with aging. Without a
clock signal, the microprocessor cannot execute any program.
(ii) CLK (output): This output clock pin is used to provide the clock signal to the
rest of the system.
Power supplies: Vcc—1-5 V supply; Vss—ground reference.
2.4 MICROCOMPUTER SYSTEM BASED ON 8085

To make a complete microcomputer system, the 8085 microprocessor has to be
interfaced with the memories and input and output devices. The memories required
are of two types—RAM and ROM. ROM is necessary to store fixed programs.
These programs are executed when the system is powered up. RAM is required in
any system to store temporary programs and data. A specific memory location is
selected from the memory devices by issuing the address for that memory location
and the control signals discussed in Section 2.3.2. The microprocessor is the
master in any microcomputer system as it issues the required control signals to the
peripherals. Each location in a memory is given a number, called an address. The
maximum number of locations that can be addressed will depend on the number
of bits in the address. Generally 2" is the number of memory locations addressed,
where n is the number of bits in the address. Memory interfacing is explained in
detail in Chapter 6. Similar to memory locations, each input and output device is
also selected by giving a particular address. Any microprocessor-based system,
in addition to memory and I/O devices, has features such as interrupt, serial data
transfer, etc. A detailed study of 8085-based system is presented in Chapter 8.
POINTS TO REMEMBER
• The microprocessor is a semiconductor device consisting of electronic logic circuits

manufactured using either large-scale integration (LSI) or very large-scale integration
(VLSI) technique. It works at a fixed clock frequency.
• A bus is a collection of wires connecting two or more chips.
• A typical microprocessor communicates with memory and other input/output devices
using three buses—address bus, data bus, and control bus.
• Salient features of the 8085 microprocessor manufactured by Intel
/ ■ It is an 8-bit microprocessor.
■ It has a 16-bit address bus (A0-A15) and hence, can address up to 216 = 65,536 bytes
(64 KB).
■ The 8085 has a multiplexed bus (AD0-AD7), which is used as the lower-order
address bus and the data bus. It can be de-multiplexed using a latch and the ALE
signal.
■ The data bus is a group of eight lines (D0-D7).
■ It supports external interrupt request.
■ It has a 16-bit program counter (PC) and a 16-bit stack pointer (SP).
■ It has six 8-bit general-purpose registers, which can be arranged in pairs as BC, DE,
and HL.
s'* It requires a +5 V power supply and operates at 3 MHz clock frequency.
■ It contains 40 pins and is available as a dual in-line package (DIP).
It has five flags—-sign, zero, auxiliary carry, parity, and carry.
KEY TERMS
Accumulator It is an 8-bit register; it is a part of the ALU and is the most important
register. It is used to store 8-bit data and to perform arithmetic and logical operations. The
output of an operation is also stored in the accumulator. The accumulator is identified as
register A.
Address bus This bus carries the binary number (i.e., the address) used to access a
memory location. Binary data can then be written into or read from the addressed memory
location. The address bus consists of 16 wires and can, therefore, handle 16 bits.
Bus It is a group of conducting lines that carry data, address, and control signals
Clock speed This determines how many instructions per second the processor can
execute. It is specified in megahertz (MHz).
Control bus This bus has various lines for coordinating and controlling microprocessor
operations. For example, RD and WR lines.
Data bus This bus carries data in binary form between the microprocessor and external
units such as memory. Typical size is eight or 16 bits.
DMA controller It is used to take control of the system bus by placing a high signal on
the Hold pin.
Flag It is a flip-flop used to store information about the status of the processor and the
status of the instruction executed most recently.
Hold and HLDA These signals are used for direct memory access (DMA) type of data
transfer. The Hold request makes the 8085 drive all its tri-stated pins to high impedance
state. The HLDA signal goes high to acknowledge the receipt of the Hold signal.
IO/M signal This signal is used to differentiate memory access and I/O access. For
input/output instructions it is high; for memory reference instructions it is low.
Ready It is an input signal to the processor. It is used by the memory or I/O devices to get
extra time for data transfer or to introduce wait states in the bus cycles.
Trap It is a non-maskable interrupt of the 8085 and is not disabled by processor reset or
after reorganization of interrupt.
REVIEW QUESTIONS ]
1. Name any three features of the 8085.

2. What are the operations performed by the ALU of the 8085?
3. What are the various registers in the 8085?
4. What is a flag? List its types. What is the structure of the flag register? Explain each
flag with an example.
5. List the 16-bit registers of the 8085 microprocessor.
6. What is a bus?
7. Why is the data bus bidirectional?
8. How are the signals of the 8085 classified?
9. How are clock signals generated in the 8085? What is the frequency of the internal
clock?
10. How does the 8085 processor differentiate a memory access (read/write) signal from
an I/O access (read/write) signal?
11. Why is crystal a preferred clock source?
12. Which interrupt has the highest priority in the 8085? What is the priority of the other
interrupts?
13. When and where is the Ready signal used?
14. What are Hold and HLDA? How are they used?
15. Draw a general block diagram of a microprocessor-based system. Explain briefly the
various blocks of the system. Give some examples of the types of devices used for
each block.
16. What is a microprocessor? Sketch and explain the various pins of the 8085.
17. Explain the operation of these 8085 signals: Ready, SI and SO, Hold and HLDA, and
ALE.
18. Explain the architecture of the 8085 with the help of its internal block schematic
diagram.
CHAPTER 3
INSTRUCTION SET AND

EXECUTION IN 8085
LEARNING OUTCOMES I
• Format and types of instructions used in the 8085 microprocessor
• Data addressing modes and their usage in instructions
• Selection of the appropriate addressing modes to accomplish given tasks
* Machine cycles and their classification
• Timing diagrams and T-states of various instructions
3.1 MICROPROCESSOR INSTRUCTIONS

Every microprocessor has its own instruction set. Based on the design of the
ALU and the decoding unit, microprocessor manufacturers generally list out the
instructions for every microprocessor manufactured. The instruction set consists
of both assembly language mnemonics and the corresponding machine code.
The purpose of the instruction set is to facilitate the development of efficient
programs by the users. The instruction set is based on the architecture of the
processor. So to understand the instruction set of a processor, it is necessary to
understand the basic architecture of the microprocessor and the user-accessible
registers in it. An instruction is a bit pattern that is decoded inside a microprocessor
to perform a specific function. The assembly language mnemonics are the codes for
these binary patterns so that the user can easily understand the functions performed
by these instructions. The entire group of instructions that a microprocessor
can handle is called its instruction set; this determines the microprocessor’s
functionality. The Intel 8085 processor has its own set of instructions listed both
in mnemonics and machine code, also called as object code. As the 8085 is an 8-
bit processor, the machine codes for the instructions are also 8 bits wide.
The syntax for 8085 instructions may contain one or more of the following
notations:
R = 8-bit register (A, B, C, D, E, H, and L)
Rs = Source register 1
Rd = Destination register J (A, B, C, D, E, H, and L)
Rp = Register pair (BC, DE, HL, and SP)
P = Port address (8-bit binary number or two hex digits)
8-bit = 8-bit data or two hex digits
16-bit = 16-bit data/address or four hex digits
( ) = Contents of
3.2 CLASSIFICATION OF INSTRUCTIONS

Microprocessor instructions can be classified based on parameters such as
functionality, length, and operand addressing.
3.2.1 Instruction Classification based on Functionality

Based on the functionality, the instructions are classified into the following five
categories:
(i) Data transfer (copy) operations (ii) Arithmetic operations
(iii) Logical operations (iv) Branching operations
(v) Machine control operations
3.2.1.1 Data Transfer (Copy) Operations
This group of instructions copies data from a location called source register to
another location called destination register. Generally, the contents of the source
register are not modified. Although the term data transfer is used for the copy
operation, it is misleading because it implies that the contents of the source
memory location are destroyed. The various types of data transfer are listed in
Table 3.1 along with examples of each type.
Table 3.1 Types of data transfer
Type Example
Transferring data between one register MOV A, D—Copies the content of

and another register D to the accumulator
Storing a data byte in a register or MVI C, 66H—Loads register C with
memory location the data 66H
Transferring data between a memory LDA 8800H—Loads the contents of
location and a register memory location 8800H in the accumulator
Transferring data between an I/O device IN PORT1—Transfers data from an input
and the accumulator device to the accumulator
3.2.1.2 Arithmetic Operations

Arithmetic operations include addition, subtraction, increment, and decrement. As
the 8085 has an accumulator-oriented ALU, one of the data used in the arithmetic
operations is stored in the accumulator; the result is also stored in the accumulator.
Arithmetic and logical operations cannot be executed without the accumulator.
Addition (ADD) The addition instructions of the 8085 add the contents of
a register or memory location with the contents of the accumulator. The result
is stored in the accumulator. The Intel 8085 instruction set supports two types
of addition instructions—with and without addition of the carry flag content to
the least significant bit of the numbers. The instruction set also supports 16-bit
addition, i.e., the content of the HL register pair can be added to that of another
register pair and the result stored in the HL register pair.
Subtraction (SUB) The instruction set of the 8085 supports two types of
subtraction—with borrow and without borrow. Like addition, the subtraction
INSTRUCTION SET AND EXECUTION IN 8085 35
operation also uses the accumulator as reference, i.e., it subtracts the content of a
register or memory location from that of the accumulator and stores the result in
the accumulator.
Increment/Decrement These operations can be used to increment or decrement
the contents of any register, register pair, or memory location. Unlike the arithmetic
and logical operations, the increment and dccrcment operations need not be based
upon the accumulator.
3.2.1.3 Logical Operations
Logical instructions are also accunHilator-oriented, i.e., they require one of the
operands to be placed in the accumulator. The other operand can be any register or
memory location. The result is stored in the accumulator. The operations that use
twooperands are logical AND, OR, and EXOR. The operation that uses a single
operand (i.e., the accumulator) is the logical complement orNOT operation.
The instruction set of the 8085 supports rpjtajdon of the data stored in accumulator.
The data can.be rotated left or right, through the carry or without the carry.
The most important 8085 instruction is the compare instruction. This instruction
is used to compare register or memory content with the accumulator content. The
result of comparison such as equal to, greater than, or less than is reflected in the
flag register bits.
3.2.1.4 Branching Operations
Branching instructions are important for programming a microprocessor. These
instructions can transfer control of execution from one memory location to another,
either conditionally or unconditionally. Branching can take place in the following
two ways:
(i) Execution control cannot return to the point of branching. Example: Jump
instructions
(ii) Execution control can return to the point of branching, which is stored by the
8085. Example: Subroutine call instructions
3.2.1.5 Machine Control Operations
These instructions can be used to control the execution of other instructions.
They include halting the operation of the microprocessor, interrupting program
execution, etc. Detailed explanations for 8085 instructions are given in
Section 3.3.
3.2.2 Instruction Classification based on Length

Based on the length of the machine language code, 8085 instructions can be
classified into the following three types:
(i) One-byte instructions (ii) Two-byte instructions
(iii) Three-byte instructions
Assembly language instructions should be converted into machine code for
storage and execution by the processor. So the length of the machine language
code instructions determines the length of the program. This in turn determines
the amount of memory required for the program.
3.2.2.1 One-byte Instructions

Instructions that require only one byte in machine language are called one-byte
instructions. These instructions just have the machine code or opcode alone to
represent the operation to be Table 3 2 One-byte instructions
performed. The common examples ---------------------------------------------------------- -
are the instructions that have their Opcode Operand Machine code/Opcode/
Hex code
operands within the processor
itself. Some examples of one-byte MOV A, B 78
instructions are given in Table 3.2. ADD M 86
Even though the instruction ADD XRA A AF
M adds the content of a memory
location to that of the accumulator, its machine code requires only one byte.
Let us now understand the instruction MOV Rd, Rs. This instruction copies the
contents of source register Rs to destination register Rd. (Rd <- Rs)
It is coded as Oldddsss. Here, ddd is the binary code of one of the seven general-
purpose registers that is the destination of the data and sss is the binary code of
the source register.
Example:
MOV A, B (coded as 01111000 = 78H)
3.2.2.2 Two-byte Instructions
Instructions that require two bytes in machine code are called as two-byte
instructions. The first byte of the two-byte instructions is the opcode, which
specifies the operation to be performed. The second byte is the 8-bit operand,
which is either an 8-bit number or an address. Some common examples of two-
byte instructions are listed in Table 3.3.
Table 3.3 Two-byte instructions
Opcode Operand Machine code/Opcode/Hex code Byte description

MVI A, 7FH 3E First byte
7F Second byte
ADI OFH C6 First byte
OF Second byte
IN 40H DB First byte
40 Second byte
The instruction is stored in two consecutive memory locations.

MVI R, data—(R <— data)
Example:
MVI A, 32H (coded as 3E 32 in two contiguous bytes)
This is an example of immediate addressing.
The following two instructions are also examples of two-byte instructions:
(i) ADI data (A <—A + data)
(ii) OUT port (where port is an 8-bit device address. (Port) <<- A) Since the byte
is not the data itself, but points directly to where it is located, this is called
direct addressing. For a detailed account of addressing modes, see Section
3.2.3.
3.2.2.3 Three-byte Instructions
Instructions that require three bytes in machine code are called three-byte
instructions. In 8085 machine language, the first byte of the three-byte instructions
is the opcode which specifies the operation to be performed. The next two bytes
refer to the 16-bit operand, which is either a 16-bit number or the address of a
memory location. Some common examples of three-byte instructions are listed in
Table 3.4.
Table 3.4 Three-byte instructions
Opcode Operand Machine code/Opcode/Hex code Byte description
IMP 9050H C3 First byte

50 Second byte
90 Third byte
LDA 8850H 3A First byte
50 Second byte
88 Third byte
LXI H, 0520H 21 First byte
20 Second byte
05 Third byte
The instruction LXI Rp, 16-bit data can be explained as follows:

Rp is one of the pairs of registers BC, DE, or HL, which are used as 16-bit
registers. The two data bytes are to be stored as a 16-bit number in L and H in
sequence. LXI H, 0520H is coded as 21H 20H 05H in three bytes. (This is an
example of immediate addressing.)
In executing the instruction LDA addr, the accumulator is loaded with the
memory content of the address given in the instruction. Addr is a 16-bit address.
LDA 8850H is coded as 3AH 50H 88H. (This is an example of direct addressing.)
3.2.3 Addressing Modes in Instructions

Every instruction in a program has to operate on data. The process of specifying
the data to be operated on by the instruction is called addressing. Efficient
software development for the microprocessor requires complete familiarity with
the addressing mode employed for each instruction. For example, the instructions
MOV B, A and MVI A, 82H are used to copy data from a source to a destination.
In these instructions, the source can be a register or an 8-bit number (OOH to FFH);
the destination is a register. The source and destination are operands. The various
formats for specifying operands are called addressing modes. The 8085 has the
following five types of addressing:
(i) Immediate addressing (ii) Memory direct addressing
(iii) Register direct addressing (iv) Indirect addressing
(v) Implied or implicit addressing
3.2.3.1 Immediate Addressing

Immediate addressing transfers the Instruction
operand given in the instruction—a byte
or word—to the destination register or
memory location. The operand is part of
the instruction. The format for immediate Fig. 3.1 Format of immediate addressing
addressing is given in Fig. 3.1.
Example:
MVI A, 9AH
(a) The operand is part of the instruction.
(b) The operand is stored in the register mentioned in the instruction.
Example:
ADI 05H
(a) Add 05H to the contents of the accumulator.
(b) 05H is the operand.
Immediate addressing has no memory reference to fetch data. It executes faster,
but has limited data range.
3.2.3.2 Memory Direct Addressing
Memory direct addressing moves a byte or word between a memory location and
register. The memory location address is given in the instruction. The instruction
set does not support memory-to-memory transfer. Memory direct addressing is
illustrated in Fig. 3.2.
Fig. 3.2 Format of memory direct addressing
Example:
'' LDA 850FH
This instruction is used to load the contents of the memory location 850FH in the
accumulator.
Example:
-ZSTA 9001H
This instruction is used to store the contents of the accumulator in the memory
address 9001H.
In these instructions, the memory address of the operand is given in the instruction.
Direct addressing is also used for data transfer between the processor and
input/output devices. For example, the IN instruction is used to receive data from
the input port and store it in the accumulator; the OUT instruction is used to send
the data from the accumulator to the output port.
Example:
IN OOH and OUT 01H
3.2.3.3 Register Direct Addressing

Register direct addressing transfers a copy of a byte or word from the source
register to the destination register. The operand is in the register named in the
instruction. It executes very fast, has very limited register space, and requires
good assembly programming. The operand is within in the processor itself; so the
execution is faster. Register direct addressing is illustrated in Fig. 3.3.
Example:
MOV Rd, Rs
MOV B, C
It copies the contents of register C to register B.
Example:
s' ADD B
It adds the contents of register B to the accumulator and saves it in the accumulator.
3.2.3.4 Indirect Addressing
Indirect addressing transfers a byte or word between a register and a memory
location. The address of a memory location is stored in a register and that register
is specified in the instruction. This is illustrated in Fig. 3.4.
In indirect addressing, the effective address is calculated by the processor using
the contents of the register specified in the instruction. This type of addressing
employs several accesses—two accesses to retrieve the 16-bit address and a further
access (or accesses) to retrieve the data which is to be loaded in the register.
Example:
MOV A* M
Here, the data is in the memory location pointed to by the contents of the HL pair.
The data is moved to the accumulator.
3.2.3.5 Implied or Implicit Addressing

In implied addressing mode, the instruction itself specifies the data to be operated
upon. For example, CMA complements the contents of the accumulator. No
specific data or operand is mentioned in the instruction.
3.3 INSTRUCTION SET OF 8085

The 8085 microprocessor instruction set has 74 operation codes and 246
instructions. It is compatible with that of its predecessor, the 8080A, but has
two additional instructions—SIM (set interrupt mask) and RIM (read interrupt
mask)—related to serial I/O. The complete instruction set is listed in Appendix 1
with additional information such as number of T-states required for execution and
the flags affected. The concept of T-states is explained in Section 3.5.
3.3.1 Format of Assembly Language Instructions and Programs

Assembly language programs are written for performing specific functions,
converted into machine language code, and then stored in the memory of the
microprocessor-based system. The conversion of an assembly language program
into machine language code is called assembling; the application that performs this
task is called assembler. This conversion or assembling can also be done manually
by the programmers. To facilitate the process of assembling, the assembly language
programs are written in a specific format as shown in Fig. 3.5.
Memory address Machine code/Opcode Label Mnemonics with operands Comments
Fig. 3.5 Format for writing assembly language programs
In general, the assembly language mnemonics with their operands are written
first. The address where the instructions are stored is given a dummy name called
label. The purpose of labels is to give the correct branch addresses in instructions.
Labels are separated from mnemonics with a colon.
The comments column is essential for any program as it helps the programmer
understand the logic of the program at any point in time. Without comments, it is
difficult to understand an assembly language program. Comments are separated
from the mnemonics with a semicolon.
The first two columns correspond to the physical memory address and the
actual machine code. These two columns are filled in after completing the assembly
language programming. These columns must contain only binary numbers, but for
easy understanding, hexadecimal numbers are used. For manual assembling, these
two columns are filled in by the programmer. An assembler can generate these
columns automatically.
An example of the assembly language program format is given in Table 3.5.
Table 3.5 Sample assembly language program
Memory Machine code/ Label Mnemonics Comments

address Opcode with operands
8000 3E START: MVI A, 5FH ; Load data in the accumulator.

8001 5F
8002 ; Address of the next memory
location
The instruction in Table 3.5 moves the data 5FH to the accumulator.
3.3.2 Data Transfer Instructions

Data transfer instructions are used to transfer data between two registers in the
microprocessor or between a peripheral device and the microprocessor. Some
instructions and their features are given in the following points. The complete list
with explanations is given in Table 3.6.
(i) MVI instruction is used for storing 8-bit data in a microprocessor register.
-Tn) LXI instruction is used for storing 16-bit data in a register pair.
(iii) In direct addressing mode, MOV instruction is used for data transfer between
registers. In indirect addressing mode, MOV is used for data transfer between
a memory location and a register. If the instruction has M in the operand
field, the memory location pointed to by the HL pair is considered for data
transfer.
Table 3.6 Data transfer instructions
Mnemonics Tasks performed on Addressing Instruction Example

execution mode length
MVI R, 8-bit Moves the 8-bit data Immediate Two bytes MVI B, 3FH
to the register
LXI Rp, 16-bit Loads the 16-bit data in Immediate Three bytes LXI B, 5AF3H
the register pair
MOV Rd, Rs Copies the data from Register One byte MOV A, B
the source register to direct
the destination register
LDA 16-bit Loads the accumulator Register Three bytes LDA 905FH
with the data from the direct
memory location
indicated by the
16-bit address
(Contd)
Table 3.6 Data transfer instructions (Contd)
Mnemonics Tasks performed on Addressing instruction Example

LHLD 16-bit Loads the H and L Memory Three bytes LHLD 900AH
registers directly from direct
the two consecutive
memory locations
indicated by the
16-bit address
STA 16-bit Stores the contents of Memory Three bytes STA 9050H
the accumulator in the direct
memory location
indicated by the
16-bit address
SHLD 16-bit Stores the contents of Memory Three bytes SHLD 809FH
the H and L registers direct
in two consecutive
memory locations
indicated by the
16-bit address
PUSH Rp Pushes the contents of Register One byte PUSHB
the register pair onto direct
a stack
POPRp Pops the top two memory Register One byte POPH
locations of the stack direct
Qjito a register pair
OUT 8-bit Outputs the data in the I/O Two bytes OUT 40H
accumulator to the port
indicated by the
8-bit address
IN 8-bit Inputs the data from the I/O Two bytes IN 3 OH
port indicated by the
8-bit address to the
accumulator
MOV Rd, M Copies the contents of Indirect One byte MOV B, M
the memory location
pointed to by the HL
register pair to
y a
the register
MOV M, Rs Copies the contents of the Indirect One byte MOVM7C
register to the memory
location pointed to by
the HL register pair
LDAX Rp Loads accumulator with Indirect One byte LDAX B
the contents of the
memory location pointed
to by the register pair
(Contd)
Table 3.6 Data transfer instructions (Contd)

STAX Rp Stores the contents of the Indirect One byte STAX D

accumulator in the
to by the register pair
XCHG Exchanges the contents Implicit One byte XCHG
of the HL register pair
with that of the D and E
register pair
SPHL Copies the contents of Implicit One byte SPHL
the H and L registers to
the stack pointer
XTHL Exchanges the contents Implicit One byte XTHL
of the HL register pair
with the top of stack
(iv) LDA and STA use memory direct addressing mode and a 16-bit memory
address as operand.
(v) LDAX and STAX use indirect addressing mode for data transfer. The
operand given in the instruction is one of the register pairs BC or DE.
Register pair HL is not used with LDAX due to the availability of the
alternative instruction MOV A, M.
(vi) LHLD and SHLD are the instructions used to transfer 16-bit data between
the HL register pair and two consecutive memory locations. For example,
executing SHLD 9000H instruction will store the contents of L register in
9000H and the contents of H register in 9001H.
(vii) PUSH and POP instructions are used for data transfer between a register
pair and a stack. The stack is a set of memory locations configured as a last
in, first-out (LIFO) or first-in, last-out (FILO) array. The top of the stack
locations is pointed to by a special register, the stack pointer, which is within
the microprocessor. PUSH instruction will store the register pair given in
the instruction to the top two memory locations of the stack. Similarly, POP
instruction will copy the last two bytes stored in the stack to the register pair
mentioned in the instruction. Care must be taken in using these instructions as
the stack is configured as a LIFO array. Another instruction to store data in the
stack is XTHL, which exchanges the top two memory locations of the stack
with the contents of the HL register pair.
(viii) Stack pointer can be initialized using LXI or SPHL instructions. SPHL
instruction will copy the contents of the HL register pair to the stack pointer.
(ix) IN and OUT instructions use 8-bit port addresses as operand. IN instruction
is used to get data from the input port and the data obtained is stored in the
accumulator. OUT instruction is used to issue data from the accumulator to
an output port.
(x) XCHG instruction is used to exchange the contents of the HL and DE

register pairs.
3.3.3 Arithmetic Instructions

The arithmetic instructions supported by the 8085 are addition, subtraction, and
their variants. The arithmetic instructions are listed in Table 3.7.
Table 3.7 Arithmetic instructions

ADI 8-bit Adds the 8-bit data to Immediate Two bytes ADI 30H
the contents of the
accumulator
ACI 8-bit Adds the 8-bit data and Immediate Two bytes ACI 4FH
the carry flag to the
contents of the
accumulator
SUI 8-bit Subtracts the 8-bit data Immediate Two bytes SUI 2AH
from the contents of the
accumulator
SBI 8-bit Subtracts the 8-bit data Immediate Two bytes SBI 5CH
and the borrow from the
contents of the
accumulator
ADDR Adds the contents of the Register One byte ADDC
register to the contents direct
of the accumulator
ADCR Adds the contents of the Register One byte ADCE
register and the carry to direct
the contents of the
accumulator
SUBR Subtracts the contents of Register One byte SUBB
the register from that of direct
the accumulator
SBB R Subtracts the contents Register One byte SBB C
of the register and the direct
borrow from that of the
accumulator
DADRp Adds the contents of the Register One byte DADB
register pair to that of the direct
H and L registers
INRR Increments the register Register One byte INRB
by 1 direct
INX Rp Increments the register Register One byte INXB
pair by 1 direct
(Contd)
Table 3.7 Arithmetic instructions (Contd)

DCRR Decrements the register Register One byte DCRE

by 1 direct
DCX Rp Decrements the register Register One byte DCX D
pair by 1 direct
ADDM Adds the contents of the Indirect One byte ADDM
to by the HL register pair
to that of the accumulator
ADCM Adds the contents of the Indirect One byte ADCM
to by the HL register pair
and the carry to that of
the accumulator
SUBM Subtracts the contents of Indirect One byte SUBM
the memory location
pointed to by the HL
register pair from that
of the accumulator
SBBM Subtracts the borrow and Indirect One byte SBBM
the contents of the
to by the HL pair from
that of the accumulator
INRM Increments the memory Indirect One byte INRM
location pointed to by the
HL register pair by 1
DCRM Decrements the memory Indirect One byte DCRM
location pointed to by the
HL register pair by 1
DAA Converts the contents of Implicit One byte DAA
the accumulator from
binary to BCD (Decimal-
Adjust Accumulator)
The following points list some key features of arithmetic operations:

(i) For arithmetic operations, one of the data must be stored in the accumulator
and the other given or addressed in the instruction.
(ii) Add-with-carry instructions are used for multi-byte and higher-order byte
addition.
(iii) Similarly, subtract-with-borrow instructions are used in multi-byte and
higher-order byte subtraction.
(iv) Increment and decrement instructions can be operated not only on the
accumulator, but also on other registers including memory locations.
(v) The contents of a register pair can be incremented or decremented using INX
and DCX instructions.
(vi) DAA is the 8085 instruction that supports BCD addition. The addition of
BCD data is done like binary addition, using the ADD instruction. DAA is
used to convert the result of the binary addition of BCD numbers into a BCD
number. This instruction cannot be used to directly convert binary numbers
into BCD numbers.
3.3.4 Logical Instructions

The most important logical instructions supported by the 8085 are AND, OR,
EXOR, and NOT. The complete list is given in Table 3.8.
Table 3.8 Logical instructions

ANI 8-bit The 8-bit data is logically ANDed Immediate Two bytes ANI OFH
with the contents of the accumulator
XRI 8-bit The 8-bit data is logically EXORed Immediate Two bytes XRI01H
ORI 8-bit The 8-bit data is logically ORed Immediate Two bytes ORI 80H
ANAR The contents of the register are Register One byte ANAC
logically ANDed with the contents direct
of the accumulator
XRAR The contents of the register are Register One byte XRAD
logically EXORed with the contents direct
of the accumulator
ORAR The contents of the register are Register One byte ORAE
logically ORed with the contents direct
of the accumulator
ANAM The contents of the memory Indirect One byte ANAM
location pointed to by the HL
register pair is logically ANDed
XRAM The contents of the memory Indirect One byte XRAM
register pair is logically EXORed
ORAM The contents of the memory Indirect One byte ORAM
register pair is logically ORed
RLC Rotates the bits of the accumulator Implicit One byte RLC
left by one position
(Contd)
Table 3.8 Logical instructions (Contd)

RRC Rotates the bits of the accumulator Implicit One byte RRC
right by one position
RAL Rotates the bits of the accumulator Implicit One byte RAL
left by one position, through the carry
RAR Rotates the bits of the accumulator Implicit One byte RAR
right by one position, through
the carry
CPI 8-bit Compares the 8-bit data with the Immediate Two bytes CPI FFH
contents of the accumulator
CMPR Compares the contents of the register Register One byte CMPB
with that of the accumulator direct
CMPM Compares the contents of the memory Indirect One byte CMPM
location pointed to by the HL register
pair with that of the accumulator
CMA Complements the contents of the Implicit One byte CMA
accumulator
CMC Complements the carry Implicit One byte CMC
STC Sets the carry Implicit One byte STC
For logical operations, one of the data must be stored in the accumulator and the
other given or addressed in the instruction. Logical operations can be performed
with immediate data, data stored in a register, or indirectly addressed memory
location content.
Besides the instructions already mentioned, two types of rotate instructions
are available in the 8085. One set—RLC and RRC—rotates the accumulator
contents within itself. The RLC instruction shifts the accumulator content left by
one bit. In the process, the most significant bit of the accumulator becomes the
least significant bit. The RRC instruction shifts the accumulator content right by
one bit.
The other set of rotate instructions—RAL and RAR—rotates the accumulator
content along with the carry flag. The RAL instruction shifts the accumulator
content left by one bit and in the process, the most significant bit will be shifted to
the carry flag and the carry flag content will be shifted to the least significant bit of
the accumulator.
The instruction set of the 8085 supports a compare instruction for comparing
the magnitude of two binary numbers. The compare instructions are used to
compare the accumulator content with the operand specified in the instruction.
CPI instruction uses immediate addressing and CMP uses registers or indirectly
addressed memory location for comparing with the accumulator. The result ot the
compare instruction is indicated in the flag register, as follows:
If [(A) - operand J = 0, i.e., (A) - operand, the zero flag is set.
If [(A) - operand] < 0, i.e., (A) < operand, the carry flag is set.
If [(A) - operand] > 0, i.e., (A) > operand, the zero and carry flags arc reset.
3.3.5 Branching Instructions

Branching instructions are used to transfer the program execution to a different
address. Branching instructions are of two types—-jump instructions and
subroutine instructions. The jump instructions merely transfer the execution from
one location in the program to another, whereas the subroutine instructions in the
main program transfer execution to a new location and also return to the main
program. Return instructions are used for this purpose. The branching can take
place unconditionally or conditionally, based on the flag conditions shown in
Table 3.9. PCHL instruction is a special instruction used to branch to the address
stored in the HL register pair.
RST n is the restart instruction supported by the 8085. Upon execution of the
RST n instruction, the program execution will be transferred to the address given
by n x 8. For example, RST 4 instruction will transfer the execution to the address
0020H which is the hexadecimal equivalent of 32 (in decimal form).
In machine code or opcode, the 16-bit or 4 hex digit addresses in the branching
instructions are given such that the lower-order byte of the address follows the
higher-order byte. For example, JMP 8030H is coded as C3 30 80. The opcode for
JMP, C3, is stored first, followed by 30 and then by 80.
Table 3.9 Branching instructions
Mnemonics Tasks performed on Instruction Example

execution length
JMP 16-bit Jump unconditionally Three bytes JMP 9500

JC 16-bit Jump if carry is set Three bytes JC 9500
JNC 16-bit Jump on no carry Three bytes JNC 9500
JP 16-bit Jump on positive Three bytes JP 9500
JM 16-bit Jump on minus Three bytes JM 9500
JZ 16-bit Jump on zero Three bytes JZ 9500
JNZ 16-bit Jump on no zero Three bytes JNZ 9500
JPE 16-bit Jump on parity even Three bytes JPE 9500
JPO 16-bit Jump on parity odd Three bytes JPO 9500
CALL 16-bit Call unconditionally Three bytes CALL 9500
CC 16-bit Call on carry Three bytes CC 9500
CNC 16-bit Call on no carry Three bytes CNC 9500
CP 16-bit Call on positive Three bytes CP 9500
CM 16-bit Call on minus Three bytes CM 9500
CZ 16-bit Call on zero Three bytes CZ 9500
CNZ 16-bit Call on no zero Three bytes CNZ 9500
CPE 16-bit Call on parity even Three bytes CPE 9500
CPO 16-bit Call on parity odd Three bytes CPO 9500
RET Return unconditionally One byte RET
RC Return on carry One byte RC
(Contd)
Table 3.9 Branching instructions (Contd)
Mnemonics Tasks performed on Instruction Example

execution length
RNC Return on no carry One byte RNC

RP Return on positive One byte RP
RM Return on minus One byte RM
RZ Return on zero One byte RZ
RNZ Return on no zero One byte RNZ
RPE Return on parity even One byte RPE
RPO Return on parity odd One byte RPO
PCHL Copy HL contents to One byte PCHL
the program counter
RST 0/1/2/3/4/ Restart One byte RST 5
5/6/7
3.3.6 Machine Control Instructions

Machine control instructions are used to control the microprocessor execution
and functioning and are listed in Table 3.10. They are explained in detail in the
following points:
(i) NOP means no operation. When this instruction is executed, nothing is done;
no changes occur in the contents of the registers. The program counter alone
is incremented to fetch and execute the next instruction.
(ii) HLT instruction is used to halt the execution of the program. The operation
of the microprocessor is suspended when HLT instruction is executed. The
only way to exit the halt state is to apply the hardware reset signal.
(iii) Interrupts are disabled and enabled using DI and EI signals, respectively.
Once the DI instruction has been executed, the processor ignores any
interrupt request received. To enable interrupts again, the EI instruction has
to be executed. Interrupts are discussed in detail in Chapter 5.
(iv) The SIM instruction is used to send serial data on the serial output data
(SOD) line of the microprocessor and the RIM instruction is used to receive
serial data on the serial input data (SID) line of the processor. RIM and SIM
are explained in detail in Chapter 5.
Table 3.10 Machine control instructions
Mnemonics Tasks performed on execution Addressing Instruction

mode length
NOP No operation Implicit One byte

HLT Halts the microprocessor execution Implicit One byte
DI Disables interrupts Implicit One byte
EI Enables interrupts Implicit One byte
RIM Reads interrupt mask Implicit One byte
SIM Sets interrupt mask Implicit One byte
3.4 SAMPLE PROGRAMS

1. Write an assembly language program to add two numbers.
The program given in Table 3.11 uses immediate addressing for the two data to
be added. The data to be added are stored in memory locations 8001H and 8003H.
The sum is stored in the memory location 8500H. This program assumes that no
cany is generated from the addition.
Table 3.11 Program for adding two 8-bit numbers
Memory Machine code/ Labels Mnemonics with Comments

address Opcode operands
8000 3E START: MVI A, 32H ; Load the first number in

8001 32 the accumulator.
8002 C6 ADI 64H ; Add the second number with
8003 64 the contents of the accumulator.
8004 32 STA 8500H ; Store the sum in the memory
8005 00 location 8500H.
8006 85
8007 76 HLT ; Terminate program execution.
2. Write an assembly language program to add two numbers of 16 bits each.

This program also uses immediate addressing for loading the data in the processor
registers. The sum is stored in the memory locations 8500H and 8501H, as shown
in Table 3.12.
Table 3.12 Program for adding two 16-bit numbers
Memory Machine Labels Mnemonics with Comments

address code/ operands
Opcode
8000 21 START: LXI H, 805FH ; Load the first 16-bit number in

8001 5F the HL register pair.
8002 80
8003 01 LXI B, 123AH ; Load the next number in the BC
8004 3A register pair.
8005 12
8006 09 DAD B ; Add the two numbers using
double addition instruction.
8007 22 SHLD 8500H ; Store the result in the memory
8008 00 locations 8500H and 8501H.
8009 85
800A 76 HLT ; Terminate program execution.
3. Write an assembly language program to add the two numbers stored in the
memory locations 85OOH and 8501H and store the result in 8502H.
This program uses indirect addressing instructions to load the numbers to be
added in the processor registers. The carry, if generated, is ignored. The program
is shown in Table 3.13.
Table 3.13 Program for adding two numbers from memory
Memory Machine Labels Mnemonics with Comments

address code/ operands
Opcode
8000 21 START: LXI H, 8500H ; Initialize HL register pair to point

8001 00 to the memory location of the
8002 85 first number.
8003 7E MOV A, M ; Load the first number in the
accumulator.
8004 23 - INXH ; Increment the HL pair to point to
the memory location of the next
number.
8005 86 ADDM ; Add the two numbers.
8006 23 INXH ; Increment the HL pair to point to
the next memory location.
8007 77 MOV M, A ; Store the contents of the
accumulator in the memory location
pointed to by the HL register pair.
8008 76 HLT ; Terminate program execution.
3.5 INSTRUCTION EXECUTION AND TIMING DIAGRAMS

*
The 8085 microprocessor is designed to fetch the instruction pointed to by the

program counter, and then decode and execute the instruction within the processor.
If necessary, further operand fetch takes place before completing the execution.
Each instruction, as we have already seen, has two parts—operation code (known
as opcode) and operand. The opcode is a command such as ADD and the operand
is an object to be operated on, such as a byte or the contents of a register.
Instruction cycle is the time taken by the processor to complete the execution
of an instruction. An instruction cycle consists of one to six machine cycles.
Machine cycle is the time required to complete one operation—accessing either
the memory or an I/O device. A machine cycle consists of three to six T-states.
T-state is the time corresponding to one clock period. The T-state is the basic
unit used to calculate the time taken for execution of instructions and programs in
a processor.
To execute a program, the 8085 performs various operations such as opcode fetch,
operand fetch, and memory read/write or I/O read/write. The microprocessor’s
external communication function can be divided into three categories:
(i) Memory read/write (ii) I/O read/write
(iii) Interrupt request acknowledge
Table 3.14 gives the various possible states of the processor based on the
control signals IO/M, SO, and SI.
Table 3.14 Processor states and control signals
IO/M S1 SO Processor state
Z A Au
u Halt
(high impedance)
0 0 1 Memory write
1 0 1 I/O write
0 1 0 Memory read
1 1 0 I/O read
0 1 1 Opcode fetch
1 1 1 Interrupt acknowledge
The 8085 microprocessor takes four T-states to execute the opcode fetch machine
cycle and three T-states to execute the memory and I/O read/write cycles. The
interrupt acknowledge cycle is similar to the opcode fetch cycle and is explained
in Chapter 5. Every instruction of the 8085 requires a definite number of machine
cycles. Sections 3.5.1-3.5.5 explain the execution of some instructions, dividing
them into the corresponding machine cycles and further into many T-states.
Figure 3.6 shows the common waveform of the clock signal used in
microprocessor systems. The clock signal is a square waveform of high frequency
in the range of MHz. The rising and falling edge of the clock signal can be clearly
seen, as its frequency is very high and time period is correspondingly very low.
Time period T = 1/f, where f = internal clock frequency
Fig. 3.6 Clock signal for processors
The timing diagram for an instruction is obtained by drawing the binary levels
on the various signals of the 8085. It is drawn with respect to the clock input of
the microprocessor. It explains the execution of the instruction using the basic
machine cycles of that instruction.
3.5.1 Opcode Fetch Machine Cycle

The opcode fetch cycle is the first step in the execution of any instruction. In this
cycle, the microprocessor reads the opcode of an instruction from the memory.
The control and status signals for this machine cycle are IO/M = 0, SO and S1 =
1. This differentiates it from the memory read machine cycle. Every instruction
has a one-byte opcode, which is stored in the memory. Hence, every instruction
execution starts with opcode fetch machine cycle. The timing diagram for this
cycle is shown in Fig. 3.7.
SIGNAL T1 T2 T3 T4
CLOCK
A8-A15 Higher-order memory address Unspecified
AD0-AD7 \/ Lower-order > °Pcocle (D7-D0) V

memory address
ALE
y
IO/M, S1, SO IO/M = 0, S1 = 1 SO = 1
RD
———
Fig. 3.7 Timing diagram for opcode fetch cycle
The following points explain the various operations that take place and the
signals that are changed during the execution of the opcode fetch machine cycle:
During T1 clock cycle
(i) The content of the program counter is placed in the address bus. The lower-
order address is placed in the AD0-AD7 lines and the higher-order address
is placed in the A8-A15 lines. The change of binary levels on these lines is
shown in the timing diagram by a cross.
(ii) IO/M signal goes low to indicate that a memory location is being accessed.
This signal is used by external devices to identify memory and I/O device
accesses for interfacing. The signals on the status lines SO and SI are also
changed to the levels indicated in Table 3.14.
(iii) ALE signal becomes active high to indicate that the multiplexed AD0-AD7
lines are acting as the lower-order address bus.

(i) The multiplexed lower-order address bus is now changed to the data bus. So,
the lower-order address bits in this bus are removed by the processor.
(ii) The active low RD signal is made low by the processor. This signal makes
the memory devices load the data bus with the contents of the memory
location addressed by the processor.
(i) The opcode available in the data bus is read by the processor and moved to
the instruction register.
(ii) After this, the control signal RD is deactivated by making it logic 1.

(i) The opcode placed in the instruction register is decoded by the processor and
the necessary control signal is generated to execute the instruction. Based on
the opcode of the instruction, further operations such as fetching operands,
writing into memory, etc., take place.
The time taken by the processor to execute the opcode fetch cycle is 4 T. The
first three T-states are used for fetching the opcode from memory and the remaining
T-state is used for internal instruction decoding and execution by the processor.
3.5.2 Memory Read Machine Cycle

The memory read machine cycle is executed by the processor to read a data byte
from memory. Instructions that are more than one byte long have the memory read
cycle to read the second byte of the instruction after the opcode fetch cycle.
The memory read machine cycle is exactly the same as the opcode fetch except
for the following:
(i) It only has three T-states. (ii) The SO signal is set to 0.
The timing diagram for the memory read machine cycle is given in Fig. 3.8.
The operations are similar to those in the opcode fetch cycle.
Fig. 3.8 Timing diagram for memory read cycle
3.5.3 Memory Write Machine Cycle

The memory write machine cycle is executed by the processor to write a data byte
in a memory location. The processor takes three T-states to execute this machine
cycle. The active low WR signal is made low, indicating the execution of a write
operation. The timing diagram for this machine cycle is given in Fig. 3.9.
3.5.4 I/O Read Cycle

The I/O read cycle is executed by the processor to read a data byte from an I/O
port or from a peripheral, which is I/O-mapped in the system. The 8085 uses 8-bit
port addresses. So the port address is placed in the lower-order address bus. At the
same time, the port address is also placed in the higher-order address bus. This
facilitates easy design of hardware for address decoding. The processor takes three
T-states to execute this machine cycle. The IN instruction uses this machine cycle.
The timing diagram is given in Fig. 3.10.
3.5.5 I/O Write Cycle

The I/O write machine cycle is executed by the processor to write a data byte to
an I/O port or to a peripheral which is I/O mapped in the system. The processor
takes three T-states to execute this machine cycle. The OUT instruction uses this
machine cycle. The timing diagram is given in Fig. 3.11.
Fig. 3.11 Timing diagram for I/O write cycle
3.5.6 Timing Diagrams for Select Instructions

All 8085 instructions use a combination of the five basic machine cycles—opcode
fetch, memory read, memory write, I/O read, and I/O write. Opcode fetch is
common to all instructions and is the first machine cycle in the execution of any
instruction. Depending on the instruction type, the execution may require further
machine cycles. Sections 3.5.6.1-3.5.6.4 discuss the timing diagrams of select
8085 microprocessor instructions.
3.5.6.1 Timing Diagram for STA 9000H
The STA instruction, upon execution, stores the accumulator contents in the
memory address given in the instruction. STA 9000H stores the accumulator
contents in the memory location 9000H, Since it is a three-byte instruction, it
is fetched in three different machine cycles. Instruction execution is completed

by a memory write machine cycle, which stores the accumulator contents in the
memory.
(i) During the first machine cycle, the program counter content (assumed to
be 800FH) is stored in the address bus and the opcode 32H is fetched and
decoded by the processor.
(ii) During the second machine cycle, the lower-order memory address OOH is
fetched by the processor.
(iii) During the third machine cycle, the higher-order memory address 90H is
loaded in the processor.
(iv) During the fourth machine cycle, the address 9000H is placed on the
address bus and the accumulator contents, 3FH in this case, is written in that
address.
STA requires four machine Table 3.15 STA instruction
cycles and 13 T-states for
execution. The instruction and the Address Mnemonics Opcode
corresponding codes and memory 800F STA 9000H 32

locations are given in Table 3.15. 8010 00
The instruction’s timing 8011 90
diagram is given in Fig. 3.12.
Opcode fetch Memory read Memory read Memory write
Fig. 3.12 Timing diagram for the STA instruction
3.5.6.2 Timing Diagram for IN 80H

The IN instruction is a two-byte instruction and has one opcode followed by the input
port address. This instruction requires three machine cycles—to read the instruction
and then to write the data from the input port address to the accumulator.
(i) During the first machine cycle, the opcode DBH is fetched from the memory,
placed in the instruction register, and decoded.
(ii) During the second machine cycle, the port address 80H is read from the next
memory location.
(iii) During the third machine cycle, the address 80H is placed in the address bus
and the data read from that port address is placed in the accumulator.
The instruction and the Table 3.16 IN instruction
corresponding codes and memory

Address Mnemonics Opcode
locations are given in Table 3.16.
The instruction’s timing 800F IN80H DB
diagram is given in Fig. 3.13. 8010 80
3.5.6.3 Timing Diagram for INR M

Table 3.17 INR instruction
INR M is a one-byte instruction
that increments the contents of a Address Mnemonics Opcode
memory location. The instruction
8100 INRM 34
and the corresponding code and
memory location are given in Table 3.17.
The memory content cannot be changed in the memory location itself. It has to
be read into the processor and then modified. After modification, it has to be written
into the same memory address. So this instruction requires three machine cycles.
(i) During the first machine cycle, the opcode is fetched from the memory
location. In the example shown, the opcode 34H is fetched from the location
81(X)H.
(ii) During the second machine cycle, the contents of the HL register pair are
placed in the address bus, the memory content is brought to the processor,
and its value is incremented.
(iv) During the third machine cycle, the incremented data is again written back
into the same address, as shown in the timing diagram given in Fig. 3.14.
3.5.6.4 Timing Diagram for MVI B, 3FH

Let us study the execution of the instruction MVI B, 3FH. It has the code 06H,
followed by 3FH. The first byte 06H represents the opcode for loading a byte into
register B. The second byte is the data to be loaded.
The 8085 needs two machine cycles to read these two bytes from memory
before it can execute the instruction. The first machine cycle is the opcode fetch,
as discussed earlier. The code 06H is fetched from the memory location 8100H
to the instruction register. The second machine cycle is the memory read cycle.
The operand 3FH is read from the
Table 3.18 MVI instruction
memory location 8101H using the
memory read machine cycle. Address Mnemonics Opcode
The instruction and the 06
8100 MVI B, 3FH
corresponding codes and memory 8101 3F
locations are given in Table 3.18.
The timing diagram for the MVI instruction is given in Fig. 3.15.
3.6 DE-MULTIPLEXING AD0-AD7

The 8085 uses a multiplexed data bus and lower-order address bus. This multiplexing
is done to reduce the pin count of the device. However, external memory or I/O
devices need the complete 16-bit address for decoding and selecting a device. So,
Fig. 3.15 Timing diagram for the MVI instruction
the multiplexed address and data bus must be de-multiplexed. The de-multiplexing
can be done with the help of the signal ALE given by the processor for this purpose.
The hardware needed for de-multiplexing is given in Fig. 3.16.
Fig. 3.16 Hardware interfacing for de-multiplexing lower-order address bus and data bus
During the first T-state in all the machine cycles, the AD0-AD7 lines act
as address bus and the lower-order address is available on these lines. The
AD0-AD7 lines are converted into the data bus during the second T-state.
However, the memory devices require the lower-order address lines during the
entire machine cycle. So, during the first T-state, the lower-order address lines sent
out by the microprocessor is stored into a separate latch or register. The common
74LS373 latch, which has inputs and outputs of 8 bits each, can be used for this
purpose. The ALE control signal is used for latching the address lines available in
the AD0-AD7 lines to the latch in the first T-state. The latched address lines are
available for the entire machine cycle. Memory interfacing and address decoding
are then done using the lines A0-A15 (which are available for the entire machine
cycle). Memory interfacing is discussed in detail in Chapter 6.
POINTS TO REMEMBER^
• The microprocessor operations related to data manipulation can be summarized in the

following four functions:
(i) Transferring data
(ii) Performing arithmetic operations
(iii) Performing logical operations
(iv) Testing for a given condition and altering the program sequence
• The instructions are classified into three groups according to word size: one-, two-, and
three-byte instructions.
• An instruction has two parts—opcode (operation to be performed) and operand (data
to be operated on). The operand can be data (8-bit or 16-bit), addresses, registers, or
implicit in the opcode. The method of specifying an operand (directly, indirectly, etc.)
is called addressing mode.
• The instructions are executed in steps of machine cycles and each machine cycle
requires many T-states.
Addressing mode It is the method of specifying the data to be operated on by the

instruction.
Immediate addressing It transfers the operand given in the instruction—a byte or
word—to the destination register or memory location.
Implied addressing In this addressing mode, the instruction itself specifies the data to
be operated on.
IN This instruction is used to move data from an I/O port to the accumulator.
Indirect addressing It transfers a byte or word between a register and a memory location
addressed by another register.
Instruction cycle It is the time required to execute an instruction.
JMP and CALL JMP instruction permanently changes the program counter. CALL
instruction leaves information on the stack so that the original program execution sequence
can be resumed.
Machine cycle It is the time required to access the memory or input/output devices.
Memory direct addressing It moves a byte or word between a memory location and a
register.
Opcode It is the part of the instruction that specifies the operation to be performed.
Operand It is the data on which the operation is performed.
OUT This instruction is used to move data from the accumulator to an I/O port.
Register direct addressing It transfers a copy of a byte or word from a source register
to a destination register.
Timing diagram It is a graphical representation of the time taken by each instruction for
execution. The execution time is represented in T-states.
T-state It is the basic unit used to calculate the time taken for execution of instructions
and programs in a processor. It is the time corresponding to one clock period.
REVIEW QUESTIONS j
1. List the four categories of 8085 instructions that are used for data manipulation.
2. Define opcode and operand. Identify the opcode and the operand in the instruction
MOV H, L.
3. Explain the instruction XCHG.
4. What is an instruction? List any four arithmetic instructions and their uses.
5. Define stack. Explain the instructions related to stack operations.
6. When is the instruction XRA A used?
7. How many operations are there in the instruction set of the 8085 microprocessor?
8. Explain with examples the different instruction formats, based on the length of the
instructions.
9. List the four instructions which control the interrupt structure of the 8085
microprocessor.
10. What is the last instruction executed in a program? Why?
11. What is the significance of XCHG and SPHL instructions?
12. Explain the operation carried out when the 8085 executes the instruction RST 0.
13. What is addressing? What are the various addressing modes available in the 8085?
14. Explain direct addressing with an example.
15. Explain implied addressing with an example.
16. What are the machine cycles in the 8085 microprocessor?
17. Define T-state. In which T-state is the ALE signal activated?
18. Explain the various timing parameters involved in read and write timings of a typical
RAM.
19. Draw the timing diagram of the instruction MOV C, A.
20. Explain, with the help of a timing diagram, the instruction IN 82H.
21. Explain the timing diagrams for (i) opcode fetch cycle and (ii) I/O write cycle.
22. Draw and explain in brief the timing diagrams for the instruction CALL 2000H, with
appropriate control and status signals.
23. Draw the timing diagram for the instruction STA 4500H and explain.
THINK AND ANSWER
1. Compare the instructions CALL and PUSH.

2. What is the difference between the shift and rotate instructions?
3. How many address lines are there in a 4096 x 8 EPROM chip?
4. Explain the difference between the instructions JMP and CALL.
5. If the instructions CALL and RET were not available in the 8085, would it still be
possible to write subroutines? How would the subroutine be called? How would one
return to the main program?
6. If a 5 MHz crystal is connected with the 8085, what would the system clock frequency
and duration of one T-state be?
7. How long would the processor take to execute the instruction LDA 1753H if the T-state
duration is 2 ps?
CHAPTER 4 I
ASSEMBLY LANGUAGE
PROGRAMMING OF 8085
LEARNING OUTCOMES
• Assemblers and their types
• Assembler directives
• Programming examples based on simple arithmetic and logical operations
♦ Programming examples based on looping and branching operations
• Code conversion, decimal arithmetic, and bit manipulation
• Programming examples based on subroutine concepts
• Programming examples based on counters and time delays
4.1 ASSEMBLER
An assembler is a program that is used to translate assembly language mnemonics
into equivalent binary code. The assembly language, and hence the assembler
program, varies from one processor to another. The 8085 assembler program
converts mnemonic code into binary object code or machine code, which can be
executed by the 8085 microprocessor. The assembler is a software tool or program
to be used with a computer. The functioning of an assembler program is shown in
Fig. 4.1. The object code or machine code file generated in the computer system is
then used in an 8085-based system.
Fig. 4.1 Functioning of an assembler
The input to the assembler is a file with the extension .asm. The assembler
output consists of at least two possible files:
(i) The object or the hex fi ie that contains the binary machine code corresponding
to each mnemonic in the source assembly language program.
(ii) The list file containing the source assembly code along with the corresponding
machine code generated by the assembler and the list of symbols used in the
assembly program.
While different types of assemblers are commercially available, the most
common are the one-pass assembler, two-pass assembler, macro assembler, and
cross assembler. In one-pass assembler, the assembly language program is processed
only once from start to end. In two-pass assembler, the assembly language program
is processed twice—once for symbols and labels, to assign memory locations for
them, and then once again for the actual assembly process. Cross assemblers are
used to convert assembly language programs into machine codes that can be run on
other processors. This assembly process can be done on any PC.
The macro assembler is an assembler that contains a provision for the
programmer to define macro instructions. Macros are user-defined abbreviations
for particular sequences of program routine. When the program is assembled, each
occurrence of the macro is replaced by the instructions for which it stands.
4.1.1 Need and Advantages

Assemblers are very useful to programmers who develop projects in assembly
language. The major benefits of using assemblers are as follows:
(i) Assembly language programs can be converted into machine language
manually if the programs are small. However, in the case of large programs
it is very difficult to compute the data manually. Hence, assemblers are used
to translate the assembly language programs to machine language codes.
(ii) Assembly language programs provide the flexibility of using symbols
for variables and constants used in the program. The assembler will then
allocate memory locations for the symbols used. Normally, programmers
have to use the variables and data in their programs. Program instructions
use memory locations to store and retrieve data. If at any time the data has
to be changed, the symbols used in the assembly language simplify the
task. This, in turn, simplifies program development. In addition, it is easy
to change the values assigned to the symbols. The assembler can reserve
memory locations for the data, results, and arrays in the program.
(iii) Similarly, assembly language programs allow the programmer to use labels
instead of physical addresses. This feature offers the flexibility to specify
jump addresses indirectly; any change in the physical address is taken care
of by the assembler.
(iv) The program can be written starting at any physical address. So the
programmer need not bother about the jump addresses every time the
program is edited; the assembler will calculate the correct addresses
automatically, if the starting address alone is given.
(v) The assembler converts mnemonics into machine code with high speed and
accuracy—this eliminates human errors.
ASSEMBLY LANGUAGE PROGRAMMING OF 8085 65
(vi) The assembler checks for syntax errors such as errors in opcodes, labels,
and expressions and indicates the occurrence of these errors.
4.1.2 Assembler Directives

Assembler directives are instructions passed on to the assembler by the
programmer. They inform the assembler about the issues in generating the object
code. Generally, directives are in the form of mnemonics and can be placed
anywhere in the assembly language program. The assembler directives provide
information such as the start and end points of a program, values of variables used,
storage locations for input and output data, etc., to the assembler. The assembler
directives are also called pseudo instructions because the information they pass
to the assembler is not translated into machine code. Table 4.1 gives the list of
assembler directives used by common 8085 assemblers.
Table 4.1 Assembler directives
Assembler directive Example Description
ORG (origin) ORG 8000 The next block of instructions or data

should be stored in memory locations
starting at 8000. Either hex or decimal
numbers are acceptable.
END end start End of assembly. A HLT instruction may
suggest the end of a program, but does not
necessarily mean it is the end of assembly.
‘Start’ is the label at the beginning of the
program.
EQU (equate) lookup equ 2 The value of the term, lookup, is equal
to 2. Lookup’s value may be referred by
name in the program. Similar to a constant
statement.
inbuf equ 2099 The value of the term, inbuf, is 2099. This
may be the memory location used as an
input buffer.
DB (define byte) data: db 34 Initializes an area byte by byte. Assembled
or bytes of data are stored in successive
data: db 34 memory locations until all values are stored.
db A2 The label is optional and may be used as
db 93 the memory location of the beginning of the
data.
DW (define word) long: dw 2050 Initializes an area two bytes at a time.
DS (define storage) table: ds 10 Reserves a specified number of memory
locations. In this example, 10 memory
locations are reserved for ‘table’. The label
may be used as the memory location at the
beginning of the block of memory.
The assembler directive ORG is placed at the beginning of the program; it

specifies the first of a series of addresses where the machine language program
must be stored. The start and end directives are used to indicate the start and end of
the assembly language program and so the assembly process. The EQU directive
is used to set constants and assign values to them. The EQU statement ensures
that the programmer need not change all occurrences of the constant value; it is
enough to change the EQU directive. The DB, DW, and DS directives are used to
assign memory locations to the variables and allocate values to them as explained
in Table 4.1.
4.2 ASSEMBLY LANGUAGE PROGRAMS

The 8085 instruction set contains about 74 different operation mnemonics,
which are classified as data transfer instructions, arithmetic instructions, logical
instructions, branch control instructions, and machine control instructions. A good
assembly language programmer must know all the instructions of a microprocessor
in order to write an efficient and effective program.
To write a program, the problem must first be understood. Then the functional
objectives, inputs, and outputs must be identified clearly. Writing an assembly
language program needs proper planning. The given problem should be broken
down into smaller functions or operations that can be programmed independently.
This approach is called the modular design approach. Subroutines are the functional
subprograms within assembly language programs. When a set of operations are
repeated several times in a program, it is efficient to write that set of operations
as a subroutine. Every subroutine is written for a specific operation and can be
called from the main program. The programmer has to pass the arguments for the
subroutine properly.
Writing a program then involves giving specific instructions in a sequence to
the microprocessor, to complete the required operation. The sequence of operations
used to solve a problem is called algorithm. A single problem can be solved in more
than one way, meaning that there is more than one algorithm to solve a programming
problem. The algorithm developed for a program can be written in simple steps or
can be easily represented in a diagrammatic format called flowchart. A flowchart
uses different shapes to represent operations such as commencement of program
execution, input/output operation, process, subroutine, and termination.
To summarize, the general steps in writing an assembly language program are
Step 1: Read the programming problem carefully.
Step 2: Identify the input and output arguments in the program.
Step 3: Break the problem down into small steps. If necessary, plan for
subroutines.
Step 4: Represent these small steps in a possible sequence with a flowchart.
Step 5: Translate each block of the flowchart into appropriate mnemonic
instructions. Keep track of the variables and memory locations used.
Step 6: Convert the assembly language mnemonics into the machine code either
manually or using an assembler. Enter the machine code in the memory
and execute.
Step 7: Debug the program.

The following sections list a few programming examples that use 8085
assembly language mnemonics. Although there are multiple ways to write the
programs, only one/two programs are given for each question.
4.2.1 Programming Examples based on Simple Arithmetic and Logical Operations

This section lists programs that use arithmetic and logical operations. Let us now
recollect some of the arithmetic operations we saw in Chapter 3.
4.2.1.1 Arithmetic Operations
The 8085 microprocessor performs various arithmetic operations such as addition,
subtraction, increment, and decrement. The mnemonics used for these arithmetic
operations are reproduced here.
ADD : Add Adds the contents of a register and the
accumulator
ADI : Add Immediate Adds 8-bit data to the accumulator
SUB : Subtract Subtracts the contents of a register
from the accumulator
SUI : Subtract Immediate Subtracts 8-bit data from the
accumulator
INR : Increment Increases the contents of a register by 1
DCR : Decrement Decreases the contents of a register by 1
The 8085 uses an accumulator-oriented ALU. So one of the operands used in

arithmetic operations must be stored in the accumulator. Arithmetic operations
such as ADD and SUB need one data to be stored in the accumulator. However,
the increment and decrement operations can be performed in any register.
4.2.1.2 Logical Operations
The 8085 instruction set includes the logic functions AND, OR, EXOR, and NOT.
One of the operands in logical operations must be placed in the accumulator, just
like in arithmetic operations. The mnemonics of these operations are as follows:
ANA : AND Logically AND the contents of a
register with the accumulator
ANI : AND Immediate Logically AND 8-bit data with the
accumulator
ORA : OR Logically OR the contents of a
ORI : OR Immediate Logically OR 8-bit data with the
accumulator
XRA : EXOR Exclusive OR the contents of a
XRI : EXOR Immediate Exclusive OR 8-bit data with the
accumulator
4.2.1.3 Programming Examples

This section gives examples of programs that use arithmetic and logic instructions.
Example 4.1:
Store the data byte FFH in the memory location 9000H.
Program 1:
This uses direct addressing to access the memory location, as shown in Table 4.2 (a).
Table 4.2 (a) Program for storing data in memory using direct addressing
Mnemonics Comments
MVI A, FFH ; Store FFH in the accumulator.

STA 9000H ; Copy accumulator contents to the address 9000H.
HLT ; Terminate program execution.
Program 2:
This uses indirect addressing to access the memory location, as shown in
Table 4.2 (b).
Table 4.2 (b) Program for storing data in memory using indirect addressing
Mnemonics Comments
LXI H, 9000H ; Load HL with 9000H.

MVI A, FFH ; Store FFH in the accumulator.
MOV M, A ; Store FFH in the memory location pointed to by the HL register
pair (9000H).
The result of both programs will be the same.

Example 4.2:
Exchange the contents of memory locations 9000H and 9050H.
The contents of two memory locations can be exchanged using direct and indirect
addressing, as shown in Tables 4.3 (a) and 4.3 (b), respectively.
Program 1:
Table 4.3 (a) Program for exchanging contents of memory locations using direct addressing
Mnemonics Comments
LDA 9000H ; Load the contents of memory location 9000H in the accumulator.
MOV C, A ; Move the contents of the accumulator to register C.
LDA 9050H ; Load the contents of memory location 9050H in the accumulator.
(Contd)
Table 4,3 (a) Program for exchanging contents of memory locations using direct addressing
(Contd)
Mnemonics Comments
STA 9000H ; Store the contents of the accumulator in memory address 9000H.
MOV A, C ; Move the saved contents in register C back to the accumulator.
STA 9050H ; Store the contents of the accumulator in 9050H.
Program 2:
Table 4.3 (b) Program for exchanging contents of memory locations using indirect addressing
Mnemonics Comments
LXI H, 9000H ; Load the first address 9000H in the HL register pair.
LXI D, 9050H ; Load the second address 9050H in the DE register pair.
MOV C, M ; Move the contents of memory location 9000H to register C.
LDAXD ; Move the contents of memory location 9050H to the
accumulator.
MOV M, A ; Store the contents of the accumulator in memory location
9000H.
MOV A, C ; Move the contents of register C to the accumulator.
STAXD ; Store the contents of the accumulator in the memory location
9050H.
Example 4.3:
Add the numbers present in memory locations 9000H and 9001H. Store the result
in memory location 9002H.
Sample data:
(9000H) = 32H
(9001H) = AAH
Result = 32H + AAH = DCH
Flowchart:
The algorithm for this problem is explained in the form of a flowchart in
Fig. 4.2.
Program:
It neglects the carry (if any) produced in the addition. So it works only for 8-bit
sum. The program is given in Table 4.4.
Fig. 4.2 Algorithm for adding two numbers
Table 4.4 Program for adding two numbers and placing the result in a memory location
Mnemonics Comments
MOV A, M ; Load the first operand in the accumulator.
INXH ; Load the second address 9001H by incrementing the HL pair by 1.
ADDM ; Add the content of 9001H to the accumulator.
INXH ; Load the third address 9002H by incrementing the HL pair by 1.
MOV M, A ; Store the result of addition in 9002H.
Example 4.4:
Subtract the contents of memory location 9001H from that of memory location
9000H and store the result in memory location 9002H.
Sample data:
(9000H) = CCH
(9001H) = AOH
Result = CCH - AOH = 2CH
Flowchart:
The algorithm for this problem is explained in the form of a flowchart in
Fig. 4.3.
Program:
The program given in Table 4.5 subtracts one 8-bit number from another and
stores the result in a memory location.
Fig. 4.3 Algorithm for subtracting one number from another
Table 4.5 Program for subtracting one number from another and placing the result in
a memory location
Mnemonics Comments
MOV A, M ; Load the first operand in the accumulator.
INXH ; Load the second address 9001H by incrementing the HL pair by 1.
SUB M ; Subtract the second operand from the first.
INXH ; Load the third address 9002H by incrementing the HL pair by 1.
MOV M, A ; Store the result of subtraction in 9002H.
Example 4.5:
Two 16-bit numbers are available in memory locations 9000H and 9001H, and
in 9002H and 9003H, where the most significant bits are in 9001H and 9003H.
Add the two numbers and save the result in 9004H and 9005H, with the most
significant byte in 9005H.
Sample data:
(9000H) = AAH
(9001H) = 55H
(9002H) = BBH
(9003H) = 21H
Result = 55 AAH + 21 BBH = 7765H
(9004H) = 65H
(9(X)5H) = 77H
Flowchart:
The step-by-step solution to this problem is illustrated in Fig- 4-
Fig. 4.4 Algorithm for adding two 16-bit numbers
Tables 4.6 (a) and 4.6 (b) illustrate two programs that add two 16-bit numbers and
store the result in two consecutive memory locations.
Program I:
Table 4.6 (a) Program for adding two 16-bit numbers using ADD and ADC instructions
Mnemonics Comments
LHLD 9000H ; Load the first 16-bit number in the HL register pair.
XCHG ; Save the first 16-bit number in the DE register pair.
LHLD 9(X)2H ; Load the second 16-bit number in the HL register pair.
MOV A, E ; Move the lower-order byte of the first number to the accumulator.
ADD L ; Add the lower-order bytes of the two numbers.
(Contd)
Table 4.6 (a) Program for adding two 16-bit numbers using ADD and ADC instructions (Contd)
Mnemonics Comments
MOV L, A ; Store the result in register L.
MOV A, D ; Move the higher-order byte of the first number to the accumulator.
ADC H ; Add the higher-order bytes of the two numbers with carry.
MOV H, A ; Store the result in register H.
SHLD 9004H ; Store the 16-bit result in memory locations 9004H and 9005H.
Program 2:
Table 4.6 (b) Program for adding two 16-bit numbers using DAD instruction
Mnemonics Comments
LHLD 9002H ; Load the second 16-bit number in the HL register pair.
DADD ; Add the DE and HL register pairs.
In Program 1, the 8-bit addition instructions ADD and ADC are used and addition
is performed in two steps. The lower-order bytes are added first, using ADD
instruction, and then the higher-order bytes using ADC instruction. In Program 2,
the 16-bit addition instruction DAD is used. Both programs assume that the result
is only 16-bits wide and neglect any carry generated.
Example 4.6:
Two numbers are stored in memory locations 9000H and 9001H. Add them and
store the result (including the carry) in memory locations 9002H and 9003H.
Sample data:
(9OOOH) = F1H
(9001H) = 5AH
Result = Fl H + 5AH = 014BH
(9002H) = 4BH
(9003H) = 01H
Flowchart:
Figure 4.5 illustrates the step-by-step method to solve this programming exercise.
Program:
This program includes the carry generated after 8-bit addition; the result is stored
in two registers, as shown in Table 4.7.
Fig. 4.5 Algorithm for adding two numbers including carry
Table 4.7 Program for adding two numbers including carry
Label Mnemonics Comments
MVI B, OOH ; Initialize register B to OOH for storing the carry

(if any).
MOV A, M ; Load the first number in the accumulator.
INXH ; Load the second address 9001H by incrementing the
HL pair by 1.
ADDM ; Add the two numbers.
' JNC NEXT ; If no carry is generated, do not increment register B.
INRB ; If a carry is generated, increment register B.
NEXT: INX H ; Load the third address 9002H by incrementing the HL
pair by 1.
MOV M, A ; Store the lower-order byte of the result in 9002H.
MOV A, B ; Move the carry to the accumulator.
INX H ; Load the fourth address 9003H by incrementing the
HL pair by 1.
MOV M, A ; Store the higher-order byte of the result in 9003H.
Example 4.7:
Two 16-bit numbers are available in memory locations 9000H and 9001H, and
in 9002H and 9003H, where the most significant bits are in 9001H and 9003H.
Subtract the latter from the former and save the result in 9004H and 9005H, with
the most significant byte in 9005H.
Sample data:
(9000H) = FFH
(9001H) = EEH
(9002H) = 43H
(9003H) = 21H
Result = EEFFH - 2143H = CDBCH
(9004H) = BCH
(9005H) = CDH
Flowchart:
The algorithm for this programming exercise is given in Fig. 4.6.
Fig. 4.6 Algorithm for subtracting one 16-bit number from another
Program:
The program for subtracting one 16-bit number from another and saving the result
in two consecutive memory locations is given in Table 4.8.
Table 4.8 Program for subtracting one 16-bit number from another
Mnemonics Comments
LHLD 9002H ; Load the second 16-bit number in the HL register pair.
MOV A, E ; Move the lower-order byte of the first number to the
accumulator.
SUB L ; Subtract the lower-order byte of the second number from that of
the first.
MOV L, A ; Store the result in register L.
MOV A, D ; Move the higher-order byte of the first number to the
accumulator.
SBB H ; Subtract the higher-order byte of the second number and borrow
from the contents of the accumulator.
MOV H, A ; Store the result in register H.
Example 4.8:
Find the l’s complement of the number stored in memory location 9000H. Store
the result in memory location 9001H.
Sample data:
(9000H) = 55H
Result = (9001H) = AAH
Flowchart:
The algorithm for finding the
l’s complement of a number is
given in Fig. 4.7.
Cl End 2-^
Fig. 4.7 Algorithm for finding 1 's complement of a number
Program:
Table 4.9 shows the program for finding the l’s complement of a number.
Table 4.9 Program for finding 1 's complement of a number
Mnemonics Comments
LDA 9000H ; Load the number to be complemented in the accumulator.
CMA ; Complement the number.
STA 9001H ; Store the result.
Example 4.9:
Find the 2’s complement of the number stored in memory location 9000H. Store
the result in memory location 9001H.
Sample data:
(9000H) = 55H
Result = (9001H) = AAH + 1 = ABH
Flowchart:
The procedure for finding the 2’s complement of a number is illustrated in
Fig. 4.8.
Program:
The 2’s complement of a number can be found using the program given in
Table 4.10.
Fifl. 4.8 Algorithm for finding 2's complement of a number

Table 4.10 Program for finding 2’s complement of a number
Mnemonics Comments
LDA 9000H ; Load the number to be complemented in the accumulator.

CMA ; Complement the number.
ADI01H ; Add one to the complement.
STA 9001H ; Store the result.
Example 4.10:
Write a set of instructions to read and complement the contents of the flag
register.
Program:
In the 8085, the contents of the flag register and the accumulator together are
called program status word (PSW). The PSW can be accessed only using PUSH
and POP instructions. The PUSH instruction moves the flag register contents (as
the lower-order byte) and the accumulator contents (as the higher-order byte) to
the stack.
The contents of the flag register can be read and complemented using the program
given in Table 4.11.
Table 4.11 Program for reading and complementing the contents of the flag register
Mnemonics Comments
PUSH PSW ; Push the contents of the accumulator and the flag register onto the stack.
POPH ; Bring the PSW to the HL pair.
MOV A, L ; Move the contents of the flag register to the accumulator.
CMA ; Complement the accumulator.
MOV L, A ; Store the complemented flags in register L.
PUSHH ; Push the contents of the HL register pair onto the stack.
POP PSW ; Pop it back to the PSW.
Example 4.11:
Write a program to shift the 16-bit number in the HL register pair left by one bit.
Program:
A binary number can be shifted left by one bit by adding the number to itself.
Adding a number to itself also multiplies it by two.
DAD H: Adds the content of the HL register pair to itself.
Sample data:
(HL) = 57EAH = 0101 0111 1110 1010
(HL) + (HL) = 1010 1111 1101 0100

Result =1010 1111 1101 0100 = AFD4H
Example 4.12:
Write a program to shift
the 8-bit number in
memory location 9000H
right by four bits.
Rotating a binary
number right once is
equivalent to dividing by
two. So rotating it right
four times is equivalent
to dividing by 16. Store the result in another memory location
Flowchart:
The algorithm for
shifting an 8-bit number
right by four bits is
shown in Fig. 4.9.
Fig. 4.9 Algorithm for shifting an 8-bit number right by four bits
Program:
The program given in Table 4.12 shifts an 8-bit number right by four bits.
Table 4.12 Program for shifting an 8-bit number right by four bits
Mnemonics Comments
LDA 9000H ; Load the number in the accumulator.
RRC ; Rotate right without carry.
STA 9001H ; Store the result in memory location 9001H.
Example 4.13:
Write a program to shift a 16-bit number right by one bit. Assume that the data is
in memory locations 9000H and 9001H. Store the result in 9002H and 9003H.
Flowchart:
The algorithm for shifting a 16-bit number right by one bit is shown in Fig- 4.10.
Fig. 4.10 Algorithm for shifting a 16-bit number right by one bit
Program:
The program for shifting a 16-bit number right by one bit is given in Table 4.13.
Table 4.13 Program for shifting a 16-bit number right by one bit
Mnemonics Comments
LHLD 9000H ; Load the number in the HL register pair.

MOV A, H ; Move the higher-order byte to the accumulator.
RAR ; Rotate the accumulator right through carry.
MOV & £ fr ; Move the result to register H.
MOV A, L ; Move the lower-order byte to the accumulator.
RAR ; Rotate the accumulator right through carry.
MOV L, A ; Move the result to register L.
^SHLD 9002H
; Store the result in memory locations 9002H and 9003H.
T) —----------
Êxample 4.14:
Pack the two unpacked 4-bit single digit BCD numbers stored in memory locations
9000H and 9001H. The least significant digit is in 9000H. Store the result in
memory location 9002H.
Sample data:
(9000H) = 07H
(9001H) = 01H
Result = (9002H) = 17H
Flowchart:
The algorithm for packing two unpacked BCD numbers is given in Fig. 4.11.
Fig. 4.11 Algorithm for packing two unpacked BCD numbers
Program:
The program for packing two unpacked BCD numbers is given in Table 4.14.
Table 4.14 Program for packing two unpacked BCD numbers
Mnemonics Comments
LDA 9000H ; Load the least significant BCD digit in the accumulator.
MOV B, A ; Move it to register B.
LDA 9001H ; Load the most significant BCD digit in the accumulator.
RLC ; Rotate the accumulator left without carry.
RLC ; Move the digit to the higher-order four bits by shifting left four times.
ORA B ; Add the lower-order BCD digit, keeping the higher-order unchanged.
(Contd)
Table 4.14 Program for packing two unpacked BCD numbers (Contd)
Mnemonics Comments
STA 9002H ; Store the result in memory location 9002H.

Example 4.15:
Unpack the 2-digit BCD number in memory location 9000H and store the two
digits in memory locations 9001H and 9002H, with the units digit in 9001H.
Sample data:
(9000H) = 31H
Result = (9001H) = 01H and (9002H) = 03H
Flowchart:
The algorithm for unpacking a packed BCD number is given in Fig. 4.12.
Fig. 4.12 Algorithm for unpacking a packed BCD number

Program:
The program given in Table 4.15 unpacks a packed BCD number.
Table 4.15 Program for unpacking a packed BCD number
Mnemonics Comments
LDA 9000H ; Load the packed BCD number in the accumulator.

ANI F0H ; Mask the lower-order nibble.
RRC ; Rotate the accumulator right without carry.
RRC ; Move the higher-order BCD digit to the least significant four bits by
shifting it right four times.
STA 9001H ; Store the partial result in 9001H.
LDA 9000H ; Load the original BCD number in the accumulator.
ANI0FH ; Mask the higher-order nibble.
STA 9002H ; Store the result in 9002H.
Example 4.16:
A 4-digit BCD number is stored in memory locations 9000H and 9001H and
another in memory locations 9002H and 9003H. Add the two BCD numbers and
store the result in memory locations 9004H and 9005H. Ignore the carry after the
16th bit.
Sample data:
(HL) = 3629
(DE) = 4738
Step 1:29 + 38 = 61 and auxiliary carry flag = 0
Auxiliary carry flag is set. So add 06 (decimal adjust accumulator)
61+06 = 67
Step 2: 36 + 47 + 0 (carry of LSB) = 7D
Lower nibble is greater than 9. So add 06.
7D + 06 = 83 (decimal adjust accumulator)
Result = 8367
Flowchart:
The algorithm for adding two 4-digit BCD numbers is given in Fig. 4.13.
Program:
The program for adding two 4-digit BCD numbers is given in Table 4.16.
f-
S'-
'»■
Fig. 4.13 Algorithm for adding two 4-digit BCD numbers

Table 4.16 Program for adding two 4-digit BCD numbers
Mnemonics Comments
LHLD 9000H ; Load the first 4-digit BCD number in the HL register pair.
XCHG ; Move it to the DE register pair.
LHLD 9002H ; Load the second 4-digit BCD number in the HL register pair.
MOV A, L ; Load the two lower-order digits of the first number in the
accumulator.
ADDE ; Add with the two lower-order digits of the second number.
DAA ; Adjust the result to make it a valid BCD number.
MOV A, H ; Load the two higher-order digits of the first number in the
accumulator.
ADCD ; Add with the two higher-order digits of the second number and the
carry of the previous addition.
DAA ; Adjust the result to make it a valid BCD number.
4.2.2 Programming Examples based on Looping and Branching

The examples we have discussed so far do not need branching and looping.
However, most programs need to branch and loop, depending on the result of
a status check, or data check and verification. In this section, we shall discuss
programs that require branching or looping.
4.2.2.1 Branching Operations
Microprocessors use Von-Neumann architecture and execute machine codes from
one memory location to the next in a sequential manner. Branching instructions
instruct the microprocessor to go to a different memory location and continue
executing machine codes from that new location. This type of jumping can be done
either unconditionally or conditionally based on the status of the flags. Branch
instructions can be any one of the following three categories:
(i) Jump instructions
(ii) Call and return instructions
(iii) Restart instructions
Jump instructions transfer the control of the processor execution permanently to the
jump address defined by the programmer. Call and return instructions, on the other
hand, provide the flexibility to jump to the address provided by the programmer
and then return the address from where it was called. Restart instructions jump to
the address decided by the internal hardware of the processor.
4.2.2.2 Looping Operations

Programming languages use any one of three basic structures—if-then-else,
while-do, and repeat-until—in addition to the sequential structure. The while-do
and repeat-until structures use the looping technique to repeat tasks. A loop is
set up by instructing the microprocessor to execute a task and then change the
sequence of execution and perform the task again. This process is accomplished
using jump instructions. Techniques such as counting and indexing are used in
setting up a loop. Loops can be classified into two groups:
(i) While-do continuous loop—repeats a task if a condition is satisfied.

(ii) Repeat-until conditional loop—repeats a task until certain conditions are
met. This is similar to the FOR loop in high-level languages.
4.2.2.3 Programming Examples
The following programs use branching and looping operations.
Example 4.17:
Count the number of Is in the contents of the memory location 9000H and store
it in 9001H.
This program uses a counter to check all the eight bits of the number in register D.
This is similar to the FOR loop.
Flowchart:
The algorithm for counting the number of Is in a register and storing it in another
is given in Fig. 4.14.
Program:
The*program for counting the number of Is in a register and storing it in another
is given in Table 4.17.
Table 4.17 Program for counting the number of 1s in a register

MVI B, OOH ; Initialize register B as a counter with initial value OOH.
MVI C, 08H ; Initialize register C as a counter for looping, with initial
value 08H.
LOOP: RAR ; Rotate the contents of the accumulator right, through the
carry, to check each bit.
JNC NEXT ; If the bit is not 1, go to NEXT.
INRB ; If the bit is 1, increment counter B.
NEXT: DOR C ; Decrement counter C.
JNZ LOOP ; If counter C is not zero, jump to LOOP.
MOV A, B ; Move the result from register B to the accumulator.
STA 9001H ; Store the result in 9(XJ1H.
Fig. 4.14 Algorithm for counting the number of 1s in a register
Example 4.18:
Transfer ten bytes of data from one memory block to another. The source memory
block begins at 9000H, while the destination memory block begins at 9100H.
Program:
The program for transferring a block of data from one series of memory locations
to another is given in Table 4.18.
Table 4.18 Program for transferring a block of data between memory locations
LXI H, 9000H ; Initialize source memory pointer.

LXI D, 91 OOH ; Initialize destination memory pointer.
MVI B, OAH ; Initialize counter to count ten bytes of data.
LOOP: MOV A, M ; Get data from the source address.
STAXD ; Store it in the destination address.
INXH ; Increment the source address.
INXD ; Increment the destination address.
DCRB ; Decrement the counter.
JNZ LOOP ; If value of the counter is not equal to zero, jump to

LOOP.
HLT ; If it is zero, terminate the program.
Example 4.19:
Two 8-bit numbers are available in memory locations 9000H and 9001H. Multiply
them by repetitive addition and store the result in memory locations 9002H and
9003H.
Sample data:
(9000H) = A1H
(9001H) = 04H
Result = A1H + A1H + A1H + A1H = 284H
(9002H) = 84H
(9003H) = 02H
Flowchart:
The algorithm for multiplying two 8-bit numbers by repetitive addition is given
in Fig. 4.15.
Program:
The program given in Table 4.19 multiplies two 8-bit numbers by repetitive
addition.
Table 4.19 Program for multiplying two 8-bit numbers by repetitive addition
LDA 9000H ; Load the first number in the accumulator.

MOV E, A ; Move the first number to register E.
MVI D, OOH ; Load register D with OOH so that the DE register pair
now contains the first number.
LDA 9001H ; Load the second number in the accumulator.
(Contd)
Table 4.19 Program for multiplying two 8-bit numbers by repetitive addition (Contd)
MOV C. A ; Initialize the second number as a counter in register C.

LXI H, 0000H ; Initialize Result = 0.
LOOP: DAD D ; Result = Result + first number.
DCR C ; Decrement the counter.
JNZ LOOP ; If the counter is not equal to zero, repeat the addition
process.
SHLD 9002H ; Store the result in 9002H and 9003H.
Fig. 4.15 Algorithm for multiplying two 8-bit numbers by repetitive addition
Example 4.20:
A 16-bit number is stored in memory locations 9000H and 9001H and an 8-bit
number in 9002H. Divide the former by the latter; store the quotient in 91 OOH and
9101H and the remainder in 9102H and 9103H.
Sample data:
(9000H) = 9FH
(9001H) = 70H
(9002H) = OFH
Result = 709FH/0FH = 782H (quotient) and 01H (remainder)
(9100H) = 82H
(9101H) = 07H
(9102H) = 01H
(9103H) = OOH
Flowchart:
Figure 4.16 shows the algorithm for dividing a 16-bit number by an 8-bit
number.
Fig. 4.16 Algorithm for dividing a 16-bit number by an 8-bit number

Program:
The program for dividing a 16-bit number by an 8-bit number is given in
Table 4.20.
Table 4.20 Program for dividing a 16-bit number by an 8-bit number
LHLD 9000H ; Load the dividend in the HL register pair.

LDA 9002H ; Load the divisor in the accumulator.
MOV C, A ; Move the divisor to register C.
LXI D, 0000H ; Initialize quotient = 0 in the DE register pair.
BACK: MOV A, L ; Move the lower-order byte of the dividend to the
accumulator.
SUB C ; Subtract divisor from the contents of the accumulator.
MOV L, A ; Move the partial result back to register L.
JNC SKIP ; If no carry is generated, jump to SKIP.
MOV A, H ; If a carry is generated, move the higher-order byte of the
dividend to the accumulator.
CPI OOH ; Check if the higher-order byte is zero.
JZ NEXT ; If it is, jump to NEXT.
DCRH ; If it is not, subtract the borrow of the previous
subtraction from the higher-order byte.
SKIP: INXD ; Increment the quotient.
JMP BACK ; Loop back for the next subtraction.
NEXT: MOV A, L ; Correct the remainder by adding the divisor to it.
ADDC
MOV L, A
SHLD9102H ; Store the remainder.
XCHG ; Exchange the contents of the HL and DE register pairs.
SHLD 91 OOH ; Store the quotient.
Example 4.21:
Two 8-bit unsigned numbers are stored in memory locations 9000H and 9001H.
Multiply them and store the result in memory locations 9002H and 9003H, with
the most significant bits in 9003H.
Sample data:
(9000H) =0000 1100 (OCH)
(9001H) =0000 0101 (05H)
Multiplicand = 1100(12D)
Multiplier =0101 (5D)
Result =12x5 = (60D)
1100 —Multiplicand
0101 — Multiplier
0001100 — Least bit of multiplier multiplied with multiplicand
000000- — Second bit of multiplier multiplied with shifted multiplicand
01100— — Third bit of multiplier multiplied with shifted multiplicand
0000— — Fourth bit of multiplier multiplied with shifted multiplicand
0111100 — Added to get product
Flowchart:
The algorithm for multiplying an 8-bit number by another is given in Fig. 4.17.
Program:
The program for multiplying an 8-bit number by another is given in Table 4.21.
Table 4.21 Program for multiplying an 8-bit number by another
LXI H, 9000H ; Initialize the memory pointer.

MOV E, M ; Load the multiplicand in register E.
MVI D, OOH ; Extend it to 16 bits.
INXH ; Increment the memory pointer.
MOV A, M ; Load the multiplier in the accumulator.
LXI H, 0000H ; Initialize Product = 0.
MVI B, 08H ; Initialize the bit counter with initial value = 08H.
MULT: RAL ; Check the bit of the multiplier.
JNC SKIP ; Is the bit 1?
DADD ; If it is, Product = Product + multiplicand.
SKIP: XCHG ; Exchange the contents of the DE and HL register pairs.
DADH ; Shift the multiplicand left by one bit by adding it to itself.
XCHG ; Exchange the contents of the DE and HL register pairs.
DCRB ; Decrement the bit counter.
JNZ MULT ; If it is not equal to zero, repeat the process.
SHLD 9002H ; Store the result.

Fig. 4.17 Algorithm for multiplying an 8-bit number by another
Example 4.22:
A 16-bit unsigned number is stored in memory locations 9000H and 9001H (most
significant bits in 9001H) and an 8-bit unsigned number in memory location
9002H. Divide the former by the latter and store the quotient in memory location
91 OOH and the remainder in 9101H.
Sample data: The numerical calculation shown explains the algorithm used
10101 in this exercise. The example here shows an 8-bit dividend
0100)01010 ’ divided by a 4-bit divisor. The calculation shown is 86/4. This
oiooj produces a quotient of 21, which is 10101 in binary form and
ooioj a remainder of two, which is 10 in binary form. The number of
00101 comparisons needed here is five. The first comparison is with
0100H the higher-order nibble. Then there are four comparisons for
000110 the next four bits, with one bit being rotated left each time.
0100 In the program, a 16-bit dividend and an 8-bit divisor are
0010 considered. The number of comparisons required is nine. So a
count is set up for nine.
Flowchart:
The algorithm for dividing a 16-bit number by an 8-bit number is given in
Fig- 4.18.
Fig. 4.18 Algorithm for dividing a 16-bit number by an 8-bit number

Program:
The program for dividing a 16-bit number by an 8-bit number is given in
Table 4.22.
Table 4.22 Program for dividing a 16-bit number by an 8-bit number
MVI E, OOH ; Initialize register E as the quotient with initial value = 0.
LHLD 9000H ; Load the dividend in the HL register pair.
LDA 9002H ; Load the divisor in the accumulator.
MOV B, A ; Move the divisor to register B.
MVI C, 09H ; Initialize register C as a counter with initial value = 9.
NEXT: MOV A, H ; Move the most significant byte of the dividend to the
accumulator.
SUB B ; Check if MSB of dividend > divisor.
JC SKIP ; If it is not, jump to SKIP.
MOV H, A ; If it is, move it back to register H.
INRE ; Quotient = quotient + 1
SKIP: DADH ; Dividend = dividend x 2
MOV A, E ; Move the quotient to the accumulator.
RLC ; Shift left to multiply by two.
MOV E, A ; Move the quotient back to register E.
DCRC ; Count = count - 1
JNZ NEXT ; If the value of count is not equal to zero, jump to NEXT.
MOV A, E ; Move the quotient to the accumulator.
STA9100H ; Store the quotient.
MOV A, H ; Move the remainder to the accumulator.
STA9101H ; Store the remainder.
Example 4.23:
Calculate the sum of an array of numbers. The length of the array is stored in
memory location 9000H; the array begins at memory location 9001H.
(a) Assume that the sum is an 8-bit number. So ignore the carry and store the sum
in memory location 9100H.
(b) Assume that the sum is a 16-bit number. Store the sum in memory locations
9100H and 9101H.
Flowchart:
The algorithm for adding an array of numbers is given in F’S-
Fig. 4.19 Algorithm for adding an array of numbers
(a) Sample data:

(9000H) = 04H
(9001H) = 10H
(9002H) = 4CH
(9003H) = 33H
(9004H) = 2AH
Result = 10H + 4CH + 33H + 2AH = B9H
(9100H) = B9H
Program:
The program for finding the 8-bit sum of an array of numbers is given in
Table 4.23.
Table 4.23 Program for finding 8-bit sum of an array of numbers

LDA 9000H ; Load the length of the array in the accumulator.
MOV C, A ; Initialize register C as a counter with initial value =
length of the array.
XRA A ; Make Sum = 0.
LXI H. 9001H ; Initialize the memory pointer.
LOOP: ADD M ; Sum = Sum + data from array
INXH ; Increment the pointer.
DCRC ; Decrement the counter.
JNZ LOOP ; If counter is not equal to zero, repeat addition.
STA9100H ; Store Sum in 91 OOH.
(b) Sample data:

(9000H) = 04H
(9001H) = 9AH
(9002H) = 52H
(9003H) = 89H
(9004H) = 3EH
Result = 9AH + 52H + 89H + 3EH = 1B3H
(91 OOH) = B3H (lower-order byte)
(9101H) = 01H (higher-order byte)
Program:
The program for finding the 16-bit sum of an array of numbers is given in
Table 4.24.
Table 4.24 Program for finding 16-bit sum of an array of numbers

LDA 9000H ; Load the length of the array in the accumulator.
MOV C, A ; Initialize register C as a counter with initial value = length
of the array.
XRA A ; Lower-order byte of Sum = 0
MOV B, A ; Higher-order byte of Sum = 0
LOOP: ADD M ; Sum = Sum + data from array
JNC SKIP ; If no carry is produced, jump to SKIP.
INR B ; If a carry is produced, add it to the higher-order byte of Sum.
(Contd)
Table 4.24 Program for finding 16-bit sum of an array of numbers (Contd)

SKIP: INXH ; Increment the pointer.
JNZ LOOP ; If the counter is not equal to zero, repeat the addition
process.
STA 91 OOH ; If the counter is equal to zero, store the lower-order byte of
Sum in 9100H.
MOV A, B ; Move higher-order byte of Sum to the accumulator.
STA 9101H ; Store the higher-order byte of Sum in 9101H.
Example 4.24:
Given a series of numbers, calculate the sum of the even numbers only. The
length of the series is available in memory location 9000H. The series begins at
9001H. Ignore the carries; assume that the sum is only eight bits long and store it
in memory location 91 OOH.
Sample data:
(9000H) = 4H
(9001H) = 20H
(9002H) = 15H
(9003H) = 13H
(9004H) = 22H
Result = (91 OOH) = 20 + 22 = 42H
Flowchart:
The algorithm for calculating the 8-bit sum of the even numbers in a series is given
in Fig. 4.20.
Program:
The program for calculating the 8-bit sum of the even numbers in a series is given
in Table 4.25.
Table 4.25 Program for calculating 8-bit sum of even numbers in a series

LDA 9000H ; Load the length of the series in the accumulator.
MOV C, A ; Initialize register C as a counter with initial value = length
of the series.
MVI B, OOH ; Initialize Sum = 0.
LOOP: MOV A, M ; Load data from the series in the accumulator.
RAR ; Rotate right through the carry to check the LSB of the data.
(Contd)
Table 4.25 Program for calculating 8-bit sum of even numbers in a series (Contd)

JC SKIP ; Do not add if the number is odd, i.e., LSB is 1.
MOV A, B ; If the number is even, load Sum in the accumulator.
ADDM ; Sum = Sum + data from the series
MOV B, A ; Store the result in register B.
JNZ LOOP ; If counter is not equal to zero, repeat the process.
STA 91 OOH ; If it is equal to zero, store Sum in 9100H.
.....................
Fig. 4.20 Algorithm for calculating 8-bit sum of even numbers in a series
Example 4.25:
Given a list of numbers, calculate the sum of the odd numbers only. The length of
the series is available in 9000H; the series starts at 9001H. Assume that the sum is
16 bits long. Store it in memory locations 91 OOH and 9101H.
Sample data:
(9000H) = 04H
(9001H) = 9AH
(9002H) = 52H
(9003H) = 89H
(9004H) = 7FH
Result = 89H + 7FH = 108H
(9100H) = 08H (lower-order byte)
(9101H) = 01H (higher-order byte)
Flowchart:
The algorithm for calculating the 16-bit sum of the odd numbers in a series is
given in Fig. 4.21.
Fig. 4.21 Algorithm for calculating 16-bit sum of odd numbers in a series
Program:
The program for calculating the 16-bit sum of the odd numbers in a series is given
in Table 4.26.
Table 4.26 Program for calculating 16-bit sum of odd numbers in a series

length of the series.
MVI E, OOH ; Lower-order byte of Sum = 0.
MOV D, E ; Higher-order byte of Sum = 0.
RAR ; Rotate right through the carry to check the LSB of the
data.
JNC NEXT ; Do not add if the number is even.
MOV A, E ; If it is odd, load the lower-order byte of Sum in the
accumulator.
ADDM ; Lower-order byte of Sum = Lower-order byte of Sum +
data from the series
MOV E, A ; Move the result to register E.
JNC NEXT ; If no carry is produced, jump to SKIP.
INRD ; If a carry is produced, add it to the higher-order byte of
Sum.
NEXT: INXH ; Increment the pointer.
JNZ LOOP ; If the value of the counter is not zero, repeat the
process.
MOV A, E ; If it is zero, move the lower-order byte of Sum to the
accumulator.
STA9100H ; Store it in 91 OOH.
MOV A, D ; Move the higher-order byte of Sum to the accumulator.
STA 9101H ; Store it in 9101H.
HLT ; Terminate program execution
Example 4.26:
Calculate the sum of an array of numbers. The array starts at memory location
9000H. The memory location after the last element of the array has the data FFH.
The length of the array is not known. Consider the sum to be a 16-bit number.
Store the sum in memory locations 9100H and 9101H.
This program cannot use a counter to terminate the addition loop. The loop is
terminated by checking each number in the array. If the number is not FFH, the
addition is carried out. If the number is FFH, the loop is terminated and the result
is stored. The last number FFH is not added to the sum. This type of looping is
similar to the do-while loop in high-level languages.
Sample data:
(9000H) = 13H
(9001H) = E4H
(9002H) = 6BH
(9OO3H) = 33H
(9004H) = FFH
Result = 13 + E4 + 6B + 33 = 195H
(9100H) = 95H
(9101H) = 01H
Flowchart:
The algorithm for calculating the sum of a series of numbers when the length of
the series is not given is shown in Fig. 4.22.
Pig. 4.22 Algorithm for calculating the sum of a series of numbers when the length of the series
is not given
Program:
Table 4.27 shows the program for calculating the sum of a series of numbers when
the length of the series is not given.
Table 4.27 Program for calculating the sum of a series of numbers when the length of the series
is not given

MVI C, OOH ; Lower-order byte of Sum = 0.
MOV B, C ; Higher-order byte of Sum = 0.
CPI FFH ; Compare the data with FFH.
JZ LAST ; If it is FFH, jump to LAST.
ADDC ; If it is not, lower-order byte of Sum = lower-order byte
of Sum + data from the series.
MOV C, A ; Move the result to register C.
INC SKIP ; If no carry is produced, jump to SKIP.
INRB ; If a carry is produced, add it to the higher-order byte of Sum.
JMP LOOP ; Jump to LOOP to repeat the process.
LAST: MOV A, C ; Move the lower-order byte of Sum to the accumulator.
STA 91 OOH ; Store lower-order byte of Sum in 91 OOH.
MOV A, B ; Move the higher-order byte of Sum to the accumulator.
STA9101H ; Store higher-order byte of Sum in 9101H.
Example 4.27:
Find the number of negative numbers (indicated by an MSB of 1) in a given series
and store it in memory location 91 OOH. The length of the series is in memory
location 9000H. The series begins at 9001H.
Sample data:
(9000H) = 04H
(9001H) = 56H
(9002H) = A9H
(9003H) = 73H
(9004H) = 82H
Result = 02 since 9002H and 9004H contain numbers with an MSB of 1.
Flowchart:
The algorithm for finding the number of negative numbers in a series is given in
Fig. 4,23.
Fig. 4.23 Algorithm for finding the number of negative numbers in a series
Program:
The program for finding the number of negative numbers in a series is given in
Table 4.28.
Table 4.28 Program for finding the number of negative numbers in a series

MVI B. OOH ; Initialize register B as the count of negative elements
with initial value = OOH.
LOOP: MOVA, M ; Load data from the series in the accumulator.
RAL ; Rotate left through the carry to check if the MSB is 1.
JNC SKIP ; If MSB is not equal to one, jump to SKIP.
INRB ; If MSB is equal to one, increment the negative number
count.
JNZ LOOP ; If the counter is not equal to zero, repeat the process.
MOVA, B ; If the counter is equal to zero, move the result to the
accumulator.
STA91OOH ; Store the result in 91 OOH.
Example 4.28:
Add the corresponding elements of two arrays having ten 8-bit numbers each and
store them in a third array. The arrays start at memory locations 9000H, 91 OOH,
and 9200H, respectively. Assume that all the sums obtained in the process are not
more than eight bits long.
Flowchart:
The algorithm for adding the corresponding elements of two arrays is given in
Fig. 4.24.
Program:
The program for adding the corresponding elements of two arrays is given in Table
4.29.
Table 4.29 Program for adding the corresponding elements of two arrays
LXI H, 9000H ; Initialize memory pointer 1 for the first data array.
LXI B, 91 OOH ; Initialize memory pointer 2 for the second data array.
LXI D, 9200H ; Initialize memory pointer 3 for the result array.
LOOP: LDAX B ; Load data from the second array in the accumulator.
(Contd)
Table 4.29 Program for adding the corresponding elements of two arrays (Contd)

ADD M ; Add it with the corresponding number in the first array.
STAX D ; Store the result of addition in the result array.
INX H ; Increment pointer 1.
INXB ; Increment pointer 2.
1NXD ; Increment result pointer.
MOV A, L ; Move the lower-order byte of pointer 1 to the
accumulator.
CPI OAH ; Compare the lower-order byte with OAH.
JNZ LOOP ; If it is not equal to zero, repeat the process.
HLT ; If it is equal to zero, terminate program execution.
pig. 4.24 Algorithm for adding the corresponding elements of two arrays
Example 4.29:
Two decimal numbers of six digits in packed BCD format each, occupying a
sequence of memory bytes are stored. The starting address of the first number
is 9(X)0H and that of the second number is 9100H. Write an assembly language
program to add these two numbers and store the sum in the same format, starting
at memory location 9200H.
Flowchart:
The algorithm for adding two 6-digit packed BCD numbers is given in Fig- 4.25.
Fig. 4.25 Algorithm for adding two 6-digit BCD numbers

Program:
The program for adding two 6-digit BCD numbers is given in Table 4.30.
Table 4.30 Program for adding two 6-digit BCD numbers
LXI H, 9000H ; Initialize pointer 1 to the memory location of the first

number.
LXI D, 91 OOH ; Initialize pointer 2 to the memory location of the second
number.
LXI B, 9200H ; Initialize pointer 3 to the memory location of the result.
STC ; Set carry to 1.
CMC ; Carry = 0
LOOP: LDAX D ; Load the BCD digit of the second number in the
accumulator.
ADCM ; Add with the BCD digit of the first number.
DAA ; Adjust for decimal values.
STAXB ; Store the result.
INXH ; Increment pointer 1.
INXD ; Increment pointer 2.
INXB ; Increment the result pointer.
MOVA, L ; Move the lower-order byte of the memory location of the
first number to the accumulator.
CPI 06H ; Compare it with 06H.
JNZ LOOP ; If it is not equal to 06H, repeat the process.
HLT ; If it is equal to 06H, terminate program execution.
Example 4.30:
Find the largest number in a given series of 8-bit unsigned binary numbers. The
length of the series is stored in memory location 9000H. The series begins at
9001H. Store the result in memory location 91 OOH.
Sample data:
(9000H) = 04H
(9001H) = 34H
(9002H)=A9H
(9003H) = 78H
(9004H) = 56H
Result = (91 OOH) = A9H
Flowchart:
The algorithm for finding the largest number in a series is given in Fig- 4.26.
I
I
r-*
Fig. 4.26 Algorithm for finding the largest number in a series
Program:
The program for finding the largest number in a series is given in Table 4.31.
Table 4.31 Program for finding the largest number in a series

(Contd}
Table 4.31 Program for finding the largest number in a series (Contd)
XRA A ; Initialize Max = 0.

LOOP: CMP M ; Check if data from the series > Max.
JNC SKIP ; If not, jump to SKIP.
MOV A. M ; If it is, replace Max with the data from the series.
SKIP: INX H ; Increment the pointer.
JNZ LOOP ; If the value of the counter is not equal to zero, repeat the
process.
STA9100H ; If it is equal to zero, store Max in 91 OOH.
Example 4.31:
Sort a given list of 10 numbers starting at memory location 9000H in ascending
order.
Flowchart:
The algorithm for sorting a series of numbers in ascending order is given in
Fig. 4.27.
Program:
The program for sorting a series of numbers in ascending order is given in
Table 4.32. 7
\ /Table 4.32 Program for sorting a series of numbers in ascending order
MVI B, 09H ; Initialize outer counter (1).

LOOP2: LXI H, 9000H ; Initialize the memory pointer.
MVI C, 09H ; Initialize inner counter (2).
LOOP1: MOVA, M ; Load data from the series in the accumulator.
CMPM ; Compare the number with the next number in the series.
JC SKIP ; If it is lesser, do not interchange the numbers.
MOV D, M ; Get the data from memory to register D.
MOV M, A ; Move the contents of register A to memory.
DCX H ; Point to the previous data.
MOV M, D ; Move the contents of register D to memory.
(Contd)
Fig. 4.27 Algorithm for sorting a series of numbers in ascending order

Program for sorting a series of numbers in ascending order (Contd)
INX H ; Increment pointer (interchange of numbers complete).

SKIP: DCRC ; Decrement inner counter (2).
JNZ LOOP1 ; If it is not zero, repeat the process.
DCR B ; Decrement outer counter (1).
JNZ LOOP2 ; If it is not zero, jump to LOOP2.
Example 4.32:
Arrange an array of 8-bit unsigned numbers in descending order.
Program:
The program for arranging an array of 8-bit unsigned numbers in descending order
4.33 Program for arranging an array of 8-bit unsigned numbers in descending order
MVIB,09H ; Initialize outer counter (1).

LOOP2: LXI H, 9000H ; Initialize pointer.
MVI C, 09H ; Initialize inner counter (2).
LOOP1: MOV A, M ; Load data from the series in the accumulator.
CMPM ; Compare the number with the next number in the
series.
JNC SKIP ; If it is not lesser, do not interchange the numbers.
MOV D, M ; Get the data from the memory to register D.
MOV M, A ; Move the content of register A to the memory.
DCXH ; Point to the previous data.
MOV M, D ; Move the content of register D to the memory.
INXH ; Increment pointer (interchange of numbers
complete).
SKIP: DCRC ; Decrement inner counter (2).
JNZ LOOP1 ; If it is not zero, repeat the process.
DCR B ; Decrement outer counter (1).
JNZ LOOP2 ; If it is not zero, jump to LOOP2.
Example 4.33:
Tind the square of the numbers stored as an array starting at memory location
9000H. Store the result as an array starting at 91(X)H. Assume that there are five
numbers in the array.
The following program uses the look-up table concept. Instead of finding the squares
by arithmetic operations, the calculated values of squares of 0 to 9 are stored in
memory locations. These memory locations are accessed using their addresses, the
last digits of which are from zero to nine. The program given in Table 4.34 uses
three register pairs and indirect addressing mode for data transfer.
Look-up table:
Table 4.34 lists the squares of numbers 0-9.
Table 4.34 Look-up table for squares of numbers 0-9
Decimal number Square Memory location

0 OOH 9200
1 01H 9201
2 04H 9202
3 09H 9203
4 10H 9204
5 19H 9205
6 24H 9206
7 31H 9207
8 40H 9208
9 51H 9209
Flowchart:
The algorithm for finding the squares of an array of numbers is given in
Fig. 4.28.
Program:
The program for finding the squares of an array of numbers is given in
Table 4.35. Here the array size is 5.
Table 4.35 Program for finding the squares of an array of numbers
LXI H, 9200H ; Initialize the look-up table pointer.

LXI D, 9000H ; Initialize the source memory array pointer.
LXIB,9100H ; Initialize the destination memory array pointer.
LOOP: LDAXD ; Get a number from the source array.
MOV L, A ; Move the number to register L.
(Contd)
Table 4.35 Program for finding the squares of an array of numbers (Contd)

MOV A, M ; Load the square in the accumulator.
STAX B ; Store the result in the destination memory location.
INXD ; Increment the source memory pointer.
INX B ; Increment the destination memory pointer.
MOV A, E ; Move the lower-order byte of the source memory location
to the accumulator.
CPI 05H ; Compare it with 05H.
JNZ LOOP ; If it is not equal to 05H, repeat the process.
HLT ; If it is equal to 05H, terminate program execution.
Fig-428 Algorithm for finding the squares of an array of numbers

Search for the first occurrence of the byte in register C in a list of 50 numbers
stored in the consecutive memory locations starting at 9000H. Store the memory
location containing the given byte in 9100H and 9101H. If the byte is not found
in the list, store OOH in 91 OOH and 9101H.
Flowchart:
The algorithm for finding a number from a list is given in Fig. 4.29.
Program:
The program for finding a number from a list is given in Table 4.36.
pig. 4.29 Algorithm for finding a number from a list

Viable 4.36 Program for finding a number from a list

MVIB, 32H ; Initialize register B as a counter for 50 numbers.
LOOP: MOV A, M ; Get a number from the series.
CMPC ; Compare the number with the given byte.
JZ STORE ; If they are equal, jump to STORE.
INXH ; If they are not equal, increment the memory pointer.
DCRB ; Decrement the counter.
JNZ LOOP ; If the counter is not equal to zero, repeat the process.
LXI H, 0000H ; If the counter is equal to zero, load 0000H in the HL
register pair.
SHLD 91 OOH ; Store OOH at 91 OOH and 9101H.
JMP LAST ; Jump to LAST.
STORE: SHLD 91 OOH ; Store the memory address in 91 OOH and 9101H.
LAST: HLT ; Terminate program execution.
Example 4.35:
Identify the even numbers from a series of 50 numbers starting at 9000H and store
them as another series starting at 9100H.
Flowchart:
The algorithm for finding the even numbers from a list of 50 numbers is given in
Fig. 4.30.
Program:
The program fof finding the even numbers from a list of 50 numbers is given in
Table 4.37. /
x'~Table 4.37 Program for finding even numbers from a list of 50 numbers
LXI H, 9000H ; Initialize pointer 1 to the memory location of the first

number.
LXI D, 91 OOH ; Initialize pointer 2 to the destination memory location.
MVI C, 32H ; Initialize register C as a counter with initial value 50
(32H).
LOOP: MOV A, M ; Get data from the series.
RAR ; Check if it is an even number by rotating right once.
JC SKIP ; If it is odd, do not store.
(Contd)
r
f
Fig. 4.30 Algorithm for finding even numbers from a list of 50 numbers
Table 4.37 Program for finding even numbers from a list of 50 numbers (Contd)

MOV A, M ; If it is even, move the number to the accumulator.
STAXD ; Store the number in the destination memory location.
INXD ; Increment pointer 2.
SKIP: INXH ; Increment pointer 1.
process.
Example 4.36:
Move a block of data 256 bytes long from the series of memory locations starting
at 9000H to the series starting at 9050H. In the process of shifting, do not transfer
the data to any other memory location.
The two blocks of data (9000-90FF and 9050-914F) are overlapping.
Therefore, it is necessary to transfer the last byte first and the first byte last.
Program:
The program to transfer a block of data between two overlapping blocks of memory
locations is given in Table 4.38.
Table 4.38 Program to transfer a block of data between two overlapping blocks
of memory locations
MVI C, FFH ; Initialize register C as a counter with initial value FFH.

LXI H, 90FFH ; Initialize HL register pair to the last memory location of
the source block.
LXI D, 914FH ; Initialize DE register pair to the last memory location of
the destination block.
LOOP: MOV A, M ; Get data from the source memory block.
STAXD ; Store it in the destination memory block.
DCXH ; Decrement the source memory pointer.
DCXD ; Decrement the destination memory pointer.
process.
Example 4.37:
Find the number of occurrences of negative numbers, zeros, and positive numbers
from a list of 50 numbers stored in a block of memory locations starting at 9000H.
Store the counts in memory locations 91 OOH, 9101H, and 9102H, respectively.
Flowchart:
The algorithm for finding the number of occurrences of negative numbers, zeros,
and positive numbers from a list of 50 numbers is given in Fig. 4.31.
Program:
The program for finding the number of occurrences of negative numbers, zeros,
and positive numbers from a list of 50 numbers is given in Table 4.39.
T^bie 4.39 Program for finding the number of occurrences of negative numbers, zeros, positive
numbers in a list

LXI H, 9000H ; Initialize HL register pair to the first memory location
of the list.
MVI C, 32H ; Initialize register C as a counter for 50 numbers.
MVI B, OOH ; Initialize register B as the counter for negative
numbers.
MVI E, OOH ; Initialize register E as the counter for zeros.
MVI D, OOH ; Initialize register D as the counter for positive
numbers.
START: MOV A, M ; Get data from the list.
CPI OOH ; Compare it with OOH.
JZ ZERO ; If it is equal to zero, jump to ZERO.
RAL ; If it is not equal to zero, check if it is negative, i.e.,
MSB = 1.
JC NEG ; If the number is negative, jump to NEG.
INRD ; If it is not negative, increment the positive number
counter.
ZERO: INRE ; Increment zero counter.

NEG: INRB ; Increment negative number counter.
LAST: INXH ; Increment memory pointer.

DCRC ; Increment number counter.
JNZ START ; If it is not equal to 50, repeat the process.
(Contd on page 121)

Fig. 4.31 Algorithm for finding the number of occurrences of negative numbers, zeros
and positive numbers in a list
Table 4.39 Program for finding the number of occurrences of negative numbers, zeros, and
positive numbers in a list (Contd)
LXI H, 91 OOH ; If it is equal to 50, initialize HL pair to the destination

memory location for negative number count.
MOV M, B ; Store the number of occurrences of negative numbers.
INXH ; Increment HL register pair.
MOV M, E ; Store the number of occurrences of zeros.
INXH ; Increment HL register pair.
MOV M, D ; Store the number of occurrences of positive numbers.
Example 4.38:
Given an array 50 bytes long, insert four bytes in the array starting from the tenth
memory location. Assume that the array starts at 9000H and that the string of bytes
to be inserted start at 91 OOH.
Solution:
Step 1: Move all the bytes starting from the 10th memory location, four bytes
down.
Step 2: Insert four bytes at the 10th, 11th, 12th, and 13th memory locations.
Program:
The program for inserting four bytes in an array of 50 bytes is given in
Table 4.40.
Table 4.40 Program for inserting four bytes in an array of 50 bytes

LXI H, 9031H ; Initialize pointer to the last memory location of the
array.
MVI C, 04H ; Initialize register C as a counter with initial value =
number of bytes to be inserted.
LXI D, 9035H ; Initialize another pointer to point to the last destination
memory location.
LOOP: MOV A, M ; Get a byte from the array.
STAXD ; Store the byte in the new memory location.
DCXD ; Decrement the destination pointer.
DCX H ; Decrement the source pointer.
MOV A, L ; To check whether bytes up to the 10,h location (9009H)
have been shifted, move the lower-order byte of the
source memory location to the accumulator.
(Contd)
Table 4.40 Program for inserting four bytes in an array of 50 bytes (Contd)
CPI 08H ; Check whether it is equal to 08H after decrementing.
JNZ LOOP ; If it is not, repeat the process.
LXI D, 91 OOH ; If it is, initialize the DE register pair to point to the

string to be inserted.
INXH ; Increment the HL pair to point to the 10th location, i.e.
9009H.
LOOP1: LDAXD ; Get a byte from the data to be inserted.
MOV M, A ; Store it in the array.
INXD ; Increment the source pointer.
INXH ; Increment the destination pointer.
JNZ LOOP1 ; If the value of the counter is not equal to zero, repeat
the process.
Example 4.39:
Given an array 50 bytes long, delete four bytes in the array starting from the 10th
memory location.
Solution:
Move all bytes starting at the 14th memory location up by four bytes.
Program:
The program for deleting four bytes from an array of 50 bytes is given in
Table 4.41.
Table 4.41 Program for deleting four bytes from an array of 50 bytes
LXI H, ; Initialize source memory pointer to the 14th location of the

900DH array.
LXI D, 9009H ; Initialize destination memory pointer to the 10th location
of the array.
LOOP: MOV A, M ; Load a byte from the array in the accumulator.
STAX D ; Store the byte in the new memory location.
INX D ; Increment the destination pointer.
(Contd)
Table 4.41 Program for deleting four bytes from an array of 50 bytes (Contd)

INXH ; Increment the source pointer.
MOV A, L ; To check if all the bytes have been shifted, move the
lower-order byte of the source memory pointer to the
accumulator.
CPI 32H ; Check if it is equal to 50, i.e., 32H.
HLT ; If it is, terminate program execution.
4.2.3 Code Conversion, Decimal Arithmetic, and Bit Manipulation

In microprocessor applications, various number systems and codes are used
for representing data. Inside the microprocessor hardware, data is processed as
if it is binary. However, the instruction set of the 8085 processor provides the
flexibility of handling data in BCD format and signed format. Similarly, text data
also has different forms of representation such as ASCII code, Excess 3 code,
etc. There are instances in which data need to be converted from one code to
another. The programming techniques used for code conversion fall into three
general categories:
(i) Conversion based on the number system

followed in a number (BCD to binary Table 4.42 Conversion table—
hexadecimal to ASCII
and vice versa).
(ii) Conversion based on hardware
Hex digit ASCII code
requirement (binary to seven-segment r\u 30H
code using look-up procedure).
(iii) Conversion based on text format of digits 1 31H
(binary to ASCII and vice versa). 2 32H
3 33H
The following programming examples deal
4 34H
with code conversion.
5 35H
Example 4.40: 6 36H
Convert the data in five memory locations 7 37H
starting 9000H into ASCII characters and store 8 38H
them in the array starting 91 OOH. 9 39H
Hexadecimal digits from 0 to F and the
A 41H
corresponding ASCII values are given in R 42H
Table 4.42. The conversion can be done by
adding 30H to the given hexadecimal number if c 43H
it is less than OAH. If the hexadecimal number D 44H
is between OAH and OFH, the conversion is E 45H
done by adding 41H-0AH, i.e., 37H. F 46H
Sample data:
(9000H) = 01H
(9001H) = 02H
(9002H) = 09H
(9003H) = OAH
(9004H) = OBH
Result = (9100H) = 31H
(9101H) = 32H
(9102H) = 39H
(9103H) = 41H
(9104H) = 42H
Flowchart:
The algorithm for converting a hexadecimal number into ASCII code is given in
Fig. 4.32.
Program:
The program for converting a hexadecimal number into ASCII code is given in
Table 4.43.
Table 4.43 Program for converting a hexadecimal number into ASCII code
LXI H, 9000H ; Initialize the source memory pointer.

LXID, 91 OOH ; Initialize the destination memory pointer.
MVI C, 05H ; Initialize the counter.
LOOP: MOV A, M ; Get a number from the list.
CALL ASCII ; Call subroutine ASCII.
STAXD ; Store the result.
INXH ; Increment the source memory pointer.
INXD ; Increment the destination memory pointer
JNZ LOOP ; If it is not equal to zero, repeat the process.
ASCII SUBROUTINE
ASCII: CPI OAH ; Check if the number is equal to OAH.
JNC NEXT ; If it is, jump to NEXT.
ADI 30H ; If it is not, add 30H.
RET ; Return to the main program.
NEXT: ADI 37H ; Add 37H to the number from the list.
pig- 4-32 Algorithm for converting a hexadecimal number into ASCII code
Example 4.41:
Convert the ASCII number in memory location 9000H into its equivalent decimal
number and store it in 9001H. If the ASCII code is not that of a decimal number,
store FFH in 9001H.
The algorithm for this conversion follows in reverse order, the steps explained in
the previous problem. If the ASCII code value is between 30H and 39H, subtract
30H to get its decimal equivalent.
Piogram:
The program for converting an ASCII number into its decimal equivalent is given
in Table 4.44.
Table 4.44 Program for converting ASCII number into decimal equivalent
LXI H, 9000H ; Load the memory location where the ASCII number is
available in the HL register pair.
MOV A, M ; Load the number in the accumulator.
SUI 30H ; Convert it to decimal form.
CPI OAH ; Check whether it is a valid decimal number.
JC NEXT ; If it is, jump to NEXT.
MVI A, FFH ; If it is not, load FFH in the accumulator.
NEXT: INX H ; Increment HL register pair.

MOV M, A ; Store the result.
Example 4.42:
Convert the hexadecimal number in memory location 9000H into its equivalent
decimal number and store it in the succeeding memory locations.
Solution:
This is done by converting the binary value of the hexadecimal number into its
equivalent BCD value. For example, FFH is converted to 255. So, an 8-bit binary
value is converted into 3-digit BCD format. The program checks the number of
100s (hundreds digit) in the binary number by repeated subtraction. From the
remainder, the number of 10s (tens digit) is calculated and then the number of
ones (units digit). These three results form the 3-digit BCD equivalent of the given
binary number (or the decimal equivalent of the given hexadecimal number).
Program:
The program for converting a hexadecimal number into its decimal equivalent is
given in Table 4.45,
Table 4.45 Program for converting hexadecimal number into decimal equivalent
LXI H, 9000H ; Initialize the HL register pair as a pointer to the

hexadecimal number.
MVI E, OOH ; Initialize hundreds digit = 0.
LXI B, 0000H ; Initialize tens digit = 0 and units digit = 0.
MOV A, M ; Load the hexadecimal number in the accumulator.
LOOP: SUI 64H ; Subtract 100 (64H) to find the number of 100s in the
hexadecimal number.
JC NEXT ; If the hexadecimal number is lesser than 64H, jump
to NEXT.
INRE ; If the hexadecimal number is not lesser than 64H,
increment the hundreds digit.
JMP LOOP ; Repeat the process.
NEXT: ADI 64H ; Get the remainder after the previous operation.
LOOP 1: SUI OAH ; Subtract 10 (OAH) to find the number of 10s in the
remainder.
JC STORE ; If the remainder is lesser than OAH, jump to STORE.
INRB ; If the remainder is not lesser than OAH, increment
the tens digit.
JMP LOOP 1 ; Repeat the process.
STORE: ADI OAH ; Get the remainder after the previous operation.
MOV M, E ; Store the hundreds digit in the memory.
MOV C, A ; Move the ones digit to register C.
MOV A, B ; Move the tens digit to the accumulator.
RLC ; Shift the tens digit left four times so that it occupies
the higher-order bits.
ADDC ; Add the units digit and the tens digit to make it a
single 8-bit number (packing).
MOV M, A ; Store the packed tens and units digits in memory.
Example 4.43:
Add even parity to a string of 7-bit ASCII characters and place it in the most
significant bit of each character. The length of the string is in memory location
9000H and the string begins in memory location 9001H. Store the result in the
array starting at memory location 9101H.
Flowchart:
The algorithm for adding even parity to a string of 7-bit ASCII characters is given
in Fig- 4.33.
Initialize memory pointer and character counter
Add even parity in MSB
_______ t______ _
Store ASCII character with parity in
memory location
f
Increment memory pointer
pig. 4.33 Algorithm for adding even parity to a string of 7-bit ASCII characters
Program:
The program for adding even parity to a string of 7-bit ASCII characters is given
in Table 4.46.
Table 4.46 Program for adding even parity to a string of 7-bit ASCII characters
LXI H, 9000H ; Initialize the HL register pair to the length of the

ASCII string.
LXID, 9100H ; Initialize the destination pointer.
MOV C, M ; Initialize register C as a counter with initial value =
length of the ASCII string.
REPEAT: INXH ; Increment the source pointer.
INXD ; Increment the destination pointer.
MOV A, M ; Load a character from the ASCII string in the
accumulator.
ORA A ; OR the accumulator with itself to check parity.
JPE PARI ; If painty is even, jump to PARI.
ORI 80H ; If parity is odd, place 1 in bit D7.
PARI: LDAXD ; Store the converted even parity character.
JNZ REPEAT ; If the value of the counter is not zero, repeat the
process.
HLT ; If it is zero, terminate program execution.
Example 4.44:
Convert a 2-digit BCD number stored in memory address 9000H into its equivalent
binary form. Store the result in memory location 91 OOH.
Sample data:
(9000H) = 59H
(9100H) = 5 x OAH + 9 = 32H + 9 = 3BH
Flowchart:
The algorithm for converting a BCD number into its equivalent binary form is
given in Fig. 4.34.
Program:
The program for converting a BCD number into its equivalent binary form is given
in Table 4.47.
Fig. 4.34 Algorithm for converting BCD number into equivalent binary form
Table 4.47 Program for converting BCD number into equivalent binary form
LDA 9000H ; Load the BCD number in the accumulator.

MOVB, A ; Move it to register B.
ANI OFH ; Mask the most significant four bits.
; Save the lower-order byte of the unpacked BCD number
MOV C, A
(BCD1) in register C.
MOV A, B ; Load the BCD number in the accumulator.
ANI FOH ; Mask the least significant four bits.
(Contd)
Table 4,47 Program for converting BCD number into equivalent binary form (Contd)
; Shift the tens digit of the BCD number to the ones place by
RRC
shifting right four times.
MOV B, A ; Move the unpacked tens digit (BCD2) to register B.
XRA A ; Clear- the accumulator, i.e., sum = 0.
MVI D, OAH ; Load the multiplier 10 (OAH) in register D.
SUM: ADD D ; Add register D to the accumulator.
DCRB ; Decrement BCD2.
JNZ SUM ; If the value of BCD2 is not equal to zero, repeat the
process.
ADDC ; If the value of BCD2 is equal to zero, add BCD1 to the
accumulator.
STA9100H ; Store the result.
4.2.4 Programming Examples based on Subroutine Concepts

Subroutine is a group of instructions that are written to perform a specific task. The
subroutine can be called by a main program repeatedly as and when required. It
simplifies the main program as it eliminates the need to write the code repeatedly.
For example, in order to find the factorial of a number, the multiplication routine has
to be written many times. However, a subroutine can be written for multiplication
and this can be called repeatedly to find the factorial. The subroutine makes use of
the stack to return to the main program after the subroutine is over. The stack is
used to store the return address whenever the subroutine is called. The instructions
used for subroutine call and return are CALL and RET. The conditional call and
return instructions in the 8085 have already been explained in Chapter 3.
The important aspects to be considered while developing subroutines are as
follows:
(i) Parameter passing: In the 8085, it is necessary to pass the arguments or
variables to the subroutine from the main program. The variables are
passed to the subroutine through the registers. For example, we can write
a subroutine to find the square of a number stored in C register and return
the result in BC register pair. It must be clearly decided how to pass the
parameters from the main to subroutine and from the subroutine to the main
program.
(ii) Use of stack: The subroutine, in addition to the registers used for parameter
passing, may require some more registers. However, the main program
may have stored some data in these registers. So care must be taken in
the subroutine to not affect the register contents. This can be safely done
by storing the processor register contents on to the stack before using
that register in the subroutine. At the end of the subroutine, these register
contents can be replaced in the corresponding registers from the stack.
(iii) Proper use of stack: The processor register contents can be stored in the
stack. However, it must be remembered that stack is a Last In First Out
array of registers. So the data retrieved from the stack is in the reverse order
in which it was stored.
(iv) Retaining return address: The processor also uses the stack to store the
return address in the main program when a subroutine is called. So the stack
content at the start and end of the subroutine execution must be the same.
This can be ensured only if there are an equal number of PUSH and POP
instructions within the subroutine. If this is not ensured, the return address
will be modified and the program may not be executed as desired.
In the following example, the subroutine ASCII converts a hexadecimal digit
to ASCII. The digit is passed using the accumulator and the result is stored in the
accumulator and D and E registers. The HL and BC register pairs are stored in the
stack and retrieved in reverse order.
Example 4.45:
A binary number is stored in memory location 9000H. Write a main program and
a conversion subroutine to convert it into its equivalent BCD form and store the
result in a series of memory locations starting 91 OOH.
Sample data:
(9000H) = 8AH
1. 8AH/64H (Decimal 100) : Divide by 64H (Decimal 100)
8AH/64H Quotient = 1, Remainder = 26H
26H < 64H (Decimal 100) : Go to step 2; Digit 2=1
2. 26H/0AH (Decimal 10) : Divide by OAH (Decimal 10)
26H/0AH Quotient = 3, Remainder = 08H
08H < OAH (Decimal 10) : Go to step 3; Digit 1 = 3
3. Digit 0 = 08H
Flowchart:
The algorithm for converting a binary number into its equivalent BCD form is
given in Fig. 4.35.
Program:
The program for converting a binary number into its equivalent BCD form is
given in Tables 4.48 (a) and 4.48 (b). The subroutine given in Table 4.48 (a)
converts the binary number in the accumulator into three unpacked BCD digits
with the hundreds digit in register E, tens digit in register D, and units digit in the
accumulator.
Fig. 4.35 Algorithm for converting a binary number into its equivalent BCD form
Table 4.48 (a) Subroutine for converting a binary number into its equivalent BCD form

SUBROUTINE: PUSH B ; Save the contents of the BC register pair.
MVI B, 64H ; Load the divisor (100 in decimal value) in register B.
MVI C, OAH ; Load the divisor (10 in decimal value) in register C.
MVI D, OOH ; Initialize digit 1.
MVI E, OOH ; Initialize digit 2.
STEP1: CMPB ; Check if the binary number < 100 (in decimal
value).
JC STEP2 ; If it is, jump to STEP2.
SUB B ; If it is not, subtract the decimal value 100 from
the number.
INRE ; Increment digit 2 of the quotient.
JMP STEP1 ; Repeat the process.
STEP2: CMPC ; Check if the binary number < 10 (in decimal
value).
JC STEP3 ; If it is, jump to STEP3.
SUBC ; If it is not, subtract the decimal value 10 from the
number.
INRD ; Increment digit 1 of the quotient.
JMP STEP2 ; Repeat the process.
STEP3: POPB ; Restore the original value of the BC register pair.
Table 4.48 (b) Program for converting a binary number into its equivalent BCD form
LXI SP, 9FFFH ; Initialize stack pointer to the highest address.

LDA 9000H ; Load the binary number in the accumulator.
CALL SUBROUTINE ; Call the subroutine.
STA9100H ; Store digit 0—the units digit.
MOV A, D ; Load the value of digit 1 in the accumulator.
STA 9101H ; Store digit 1—the tens digit.
MOV A, E ; Load the value of digit 2 in the accumulator.
STA9102H ; Store digit 2—the hundreds digit.
Example 4.46:
Write a program to test the RAM by writing ‘1’ in all bit positions and reading it
back and later writing ‘0’ and reading it back. The RAM addresses to be checked
are 9000H to 90FFH. In case of occurrence of an error, it is indicated by writing
FFH in port 40H.
Program:
The program for testing the RAM is given in Table 4.49.
Table 4.49 Program for testing the RAM

LOOP: MVI M, FFH ; Write T into the RAM.
MOV A, M ; Read data from the RAM.
CPI FFH ; Check for error.
JNZ ERROR ; If an error has occurred, jump to ERROR.
INXH ; If not, increment the memory pointer.
MOV A, L ; Move the lower-order byte of the address to the
accumulator.
CPI OOH ; Check incremented pointer for OOH so that locations up
to 90FFH have been checked for error.
LXI H, 9000H ; If it is, initialize the memory pointer.
LOOP1: MVI M, OOH ; Write ‘0’ into the RAM.
MOV A, M ; Read data from the RAM.
CPI OOH ; Check for error.
JNZ ERROR ; If an error has occurred, jump to ERROR.
INXH ; If not, increment the memory pointer.
MOV A, L ; Move the lower-order byte of the address to the

accumulator.
CPI OOH ; Check incremented pointer for OOH so that locations up
to 90FFH have been checked for error.
JNZ LOOP1 ; If it is not, repeat the process.
ERROR: MVI A, FFH ; If there is an error in the memory, load FFH in the
accumulator.
OUT 40H ; Output it to port 40H.

Example 4.47:
Write a program to generate the Fibonacci series. Store it in the series of memory
locations starting 9000H.
Program:
The program for generating the Fibonacci series is given in Table 4.50.
Table 4.50 Program for generating Fibonacci series

MVI D, COUNT ; Initialize a counter for the number of data in the series.
MVI A, OOH ; Load the first number of the series in the accumulator.
MOV B, A ; Move this to the accumulator (register B holds the
previous number in the series at any point of time).
MOV M, A ; Store the first number.
MVI A, 01H ; Load the second number of the series in the
accumulator.
MOV C, A ; Initialize C to store the current number.
MOV M, A ; Store the second number.
LOOP: MOV A, B ; Load the previous number in the accumulator.
ADDC ; Add the two numbers.
MOV B, C ; Make the current number the previous number.
MOV C, A ; Save the result as the new current number.
MOV M, A ; Store the number.
DCRD ; Decrement count.
JNZ LOOP ; If the value of count is not equal to zero, repeat the
process.
HLT ; If the value of count is equal to zero, terminate
program execution.
4.2.5 Programming Examples based on Counters and Time Delays

Timing delay In a microprocessor, the timing of events is very important. Many
microprocessor applications require periodic actions. One example for such tinning
is data acquisition. It is customary to acquire data from the sensors in an industrial
environment at regular intervals and store them in memory. It may be necessary to
read temperature after every second and store the values in memory.
There are many techniques to maintain timing and delays. The simplest method
is using a software counter or timer. A software time delay is designed by loading

a register with a delay count and setting up a loop to decrement the count until it
reaches zero. The total time delay produced is determined by the clock period of
the system and the time required for executing instructions in the loop.
Counters and time delays are commonly used in applications such as traffic
signals, digital clocks, process control, and serial data transfer.
Example 4.48:
Write a subroutine to generate a delay of 1 ms in a processor with crystal frequency
3 MHz.
As we have just learnt, the time delay is produced by loading a register with a
count and then decrementing it until it becomes zero. Here, register C is used for
counting.
Program:
The subroutine for generating a delay of 1 ms is given in Table 4.51.
Table 4.51 Subroutine for generating delay of 1 ms
Number of T-states for

Mnemonics Comments
execution
DELAY: MVI C, count ; Load an 8-bit count in register C. 7
LOOP: DCR C ; Decrement count. 4
JNZ LOOP ; If the value of count is not equal 7/10
to zero, repeat the process.
RET ; If it is, return to the main 10
program.
Now, it is necessary to calculate the count required for executing this program in
1 ms.
Time delay calculation:
In the 8085, the operating frequency is 3 MHz. The time required for executing
each instruction is given in Table 4.51 in T-states. One T-state corresponds to
one clock period. So the time required for execution of the entire program can be
calculated. The instructions DCR C and JNZ LOOP are executed inside the loop
‘count’ times. The other two instructions are executed only once.
Time for execution of the program (in terms of number of T-states) = (10 + 4) x
count + 14
Time for execution of program in seconds = [14 x count + 14] x (time period T)
For a frequency of 3 MHz, time for execution = [14 x count + 14] x (1/3 MHz)
The time delay required is 1 ms.
So, 1ms = [14 x count + 14] x (1/3 MHz). Simplifying this equation gives the
count required for the 1 ms delay. Here, the value of count is approximately 213
(decimal) or D5 (hexadecimal).
Note; In the program given in Table 4.51, the maximum delay is produced by
using a count of 255; the corresponding maximum delay is 1.19ms for a clock
frequency of 3 MHz. If the clock frequency is increased, the execution becomes

faster and the time delay is reduced.
Note: The expressions given in this chapter for number of T-states taken by the
delay subroutine are approximate. Exact calculation is to be done by considering
the instruction time of each instruction in the subroutine separately.
Example 4.49:
The delay routine given is in an infinite loop. Identify the error and correct the
program.
Delay routine with error:
DELAY : LXI H, count
LI :DCXH
JNZL1
Solution:
(i) The fault is in the instruction JNZ LI. In the given program this condition
is always true, hence the occurrence of an infinite loop.
(ii) Reason for infinite looping: In the 8085 the instruction DCX H decrements
the HL register pair by one, but does not affect the zero flag. So when
the count reaches 0000H in the HL pair, the zero flag is not affected. The
instruction JNZ LI is, therefore, always true and the loop continues to
execute infinitely. So the HL pair decrements below 0000H to FFFFH and
the execution continues.
(iii) The modification in the program is given in Table 4.52. It is written as a
subroutine.
Table 4.52 Subroutine for producing time delay
Label Mnemonics Comments No. of T-states for execution
DELAY: LXI H, count ; Load the 16-bit count in the HL 10

register pair.
LOOP: DCXH ; Decrement count. 6
MOV A, L ; Move the lower-order byte of the 4
16-bit count to the accumulator.
ORAH ; Logically OR registers H and L. 4
JNZ LOOP ; If the result is not equal to zero, 7/10
repeat the process.
RET ; Return to the main program. 10

Total time delay in T-states = (6 + 4 + 4+ 10) x count + 20
Time for execution of program in seconds = [24 x count + 20] x T
For 3 MHz, maximum delay (with FFFFH as the count) is
= [24 x FFFF + 20] x (1/3 MHz)
= (24 x 65535 + 20] x (1/3 MHz) = 0.524s
ASSEMBLY LANGUAGE PROGRAMMING OF 8085 1 39
Example 4.50:
Write a program for displaying a binary up counter. It should count numbers from
OOH to FFH and increment every 0.5 s. Assume that the operating frequency of the
8085 is equal to 2 MHz and that the display routine is available.

Operating frequency = 2 MHz
Time for one T-state = 1/2 MHz = 0.5 ps
Time for execution of the program in seconds = [24 x count + 20] x T = 0.5 s
Required count = [(0.5/T) - 20]/24
Time required for one T-state = T = 1/(2 x 106) = 0.5 ps
Count = [(0.5/0.5 ps) - 20]/24 = 41666 = A2C2H
Flowchart:
The algorithm for displaying a binary up counter is given in Fig. 4.36.
Program:
The program for displaying a binary up counter is given in Tables 4.53 (a) and
4.53 (b).
Fig. 4.36 Algorithm for displaying binary up counter

Table 4.53 (a) Program for displaying binary up counter
LXI SP, 9FFFH ; Initialize the stack pointer.

MVI C, OOH ; Initialize a counter.
LOOP: CALL DISPLAY ; Call the subroutine DISPLAY.
CALL DELAY ; Call the subroutine DELAY.
INRC ; Increment the counter.
MOV A, C ; Move the value of the counter to the accumulator.
CPI OOH ; Check if the value of the counter is has reached FFH by
comparing it with OOH.
Delay subroutine:
Table 4.53 (b) Time delay subroutine
DELAY: LXI D, A2C2H ; Initialize count.

RPT: DCX D ; Decrement count.
MOV A, E ; Move the contents of register E to the accumulator.
ORAD ; Logically OR D and E.
JNZ RPT ; If the result is not zero, repeat the process.
RET ; If it is zero, return to the main program.
Example 4.51:
Write a program for displaying a BCD up counter. It should count numbers from
00 to 99 and increment every 1 s. Assume that the operating frequency of the 8085
is equal to 3 MHz and that the display routine is available.
Operating frequency = 3 MHz
Time for one T-state = 1/3 MHz = 0.333 ps
Let the external loop multiplier count be 3.
So, time delay required for the inner loop = 1 s/3 = 0.333 s
Required count = [(0.333/T) - 20]/24
Required count = 41624 = A298H
Program:
The program for displaying a BCD up counter is given in Tables 4.54 (a) and
4.54 (b).
Table 4.54 (a) Program for displaying BCD up counter

MVI C, OOH ; Initialize a counter.
MOV A, C ; Move the contents of the counter to the accumulator.
ADI01H ; Increment the counter.
DAA ; Adjust to make it a decimal number.
MOV C, A ; Store the counter.
CPI OOH ; Check if the counter is > 99.
Table 4.54 (b) Subroutine for time delay using two loops
DELAY: MVI B, 03H ; Initialize multiplier count (outer loop).

LOOP1: LXI D, A298H ; Initialize count (inner loop).
LOOP2: DCX D ; Decrement count.
MOV A, E ; Move the lower-order byte to the accumulator.
ORAD ; Logically OR the higher- and lower-order bytes.
JNZLOOP2 ; If the result is not equal to zero, repeat the process.
DCRB ; If it is equal to zero, decrement multiplier count.
JNZ LOOP1 ; If the value of multiplier count is not equal to zero, repeat
the process.
RET ; If it is equal to zero, return to the main program.
Example 4.52:
Write a program for displaying a BCD down counter. It should count numbers
from 99 to 00 and decrement every 1 s. Assume that the operating frequency of
the 8085 is 3 MHz and that the display routine is available.
Flowchart:
The algorithm for displaying a BCD down counter is given in Fig. 4.37.
Program:
The program for displaying a BCD down counter is given in Table 4.55.
Fig. 4.37 Algorithm for displaying BCD down counter
Table 4.55 Program for displaying BCD down counter
LXI SP, 9FFFH ; Initialize stack pointer.

MVI C, 99H ; Initialize counter = 99H.
MOV A, C ; Move the contents of the counter to the accumulator.
SUI01H ; Decrement the counter.
DAA ; Adjust to make it a decimal number.
CPI OOH ; Compare it with last value that the counter can take.
JNZ LOOP ; If they are not equal, repeat the process.
CALL DISPLAY ; Call the subroutine DISPLAY, to display 00.
Example 4.53:
Write a delay routine for producing a delay of 0.5 s. The operating frequency of
the microprocessor is 3.072 MHz.
1 T-state = 1/operating frequency
= 1/(3.072 x 106)
Count = [(0.5/T) - 20J/24 = 62499 = F423H
Delay subroutine:
The subroutine for generating a delay is given in Table 4.56.
Table 4.56 Subroutine for generating delay

DELAY: LXI D, F423H ; Initialize count—10 T-states
LOOP: DCXD ; 6 T-states
MOV A, D ; 4 T-states
ORAE ; 4 T-states
JNZ LOOP ; 10 T-states
RET ; Return to the main program—10 T-states
Example 4.54:
Write a program to calculate the factorial of a number between zero and eight.
The number is stored in the memory location 9000H. Store the result in 9100H
and9101H.
Flowchart:
The algorithm for finding the factorial of a number between zero and eight is given
in Fig. 4.38.
Program:
The program for finding the factorial of a number between zero and eight is given
in Tables 4.57 (a) and 4.57 (b).
Table 4.57 (a) Program for finding factorial of a number between zero and eight

CPI 02H ; Check if the number is lesser than 2.
JC LAST ; If it is, store 1 as the result.
MOV E, A ; Move the number for which factorial is to be found to
register E.
CALL FACTO ; Call the subroutine FACTO.
(Contd)
Table 4.57 (a) Program for finding factorial of a number between zero and eight (Contd)
XCHG ; Load the result in HL register pair.

SHLD 91 OOH ; Store the result.
JMP END ; Jump to END.
LAST: LXI H, 0001H ; Load the value 0001H in the HL register pair.
END: SHLD 91 OOH ; Store the result.
Subroutine:
This subroutine finds the factorial of the number stored in register E and stores the
result in the DE register pair.
pig. 4.38 Algorithm for finding the factorial of a number between zero and eight
Table 4.57 (b) Subroutine for finding factorial of a number between zero and eight

FACTO: LXI H, 0000H ; Load the value 0000H in the HL register pair.
MVI D, OOH ; Initialize register D with the value OOH.
MOV A, E ; Move the number N to the accumulator.
DCR A ; Decrement the accumulator.
MOV C, A ; Initialize register C with N - 1.
LOOP1: MOV B, C ; Initialize the counter B with the number for
multiplication.
LOOP: DADD ; Multiply by repeated addition until register B is zero.
DCRB ; Decrement register B.
JNZ LOOP ; If the value is not equal to zero, repeat the process.
XCHG ; Store the result in the DE register pair.
LXI H, 0000H ; Clear the HL register pair.
JNZ LOOP1 ; Loop again for the next multiplication in the factorial.
Example 4.55:
Write a program to find the square root of an 8-bit binary number stored in memory
location 9000H. Store the square root in 9100H.
Flowchart:
Figure 4.39 shows the algorithm followed in the division subroutine used in this
program.
This program assumes that X, whose initial value is taken as 2, is the square root
of Y. For every assumed value of X, ((Y/X) + X)/2 is calculated and this is taken
as the new value of X. If the new value of X equals the earlier value of X, then that
value is taken as the square root of Y.
Program:
The program for finding the square root of an 8-bit number is given in
Tables 4.58 (a) and 4.58 (b).
Table 4.58 (a) Program for finding the square root of an 8-bit number
LDA 9000H ; Load the given data (Y) in the accumulator.

MOV B, A ; Move it to register B.
MVI C, 02H ; Load the divisor (02H—assumed value of X) in register C.
(Contd)
Table 4.58 (a) Program for finding the square root of an 8-bit number (Contd)
CALL DIV ; Call the subroutine DIV to get the initial value of X in
register D.
REP: MOV E, D ; Move the initial value of X to register E.
MOV A, B ; Move the dividend Y to the accumulator.
MOV C, D ; Move the initial value of X to register D.
CALL DIV ; Call the subroutine DIV to get the initial value (Y/X) in
register D.
MOV A, D ; Move Y/X to the accumulator.
ADDE ; Add X to the accumulator content to make it (Y/X) + X.
MVI C, 02H ; Load the divisor (02H) in register C.
CALL DIV ; Call the subroutine DIV to get ((Y/X) + X)/2 in register D.
This is XNEW.
MOV A, E ; Load the initial value of X in the accumulator.
CMPD ; Compare X and XNEW.
JNZ REP ; If XNEW is not equal to X, repeat the process.
STA 91 OOH ; Save the square root in memory location 91 OOH.
Subroutine:
This subroutine loads the dividend in the accumulator, the divisor in register C,
and the quotient in register D.
Table 4.58 (b) Subroutine for finding the square root of an 8-bit number
DIV: MVI D, OOH ; Load OOH in register D as initial value of the quotient.
NEXT: SUB C ; Subtract the divisor from the dividend.
INRD ; Increment the quotient.
CMPC ; Compare the dividend with the divisor.
JNC NEXT ; Repeat the subtraction process until the divisor is lesser
than the dividend.
Fig. 4.39 Division subroutine used in finding the square root of an 8-bit number
Example 4.56:
Subtract the BCD number stored in register E from the BCD number stored in the
register D.
Program:
The program for subtracting one BCD number from another is given in
Table 4.59.
Table 4.59 Program for subtracting two BCD numbers
Mnemonics Comments
MVI A, 63H ; Load the number 63H in the accumulator.

SUB E ; Find the 99’s complement of the subtrahend.
INRA ; Find the 100’s complement of the subtrahend.
ADDD ; Add the minuend to the 100’s complement of the subtrahend.
DAA ; Adjust the number to bring it to its equivalent BCD form.
Note: When two BCD numbers are added, the DAA instruction is used to convert
the result to BCD. Therefore, the subtraction of two BCD numbers is carried out
by 100’s complement method. The 100’s complement of a decimal number is
equal to the 99’s complement plus 1. To subtract two BCD numbers using 100’s
complement method:
(i) Find the 100's complement of the subtrahend (99 - subtrahend +1).
(ii) Add the two numbers using BCD addition method and neglect the carry, if
any.
Example 4.57:
Write a program to multiply two BCD numbers.
Program:
The program for multiplying two BCD numbers is given in Table 4.60.
Table 4.60 Program for multiplying two BCD numbers
MVI C, multiplier ; Load the BCD multiplier in register C.

MVI B, OOH ; Initialize register B as a counter with initial value
OOH.
LXI H, 0000H ; Initialize HL register pair to 0000H (result =
0000H).
MVI E, multiplicand ; Load the multiplicand in register E.
MVI D, OOH ; Extend it to 16 bits, with the higher-order bits being
OOH.
LOOP: DADD ; Result = result + multiplicand.

MOV A, L ; Load the lower-order byte of the result in the
accumulator.
ADI OOH ; Add OOH so that the DAA instruction can be used to
convert the result to BCD form.
DAA ; Convert the lower-order byte of the result to BCD

form.
MOV L, A ; Store the lower-order byte of the result.
MOV A, H ; Load the higher-order byte of the result in the

accumulator.
ACI OOH ; Add it with OOH and the carry.
DAA ; Convert it to BCD form.
MOV H, A ; Store the higher-order byte of the result.
MOV A, B ; Move the counter to the accumulator.
ADI01H ; AddOlH.
(Contd)
Table 4.60 Program for multiplying two BCD numbers (Contd)
DAA ; Convert it to BCD form.

MOV B, A ; Move it back to register B.
CMPC ; Compare it with the multiplier.
JNZ LOOP ; If they are not equal, repeat the process.
SHLD9100H ; If they are equal, store in 91 OOH.
Example 4.58:
In the program given here, what would be the contents of the registers after
execution of all instructions?
Main program:
8000H: LXI SP, 27FFH
8OO3H: LXI H, 2000H
8OO6H: LXI B, 1020H
8009H: CALL SUB
800CH: HLT
Subroutine:
8I00H: SUB: PUSH B
8101H: PUSHH
8102H: LXI B, 4080H
8105H: LXIH, 4090H
81O8H: SHLD2200H
8109H: DADB
810CH: POPH
810DH: POPB
810EH: RET
Table 4.61 gives the instruction sequence and the contents of all registers and the
stack after execution of each instruction.
Table 4.61 Register and stack contents during program execution
Register contents (in hex form) Memory locations

S.No. Instructions
A B C D E H L SP PC (in hex form)
1. LXI SP, 27FF X X X X X X X 27FF 4003

2. LXI H, 2000 X X X X X 20 00 27FF 4006
3. LXI B, 1020 X 10 20 X X 20 00 27FF 4009
(Contd)
Table 4.61 Register and stack contents during program execution (Contd)
Register contents (in hex form) Memory locations

S.No. Instructions (in hex form)
A B c D E H L SP PC
4. CALL SUB X 10 20 X X 20 00 27FD 4100 (27FE—40,
27FD—OC)
6. PUSHH X 10 20 X X 20 00 27F9 4102 (27FA—20,
7. LXI B, 4080 X 40 80 X X 20 00 27F9 4105 27F9—00)
8. LXI H, 4090 X 40 80 X X 40 90 27F9 4108
9. DADB X 40 80 X X 81 10 27F9 4109
10. SHLD 2200 X 40 80 X X 81 10 27F9 410C (2200—10,
11. POPH X 40 80 X X 20 00 27FB 4100 2201—81)
12. POPB X 10 20 X X 20 00 27FD 410E
13. RET X 10 20 X X 20 00 27FF 400C
14. HLT X 10 20 X X 20 00 27FF 4000
POINTS TO REMEMBER
• An assembler is a program used to translate the assembly language mnemonics to the

equivalent binary code for each instruction.
• The assembler directives are used to control the 8085 assembler in its generation of
object code.
• The 8085 instruction set contains only 74 different instructions, some of which are used
quite frequently.
• The assembly language program written using mnemonics is the basic interface between
the processor and the user. Programmers have the liberty to utilize the features of the
instruction set of a microprocessor in developing efficient programs.
• Programming a microprocessor involves simple arithmetic and logical operations,
complex looping and branching, and condition checking.
KEY TERMS
Access time The time required to translate the assembly code to object code is called
access time.
Arithmetic operations The 8085 microprocessor performs various arithmetic operations
such as addition, subtraction, increment, and decrement.
Assembler It translates the assembly language program text, which is given as input to
the assembler, to its binary equivalent known as object code. The assembler checks for
syntax errors and displays them before giving the object code.
Assembly language In this language mnemonics (short-hand form of instructions) are

used to write programs is called assembly language. The manufacturers of microprocessor
list the mnemonics that can be used with the processors.
Branch operations The microprocessor is a sequential machine—it executes machine
codes from one memory location after another in sequence. Branch instructions instruct
the microprocessor to go to a different memory location. The microprocessor continues
executing machine codes from that new location. The address of the new memory location
is either specified explicitly or supplied by the microprocessor or external hardware.
Logical operations A microprocessor can perform all the logic functions written in a
program, using its instruction set. Hardware implementation of these instructions is done
through hard-wired logic. The 8085 instruction set includes such logic functions as AND,
OR, EXOR, and NOT.
Looping It is the programming technique used to instruct the microprocessor to repeat
tasks.
Machine language program It is a software that consists of programs developed using
Is and Os.
REVIEW QUESTIONS
1. Write a program to arrange n numbers in ascending order.

2. Write a program to unpack a 2-digit BCD number stored at memory location 1C00H.
3. Explain the algorithm and write a program to convert a BCD number into its equivalent
decimal form.
4. Explain the algorithm and write a program to convert a BCD number to seven-segment
code.
5. Write a program to find the seven-segment codes for the lower and higher nibbles of
the given 8-bit binary number using look-up table technique and store the result in
memory.
6. Write a program to calculate the factorial of a number between zero and eight.
7. Write a program to count the number of zeros, negative and positive numbers in an
array of numbers stored in memory locations starting at 9000H.
8. Write a program to perform the following arithmetic operation: ab + ac, where a, b,
and c are 8-bit binary numbers. Explain with an algorithm and flowchart.
9. Write a program to add two 16-bit numbers from memory locations 100H and 102H
using 16-bit move and arithmetic instructions and save the result starting at 104H.
''
Part 2
--- ----------------- -------------------------------------
HARDWARE
.RFACING WITH
INTEL 8085
Chapter 5: Methods of Data Transfer and Interrupt

Structure in 8085
Chapter 6: Interfacing Memory and I/O Devices

with 8085
Chapter 7: Features and Interfacing of

Programmable Devices for 8085-based
Systems
Chapter 8: A Complete 8085-based System

E
CHAPTER □
METHODS OF DATA TRANSFER AND

INTERRUPT STRUCTURE IN 8085
....................................... ~~........ ~~ ” ............................. ™ ..... ------ ---------------- - -------------- -------- ----------- „j|_......... .
LEARNING OUTCOMES
• Different approaches to data transfer
• Different data transfer mechanisms
• Serial data transfer protocols
• Data transfer for slow peripheral devices
• Intel 8085 interrupt types and sources
• Interrupt vectors and priorities
• Interrupt masking
• Timing of interrupts
.. .11111101)1 .1 II.I UH. ....I V. 1.1.UH. . m. , . . J,,,,,,. t w
5.1 DATA TRANSFER MECHANISMS

Data transfer is essential in any microprocessor-based system. It can take place
between the processor and the memory, the processor and an input/output device,
or the memory and an input/output device.
Data can be transferred in several ways. The mechanism differs based on
characteristics such as the addressing of the devices, amount of data transferred,
method of data transfer, and interaction among the devices. The data transfer
mechanism is divided into the following types:
Based on the addressing of the device

(i) I/O-mapped I/O access (ii) Memory-mapped I/O access
Based on the program and hardware involved

(i) Programmed data transfer
(a) Polled mode of data transfer (b) Interrupt-driven data transfer
(ii) Direct memory access
(a) Burst mode (b) Cycle stealing mode
Based on the method of data transfer and access

(i) Parallel data transfer
(a) Simple data transfer (b) Handshake mode data transfer
(ii) Serial data transfer
(a) Synchronous data transfer (b) Asynchronous data transfer
5.2 MEMORY-MAPPED AND l/O-MAPPED DATA TRANSFER

In I/O-mapped device data transfer method, I/O devices and memory are handled
separately. A separate address range is assigned for input/output devices. Separate
control signals are used for memory access and for I/O device read/write operation.
The microprocessor has separate instructions for input and output device access,
such as the IN and OUT instructions of the 8085. As memory and I/O device
accesses are governed by separate control signals, a single address can be assigned
to both an I/O device and a memory location.
In memory-mapped I/O, each input/output device is treated like a memory
location. The same control signals are used for I/O device read/write operation and
for memory access. Each input or output device is identified by a unique address
in the memory address range. All memory-related instructions that are used to
read data from memory are used to access input and output devices. Since the I/O
devices use some of the memory address space, the maximum memory addressing
capacity is reduced in this system.
5.3 PROGRAMMED DATA TRANSFER

The instructions for programmed data transfer are written and controlled by the
programmer and executed by the processor. The data transfer between the processor
and I/O devices (and vice versa) takes place by executing the corresponding
instructions. Programmed I/O data transfers are identical to read and write
operations for memories and device registers. An example of programmed I/O is a
device driver writing one data byte at a time directly into the device’s memory.
Programmed data transfer can take place at a time determined by the
programmer. Based on the time of execution of the data transfer instruction,
programmed data transfer is divided into two types—polled mode of data transfer
and interrupt-driven data transfer.
In polled mode of data transfer, data is read from an input device when the
processor or CPU is ready. The processor then executes the data transfer instruction.
If the input device is not ready, the processor waits until the device is ready with
data. Similarly, data is written into an output device by the processor when it
executes the write instruction corresponding to that output device. The program is
written in such a way that the processor waits in a loop until the output device is
ready to receive data. Clearly, in waiting for the device to be ready, processor time
is wasted in this mode of data transfer.
In interrupt-driven data transfer, data is read from the input device only when
it is ready with data. When the device is ready, it gives an interrupt signal to
the processor, indicating that the data is ready. In the interrupt service routine
(1SR), a program is executed to read the data from the corresponding input device.
Similarly, the output device gives an interrupt to the processor when it can accept
data. The programmers have to write an ISR for data transfer to the corresponding
output device. Interrupt-driven data transfer is advantageous as data transfer is
done only when the device is ready; the processor need not wait until the device
is ready. The processor can execute some other main routines and data transfer
METHODS OF DATA TRANSFER AND INTERRUPT STRUCTURE IN 8085 157
program will be executed as ISRs. It is an efficient technique because processor

time is not wasted in waiting while an I/O device is getting ready or not ready.
Slow I/O devices can be interfaced for data transfer using the interrupt-driven
technique.
5.4 DIRECT MEMORY ACCESS

In programmed I/O data transfer, the processor is actively involved in the entire
data transfer process. So, the data transfer rate is limited. The processor is tied
up and processor time is wasted. To overcome these disadvantages, the direct
memory access (DMA) method of data transfer is used.
Direct memory access is a technique to transfer data between the peripheral
I/O devices and the memory, without the intervention of the processor. The basic
idea is to transfer blocks of data directly between the memory and the peripherals.
Even though the transfer is done without the processor, the processor initiates the
DMA operation. This technique is generally used to transfer large blocks of data
between memory and I/O. During DMA data transfer, the processor/CPU is kept
in an idle suspended state called as Hold state. DMA performs high-speed data
transfer to and from mass storage peripheral devices such as hard disk drives,
magnetic tapes, CD ROMs, and video controllers. A hard disk may have a transfer
rate of 5 Mbps, i.e., one byte every 200 ns. Performing such data transfer using the
CPU is not only undesirable but also unnecessary, since the CPU transfer rate is
limited by the speed of the memory and peripheral devices.
Under normal circumstances, the CPU has full control of the address and data
buses in the system. When direct memory access occurs, an external device or
DMA controller takes over the temporary control of the system bus from the CPU.
The CPU writes necessary control words into the DMA controller, to indicate the
following details about the data transfer: read or write operation, device address
involved, starting address of the data memory block and the amount of data to
be transferred. After this initialization, the DMA controller takes care of the data
transfer. In the 8085, the hold request is received and acknowledged using the
HOLD and HLDA pins, respectively.
The sequence of events in a typical DMA process is as follows:
(i) The peripheral or the DMA controller asserts one of the request pins (such
as HOLD) for holding the processor.
(ii) The processor completes its current instruction and enters into the Hold
state. In the Hold state, the processor temporarily stops the execution of the
instruction and releases the address and data buses by making them enter
into a high impedance state.
(iii) The processor issues a Hold Acknowledge (HLDA) signal to indicate the
release of bus control to the peripheral or the DMA controller.
(iv) The DMA operation starts.
(v) Upon completion of the DMA operation, the peripheral or the DMA
controller removes the Hold signal applied to the processor and relinquishes
bus control.
In general, a DMA controller can interface several peripherals that may

request DMA with the processor. It is the controller that decides the priority of
DMA requests that are received simultaneously from many peripherals. It then
communicates with the peripheral device and the processor, and provides memory
addresses for transferring data. The 8237 programmable DMA controller is the
controller device that is most commonly used with the 8085 and 8088. It is a
four-channel device, with each channel being dedicated to a particular peripheral
device. In addition, each channel is capable of addressing 64 KB of memory.
DMA data transfer can be divided into two types:
(i) burst or block transfer mode
(ii) cycle stealing or interleaved mode
In burst mode of DMA data transfer, a complete block of data is transferred in a
single DMA cycle. The system bus is released by the peripheral or DMA controller
only after the required bytes of data are transferred. In cycle stealing mode of data
transfer, a block of data is transferred over many DMA cycles. The system bus is
released to the processor after a byte or a set of bytes are transferred in one DMA
cycle. Thus, the processor is not suspended from its activities for a long time. It
takes several DMA cycles to complete the transfer of one block of data.
5.5 PARALLEL DATA TRANSFER

In parallel mode of data transfer, all the bits in a word are simultaneously
transmitted. Since the 8085 word consists of eight bits, all the eight bits are
transmitted and received in parallel form. In some special cases, the number of
data bits transferred will be lesser than eight. In general, parallel data transfer
is used for transfer of data over short distances such as within a system, within
a printed circuit board (PCB), etc. It can be done either in polled mode or in
interrupt-driven mode. In polled method, data is read from the input device by the
processor at a time determined by the processor. This polled mode of data transfer
can be done in two ways—synchronous or simple I/O and handshake I/O.
In simple or synchronous mode, data is read from the input device by the
processor irrespective of the status of the input device. It is assumed that the
input device is in synchronism with the processor and that it is ready with data
whenever the processor reads the data. Similarly, the data is written into the output
device irrespective of its status. The processor assumes that the output device is in
synchronism with the processor.
In handshake I/O mode, the processor checks for the status of the I/O devices
before data transfer. An input device gives a signal to the processor, indicating that
it is ready with the data. The processor checks continuously for the reception of
this signal and upon reception can read the data. Similarly, an output device gives
a signal to the processor, indicating that it can accept data. The processor, before
writing data to the output device, checks for this signal. If the signal indicating
readiness of the output device is available, the processor can write the data to
the output device. The signals that are transferred between the devices and the
processor are called handshake signals.
5.6 SERIAL DATA TRANSFER

Parallel data transfer has the drawback of needing several wires to transfer all the
bits of data. So, it can not be used effectively for long distance transfers. As one
wire is used for each bit, byte-wise data transfers are eight times more expensive
than a single bit transfer. Serial data transfer is the solution for data transfers over
long distances. It is a low-cost way to send data over long distances. In serial
data transfer, only one bit is transferred over a data transfer line. All the bits in
a data word can be transmitted by using a shift register and transferring the data
bit by bit. Parallel-to-serial data conversion is done by a device called Universal
Asynchronous Receiver-Transmitter (UART).
In serial data transfer, the following three aspects are important: First, the
speed or frequency at which the bits are transmitted into the serial data line.
The frequency at which the data is transmitted serially is technically called baud
rate. Baud rate is the measure of the number of bits transmitted over a second.
Second, the mode of data transfer. Serial data transfer can be done in two modes—
synchronous and asynchronous. Third, the voltage levels for logic 1 and logic
0 for the data being transmitted. Various serial communication protocols define
these aspects as standards for proper communication.
In synchronized data transfer, the device that sends the data and the device that
receives the data are synchronized with the common clock. In synchronous mode,
data transfer takes place with a fixed and known time frame. In asynchronous
data transfer, data words are transmitted with a random time frame between them.
Most microprocessor- and computer-related data communications are based on
the asynchronous mode of transmission. Microprocessors use interrupts and other
software techniques to synchronize random timing between data words, so as to
receive the data completely.
The modem plays an important role in serial transmission. It is a device that
allows transmission of serial data over communication lines such as telephone
lines. In general, communication lines are incapable of carrying the voltage changes
required for a direct digital connection. A modem overcomes this limitation by
modulating digital information into analog signals using one of the modulation
techniques and demodulating it back into digital information upon reception.
The computer or a microprocessor terminal that initiates the serial communication
is called Data Terminal Equipment (DTE). The final equipment that receives
the serial data is also called Data Terminal Equipment. Data Communication
Equipment (DCE) is a device that connects the DTE to a transmission line. So,
the transmitting DTE sends the serial data to the DCE. The DCE is generally
a modem. This helps in level shifting and transmitting the serial data over the
chosen transmission line. Similarly, at the receiving station, a DCE (generally a
modem) receives the signal and transfers the serial data to the receiving DTE.
This section introduces the RS-232, RS-485, General-Purpose Interface Bus
(GPIB), and IEEE 488 standards, which are used for data transfer between two
computer or processor systems. RS-232 is a common serial communication
protocol used in computer systems.
5.6.1 Introduction to RS-232 Standard

RS-232 is a serial communication standard given by the Electronic Industries
Association (EIA), an organization represented by a group of electronic industries.
It is used for one-to-one communication between two computers or processor
systems. RS-232 standard can also be used with modems. RS-232 can be used to
interface a processor system or DTE with a modem/DCE. It is the standard used
on personal computers’ COM port. The maximum possible speed with RS-232 is
20 kbps and the maximum possible cable length is 50 feet.
Logic 1 is represented by voltages in the range -3 V to -25 V, and typically by
-12 V. Logic 0 uses the voltage range from 3 V to 25 V, and typically 12 V. When
no data is sent over the transmission line and the transmitter is inactive, the voltage
level on the line is kept at a high level, i.e., -12 V. Figure 5.1 shows the RS-232
voltage levels.
Fig. 5.1 RS-232 voltage levels
RS-232 is a serial communication standard for asynchronous communication.

The transmitter places logic 1 on the data bus when it is inactive. To start
transmission, the transmitter sends a logic 0 as the start bit. The start bit makes the
receiver wake up from idle mode and start receiving data. After the start bit, data
bits are transmitted on the serial transmission line. The length of the data bits can
be five, six, seven, or eight depending on the transmitting equipment. The least
significant bit of the data byte is transmitted first in the data line. The data bits are
succeeded by a parity bit or any other error correcting bit set by the programmer.
After this, the stop bit is sent by the transmitter to indicate the end of the data bits.
Logic 1 is used as the stop bit in RS-232 communication standard. The format of
the signal transmitted is shown in Fig. 5.2. Here, the ASCII code for the character
Fig. 5.2 RS-232 bit format for transmitting character ‘A’

A is shown being transmitted on the line with the parity bit as 1. The format uses
two stop bits of logic 1 consecutively.
Another parameter specified by the RS-232 communication standard is the
baud rate. It is the rate at which data is transmitted and received. The baud rate
and the timing for each bit is related by the following formula:
Time period for each bit in seconds = 1/baud rate
Table 5.1 lists the standard baud rate Table 5.1 Bit timings for standard baud rates
used by the RS-232 communication
Baud rate Time for each bit in
standard and the corresponding bit microseconds
duration.
RS-232 communication connection 1200 833
is done through standard connectors. 2400 417
Two types of RS-232 connectors are 9600 104
available. One has 25 pins and the other 19,200 52
has nine. Details of the DB25S and
DB9S connectors are shown in Fig. 5.3. A cable with any one of these connectors
is used to connect the DTE (computer) with the DCE (modem).
Pin Signal
13 12 11 10 9 8 7 6 5 4 3 2 1 2 TXData
ooooooooooooo 3 RXData
oooooooooooo 4 RTS
25 24 23 22 21 20 19 18 17 16 15 14 , 5 CTS
6 DSR
(a) 7 GND
20 DTR
Pin Signal
2 RXData
5 4 3 2 1 3 TXData
o o o o o 4 DTR
o o o o 5 GND 1
9 8 7 6 6 DSR
7 RTS
(b)
8 CTS
Fig. 5.3 Basic details of RS-232 (a) DB25S and (b) DB9S connectors
The basic signals used in these connectors are given in Table 5.2.
Table 5.2 Signals of RS-232 connection
Signal name Function

Receive data line (RXD) Data is received by the processor on this line
Transmit data line (TXD) Data is sent by the processor through this line
Data Terminal Ready (DTR) Signal sent out by the processor to indicate that it is
ready for communication
Data Set Ready (DSR) Signal sent by the modem to the processor to
indicate that it is ready to transmit or receive
Request to Send (RTS) Signal sent out by the processor to the modem to
indicate that it is ready to send data
Clear to Send (CTS) Signal sent by the modem to the processor to
indicate that it can accept data for transmission
Figure 5.4 shows the standard connection for RS-232 communication between
two DTEs through two modems.
Fig. 5.4 RS-232 communication connection using modems and line
The system uses all handshake signals such as RTS, CTS, DTR, and DSR
mentioned in Table 5.2. Although the figure does not indicate the handshake
signals between the two modems, some amount of signal transfer takes place
between the modems also.
If there is no modem, and two processors or computer systems are directly
connected using the serial communication line, the connection shown in Fig. 5.5 is
used. Here, the handshake signals are not used, since they are connected within the
DTE system itself. The communication assumes that the receiver is always ready
to receive data.
Fig. 5.5 RS-232 connections with no handshaking and DCE (modem)
5.6.2 Introduction to RS-485 Standard

RS-485 is another serial communication standard defined by the EIA. The major
difference between RS-232 and RS-485 is that RS-232 is used for one-to-one
communication, whereas RS-485 is used in a network environment. The major
features of RS-485 standard are as follows:
(i) RS-485 can connect several processors or DTEs in a network structure for
communication.
(ii) RS-485 can be used for communication over longer distances than RS-232,
(iii) RS-485 can communicate with higher baud rates, i.e., faster than RS-232,
(iv) One RS-485 transmitter can drive up to 32 receivers in a network.
(v) RS-485 transmitter uses two signal lines—Fsig and -sig. The RS-485
receiver senses the voltage difference between these lines. So, any voltage
difference on the ground line between the transmitter and the receiver does
not affect the reception. However, RS-232 receiver senses the voltage level
of the signal with respect to the ground and so, the noise voltage level may
affect the data sensed.
By default, all the senders on the RS-485 bus are tri-stated, i.e., in high
impedance state. In higher-level protocols, one of the nodes is defined as a master
that sends queries or commands over the RS-485 bus. All other nodes receive these
data. Depending of the information contained in the data sent, zero or more nodes
on the line respond to the master. In this situation, bandwidth of almost 100% can
be used. There are other ways of implementing the RS-485 network, where every
node can start a data session on its own. This is comparable to the way Ethernet
networks function. Since there is a possibility of data collision in this type of
implementation, theoretically only 37% of the bandwidth will be effectively used.
With such an implementation of an RS-485 network, it is necessary to implement
error detection in the higher-level protocol so as to detect data corruption and
resend the information later.
5.6.3 GPIB/IEEE 488 Standards

Hewlett-Packard designed the Hewlett-Packard Interface Bus (HP-IB) to connect
their programmable smart instruments to computers. This standard supports many
devices connected to a common bus and forming a network. Communication can
take place between all the devices connected to the bus. This standard has a higher
transfer rate of up to 1 Mbyte/s, in comparison with the RS-232 and RS-485. This
standard has been named IEEE Standard 488. HP-IB is also called GPIB. The
devices in the GPIB bus can be connected in a linear network, star configuration,
or a combination of both.
GPIB standard categorizes the devices connected together into three types—
talkers, listeners, and controllers. A talker can send data to other devices. A listener
is a device that can receive data from other devices connected in the bus. A controller
is a device that determines which of the devices should be listeners and which of
them should be talkers. In general, a GPIB bus has one controller and many talkers
and listeners. Some of the devices in the bus network can act as both talkers and
listeners. Communication can take place from one talker to one listener or from
one talker to many listeners in the bus. The controller decides the data transfers
and also issues commands to other devices. A bus system with only one talker
does not need any controller. The talkers and listeners are generally computer or
microprocessor systems. The microprocessor systems can be configured as talkers
or listeners by interfacing it to the Intel 8291 GPIB talker-listener. Similarly, Intel
8292 GPIB controller can be interfaced to the microprocessor or computer systems
to manage the GPIB communication.
The GPIB interface system uses 24-

pin connectors, as shown in Fig. 5.6.
Among the 24 pins, eight lines are
bidirectional data lines and eight are
ground lines. Among the remaining
eight lines, three pins are for handshake
DI01 DI05
signals and five are for bus interface
DI02 DI06
management signals. The eight
DI03 DI07
data lines are used for transmission
0104 DI08
and reception of data, addresses,
EOI REN
commands, and status bytes. GND (Twisted pair with DAV)
DAV
The five bus interface management GND (Twisted pair with NRFD)
NRFD
lines and their functions are as NDAC GND (Twisted pair with NDAC)
follows: IFC GND (Twisted pair with IFC)
(i) IFC (Interface Clear)—The con SRQ GND (Twisted pair with SRQ)
troller in the bus sends this ATN GND (Twisted pair with ATN)
signal to all other devices in SHIELD SIGNAL GROUND
the bus to initialize the bus and

reset the system communication
i
upon powering on. I
(ii) ATN (Attention)—The control-
ler sends an active low ATN Fig. 5.6 GPIB bus connector and signals
signal to indicate that it is
sending a universal command or an address on the bus. This signal is made
high for data transfers.
(iii) REN (Remote Enable)—The controller makes this signal active to directly
control a device instead of the front panel controllers in the device.
(iv) EOI (End or Identify)—The EOI signal is issued by the talker to indicate
the end of block transfer of data. The controller uses the EOI line to make
devices identify themselves in a parallel poll.
(v) SRQ (Service Request)—This signal is made active by any device that
requires to transfer data on the bus.
Three lines are used as handshake signals to control the transfer of message
bytes between devices. The process is called a three-wire interlocked handshake
and it is used to transfer data from different devices at different transfer rates.
It guarantees that message bytes on the data lines are sent and received without
transmission error.
(i) NRFD (Not Ready for Data)—This signal is sent by all devices when they
are not ready to receive a message byte. When receiving data, the devices
make this line inactive by making it low.
(ii) DAV (Data Valid)—The controller makes DAV low while sending
commands, and the talker drives DAV low while sending data messages.
(iii) NDAC (Not Data Accepted)—The active low NDAC signal is low until the
transmitted data is received by the slowest listener. This signal indicates that
a device in the bus has not received a message byte. Usually, the talkers wait
METHODS OF DATA TRANSFER AND INTERRUPT STRUCTURE IN 8085 1 65
for this signal and once the NDAC is high, the DAV signal is removed by the
talkers.
The GPIB uses active low logic with standard TTL levels. For example, when
DAV is active, the devices send a TTL low level (<0.8V), and when DAV is
made inactive, the line has a TTL high level (>2.0V).
5.7 INTERRUPT STRUCTURE

Interrupt is a mechanism by which the processor (CPU) is made to transfer control
from its current program execution to another program of more importance or
higher priority. The interrupt signal may be given to the processor by any external
peripheral device. In general, interrupts are generated by a variety of sources,
either internal or external, to the CPU. Interrupts are the primary means by which
input and output devices obtain the services of the CPU.
The program or the routine that is executed upon interrupt is called interrupt
service routine (ISR). The processor must temporarily stop its current task and
execute the ISR, which relates specifically to the event or device that issues
the interrupt signal. After execution of the ISR, the processor must return to
the interrupted program. Processors have many interrupt signals and proper
identification of interrupt signals is done internally by the processor.
The key features in the interrupt structure of any microprocessor are as follows:
(i) The number and types of interrupt signals available.
(ii) The address of the memory where the ISR is located for a particular interrupt
signal. This addresses called interrupt vector address.
(iii) The masking and unmasking feature for the interrupt signals. This feature
allows the programmer to execute the ISR only when required.
(iv) The priority ofinterrupts when more than one interrupt signals are available
(v) The timing of the interrupt signals
(vi) The handling and storing of information about the interrupted program
(status information). This information must be loaded into the CPU when
the ISR is executed. When the return instruction is executed, control is
transferred back to the interrupted program.
5.8 TYPES OF INTERRUPTS

Interrupts are classified based on their maskability, interrupt vector address, and
source. These classifications are discussed in Sections 5.8.1-5.8.3.
5.8.1 Vectored and Non-vectored Interrupts

The vectored and non-vectored interrupts are as follows:
(i) Non-vectored interrupts have fixed interrupt vector address for ISRs of
different interrupt signals. They are useful for small systems, where there
are few interrupt sources and the software structure is not complicated.
(ii) Vectored interrupts require the interrupt vector address to be supplied by
the external device that gives the interrupt signal. This technique, called
vectoring, is implemented in a number of ways.
5.8.2 Maskable and Non-maskable Interrupts

The maskable and non-maskable interrupts are as follows:
(i) Maskable interrupts are interrupts that can be blocked; the corresponding ISRs
are not executed. The masking can be done by software or hardware means.
(ii) Non-maskable interrupts (NMIs) are interrupts that are always recognized;
the corresponding ISRs are executed.
5.8.3 Software and Hardware Interrupts

The software and hardware interrupts are as follows:
(i) Software interrupts are special instructions, which after execution transfer
the control to a predefined ISR. These instructions are included in the
program by the programmer.
(ii) Hardware interrupts are signals given to the processor, for recognition as an
interrupt and execution of the corresponding ISR.
5.9 INTERRUPT HANDLING PROCEDURE

When an interrupt signal is recognized, the processor will have to store information
about the current program before executing the ISR. The processor checks for the
interrupt request signals at the end of every instruction execution. If the interrupt is
masked, it will not be recognized until interrupts are re-enabled. The CPU responds
to an interrupt request by a transfer of control to another program, in a manner
similar to a subroutine call. This is shown pictorially in Fig. 5.7. The sequence of
operations that take place when an interrupt signal is recognized is as follows:
(i) Save the program counter (PC) contents (address of the next instruction)
and supplementary information about the current state (flags, registers, etc.)
in the stack.
(ii) Load PC with the beginning address of an ISR and start to execute it.
(iii) Finish ISR when the return instruction is executed.
(iv) Return to the point in the interrupted program where execution was
interrupted.
Fig. 5.7 Transfer of control from main memory to ISR
Interrupts and stack memory Stack is a special memory organization that

operates on the last-in, first-out (LIFO) principle. The data stored recently is
retrieved first. Similarly, data stored first in the stack are read last. Stack is a
temporary storage memory in the RAM area. It is basically administered by a
special register called stack pointer (SP). SP register always contains the address
of the top of the stack (ToS). Storing a data in the stack memory pointed to by the
stack pointer is called push operation. Reading a data from the stack is called pop
operation.
Stack is used by the interrupt system of the microprocessor for implementing
the subroutine call and return mechanism, passing parameters to subroutines, etc.
When the transfer of control takes place from the interrupted program to the ISR,
the program counter content is stored in the stack, because after the execution of
the ISR, the control must return to the program counter content. To facilitate this
control transfer, the stack pointer must be properly initialized to a physically available
memory with sufficient memory range. In the 8085, the stack memory grows towards
lower addresses and so, the stack pointer must be initialized with the highest memory
address allotted for the stack operation.
The stack can be accessed by the instructions PUSH and POP. The ISRs should
not disturb the return address stored by the processor in the stack. So, the ISRs
should have equal number of PUSH and POP instructions. This condition ensures
that the return address stored in the stack is retrieved properly by the processor.
5.10 INTERRUPT SOURCES AND VECTOR ADDRESSES IN 8085

Intel 8085 supports both software and hardware interrupts. Software interrupts
are in the form of instructions; hardware interrupts are applied as signals from
external devices.
5.10.1 Software Interrupts

The Intel 8085 instruction set includes eight software interrupt instructions
called Restart (RST) instructions. These are one-byte instructions that make the
processor execute a subroutine at predefined locations. The eight software interrupt
instructions and their interrupt vector addresses are given in Table 5.3
Table 5.3 Software interrupts and their vector addresses
Instruction Machine hex code Interrupt vector address
RST0 C7 0000H
RST 1 CF 0008H
RST 2 D7 001 OH
RST 3 DF 0018H
RST 4 E7 0020H
RST 5 EF 0028H
RST 6 F7 0030H
RST 7 FF 0038H
The software instructions can be treated as CALL instructions with default call
locations. The concept of priority does not apply to software interrupts as they are
inserted into the program as instructions by the programmer and executed by the
processor when the respective program lines are read.
5.10.2 Hardware Interrupts and Priorities

Intel 8085 has five hardware interrupts—INTR, RST 5.5, RST 6.6, RST 7.5, and
Trap. The details of the five interrupts are given in Table 5.4. Five pins of the 8085
are reserved for these five hardware interrupts. All the five interrupts are active
high signals. This means that to apply an interrupt, a logic 1 or high-level signal
should be applied at these pins. The processor checks the voltage on these pins
after the execution of every instruction. If the signal level on any of these five pins
is at logic 1 and the corresponding interrupt is not masked, the processor suspends
the current program and executes the corresponding ISR. RST 7.5 interrupt alone
is edge-triggered. This means that a transition from logic 0 to logic 1 is treated as
an interrupt input on this line. The rising edge interrupt can be applied at any time
and this sets a flip-flop inside the processor. The processor checks this flip flop
while checking the signal level on the other hardware interrupts.
Table 5.4 Hardware interrupts of 8085
Interrupt vector Maskable or

Interrupt Edge- or level-triggered Priority
address non-maskable
Trap 0024H Non-maskable Level-triggered 1

RST 7.5 003CH Maskable Rising edge-triggered 2
RST 6.5 0034H Maskable Level-triggered 3
RST 5.5 002CH Maskable Level-triggered 4

Decided by
INTR Maskable Level-triggered 5
hardware
The interrupt vector addresses for the hardware interrupts are given in Table
5.4. It can be seen that the four interrupts Trap, RST 7.5, RST 6.5, and RST 5.5
have fixed interrupt vector addresses. However, INTR does not have a fixed
interrupt vector address, since Intel has designed the INTR interrupt in a different
manner. When the INTR interrupt sent by an external device is recognized by the
processor, it gives an active low interrupt acknowledgement (INTA) signal. Upon
receiving this active low signal, the peripheral device that issued the INTR signal
should now place the machine code of the RST instruction to be executed by the
processor on the data bus of the processor. So the processor after issuing low
INTA signal, reads the instruction available on the data bus and places it in the
instruction register for decoding and executing.
Interrupt priority decides which interrupt must be serviced when more than one
interrupt is sensed by the processor. As there are five interrupts, it is possible that
more than one interrupt signal will be applied to the processor by the peripheral
devices. The interrupt priority indicates the order in which the interrupts must be
serviced. From Table 5.4, it can be seen that Trap is the highest priority interrupt,
followed by RST 7.5, RST 6.5, and RST 5.5. INTR has the least priority.
In addition to priorities, Intel has provided a feature using which a programmer
can suppress the hardware interrupts. This can be done by masking the interrupts.
TRAP is the only NMI; the other four interrupts can be masked.
METHODS OF DATA TRANSFER AND INTERRUPT STRUCTURE IN 8085 1 69
5.11 MASKING OF INTERRUPTS

Masking can be done for the four hardware interrupts RST 7.5, RST 6.5,
RST 5.5, and INTR. The masking of 8085 interrupts is done at different levels.
Figure 5.8 shows the organization of hardware interrupts in the 8085. The figure
clearly shows that TRAP is an NMI. RST 7.5 interrupt alone has a flip-flop to
recognize its edge transition. The masking of interrupts can be done using SIM
instruction. In addition, a separate interrupt enable flip-flop is available to mask or
allow the interrupts. Figure 5.8 is explained in detail by the following five points.
(i) The maskable interrupts are, by default, masked by the Reset signal. So no
interrupt is recognized by the hardware reset.
(ii) The interrupts can be enabled by the execution of the EI instruction. So to
enable the interrupts after resetting the processor, the EI instruction must be
used.
(iii) The three RST interrupts can be selectively masked by loading the
appropriate word in the accumulator and executing the SIM instruction.
This is called software masking.
(iv) All the maskable interrupts are disabled whenever an interrupt is recognized.
So, it is necessary to execute the EI instruction every time the interrupts are
recognized and serviced by the processor.
(v) All the maskable interrupts can be disabled by executing the DI instruction.
I
I
Fig. 5.8 Interrupt structure of Intel 8085

This instruction resets an interrupt enable flip-flop in the processor and

the interrupts are disabled. To enable interrupts, EI instruction has to be
executed.
5.11. 1 SIM Instruction

The SIM instruction is used to mask or unmask the restart (RST) hardware
interrupts. The SIM instruction when executed reads the contents of the accumulator
and accordingly masks or unmasks the interrupts. So the SIM instruction must be
executed after storing the appropriate control word in the accumulator. The format
of the control word to be stored in the accumulator before executing the SIM
instruction is shown in Table 5.5.
Table 5.5 Accumulator bit pattern for SIM instruction
Bit position D7 D6 D5 D4 D3 D2 D1 DO
Name SOD SDE X R7.5 MSE M7.5 M6.5 M5.5
Explanation Serial Serial Not Reset Mask set Set to Set to Set to
data data used RST 7.5 enable— 1 to 1 to 1 to
to be enable— flip-flop Set to 1 mask mask mask
sent set to to mask RST RST RST
1 for interrupts 7.5 6.5 5.5
sending
The least significant three bits D2-D0 are used to individually mask the
three RST interrupts, as shown in Table 5.5. These bits are made 0 to unmask
the interrupts and 1 to mask the interrupts. In addition, a master control is also
provided in the D3 bit. This bit must also be set to 1 to make the least significant
three bits meaningful. Otherwise, the data in the least significant three bits are
ignored by the processor.
As already discussed, the RST 7.5 is an edge-triggered interrupt and a separate
flip-flop is used to recognize it. This flip-flop can be reset, thereby ignoring the
RST 7.5 interrupt. This is done by making the D4 bit 1.
In addition to masking interrupts, the SIM instruction has another function. It
can send serial data on the SOD line of the processor. The data to be sent is placed
in the MSB of the accumulator and the serial data output is enabled by making the
D6 bit 1.
5.11. 2 RIM Instruction

The RIM instruction is used to read the status of the interrupt mask bits. When
the RIM instruction is executed, the accumulator is loaded with the current status
of the interrupt masks and the pending interrupts. The format and meaning of the
data stored in the accumulator after execution of the RIM instruction is shown in
Table 5.6.
The least significant three bits of the accumulatorafterexecuting RIM instruction
indicate whether the RST hardware interrupts are masked. The presence of the bit
1 indicates that the corresponding interrupt is masked.
Table 5.6 Accumulator bit pattern after execution of RIM instruction
Bit D7 D6 D5 D4 D3 D2 D1 DO
position
Name SID 17.5 16.5 15.5 IE M7.5 M6.5 M5.5

Explanation Serial Set to 1 Set to 1 Set to 1 Set to Set to 1 Set to 1 Set to 1
input if RST if RST if RST 1 if if RST if RST if RST
data 7.5 is 6.5 is 5.5 is interrupts 7.5 is 6.5 is 5.5 is
in the pending pending pending are masked masked masked
SID enabled
pin
All the hardware interrupts can be masked by executing the DI instruction. To

check whether the interrupts are enabled or disabled, the programmer can check
the D3 bit of the accumulator after executing the RIM instruction. If the D3 bit is
set to 1, it means that the interrupts are enabled. The bits D4-D6 indicate whether
there are any RST interrupts pending. Logic 1 on these bits indicates that the
corresponding interrupts are pending.
In addition to reading the interrupt mask, the RIM instruction is also used to
read the serial data on the SID pin of the processor. The data on the SID pin is
stored in the MSB of the accumulator after execution of the RIM instruction.
Example:
Write the assembly language program lines to enable all the interrupts in the 8085
after reset.
After reset, all the interrupts are disabled as shown in Fig. 5.8. So, the EI
instruction must be executed. To enable all RST interrupts, the corresponding bits
in the accumulator pattern must be 0 and the Mask Set Enable bit must be 1 before
executing the SIM instruction.
EI ; Enable Interrupts.
MVI A, 00001000B ; Unmask the interrupts.
SIM ; Set the mask and unmask using SIM instruction.
5.12 TIMING OF INTERRUPTS

The interrupts are sensed by the processor one cycle before the end of execution
of each instruction. An interrupt signal must be applied long enough for it to be
recognized. The longest instruction of the 8085 takes 18 clock periods. So, the
interrupt signal must be applied for at least 17.5 clock periods. This decides the
minimum pulse width for the interrupt signals.
The maximum pulse width for the interrupt signals is decided by the condition
that the interrupt signal must not be recognized once again. This is under the
control of the programmer. Once an interrupt is recognized, all interrupts are
disabled. The re-enabling of interrupts is done by executing the instruction El.
So, the maximum duration for the interrupts is decided by the execution of the
El instruction. The interrupt signal must be removed before the El instruction is
executed so that it will not be recognized once again.
Any other interrupt issued to the microprocessor will be recognized once the
EI instruction is executed. If the programmer has written the EI instruction at
the start of the ISR, the microprocessor can be interrupted once again before the
completion of the ISR.
5.13 INTERFACING OF INTR INTERRUPT WITH 8085

INTR interrupt requires additional hardware for selecting the interrupt vector
address. This section explains how the hardware interrupt INTR is executed and
how the interrupt vector address is selected for the processor. Figure 5.9 shows the
interfacing of the INTR interrupt. When an external peripheral device issues an
INTR request to the 8085, the processor after sensing the INTR interrupt, issues an
active low INTA signal. It then reads the instruction available on the data bus and
places it in the instruction register for decoding and executing. The hardware in
Fig. 5.9 shows the instruction RST 7 with the machine code EF being given to the
data bus when low INTA signal is given out by the processor. So, upon receiving
the opcode EF, the processor calls the subroutine at the address 0038H.
+5V
Fig. 5.9 Hardware for INTR interrupts

POINTS TO REMEMBER
• Different data transfer schemes are available for data transfer between two processors
or between a processor and an I/O device.
• The different data transfer schemes are programmed data transfer and DMA, polled and
interrupt-driven, and serial and parallel data transfer.
• Various serial port standards such as RS-232, RS-485, IEEE488, and GPIB are used for
data transfer in different applications.
• Interrupts are an important mechanism available in the processors to temporarily stop
current program execution and execute a program of higher priority.
• Interrupt vector addresses and the source, priorities, and timing of interrupts are very
important to program and understand the operation of interrupts in a processor.
• Interrupts can be either hardware generated and random, or software generated and
programmed.
• The processor can be interrupted before the completion of an interrupt service
routine (ISR) if the program has executed the EI instruction. This enables nested ISR
execution.
KEYTERMS :
DMA It is a special method of data transfer between I/O devices and memory without the
need of processor for data transfer.
I/O-mapped I/O scheme This scheme uses special control lines and different address
space for accessing I/O devices. The processor needs separate instructions for I/O-mapped
I/O access.
Interrupt priorities The sequence or order in which the interrupts are sensed by the
microprocessor. This order decides which ISR will be executed first, when more than one
interrupt is applied simultaneously to the processor.
Interrupt service routine The routine executed by the processor upon sensing an
interrupt signal is called interrupt service routine.
Interrupt vector address It is the location to which program control is transferred, upon
receipt of an interrupt.
Interrupt-driven I/O scheme This scheme uses a special signal from the I/O devices to
initiate a data transfer by the processor.
Memory-mapped I/O scheme This scheme uses the same instructions and hardware
used for memory accesses, for accessing I/O devices.
Parallel data transfer It is the method in which all the bits of a word are transmitted
simultaneously.
Polled I/O transfer This method uses a software routine to access and transfer data
between processor and I/O devices.
RIM It is an 8085 instruction to read the status of the interrupt masks and pending
interrupts.
Serial data transfer It is the method of transferring a single bit at a time over a
transmission line.
SIM It is an 8085 instruction to mask or unmask the hardware interrupts.
REVIEW QUESTIONS"
1. Explain memory-mapped I/O.

2. What is I/O-mapped I/O?
3. Compare memory-mapped I/O with peripheral-mapped I/O.
4. What are the various schemes of data transfer?
5. Discuss interrupt-driven data transfer scheme.
6. Explain DMA method of data transfer.
7. If the speed of the I/O devices is lesser than that of the processor, what type of data
transfer scheme can be used?
8. What are the advantages of serial data transfer?
9. Compare synchronous and asynchronous modes of data transfer.
10. Explain the RS-232 method of serial data transfer.
11. Design and explain a scheme to interrupt the 8085 using the INTR signal.
12. List the interrupt sources for the 8085 processor and list their priorities.
13. Indicate all the pins of the 8085 through which the processor can be interrupted. In
respect of each of these pins, describe how the processor obtains the starting address
of the interrupt service routine.
14. What is meant by ‘priority of interrupts’? Explain the operation of the interrupts
structure of the 8085, with the help of a circuit diagram.
15. Distinguish between (i) vectored and non-vectored interrupt, (ii) maskable and non
maskable interrupt, (iii) software and hardware interrupt.
16. Explain interrupt-driven I/O technique. How does the 8085 respond to the INTR
interrupt?
17. What is the location for the RST 5.5 interrupt service routine?
18. What are the non-vectored interrupts of the 8085?
THINK AND ANSWER f
1. What can be done to make the 8085 microprocessor start executing the instructions at
the address 003CH?
2. What are the ways to identify the device that has interrupted the processor in a
microprocessor-based system?
CHAPTER 6 |
INTERFACING MEMORY AND

I/O DEVICES WITH 8085
LEARNING OUTCOMES
• Basics of RAM and ROM/EPROM
• Interfacing of RAM with the 8085
• Interfacing of ROM/EPROM with the 8085
• Absolute address decoding and partial address decoding
• l/O-mapped I/O and memory-mapped I/O schemes
• Interfacing input/output devices with the 8085 using I/O-mapped I/O scheme
• Interfacing input/output devices with the 8085 using memory-mapped I/O scheme
6.1 INTRODUCTION
The programs and data that are executed by the microprocessor have to be stored
in ROM/EPROM and RAM, which are basically semiconductor memory chips.
The programs and data that are stored in ROM/EPROM are not erased even
when the power supply to the chip is removed. Hence, ROM/EPROM is called
non-volatile memory. It can be used to store permanent programs (e.g., monitor
program, also known as system start-up program) and data (e.g., look-up table),
which are necessary in microprocessor-based systems. The difference between
ROM and EPROM is that a ROM chip can be programmed only once, whereas an
EPROM chip can be programmed many times after erasing the previously stored
contents. The contents of an EPROM chip can be erased by passing UV rays for a
few minutes through the quartz window situated at the top of the chip.
In a RAM, stored programs and data are erased when the power supply to the
chip is removed. Hence, RAM is called volatile memory. Programs and data that
are modified often are stored in the RAM. Examples of such programs and data
include programs written during software development for a microprocessor-based
system, programs written when one is learning assembly language programming,
and data entered while testing these programs. RAM is also used to store data
that are variable in nature. For example, data to be used by the programmer for
arithmetic and logic operations can be stored in the RAM. Data can only be read
from a ROM or EPROM, whereas it can be written into and read from a RAM.
Input and output devices, which are interfaced to the 8085, are essential in any
microprocessor-based system. They can be interfaced using two schemes—I/O-
mapped I/O and memory-mapped I/O. In the I/O-mapped I/O scheme, the I/O
devices are treated differently from memory. In the memory-mapped I/O scheme,
each I/O device is assumed to be a memory location.
This chapter discusses the interfacing of the following:
(i) EPROM and RAM chips with the 8085—using address decoders made of
either logic gates or decoder ICs (e.g., 74LS138)
(ii) I/O devices with the 8085—using I/O-mapped I/O and memory-mapped
I/O schemes
6.2 INTERFACING MEMORY CHIPS WITH 8085

Since the 8085 has 16 address lines (A0-A15), a maximum of 64 KB (= 216 bytes)
of memory locations can be interfaced with it. The memory address space of the
8085 (i.e., the range of memory addresses that can be addressed by the 8085)
takes values from 0000H to FFFFH when represented in hexadecimal form.
While executing a program, the 8085 microprocessor needs to access the memory
regularly to read instructions and data and to store results. The 8085 initiates a
set of signals such as IO/M, RD, and WR when it wants to read from and write
into memory. Similarly, each memory chip has signals such as CE or CS (chip
enable or chip select), OE or RD (output enable or read), and WE or WR (write
enable or write) associated with it. The memory interfacing circuit must match the
processor’s signals to the memory chip’s signals.
6.2.1 Generation of Control Signals (MEMR and MEMW) for Memory

When the 8085 wants to read from and write into memory, it activates the IO/M,
RD, and WR signals as shown in Table 6.1.
Table 6.1 Status of IO/M, RD, and WR signals during memory read and write operations
IO/M RD WR Operation
0 0 1 The 8085 reads data from memory (RAM or EPROM).

0 10 The 8085 writes data into memory (RAM).
Using the IO/M, RD, and WR signals, two control signals MEMR (memory
read) and MEMW (memory write) are generated, such that only MEMR is in logic
0 when data is being read from the RAM or EPROM and only MEMW is in logic
0 when data is being written into the RAM. Figure 6.1 shows the circuit used for
generation of MEMR and MEMW signals.
Table 6.2 shows the relation between the 8085’s control signals and the memory
chip’s control signals.
Fig. 6.1 Circuit used to generate MEMR and MEMW signals

INTERFACING MEMORY AND I/O DEVICES WITH 8085 177
Table 6.2 Relation between 8085's control signals and memory chip’s control signals
IO/M RD WR MEMR MEMW Operation

0 0 1 0 1 Memory read
0 1 0 1 0 Memory write
1 X* X* 1 1 I/O read or write
Note: * denotes don’t care condition—either 0 or 1.
When the IO/M signal is high, both memory control signals are deactivated
(i.e., in logic high state) irrespective of the status of the RD and WR signals. This
is shown in the third row of Table 6.2.
6.2.2 Interfacing EPROM Chip with 8085

Figure 6.2 shows the pin
diagram of an 8 KB EPROM Vpp 1 ^cc
memory chip (IC 2764). A12 2 P

There are 8192 memory A7 3 NC
locations (8 KB = 8 x 210 or A6 4 25 A8
8192 bytes) in IC 2764 and
A5 5 24 A9
in each location, one byte of
A4 6 23 A11
information (instructions or
data) is stored. There are 13 A3 7 OE
2764 8K * 8 EPROM
address lines (since 213 bytes = A2 8 21 A10
8 KB) A0-A12 in the IC 2764, A1 9 20 CE
where AO is the least significant AO 10 19 D7
bit of the address and A12 is
DO 11 18 D6 I
the most significant bit. They
D1 12 17 D5
are used to select memory
D2 □ 13
locations in the IC during 16 D4
the memory read operation. vvss □ 14 15 D3

Table 6.3 shows the memory
locations selected for various
Fig. 6.2 Pin diagram of IC 2764
combinations of binary values
in the address lines.
The following steps are executed by the 8085 to read the content of a memory
location in an EPROM chip:
(i) The address of the memory location from where data has to be read is placed
in the address lines of the EPROM.
(ii) CE signal is made low (i.e., logic 0).
(iii) OE signal is made low (i.e., logic 0).
After this, the data in the selected memory location is available in the data lines
(D0-D7) of the EPROM. The 8085 reads the data in the data lines.
Among the 64K addresses that the 8085 can handle, some are assigned
to EPROM chips, while others are assigned to RAM chips depending on the
requirements of the 8085-based system. Normally, a block of addresses starting

at 0000H is assigned to an EPROM chip in 8085-based systems that contain
the monitor program. This is done because after the 8085 is reset, it fetches and
executes the instruction that is stored in the address 0000H. (Note: The program
counter points to 0000H after the 8085 is reset.)
Table 6.3 Memory locations selected for various values of address inputs in IC 2764
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AO CE MemorYlocatlon

selected
00000000000000 Is* location
00000000000010 2nd location
00000000000100 3rd location
1 1 1 1 1 1 1 1 1 1 1 1 0 0 8191s' location
1 1 1 1 1 1 1 1 1 1 1 1 1 0 8192nd location
XXXXXXXXXXXXX1 (Chip is not
selected)
Let us now discuss the interfacing of EPROM chip with the 8085 using logic
gates and 74LS138 decoder IC.
6.2.2.11nterfacing EPROM Chip with 8085 using Logic Gates
While the 8085 has 16 address lines, the number of address lines in an EPROM chip
depends on the storage capacity of the chip. For example, an 8K x 8 EPROM chip
has only 13 address lines. The lower-order address lines (A0-A12) of the 8085 are
connected to the address lines (A0-A12) of the 8K x 8 EPROM chip. The remaining
address lines (A13-A15) of the 8085 are connected to the address decoder, the
output of which is given to the chip enable pin (CE) of the EPROM. The memory
read signal (MEMR) from the 8085 is given to the OE pin of the EPROM. The data
lines (D0-D7) of both the 8085 and the EPROM are connected together.
The following examples illustrate this concept.
Example 6.1:
Interface an IC 2764 with the 8085 using NAND gate address decoder such that
the address range allocated to the chip is 0000H-1FFFH.
Solution:
The 13 address lines (A0-A12) of IC 2764 are connected to the corresponding 13
address lines (A0-A12) of the 8085. The remaining address lines (A13-A15) of
the 8085 are connected to the address decoder formed using logic gates, the output
of which is connected to the CE pin of IC 2764. To design the address decoder,
the address range allocated to the chip (0000H-1FFFH) is first written in binary
form as shown in the Table 6.4. Since IC 2764 has 13 address lines, a partition
is made between A0-A12 and the remaining address lines A 13-Al5, which are
shown in bold.
INTERFACING MEMORY AND I/O DEVICES WITH 8085 179 •
Table 6.4 Interfacing IC 2764 with 8085 (Example 6.1)
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0001H
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1FFEH
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1FFFH
From Table 6.4, it is observed that for the addresses 0000H to 1FFFH, the value
in the address lines A15, A14, and A13 is 0. Therefore, the address decoder can
be designed using a NAND gate and three inverters to produce a NAND output
of 0 whenever the value in the address lines A15, A14, and A13 is 0. (Note: In a
NAND gate, the output is 0 only when all inputs are 1.) The output of the NAND
gate is connected to the CE (chip enable) pin of IC 2764 so that the chip is enabled
whenever the 8085 places an address allocated to the EPROM chip in the address
bus. This is shown in Fig. 6.3. It is assumed that the circuit for de-multiplexing
lower order address bus and data bus and the circuit for generating MEMR are
available separately and these are not shown in Fig. 6.3.
Fig. 6.3 Interfacing IC 2764 with the 8085 (Example 6.1)
Example 6.2:
Interface a 27128 EPROM (16K x 8 bits or 16KB) IC with the 8085 using a
NAND gate address decoder such that the starting address assigned to the chip is
C000H.
Solution:
Since 16KB = 214 bytes, the number of address lines in IC 27128 is 14 (A0-A13).
The 14 address lines of IC 27128 are connected to the corresponding 14 address
lines (A0-A13) of the 8085. The remaining address lines (A 14 and A15) of the
8085 are connected to the address decoder formed using logic gates. The output of
the address decoder is connected to the CE pin of IC 27128.
The starting address assigned to the chip is C000H. To find the ending address,
add the hexadecimal value of a 14-bit binary number with all bits equal to 1 to the
starting address of the chip. (Note: The binary number is assumed to be 14 bits
long as the number of address lines in the IC is 14.)
14-bit binary number with all bits equal to 1----------► 11 1111 1111 1111
V I I I
Corresponding hexadecimal number-------------------- > 3 F F F
The ending address of the chip is C000H + 3FFFH = FFFFH
The addresses C000H to FFFFH are written in binary form in Table 6.5. Since IC
27128 has 14 address lines a partition is made between A0-A13 and the remaining
address lines A14 and A15, which are shown in bold.
Table 6.5 Interfacing IC 27128 with 8085 (Example 6.2)
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C000H
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 C001H
• •
• •
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 FFFEH
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFH
From Table 6.5, it is observed that for the addresses C000H to FFFFH, the value in
the address lines A15 and A14 is 1. Therefore, an address decoder can be designed
using a NAND gate to produce a NAND output of 0 only when A15 = A14=1.
The designed circuit is shown in Fig. 6.4.
Fig. 6.4 Interfacing IC 27128 with the 8085 (Example 6.2)

6.2.2.2 Interfacing EPROM Chip with 8085 using Decoder IC

When a number of memory chips having similar capacity have to be interfaced
with the 8085, decoder ICs such as 74LS138 with active low outputs are useful. A
single 74LS138 IC can be used to interface up to eight memory chips (RAM and
EPROM) with the 8085. Table 6.6 shows the truth table of this IC.
Table 6.6 Truth table of 74LS138 decoder IC
inputs Outputs
Enable inputs Select inputs
G1 G2A G2B c B A Y7 Y6 Y5 Y4 Y3 Y2 Y1 YO
X 1 X X X X 1 1 1 1 1 1 1 1
X X 1 X X X 1 1 1 1 1 1 1 1
0 X X X X X 1 1 1 1 1 1 1 1
1 0 0 0 0 0 1 1 1 1 1 1 1 0
1 0 0 0 0 1 1 1 1 1 1 1 0 1
1 0 0 0 1 0 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 0 0 1 1 1 0 1 1 1 1
1 0 0 1 0 1 1 1 0 1 1 1 1 1
1 0 0 1 1 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 1 1 1 1 1 1 1
Figure 6.5 shows the logic diagram of IC 74LS138.

IC 74LS138 has three select inputs—A (LSB), B, and C (MSB) and three
enable inputs—Gl, G2A, and G2B. In Table 6.6, G2 represents two active low
enable signals—G2A and G2B. Only
when Gl = 1 and G2A = G2B = 0, the
IC functions as a decoder. Under this
condition, depending on the value of
the select inputs, one of the outputs
will be low (i.e., logic 0). If Gl = 0,
G2A = 1, or G2B = 1, all outputs are 1,
independent of the value of the select
inputs. As we have seen earlier, X
represents don’t care condition. This
means that the value can be either 0 or
1. The following example illustrates
the interfacing of EPROM chips with
the 8085 using 74LS138 decoder IC.
Fig. 6.5 Logic diagram of the IC 74LS138
decoder IC
Example 6.3:
Interface two 2764 ICs (8K x 8 EPROM) with the 8085 using 74LS138 decoder
IC, such that the starting addresses assigned to the chips are 0000H and 8000H,
respectively.
Solution:
Since 8K x 8 EPROM has 13 address lines (A0-A12), the ending address of the
chips is obtained by adding 1FFFH (i.e., the binary number with thirteen Is) with
the starting address assigned to each chip. Therefore, the ending addresses are
1FFFH and 9FFFH, respectively. The addresses assigned to the two chips are
shown in binary form in Table 6.7. The set of addresses assigned to different
memory chips in a system is called a memory address map.
Table 6.7 Addresses assigned to EPROM chips 1 and 2 (Example 6.3)—Address Map
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AO Address

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0001H
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1FFFH
(for chip
1)
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000H
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8001H
1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 9FFFH
(for chip
2)
For EPROM chip 1 (with address range 0000H-1FFFH), the address lines
A15, A14, and Al3 carry 0. For EPROM chip 2 (with address range 8000H-
9FFFH), the address line A15 carries 1 and A14 and A13 carry 0. The address
lines A15, A14, and A13 of the 8085 are connected to the IC inputs C, B, and A,
respectively. The decoder is enabled by connecting G1 to Vcc and G2A and G2B
to ground.
Figure 6.6 shows the interfacing of the two EPROM chips with the 8085,
using 74LS138 IC. The Y0 output of the decoder is connected to the chip enable
(CE) pin of the EPROM chip 1 whose address range is 0000H-1FFFH. When
these addresses are placed in the address bus by the 8085, the select inputs of
the decoder take the value C = B = A = 0. Hence Y0 output of the decoder goes
low, selecting EPROM chip 1. The output Y4 of the decoder is connected to the
chip enable pin of EPROM chip 2. When the 8085 places any of the addresses
from 8000H to 9FFFH on the address bus, the select inputs of the decoder take
the values C = 1 and B = A = 0. The Y4 output of the decoder goes low, thereby
selecting EPROM chip 2.
6.2.3 Interfacing RAM Chip with 8085

Each RAM chip has a set of address lines, data lines, and control lines. The number
of address lines depends on the storage capacity of the RAM chip. For example, an
8K x 8 RAM chip has 13 address lines (A0-A12) and eight data lines (D0-D7). It
also has read (OE), write (WE), and chip select (CE1, CE2) signals. Table 6.8 lists
the functions of the control signals in the IC 6264.
Table 6.8 Truth table for the IC 6264 (8K x 8) RAM chip
CE1 CE2 OE WE Operation
0 1 0 1 Data is read from RAM.

0 1 1 0 Data is stored in RAM.
1 X X X RAM is not selected (no read or write operation).
X 0 X X RAM is not selected (no read or write operation)
Figure 6.7 shows the diagram of IC 6264 (8K x 8) RAM chip. Here Vcc and
Vss represent the power supply and ground terminals, respectively.
6.2.3.1 Interfacing RAM Chip with 8085 using Logic Gates
The interfacing of a RAM chip with the 8085 is the same as that of an EPROM
chip with the 8085, except that one more signal MEMW is used. This signal is
connected to the WE pin of the RAM chip. The following example illustrates this
concept.
Example 6.4:
Interface a 6264 IC (8K x 8 RAM) with the 8085 using a NAND gate decoder
such that the starting address assigned to the chip is 4000H,
Solution:
NC
The 6264 IC has 13 address
A12 WE
lines (A0-A12), since 8 KB =
213 bytes. The ending address A7 CE2
of the chip is 5FFFH (since A6 A8

4000H + 1FFFH = 5FFFH). A5 A9
When the addresses 4000H to A11
A4
5FFFH are written in binary
A3 OE
form, the values in the lines
A2 A10
A15, A14, and A13 are 0, 1,
and 0, respectively. The NAND A1 CET
gate decoder is designed such AO D7

that when the lines A15 and DO D6
A13 carry 0 and A14 carries 1,
D1 D5
the output of the NAND gate is
D2 D4
0. The NAND gate output is in
turn connected to the CE1 pin D3
of the RAM chip. A NAND

output of 0 selects the RAM Fig. 6.7 IC 6264 (8K * 8) RAM chip
chip for read or write operation,
since CE2 is already 1 because of its connection to +5V. Figure 6.8 shows the
interfacing of IC 6264 with the 8085.
Fig. 6.8 Interfacing 6264 IC with the 8085 (Example 6.4)
6.2.3.2 Interfacing RAM Chip using 74LS138 Decoder

The function of the 74LS138 decoder has been discussed in Section 6.2.2.2. The
following example illustrates the use of 74LS138 for interfacing RAM chips with
the 8085.
Example 6.5:
Interface two 6116 (2K x 8 RAM) ICs with the 8085 using 74LS138 decoder such
that the starting addresses assigned to them are 8000H and 9000H, respectively.
Solution:
The 6116 IC has 11 address lines (A0-A10) since 2KB = 211 bytes. The ending
addresses of 6116 chip 1 and 6116 chip 2 are 87FFH and 97FFH, respectively.
Table 6.9 shows the binary form of the addresses 8000H to 87FFH and 9000H to
97FFH assigned to the chips.
Figure 6.9 shows the interfacing of these RAM chips with the 8085. The
address lines A0-A10 of the 8085 are connected to the address lines A0-A10 of
the RAM chip. Since the 74LS138 decoder has three select inputs C, B, and A,
three address lines of the 8085 that have a specific value for a particular RAM chip
must be connected to them. From Table 6.9 we can see that A13 = A12 = A11 =
0 for the addresses assigned to RAM chip 1 and that A13 = 0, A12 = 1, and Al 1
= 0 for the addresses assigned to RAM chip 2. The remaining address lines of the
8085, whose values are constant for the address ranges assigned to the two RAM
chips, are connected to the enable inputs of the decoder. Since A15 = l and A14
= 0 they are connected to the decoder’s active high and active low enable inputs,
respectively.
Fig. 6.9 Interfacing two 6116 RAM chips using IC 74LS138 (Example 6.5)
When the 8085 places any of the addresses between 8000H and 87FFH in the
address bus, the select inputs C, B, and A of the decoder are all 0. The Y0 output
of the decoder also becomes 0, selecting RAM chip 1. When the 8085 places any
of the addresses between 9000H and 97FFH in the address bus, the select inputs C,
B, and A of the decoder are 0, 1, and 0, respectively. The Y2 output of the decoder
becomes 0, selecting RAM chip 2.
Table 6.9 Addresses assigned to the two 6116 RAM chips (Example 6.5)
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AO Address

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000H
1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 87FFH
(RAM
chip 1)
1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 9000H
1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 97FFH
(RAM
chip 2)
6.2.4 Partial Address Decoding for Memory

In the methods discussed so far, the entire address bus of the 8085 (A0-A15) is
used to interface memory chips with the 8085. This technique is called absolute
address decoding. Using the absolute address decoding method, a maximum of
64 KB of memory can be interfaced with the 8085. There is another method
known as partial address decoding, which is used when the amount of memory
needed in an 8085-based system is lesser than 64 KB (8 KB, 16 KB, or 32 KB). In
this method, all the address lines of the 8085 are not used in interfacing with the
memory. The lower-order address lines of the 8085 are connected to the address
lines in the memory chip, as in the absolute address decoding method. A few
higher-order address lines of the 8085 are connected to the chip enable signal of
the memory through the address decoder; other higher-order address lines are left
unconnected. Hence, the size of the address decoder is reduced. Sometimes, the
amount of hardware (number of gates) needed for interfacing is also reduced in
the partial address decoding method. However, in this system the same memory
chip is assigned multiple address ranges; any of these address ranges can be used
to access the chip. The following example illustrates this concept.
Example 6.6:
While interfacing a 16K x 8 EPROM chip and a 16K x 8 RAM chip with the 8085,
both having only one active low chip enable signal (CE), the address line A15 of
the 8085 is directly connected to the CE of the EPROM chip. The same line is
connected to the CE of the RAM chip through an inverter. Find the address ranges
that are assigned to each chip.
Solution:
Since 16K = 214, the number of address lines in a 16K x 8 EPROM chip and a
16K x 8 RAM chip is 14 (A0-A13). The 14 address lines A0-A13 of the 8085
are connected to the corresponding 14 address lines (A0-A13) of the 16K x 8
EPROM chip and the 16K x 8 RAM chip. Among the remaining address lines
(A14 and A15) in the 8085, A14 is left unconnected and only A15 is used to select
the memory chips as given in the problem.
Since the address line A15 of the 8085 is directly connected to the CE pin
of the EPROM chip and to the CE pin of the RAM chip through an inverter,
the EPROM chip is selected when A15 = 0 and the RAM chip is selected when
A15 = 1. This is irrespective of the value in the address line A14 (either 0 or 1), as
it is left unconnected. The addresses assigned to the two chips can be found using
this concept.
Address range assigned to 16K x 8 EPROM chip
(i) When A 14 = 0
A15 A14 A13 A12 All A10 A9 A8 A7 A6 A5 A4 A3 A2 Al AO
0000000000000000
= 0000H (lowest address)
0 0 11111111111111
= 3FFFH (highest address)
(ii) When A14 = 1
A15 A14A13 A12A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Al A0
0100000000000000
0 111111111111111
= 7FFFH (highest address)
So address ranges 0000H-3FFFH and 4000H-7FFFH can be used to access
the EPROM chip.
Address range assigned to 16K x 8 RAM chip
(i) When A14 = 0
A15 A14A13 A12A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Al A0
1000000000000000
10 11111111111111
= BFFFH (highest address)
(ii)When A14 = 1
A15 A14A13 A12 All A10 A9 A8 A7 A6 A5 A4 A3 A2 Al A0
1 100000000000000
= C000H (lowest address)
1111111111111111
= FFFFH (highest address)
So the address ranges 8000H-BFFFH and C000H-FFFFH can be used to
access the RAM chip.
6.3 I/O- OR PERIPHERAL-MAPPED I/O INTERFACING

In this method, the I/O devices are treated differently from memory chips. The
control signals I/O read (IOR) and I/O write (IOW), which are derived from the
IO/M, RD, and WR signals of the 8085, are used to activate input and output
devices, respectively. The IN instruction is used to access input devices and the
OUT instruction to access output devices. Each I/O device is identified by a

unique 8-bit address assigned to it. Since the control signals used to access input
devices and output devices are different, and all I/O devices use 8-bit addresses,
a maximum of 256 (= 28) input devices and 256 output devices can be interfaced
with the 8085.
For interfacing input devices such as DIP switches, 74LS244 ICs (unidirectional
octal tri-state buffers) are required; for interfacing output devices such as LEDs,
74LS373 ICs (octal latches) are required. Tri-state buffers are used to interface
input devices with the 8085 since the data from the input devices has to be placed
in the data bus, only when the 8085 executes the IN instruction. Latches are used
to interface output devices with the 8085 since the data that is to be sent to the
output devices will be available in the data bus, only for a few microseconds when
the OUT instruction is being executed. The latch captures that data and holds it
until new data is received from the 8085. The circuit for generating the IOR and
IOW control signals is shown in Fig. 6.10.
Table 6.10 shows the values in the IO/M, RD, and WR Lines of the 8085, and
the corresponding values in the signals IOR and IOW, during the I/O read and I/O
write operations.
Table 6.10 Status of IOR and IOW signals in 8085
IO/M RD WR IOR IOW Operation
1 0 1 0 1 I/O read operation

1 1 0 1 0 I/O write operation
0 X X 1 1 Memory read or write
The following examples illustrate the peripheral-mapped I/O technique.
Example 6.7:
Interface an 8-bit DIP switch with the 8085 such that the address assigned to the
DIP switch is FOH.
Solution:
The instruction IN FOH is used to get the data from the DIP switch and store it in
the accumulator. The steps involved in the execution of the instruction IN FOH are
as follows.
(i) The address in the IN instruction, which is FOH in this case, is placed in the
address lines A0-A7 and a copy of it in the address lines A8-A15.
(ii) The IOR signal is activated (i.e., IOR = 0), which makes the selected input
device to place its data in the data bus.
(iii) The data in the data bus is read and stored in the accumulator.
Figure 6.11 shows the interfacing of a DIP switch so as to assign the address
FOH to it.
When the address FOH is placed in the address bus (A0-A7) during the execution
of IN FOH by the 8085, the value in the address lines A0-A7 is as follows:
A7 A6 A5 A4 A3 A2 Al AO
1 1 1 1 0 0 0 0 = FOH
These address lines are connected to a NAND gate address decoder such
that the output of the NAND gate is 0 under this condition. The output of the
NAND gate decoder is ORed with the IOR signal and the output of the OR gate
is connected to the enable inputs 1G and 2G of the 74LS244. When the NAND
gate decoder’s output and IOR are both 0, the 74LS244 is enabled and data from
the DIP switch is placed in the data bus of the 8085. The 8085 reads that data and
places it in the accumulator. Thus, the data from the DIP switch is transferred to
the accumulator.
Example 6.8:
Interface a set of eight LEDs in common cathode configuration with the 8085 such
that the address assigned to them is F8H.
Solution:
The instruction OUT F8H is used to send the data in the accumulator to the LEDs.
The steps involved in the execution of the instruction OUT F8H are as follows:
(i) The address F8H is placed in the address lines A0-A7 and a copy of it in
the lines A8-A15.
(ii) The data in the accumulator is placed in the data bus (D0-D7).
(iii) The IOW signal (i.e., IOW = 0) is activated for some duration, during which
the data gets stored in the external latch.
Figure 6.12 shows the interfacing of a set of eight LEDs with the 8085.
Fig. 6.12 Interfacing set of eight LEDs with the 8085 using 74LS373 (Example 6.8)
When the address F8H is placed in the address bus (A0-A7) during the
execution of the instruction OUT F8H by the 8085, the value in the address lines
A0-A7 is as follows:
A7 A6 A5 A4 A3 A2 Al A0
1 1 1 1 1 0 0 0 = F8H
When the instruction OUT F8H is executed by the 8085, the address F8H is
placed in the address bus (A0-A7), the data in the accumulator is placed in the
data bus (D0-D7), and the IOW signal is activated. This causes the activation of
the clock input (CLK) of the 74LS373 (i.e., it is made 1) since both AND gates
produce logic 1 output. This latches the value in the data lines.
6.4 MEMORY-MAPPED I/O INTERFACING

In memory-mapped I/O, each input device or output device is treated as if it is a
memory location. The control signals MEMR and MEMW are used to activate input
devices and output devices, respectively. Each input or output device is identified by
a unique 16-bit address, similar to the 16-bit memory address assigned to a memory
location. All the memory related instructions used to read data from memory such
as LDA 2000H, LDAX B, MOV A, M, etc., can be used to access input devices; all
the memory related instructions used to write data into memory such as STA 3000H,
STAX D, MOV M, A, etc., can be used to send data to output devices. Since the I/O
devices use some of the memory address space of the 8085, the maximum memory
capacity (EPROM and RAM capacity) is lesser than 64KB in this method. The
following examples illustrate the memory-mapped I/O technique.
Example 6.9:
Interface an 8-bit DIP switch with the 8085 using logic gates such that the address
assigned to it is FOFOH.
Solution:
Since a 16-bit address has to be assigned to a DIP switch, the memory-mapped
VO technique must be used. Using LDA FOFOH instruction, the data from the
8-bit DIP switch can be transferred to the accumulator. The steps involved in the
execution of the instruction LDA FOFOH are as follows:
(i) The address FOFOH is placed in the address lines A0-A15.
(ii) The MEMR signal is made low (i.e. logic 0) for some time.
(iii) The data in the data bus is read and stored in the accumulator.
Figure 6.13 shows the interfacing of an 8-bit DIP switch with the 8085 so as to
assign the address FOFOH to it.
Fig. 6.13 Interfacing 8-bit DIP switch with 8085
When the 8085 executes the instruction LDA FOFOH, it places the address
FOFOH in the address lines A0-A15 as follows:
A15 A14A13 A12 All A10 A9 A8 A7 A6 A5 A4 A3 A2 Al A0
1111000011110000
= FOFOH
Since 8-input AND gate ICs such as CD4068B are available, these address
lines are connected to two 8-input AND gates so that the outputs of both the AND
gates are 1 when the address FOFOH is placed in the address bus (A0-A15) by
the 8085. These two outputs along with the inverted MEMR signal are given to a
NAND gate so that its output becomes 0 when MEMR = 0, thereby enabling the
buffer (74LS244). The data from the DIP switch is placed in the 8085’s data bus.
The 8085 reads the data from the data bus and stores it in the accumulator.
Example 6.10:
Interface a seven-segment LED display with common cathode connection to the
8085 so as to assign the address FFF3H to it.
Solution:
Since a 16-bit address has to be assigned to the seven-segment LED display,
memory-mapped I/O technique must be used. Using instructions such as STA
FFF3H, the data in the accumulator can be sent to the LED to display a particular
digit. The steps involved in the execution of the instruction STA FFF3H are as
follows:
(i) The address FFF3H is placed in the address lines A0-A15.
(ii) The contents of the accumulator are placed in the data bus (D0-D7).
(iii) The MEMW signal is activated (i.e., made 0) for some duration.
Figure 6.14 shows the interfacing of a seven-segment LED with the 8085 using
memory-mapped I/O scheme.
Fig. 6.14 Interfacing seven-segment LED with 8085

When the 8085 executes the instruction STA FFF3H, the address FFF3H is
placed in the address lines A0-A15 as follows:
A15 A14A13 A12 All A10 A9 A8 A7 A6 A5 A4 A3 A2 Al AO
1111111111110 0 11
=FFF3H
The address lines are connected to the inputs of two AND gates such that
both the AND gates produce 1 at their output for the address FFF3H. These two
outputs along with the inverted MEMW signal from the 8085 are given as inputs
to another AND gate whose output is connected to the CLK input of the latch.
Therefore, when the 8085 executes the instruction STA FFF3H, the clock input
of the 74LS374 becomes l.The data in the data bus, which is the content of the
accumulator, is stored in the latch.
6.5 PARTIAL ADDRESS DECODING FOR I/O DEVICES

In the methods discussed so far, the entire address bus of the 8085 (i.e., A0-A7 in
I/O-mapped I/O scheme and A0-A15 in memory-mapped I/O scheme) is used to
interface I/O devices with the processor. This technique is called absolute address
decoding. Partial address decoding can also be used for I/O devices using the
concept discussed in Section 6.2.4 for memory devices. In this method, there is
more than one address for a single I/O device; any one among them can be used to
access it. Here, the address lines that are not used in the interfacing are considered
to be in don’t care condition (i.e., either 0 or 1). Depending on how the remaining
address lines are connected to the address decoder, the addresses assigned to the
VO device are found. The following example illustrates the partial address
decoding technique.
Example 6.11:
While interfacing an 8-bit DIP switch with the 8085 using I/O-mapped I/O scheme
as given in Example 6.7, if the address lines A7 and A6 of 8085 are not connected
to the NAND gate shown in Fig. 6.11, find the addresses assigned to the DIP
switch.
Solution:
Since A7 and A6 of the 8085 are not connected to the address decoder, they can
take any value. There are four combinations of values that A7 and A6 can take,
based on which four different addresses are obtained for the same DIP switch.
(i) When A7 = A6 = 0
A7 A6 A5 A4 A3 A2 Al A0
0 0 1 1 0 0 0 0 = 30H
(ii) When A7 = 0 and A6 = 1
A7 A6 A5 A4 A3 A2 Al A0
0 1 1 1 0 0 0 0 = 70H
(iii) When A7 = 1 and A6 = 0
A7 A6 A5 A4 A3 A2 Al A0
1 0 1 1 0 0 0 0 = BOH
(iv) When A7 = A6 = 1
A7 A6 A5 A4 A3 A2 Al AO
1 1 1 1 0 0 0 0 = FOH
Therefore, the DIP switch can be accessed using any of these four addresses.
POINTS TO REMEMBER1
• Any microprocessor-based system needs memory and VO ports to be interfaced with it.
Systems based on the 8085 need at least two memory chips—one RAM and one ROM.
Memory address maps are important and should differentiate the addresses for different
memory chips in a system.
• The memory can be interfaced with the processor using address lines, data lines, and
control signals from the decoder and the processor. The control signals IO/M, RD, and
WR play an important role in interfacing.
• Address decoding is necessary to select a particular memory chip in a system. Chip
selection uses higher-order address lines and can be done in two ways—absolute
address decoding and partial address decoding.
• Input/output devices also follow the same interfacing concepts as memory chips.
• Input/output devices such as switches and LEDs can be interfaced to the 8085 using
either memory-mapped or peripheral-mapped interfacing techniques.
KEY TERMS
Absolute address decoding It is a decoding technique in which all the bits of the address
bus are used for accessing and decoding the addresses of memory chips.
EPROM It is a semiconductor memory in which the data can be programmed many
times. Data erasure can be done by the user. There are two types of erasures—one by
electrical means and the other using ultraviolet rays.
Memory-mapped I/O It is the technique by which input/output devices are addressed
using 16-bit memory addresses and accessed like memory locations, using memory access
instructions such as LDA, STA, etc.
MEMR and MEMW These are control signals for reading from and writing into
memory. Generally, these two control signals are generated using the IO/M, RD, and WR
signals of the 8085.
Partial address decoding It is a decoding technique in which all address bits are not used
for decoding. In particular, some higher-order bits are not used in decoding and selection
of memory locations.
Peripheral- or I/O-mapped I/O It is the technique by which input/output devices are
addressed using 8-bit I/O addresses and accessed using IN and OUT instructions.
RAM It is a semiconductor memory in which both read and write operations are possible.
IC 6264 is an 8K RAM chip with 8-bit words.
REVIEW QUESTIONS
1. What is the function of RAM and ROM chips in a microprocessor-based system?

2. What are the differences between RAM and ROM?
3. How much memory, in terms of bytes, can be interfaced with the 8085? Why?
4. What are the logic levels in the IO/M, RD, and WR lines of the 8085 during the
different machine cycles?
5. Draw the circuit used to generate the MEMR and MEMW signals in the 8085.
6. What is the function of CE and OE signals in an EPROM chip?
7. What is the function of CE, OE, and WE signals in a RAM chip?
8. What are the criteria to be considered before interfacing memory to a processor?
9. Differentiate between partial decoding and absolute decoding for device (memory and
I/O) selection. Give an example.
10. What are the differences between memory-mapped I/O and I/O-mapped I/O
schemes?
11. Calculate the maximum number of input/output devices that can be interfaced with an
8085-based system that needs 16 KB of memory while using
(i) I/O-mapped I/O scheme
(ii) Memory-mapped I/O scheme.
12. Why is a tri-state buffer required to interface an input device with the 8085?
13. Why is a latch required to interface an output device with the 8085?
14. What is the function of 1G and 2G signals in IC 74LS244?
15. What is the function of CLK and OC signals in IC 74LS373?
NUMERICAL/DESIGN-BASED EXERCISE
1. What is the output of a three-input NAND gate for the following inputs?
(i) 0, 0, 1
(ii) 1, 1,0
(iii) 1, 1, 1
2. In a 74LS138 decoder that is in enabled condition, which output of the decoder goes
low under the following conditions?
(i) C= l,B = 0, A = 1
(ii) C = 0, B = l,A = 0
3. Interface an 8K x 8 EPROM chip and a 32K x 8 RAM chip with the 8085, using
logic gates, such that the starting addresses assigned to them are 4000H and 8000H,
respectively.
4. Interface two 8K x 8 RAM chips and a 8K x 8 EPROM chip with the 8085, using
a 74LS138 decoder, such that the starting addresses assigned to them are 6000H,
8000H, and 0000H, respectively.
5. In an 8085-based system, only an 8K x 8 EPROM chip and an 8K x 8 RAM chip
are needed. Interface these chips with the 8085 using only one inverter, such that the
starting addresses assigned to the EPROM and RAM chips are 0000H and 8000H,
respectively.
6. In the previous question, find the address ranges that are assigned to the 8K x 8
EPROM chip and the 8K x 8 RAM chip.
7. Interface an 8-bit DIP switch and a seven-segment LED display with common anode
connection with the 8085, such that the addresses assigned to them are FEH and FAH,
respectively. Write a program to read the data from the DIP switch and send it to the
seven-segment display repeatedly.
8. Interface an 8-bit DIP switch and a set of eight LEDs in common anode configuration
with the 8085 such that the address assigned to both of them is FFH. Write a program
to read the data from the DIP switch and send it to the LEDs repeatedly. (Hint: Use the
same address decoder for both the DIP switch and the LEDs.)
9. Interface an 8-bit DIP switch and a seven-segment LED display with common cathode
connection with the 8085, such that the address assigned to both of them is FFH. Write
a program to read the unpacked BCD number from the DIP switch and display the
number in the seven-segment display repeatedly. (Hint: Use look-up table technique
to find the corresponding seven-segment code of the number that is read from the DIP
switch.)
10. Interface an 8-bit DIP switch and a set of eight LEDs in common anode connection
with the 8085, such that the address assigned to both is FF00H. Write a program to
read the data from the DIP switch and send it to the LEDs repeatedly.
11. Interface two input ports with addresses FFFOH and FFF1H and two output ports
with addresses 9000H and 9001H using memory-mapped I/O technique. Indicate the
assumptions made (if any).
THINK AND ANSWER ’
1. In the following ICs, calculate the number of address and data lines.
(i) 16K x 8 EPROM IC
(ii) 32K x 8 RAM IC
(iii) 16K x 4 RAM IC
2. How many 8K x 4 RAM ICs are needed to construct a 32K x 8 RAM IC?
3. The memory address of the last location of a 1 KB memory chip is FBFFH. What is the
address of the first location?
4. What is the maximum number of I/O devices that can be interfaced with the 8085 in the
I/O-mapped I/O technique?
5. While interfacing an 8-bit DIP switch with the 8085 using 74LS244, the following
circuit is used. What are the addresses that can be used to access the DIP switch?
" t|X" i. iiwr iiJ-'.nKr r ' 'L/C»)>jjijijliI|iiW W" -F C["VIFT‘U.1

CHAPTER 7
FEATURES AND INTERFACING OF

PROGRAMMABLE DEVICES FOR
8085-BASED SYSTEMS
LEARNING OUTCOMES
• Architecture, features, and operation of IC 8255
• Interfacing of switches, seven-segment displays, A/D converters, D/A converters, stepper
motors, and intelligent LCD displays using the 8255
• Features of keyboard/display interface IC 8279 and interfacing of matrix keyboard and
multiplexed LED display
• Architecture, details, interfacing, and programming of timer IC 8253
• Fundamentals and definitions of serial ports
• Features, details, interfacing, and programming of USART 8251
• Architecture and details of programmable interrupt controller IC 8259
♦ Features and operation of DMA controller 8237
7.1 INTEL 8255 PROGRAMMABLE PERIPHERAL INTERFACE

The Intel 8085 microprocessor can transfer data between external devices such
as input and output devices through ports. Normally, a register can act as an I/O
port. However, using a separate register and configuring it for input and output
operations is both difficult and tedious. So Intel has designed a separate IC,
the 8255, with the objective of interfacing input and output devices with Intel
microprocessors. The 8255 is used with a wide range of I/O cards that plug into
an available slot in a PC.
The 8255 programmable peripheral interface (PPI) is a very popular and
versatile I/O chip that can be easily programmed to function in several different
configurations. This chip can perform digital input and output (DIO) from the
processor in a preprogrammed manner. The common applications of the 8255
with the 8085 include sensing a switch, controlling movement by use of motors,
and detecting a position.
7.1.1 Features of 8255

Each 8255 has three 8-bit TTL-compatible registers or ports, which allow
programmers to control digital outputs, inputs, or a combination of both. The
common features of Intel 8255 IC are as follows:
(i) It has three 8-bit ports A, B, and C connected to the output pins.
(ii) Port C is divided into two groups, port C upper (PCU) and port C lower
(PCL), of 4 bits each. Each of them can be programmed independently or
as 4-bit ports, for input and output operations.
(iii) All the ports can be programmed for simple I/O or handshake I/O in the
input/output mode.
(iv) Each port C bit can be set/reset individually in bit set/reset mode.
(v) The bits of port A and PCU are grouped as group A (GA).
(vi) The bits of port B and PCL are grouped as group B (GB).
7.1.2 Block Diagram of Intel 8255

The block diagram of the 8255 (Fig. 7.1) shows ports A, B, and C and groups A
and B. In addition, there is another register called control register. The contents
written into the control register decide the operating modes of the three parallel
ports.
Fig. 7.1 Internal block diagram of 8255 PPI
To identify the four registers, the 8255

uses two address lines—AO and Al. These Table 7.1 Address lines and register
lines get their signals from the 8085 processor selection in the 8255
address bus. The identification of the registers
based on AO and Al is given in Table 7.1. A1 AO Register selected
The pin details of the 8255 are given in 0 0 Port A
Fig. 7.2. The three ports of the 8255 need
0 1 Port B
eight lines each. So 24 pins are allotted for the
ports and these lines are connected to external 1 0 Port C
input or output devices. D0-D7 are the lines 1 1 Control register
FEATURES AND INTERFACING OF PROGRAMMABLE DEVICES FOR 8085-BASED SYSTEMS 199
required for interfacing the 8255

with the processor. These data PA3 □1 \------- / 40 □ PA4
PA2 □2 39 □ PA5
lines are connected to the data
bus of the processor. Eight lines PA1 E3 38 □ PA6
or pins are remaining. Out of PAO E4 37 □ PA7
these eight lines, two lines—AO RD E5 36 □ WR

s
and Al—are allotted for selecting CS E6 35 □ RESET
one of the four registers available GND E7 34 □ DO
in the 8255. The control signals A1 E8 33 □ D1
for reading from and writing AO E9 32 □ D2

8255
into these registers are the active PC7 E 10 Dual in-line package 31 □ D3
low RD and WR signals. These PC6 E 11 30 □ D4
signals are obtained from the PC5 E 12 29 □ D5

processor’s control signals. The PC4 E 13 28 □ D6
chip is selected by activating the PCO E 14 27 □ D7
active low chip select (CS) signal. PC1 E 15 26 □ vcc
This signal is obtained from the PC2 E 16 25 □ PB7
decoder, which decodes the 8085 PC3 E 17 24 □ PB6
address lines and identifies the E 18 23 □ PB5
8255 address range. A common E 19 22 □ PB4
reset signal such as the RESET E 20 21 □ PB3
OUT of the 8085 processor can
be applied to reset the 8255. Fig. 7.2 Pin details of IC 8255
7.1.3 Operating Modes and Control Words of 8255

The function of each port in the 8255 is software-programmed by the programmer.
This is done by writing a control word in its control register. The control word
contains information such as mode, bit set, bit reset, etc., which initialize the
functional configuration of the 8255.
Figure 7.3 shows the basic operating modes of the 8255. There are two
configurations in the 8255—I/O mode and bit set/reset mode (BSR mode). In I/O
mode, there are three modes for the ports. The programmer can select a particular
Fig. 7.3 Operating modes of the 8255

operating mode using commands and control words. The three ports of the 8255
are grouped as groups A and B. Groups A and B accept commands from the read/
write control logic, receive control words from the internal data bus, and issue
commands to the associated ports.
The chip has to be programmed to configure its operation, before using it. The
configuration is done by the control word, which tells the 8255 whether the ports
are input, output, bidirectional, or strobed.
7.1.3.1 I/O Mode Control Word Format

The control word format for the I/O configuration is given in Table 7.2.
Table 7.2 I/O control word format of the 8255
D7 D6 D5 D4 D3 D2 D1 DO
1 Group A Port A Port C upper Group B Port B Port C
(1 = Mode select Direction Direction Mode Direction lower
I/O) 00—mode 0 select select select select Direction
01—mode 1 1—input 1—input 0—mode 0 1—input select
IX—mode 2 0—output 0—output 1—mode 1 0—output 1—input
0—output
The MSB D7 is set to 1 to indicate that the chip is configured in I/O mode. Bits
D6 and D5 are used to select the operating mode of group A. There are three basic
modes of operation for group A:
(i) Mode 0—Basic I/O (bits D6 and D5 are both 0)—Ports A and B and the
higher-order four bits of port C can be operated as inputs or outputs. This
mode uses simple I/O operation; no interrupts are used. The outputs written
into the ports are latched and available at any time. Inputs available at the
port pins are buffered through port latches.
(ii) Mode 1—Strobed or handshake input/output (bits D6 and D5 are 0 and
1, respectively)—Port A is configured in mode 1, while port C is used for
handshaking and control of data transfer in Port A. Input and output data are
latched.
(iii) Mode 2—Bidirectional I/O mode (bits D6 and D5 are 1 and X, respectively)—
Port A is bidirectional (i.e., both input and output), while port C is used for
handshaking. Port B cannot be programmed to this mode.
Bit D4 is used to select the direction of data flow in the port A bits, i.e., it
decides whether the port A pins are input pins (D4 = 1) or output pins (D4 = 0).
Bit D3 is used to decide whether the four higher-order bits of port C are used for
input (D3 = 1) or output (D3 = 0).
Bit D2 of the control word is used to select the mode for group B. As discussed
earlier, only two operating modes—mode 0 and mode 1—are possible for group B.
(i) Mode 0—Basic I/O is selected if bit D2 is 0. This mode uses simple I/O
operation and no interrupts are used.
(ii ) Mode 1—Strobed or handshake I/O is selected if bit D2 is 1. Port B is
configured in mode 1, while port C lower bits are used for handshaking and
control of data transfer.
Bit DI is used to select the data direction for port B pins. If it is 0, port B pins
are configured as output pins; if it is 1, they are configured as input pins.
Bit DO is used to select the data direction for the lower-order pins of port C. DO
= 0 for output; DO = 1 for input.
7.1.3.2 BSR Mode Control Word Format
The control word format for BSR configuration is given in Table 7.3.
Table 7.3 BSR control word format of the 8255
D7 D6 D5 D4 D3 D2 D1 DO
0 X X X B2 Bl BO Bit set/reset
(0 = BSR (Don’t (Don’t (Don’t 1 = set
Bit Select bits—select one of 8 bits
mode) care) care) care) 0 = reset
of port C
In BSR mode, any of the eight bits of port C can be set or reset using a single
control word written into the control register. This feature helps the programmer
to control the port C pin outputs individually. It is also used in mode 1 and mode
2 I/O operations, wherein the individual ports of port C can be controlled by the
programmer to indicate the status and control.
7.1.3.3 I/O Mode 1 Operation
Mode 1 configuration of the 8255 provides a means for transferring I/O data to or
from a specified port, in conjunction with strobes or handshaking signals. In mode
1, ports A and B use the lines on port C to generate or accept these handshaking
signals. In mode 1, the ports are divided into two groups—A and B. Each group
contains one 8-bit port and one 4-bit control/data port. The 8-bit data port is either
port A or port B; it can be either input or output. Both inputs and outputs are
latched. The 4-bit control port, either PCU or PCL, can be used to control and
decide the status of the 8-bit ports A and B. Figure 7.4 shows the operation of
handshake signals for input operation using the 8255.
The sequence of operations for inputting data from an input device to the
microprocessor through the 8255 is as follows:
Step 1 The input device places data in the data lines, i.e., port A or port B. This
is communicated to the 8255 by making the strobe input pin (STB) low. STB is an
active low signal applied through PC4 or PC2.
Step 2 The 8255 acknowledges the receipt of the data to the input device by
making the input buffer full pin (IBF) high. This also indicates that the data has
been latched into the input port.
Step 3 The 8255 then makes the interrupt request line (INTR) high and applies
an interrupt to the processor. This signal is applied only when the interrupt enable
signal (INTE) is high. INTE for port A is controlled by the set/reset bit PC4
Fig. 7.4 Control and handshake signal for input operation in mode 1
and INTE for port B is controlled by the set/reset bit PC2. PC2 and PC4 can be
controlled using BSR mode.
Step 4 In the interrupt service routine, the processor reads the data from the
corresponding input port. Reading from the port is done by selecting the 8255 port
and applying the active low RD signal.
Step 5 During read operation, the RD signal is low. When the RD signal goes
low, INTR signal is reset. IBF is reset by the rising edge of the RD input.
Thus, mode 1 allows an input device to request service from the CPU by simply
sending its data to the port and activating the active low STB signal.
The handshake signals used for output operation in mode 1 are OBF, ACK, and
INTR. The sequence of operations that take place for outputting data from the
processor to an output device is as follows:
Step 1 The processor initiates the data transmission by writing the data to be
transmitted to the corresponding port of the 8255. This is done by sending the port
address to the 8255, placing the data on the data lines, and activating the active
low WR signal.
Step 2 To transfer the data to the output device, the 8255 makes the active low
output buffer full signal (OBF) low to indicate that the CPU has written data to
be given to the specified device. The OBF flip-flop is set by the rising edge of the
WR input.
Step 3 The data available on the output port pins are then read by the output
device. After receiving data from the port pins, the output device acknowledges
the receipt by making ACK low. ACK is an active low input signal to the 8255
from the peripheral device, indicating that it has accepted a data. The OBF output
signal of the 8255 is reset by the ACK input going low.
Step 4 The 8255 now informs the processor that data has been transferred to the
output device, by making the interrupt request line (INTR) high. A high on this
output can be used to interrupt the CPU when an output device has accepted data
transmitted by the CPU. INTR is set when ACK, OBF, and INTE are all 1.
Step 5 In the interrupt service routine, the processor writes the next data to be
transmitted to the output device into the output port of the 8255. INTR signal is
reset by the falling edge of WR.
Figure 7.5 shows the operation of handshake signals for output operation in
mode 1.
Fig. 7.5 Control and handshake signals for output operation in mode 1
7.1.3.4 I/O Mode 2 Operation

In mode 2, data is transmitted and received via port A pins (bidirectional I/O).
Pon A is used as a bidirectional port, while port C is used for handshaking signals.
Interrupt generation and enable/disable functions are also available through port C
pins. Port B can be configured to be in mode 0 or 1, but not in mode 2. Both inputs
and outputs are latched. The 5-bit control port (port C) is used for controlling and
deciding the status of the 8-bit, bidirectional port (port A). The basic control signal
transmission and data transfer operation in mode 2 is shown in Fig. 7.6.
The input and output operation of the 8255 in mode 2 is similar to its operation
in mode 1, except that port A is a bidirectional port. For output operation, as
in mode 1, data transfer is initiated by the processor by making the active low
signal OBF low. This indicates that the processor has written data into the output
port. The output device, after reading the data, will give an acknowledgement
by making the active low acknowledge signal (ACK) low. The processor is then
interrupted by the 8255 to indicate that the output data port is ready for the next
data output. Here, the interrupt can be applied to the processor only if INTE 1
flip-flop associated with OBF and controlled by PC4 has already been set by the
processor.
The input operation is also similar to mode 1 operation. Here, the data transfer
is initiated by the input device by placing the data on the port pins. Then an active
low control signal STB is given to the 8255 by the input device. The 8255 now
latches up the data to its port and then gives an active high signal IBF to the
input device. The 8255 then issues an interrupt signal to the processor to indicate
that data is available for read operation. Here, the interrupt can be applied to the
processor only if INTE 2 flip-flop associated with IBF and controlled by PC4 has
already been set by the processor.
7.1.4 Programming Examples

Example 7.1:
Configure the ports of the 8255 as given: port A = input, port B = output, PCU =
output, PCL = input. Assume that the four registers of the 8255 PPI are located
at 40H-43H. The control word format for the given conditions is given in Table
7.4.
Table 7.4 Control word bit pattern (Example 7.1)
D7 D6 D5 D4 D3 D2 D1 DO
Port C lower
1 Group A Port A Port C upper Group B Port B ' t 1
(1 = I/O) mode—00 input--1 output—0 mode—0 output—0
The control word from this figure is 10010001B, i.e., 91H. The following
program instructions will configure the control word of the 8255.
MVI A, 91H ; Load the control word in the accumulator.
OUT 43H ; Transfer it to the control register of the 8255.
Example 7.2:
Find the data direction and modes of operation of the 8255 ports if the control
word written into it is AOH.
The control word bit pattern is given in Table 7.5.
Table 7.5 Control word bit pattern (Example 7.2)
D7 D6 D5 D4 D3 D2 D1 DO
1 0 1 0 0 0 0 0
Port A Port C upper Port B Port C lower
1 Group A Group B
direction direction direction direction
(1 = 1/0) mode—1 mode—0
0—output 0—output 0—output 0—output
The direction and modes of all ports are as follows:

Port A—output port in mode 1 Port C upper—output port
Port B—output port in mode 0 Port C lower—output port
7.2 INTERFACING SWITCHES AND LEDS

In this section, we discuss the interfacing of four switches and four LEDs to the
8085 through the 8255. Data is obtained from the switches and displayed using
the LEDs.
The 8255 is interfaced with the 8085, with the 8255 ports connected to the
switches and LEDs. A latch is used to de-multiplex the lower-order address bus
and the data bus. Since the 8085 uses 8-bit addresses for the I/O devices, the
lower-order address bus is enough to address them. While accessing I/O devices,
the higher-order bus has the same address as the lower-order address bus. So the
address decoder uses the higher-order address bus. IO/M signal is also used in
decoding and selecting the 8255. The 8255 needs two address lines AO and Al to
select one of its four registers. The RD and WR signals from the 8085 processor
are connected to the corresponding control signals of the 8255.
The four switches are assumed to be interfaced to the lower-order four bits of
port A of the 8255. The switch connection is such that when it is open it connects
logic 0, i.e., 0 V to the port and when it is closed it connects logic 1, i.e., 5 V.
These connections ensure that the port is not damaged and also that it does not
source over-current. This ensures safe operation of the ports and switches.
Figure 7.7 shows the interfacing of LEDs to the ports through an inverter driver.
When logic 1 is given out on the port pin, it is inverted by the inverter and ground
(logic 0) is connected to the cathode of the LED. This forward biases the LED
and it glows. This connection ensures that the port pin does not source enormous
amounts of current and also that the current required for LED illumination is from
the supply and driver IC.
Fig. 7.7 Interfacing switches and LEDs with the 8085 through the 8255
The software part consists of initializing the 8255 for port A input and port B
output operation. All the ports are initialized to mode 0. So the control word 90H
shown in Table 7.6 is used.
Table 7.6 Control word bit pattern for interfacing LEDs and switches
D7 D6 D5 D4 D3 D2 D1 DO
1 Group A Port A Port C upper Group B Port B Port C lower

(1=1/0) mode—00 input—1 output—0 mode—0 output—0 output—0
The program for initializing the 8255 and outputting data available in port A to
port B is given in Table 7.7.
Table 7.7 Program for initializing the 8255 and performing I/O operation
Mnemonics Comments
MVI A, 90H ; Load the control word to the accumulator.

OUT 43H ; Move it to the control register of the 8255.
IN 40H ; Get data from port A to the accumulator.
OUT41H ; Move it to port B.
Example 7.3:
Design a system (both software and hardware) that will cause four LEDs to flash
alternately when a push button is pressed. Use the 8255 PPI. The interfacing
scheme for a switch and the four LEDs is shown in Fig. 7.8. The LSB of port A is
used for the switch interface and the least significant four bits of port C are used
for the LED interface.
Fig. 7.8 Interfacing LEDs with the 8085 through the 8255 (Example 7.3)
Program:
The program for interfacing LEDs with the 8085 using the 8255 is given in Table
7.8. The program checks the switch status and accordingly, makes the LEDs blink
alternately. The data to be given to port C for making alternate LEDs blink is
00001010 (OAH) and 00000101 (05H).
Table 7.8 Program for interfacing blinking LEDs with the 8085 using the 8255
Labels Mnemonics Comments
; Load the 8255 control word to configure port A as

MVI A, 90H
an input port and port C as an output port.
OUT CR ; Send it to the control register of the 8255.
LOOP: IN PA ; Read data from port A.
RAR ; Rotate right and check the LSB for a switch press.
JC LOOP ; If switch has not been pressed, jump to LOOP.
MVI A, OAH ; Load data to light alternate LEDs
OUT PC ; Send it to port C.
CALL ; Call the subroutine DELAY to produce a delay of
DELAY 0.1s.
MVI A, 05H ; Load data to light alternate LEDs
OUT PC ; Send it to Port C
CALL ; Call the subroutine DELAY to produce a delay of
DELAY 0.1s.
JMP LOOP ; Jump back to LOOP to check for switch press.
(Contd)
Table 7.8 Program for interfacing blinking LEDs with the 8085 using the 8255 (Contd)

Delay subroutine:
DELAY: LXI B, Count ; Load the value of Count in the BC register pair.
BACK: DCXB ; Decrement the BC register pair.
MOV A, B ; Move the content of B to the accumulator.
; Logically OR the content of the accumulator with
ORAC
the content of register C.
JNZ BACK ; If the result is not zero, jump to BACK.
RET ; If the result is zero, return to the main program.
De-bouncing of keys All mechanical such as push buttons, on/off switches,

and electromechanical relays have spring contacts. These spring contacts do not
allow the keys to completely turn on or off a contact instantaneously. The contacts
are ‘bouncy’ and oscillate, i.e., make and break several times before coming to
rest. The mechanical spring arrangement with low damping is responsible for
this oscillation, which occurs every time the contacts are turned on or off. The
waveform of a switch with contact bounce, from position 1 to 0, is shown in
Fig. 7.9.
Fig. 7.9 Contact bounce waveform
If such a switch is used for sensing by the input ports of a microprocessor,

there is a chance that the microprocessor will respond several times, i.e., input will
be sensed repeatedly even though the key is pressed only once. The bouncing of
the switch may last for several milliseconds. Since the microprocessor works at a
speed of a few microseconds, it senses the input several times.
The simplest hardware solution uses an RC time constant to suppress the
bounce. The circuit for this is shown in Fig. 7.10. The RC time constant has to be
larger than the switch bounce speed and is generally around 0.1 s. The capacitor
takes at least twice the time constant to change from one position to the other.
During this time, any change in the switch position is not transmitted beyond the
buffer. The buffer is used to make the transition from high-to-low and low-to-high
sharp.
The key bouncing problem can be solved by software methods also. The easiest
software method is to make the processor wait until the bouncing oscillation
settles down. This wait-and-see technique is implemented using software time
delays. When the voltage from the switch changes, an appropriate delay routine is
Fig. 7.10 Hardware implementation of key de-bouncing
executed and the value of the voltage on the switch line is checked again to make
sure the line has stopped bouncing. The delay is normally 10 ms, as the oscillations
settle down within that period in most switches.
7.3 INTERFACING SEVEN-SEGMENT DISPLAYS

Seven-segment light emitting diode displays are commonly used low-cost displays
and are easiest to interface with microprocessors. Seven-segment displays
consist of seven LED segments. The arrangement of the seven segments and the
appearance of the ten digits is shown in Fig. 7.11. Seven-segment displays are
available in a single dual in-line package (DIP). There is one pin for each segment
and these pins are named a to f; another LED is available for decimal point (dp).
In addition to these eight pins, seven-segment displays have one more pin for
power supply. Seven-segment displays come in two types—common anode and
common cathode.
Fig. 7.11 Arrangement of LEDs and appearance of digits in seven-segment displays
In common anode display the anodes of all segments are connected together.
So to illuminate a segment, the common anode is connected to the supply and the
corresponding segment input is connected to a low-level voltage or logic 0.
In common cathode display the cathodes of all the LEDs are connected together.
So to illuminate a segment, the corresponding segment input is connected to the
high-level voltage or logic 1 and the common cathode is connected to the ground.
This forward biases the LEDs and illuminates them.
Figure 7.12 shows the circuit required to drive a single seven-segment LED
display from 4-bit BCD output. The BCD to seven-segment display decoder
IC 7447 converts
the 4-bit BCD
code applied at
its input into the t
patterns required
to display the BCD inputs
BCD number. The

patterns generated
r
are active low
outputs, meaning
that the output
corresponding to
segments that are Fig. 7.12 Driver circuit for single seven-segment display
to be illuminated is
logic 0. So the common anode display is suitable for use with the 7447.
The complete circuit used for interfacing the seven-segment display, along
with the address bus decoder and latch, is given in Fig. 7.13.
Fig. 7.13 Complete circuit for interfacing single seven-segment display
Table 7.9 shows the instructions that can be used to display data in a seven-segment
display.
Two seven-segment displays can be connected to a single 8-bit port. One
7447 IC can be connected to the four lower-order bits and another 7447 can be
connected to the four higher-order bits of port A. So six seven-segment displays
can be connected to a single 8255 that has three parallel I/O ports. This results in
a more complicated circuit. The complexity of the circuit can be reduced by using
a technique called multiplexed display. By using multiplexed display, as many as
eight displays can be connected to the two ports. The multiplexed display concept
is discussed in Section 7.9.
Table 7.9 Program to display data in a seven-segment display
Mnemonics Comments
MVI A. control word ; Load the accumulator with the 8255 control word.
OUT control_register ; Output it to the control register of the 8255.
MVI A, data ; Load the accumulator with the data to be displayed.
OUT PORTA ; Output it to port A, where the display is connected.
7.4 TRAFFIC LIGHT CONTROL

Example 7.4:
Design a four-road junction traffic control light system. The traffic control
sequence is as follows:
(i) Allow traffic from the North to the other directions,

(ii) Allow traffic from the East to the other directions,
(iii) Allow traffic from the South to the other directions,
(iv) Allow traffic from the West to the other directions.
The traffic signal scheme for a four-road junction is shown in Fig. 7.14.
The red, yellow, and green signals have to be turned on in the proper sequence.
The sub-sequences to be followed are listed in Table 7.10, along with the 8255
port pins used to control these lights.
Instead of using LEDs, actual
lights at 230 V can be used in this
microprocessor-based system. The
circuit diagram for interfacing 230
V bulbs through relays is shown in
Fig. 7.15. In this example, the port
A and port B pins of the 8255 are
assumed to control the traffic lights.
The individual pins of these ports
are connected to the different red,
yellow, and green lights as shown
in Table 7.10. For example, the red
light facing the North direction is
connected to the port A pin PAO.
Fig. 7.14 Traffic control signal scheme for
Using the traffic sequence shown in
a four-road junction
the table, the data to be given to the
port pins is calculated and given in the last two columns of this table.
Source program:
The program given in Table 7.11 assumes that the 8255 IC is interfaced to the
microprocessor at the addresses 80H, 81H, 82H, and 83H. The data for the port
is available at the address 9000H. The port data for ports A and B are stored
consecutively in the memory locations starting at 9000H.
212
Table 7.10 T ra ffic sig n a l su b -se q u e n ce s fo r a fo u r-ro a d ju n ctio n

MICROPROCESSORS AND MICROCONTROLLERS
sides (yellow)
Fig. 7.15 Traffic light control interface diagram
Table 7.11 Program for traffic light control at a four-road junction
START: MVI A, 80H ; Initialize 8255, port A and port B

OUT 83H (CR) in output mode.
LOOP: MVI C, 08H ; Initialize a count for eight sequences.
LXI H, 9000H ; Initialize a pointer for output data.
NEXT: MOV A, M ; Get the data for one group.
OUT 80H (PA) ; Send it to port A.
INXH ; Point to the next data.
MOV A, M ; Get the data.
OUT81H(PB) ; Send it to port B.
CALL DELAY ; Wait for a predefined delay period.
INXH ; Point to the next data.
DCRC ; Reduce the sequence count.
JNZ NEXT ; If it is not zero, go to the next sequence.
JMP LOOP ; If it is zero, start the sequence again.
Delay subroutine:
DELAY: MVI B, COUNT1 ; Initialize register B with COUNT1.
(Contd)
Table 7.11 Program for traffic light control at a four-road junction (Contd)
LOOP2: LXI D, COUNT2 ; Initialize the DE register pair with

COUNT2.
LOOP1: DCXD ; Decrement the DE pair.
; Move the content of register D to the
MOV A, D
accumulator.
; Check whether the DE pair has become
ORAE
zero.
JNZ LOOP1 ; If it has not, jump to LOOP1.
DCRB ; If it has, decrement register B.
JNZ LOOP2 ; If it is not zero, loop again.
RET ; If it is zero, return from subroutine.
Note: The sequence shown in the table can be changed by the programmer to suit his/her
own design and traffic flow.
7.5 INTERFACING ANALOG-TO-DIGITAL CONVERTERS

The basic function of the analog-to-digital converter is to convert the input analog
voltage levels into corresponding discrete digital signals. ADC is essential in a
microprocessor-based system as the microprocessor can handle only digital data,
even though real-world signals are all in analog form only.
There are many types of ADC. The major ones are counter ramp type ADC,
dual-slope ADC, flash type ADC, and successive approximation type ADC. Each
type of ADC has its own advantages and disadvantages. Successive approximation
type ADC is the most commonly available ADC. This ADC has a fixed conversion
time for any analog input voltage level.
The specifications of the ADC are range of analog input voltage, number of
digital bits at the output, resolution, conversion time, and number of analog input
channels. The analog input voltage can be either unipolar or bipolar. Unipolar
means that the input voltage can have only one polarity (Example: 0 to +5 V, 0 to
+10 V). Bipolar means that the input voltage can range from one polarity to the
other (Example: -5V to +5V, -10 V to +10 V). Most ADC chips come with the
option of selecting one of these voltage ranges using the Vref input pins. ADC
chips are available for various output binary bits. ADCs are available with 8-, 10-,
12-, and 16-bit digital outputs. The number of bits decides the number of voltage
levels sensed. For example, an 8-bit ADC will have 28 = 256 possible levels. The
number of bits and the input voltage range decides the resolution. The resolution
of an ADC is defined as the smallest change in the input voltage that can be sensed
or detected at the output. The resolution can be mathematically defined as the
range of input voltage divided by the number of levels at the output. For example,
an ADC with the input voltage range of 0 to +5 V with eight bits at the output
will have a resolution of 5/256, i.e., approximately 19.5 mV. The conversion time
of ADCs is decided by the type of the ADC and the clock frequency used in the
converter circuits.
Some ADC chips come with the option of having more than one analog input.
One of the analog input channels is selected using select lines and an analog
multiplexer circuit. The ADC chips also have a sample and hold circuit. The
sample and hold circuit is used to maintain the analog input voltage constant when
the conversion is in progress.
The single-chip analog-to-digital converters available in the markets have
many options. The commonly available ADC chip family is ADC080X from
National Semiconductor. ADC 0800, ADC 0804, ADC 0808, and ADC 0816
are the common chips available in this family. ADC 0804 has one analog input
channel with 8-bit output. ADC 0808/0809 has eight analog inputs with three-bit
channel select lines and an 8-bit output. ADC 0816 has 16 analog input channels
with four select lines and 8-bit outputs.
This section discusses the operation and interfacing of ADC 0816 with the
8085 microprocessor through the 8255 PPI. ADC 0816 is an 8-bit successive
approximation type ADC chip with a built-in analog multiplexer, which can select
one of the 16 analog inputs for conversion into digital format. Select lines A, B,
C, and D are used to select one of the 16 analog inputs IN0-IN15. The analog to
digital conversion is started using the active high control signal Start Conversion
(SC). The conversion of the analog voltage on the input channel selected then takes
place based on the clock signal applied to the ADC chip. After the conversion is
over, the ADC chip issues an active high End of Conversion signal on the EOC
line. The digital output is then read from the data lines after issuing the output
enable signal to the ADC chip. The interfacing of ADC 0816 with the 8255 is
given in Fig. 7.16.
Fig. 7.16 Interfacing ADC 0816 with the 8255

The 8255 PPI is in turn interfaced with the 8085 as shown in Fig. 7.7. In the
interfacing diagram shown in Fig. 7.7, it can be noted that port A of the 8255 is
used to send data to the channel select lines and the related control signals. Port B
lines are used to get the resultant digital data from the ADC chip. The LSB of port
C is used to check the end of conversion signal. With this hardware arrangement,
the ADC chip can only be interfaced with the software polling method. For an
interrupt driven interface, the EOC signal can be connected to any interrupt input.
The analog inputs can be applied to the analog input pins of ADC 0816.
The software interfacing procedure follows the steps shown in the flowchart in
Fig. 7.17.
Fig. 7.17 Flowchart for ADC conversion software
The ADC conversion process is started after applying the analog input to
the channels. The conversion process is started by initializing the 8255 with the
control word. The control word is given in Table 7.12. Then the channel selection
and start of conversion are done simultaneously, as these two control bits are tied
together in the hardware. The start conversion command must be issued as a pulse
for a very short duration. Then the conversion takes place in the ADC chip, if it
is properly powered and clock pulses are given. After the conversion, the logic
high end-of-conversion signal is issued by the ADC chip. This is sensed by the
software. The data is then read from the data lines, after issuing the logic high
output enable signal.
Table 7.12 Control word bit pattern for ADC conversion
D7 D6 D5 D4 D3 D2 D1 DO
1 Group A Port A Port C upper Group B Port B Port C lower

(1=1/0) mode 00 output output mode 0 input input
1 0 0 0 0 0 1 1 = 83H
The program for the ADC conversion process is given in Table 7.13 as a
software routine. This routine assumes that the channel number to be converted is
available in the memory location named CH_NUM.
Table 7.13 Program for ADC conversion
ADCONVERT: MVI A, 83H ; Load the 8255 control word in the

accumulator.
OUT CONTROL REG ; Move it to the control register.
LDA CHNUM ; Load the channel number in the
accumulator.
ANI OFH ; Make the four higher-order bits zero.
MVI B, 10H ; Load register B with 10H (D4 = I) to issue
ALE/SC signal.
GRAB ; Combine with channel number (LSB).
OUT PORTA ; Send it to Port A.
NOP ; Wait.
NOP ; Wait.
MVI B, OFH ; Remove the ALE/SC signal by making it 0.
ANAB ; Combine with channel number (LSB).
OUT PORTA ; Send it to port A.
CHECK: IN PORTC ; Read port C to check for EOC.
RAR ; Rotate the contents of the accumulator to
bring EOC bit to the carry.
JNC CHECK ; If there is no EOC signal, repeat the process.
LDACHNUM ; If the EOC signal is received, load the
channel number in the accumulator.
MVI B, 20H ; Make OE signal high.
ORLB ; Combine with channel number (LSB).
IN PORTB ; Read the result data from port B.
STAADCJRES ; Store it in the memory location ADC RES.
RET ; Return from subroutine.
7.6 INTERFACING DIGITAL-TO-ANALOG CONVERTERS

Digital-to-analog converters are used to get a proportional analog voltage or
current for the digital data output by the microprocessor. The D-A converters are
essential in microprocessor-based systems as real-world applications operate with
analog data. There are two types of DAC—R-2R ladder network and weighted
resistor network. Many DAC chips are available in the market. The specifications
of the DAC chips are full-scale output voltage, number of binary input bits,
resolution, linearity, and settling time. DAC chips come with an option to choose
the maximum output voltage (5 V, 10 V, etc.) or with a predefined maximum
current output. The number of binary input bits can be four, eight, 10, or 12. Both
the number of bits and the full-scale output voltage determine the resolution. For
example, an 8-bit DAC can have 256 input combinations and so has a resolution
of 1/256 or 0.39% of the full-scale output. Similarly, the 10-bit DAC will have a
resolution of 1/1024 or 0.0977% of the full-scale output. Linearity is a measure of
how straight the output is when the input is changed from minimum to maximum
value. The settling time is defined as the time taken for the output to settle within a
pre-specified band after the input digital value is applied. Normally, pre-specified
band is final value ± (1/2) x minimum possible output. The settling time is an
important specification, as the DAC output may overshoot the correct value and
oscillate for some time before settling. The settling time of the DAC chip should
be considered in applications where high frequency operation is essential. Digital-
to-analog converters are required to generate the variable analog voltage essential
for control applications. Most speech synthesizers require a DAC to convert the
binary data into the corresponding analog speech signal.
DAC 0800 is a common digital-to-analog converter chip that can be easily
interfaced to the 8085 through the 8255 (Fig. 7.18). This section describes the
interfacing of DAC 0800 with the 8085 processor. As DAC chips can be connected
Fig. 7.18 Interfacing DAC 0800 with the 8085

only to a port, there is a need for an output port to be connected between the
processor and the DAC. The 8255 can act as an output port to give data from the
processor to the DAC chip. One port is enough to interface an 8-bit DAC with the
8255. The interface diagram in Fig. 7.18 uses port A of the 8255 for connecting
the data to DAC 0800. The other control signals are directly connected to either
logic 0 or logic 1. The DAC chip gives a proportional current output. This current
output is difficult to measure in most cases and so a current-to-voltage (I-to-V)
converter is used at the output. DAC chips have a built-in latch. This latch stores
the digital input given by port A and outputs a proportional voltage.
Sections 7.6.1-7.6.4 explain the software for common application examples
involving interfacing of the DAC with the 8255. Four common applications—
square wave generation, ramp wave generation, staircase wave generation, and
sine wave generation—are discussed.
7.6.1 Square Wave Generation

Example 7.5:
Write a program to generate a square waveform using a DAC chip.
The DAC chip interfaced with the 8255 and connected to the 8085 in Fig. 7.18
is considered for all examples. In this example, a square waveform is generated
using the DAC chip. The square waveform has 0 V output for one half period and
a voltage of amplitude for the other half.
The program loads the control word in the control register of the 8255 to make
port A an output port. Then the binary data for 0 V is transferred to port A and
a delay routine is called to introduce a delay of half the time period. After this,
the data in port A is made equivalent to V1 volts and the delay routine is called
again.
The data for any voltage V] is calculated using the following formula.
Equivalent value for an output of Vj volts = [(2” - 1)/Maximum output voltage]
x Vp where n is the number of binary bits in the DAC input.
For example, in a DAC with a binary input of 8 bits and a maximum output of
5 V, the equivalent value for an output of 3 V is [(28 — l)/5] x 3 = 51 x 3 = 153 in
decimal form. The same value in hexadecimal form is 99H.
The program in Table 7.14 generates a square of amplitude 3 V, with a
predefined delay and so a predefined frequency. The time delay produced by the
delay routine is explained in Chapter 4. Using the required time delay and the
clock frequency of the system, the delay count can be calculated.
Figure 7.19 shows the square waveform generated.
Fig. 7.19 Square waveform generated

Table 7.14 Program for square waveform generation
START: MVI A, 80H ; Load the 8255 control word in the

accumulator.
OUT CONTROL REG ; Move it to the control register.
LOOP: MVI A, OOH ; Load the initial data for the DAC in the
accumulator.
OUT PORTA ; Output the data to port A where the DAC is
interfaced.
CALL DELAY ; Call the delay subroutine.
MVI A, 99H ; Load the data corresponding to Vj in the
accumulator.
OUT PORTA ; Output it to port A.
JMPLOOP ; Loop again to get a continuous waveform.
DELAY: MVI B, COUNT ; Load a register with a count value.
RPT: DCRB ; Decrement it.
JNZ RPT ; Repeat decrement until required time delay is
achieved.
RET ; If required time delay is achieved, return
from subroutine.
7.6.2 Staircase Waveform Generation

Example 7.6:
Write a program to generate a staircase waveform using a DAC chip.
The hardware used is given in Fig. 7.18. The waveform to be generated is
given in Fig. 7.20.
Fig. 7.20 Staircase waveform
Three levels V , V , and V3 are assumed in the output voltage waveform. The
hexadecimal output to be given to the port is calculated using the formula given
in Example 7.5. The program given in Table 7.15 uses the labels DATA1, DATA2,
and DATA3 for the three output voltage levels. A fixed time delay is used in all
the three levels.
Table 7.15 Program for staircase waveform generation

START: MVI A, 80H ; Load the 8255 control word in the accumulator.
OUT CONTROL_REG ; Move it to the control register.
LOOP: MVI A, DATA1 ; Load the value corresponding to V, in the
accumulator.
interfaced.
MVI A, DATA2 ; Load the value corresponding to V2 in the
accumulator.
OUT PORTA ; Output the data to port A.
MVI A, DATA3 ; Load the value corresponding to V3 in the
accumulator.
OUT PORTA ; Output the data to port A.
JMP LOOP ; Repeat the process to get a continuous waveform.
DELAY: MVI B,COUNT ; Load a register with a count value.

achieved.
RET ; If required time delay is achieved, return from

subroutine.
7.6.3 Ramp Waveform Generation

Example 7.7:
Write a program to generate a ramp waveform using a DAC chip.
Figure 7.21 shows the ramp
waveform to be generated.
The 8255 port A is loaded with
gradually increasing values starting at
zero. The hardware connections are
the same as in Fig. 7.18. The program
in Table 7.16 generates the ramp
waveform shown in Fig. 7.21, with
V, = 5 V.
The delay calculation is slightly different from the previous examples. Here,
the voltage levels are increased from 0 to FFH, i.e., 255 in decimal form. So within
T seconds, there are 255 levels. Therefore, the delay for each level will be T/255
seconds. The program given in Table 7.16 increments the value in port A from
OOH to FFH and calls a time delay routine at each level. The delay time should be
as small as possible for ramp generation. Otherwise, the waveform will look like
a staircase waveform with 255 levels.
Table 7.16 Program for ramp waveform generation

OUT ; Move it to the control register.
CONTROL_REG
MVI A, OOH ; Load the initial value of the waveform OOH in the
accumulator.
LOOP: OUT PORTA ; Output the data to port A where the DAC is interfaced.
INRA ; Increment the waveform voltage value to get a ramp wave.
JMP LOOP ; Repeat the process to generate a ramp waveform.
JNZ RPT ; Repeat decrement until required time delay is achieved.
subroutine.
7.6.4 Waveform Generation using Stored Data

Example 7.8:
Write a program to output digital data stored in the memory locations 9000H-
9050H to the DAC chip connected to port A of the 8255.
In this example, the voltage data to be given to port A is stored in memory
locations 9000H-9050H. These data can be patterned to produce any waveform.
A sine wave, for example, is divided into many levels; each level is converted into
equivalent digital data and stored in a memory location. The time delay between
the levels is fixed and is generated by the delay routine.
In the program given in Table 7.17, the memory pointer register pair HL is
initialized with the first address of the string of memory locations where the data
are stored. Register C is initialized with a count value equal to the number of bytes
to be sent to port A. The data from the memory is sent to port A. The memory
pointer is incremented and the counter decremented. The program loops and send
the next data to port A until the counter value becomes zero. Each data is sent to
port A after the required time delay.
Table 7.17 Program to generate waveform from stored data

MVI C, 50H ; Initialize register C with the count value.
LXI H, 9000H ; Initialize the memory pointer with the address of
the first memory location.
LOOP: MOV A, M ; Load data in the accumulator.
interfaced.
INXH ; Point to next memory location.
DCRC ; Decrement the count value.
JNZ LOOP ; Repeat the process if the count value is not zero.
achieved.
subroutine.
7.7 INTERFACING STEPPER MOTORS

A stepper motor is a special motor that rotates in incremental steps, unlike other
motors that run continuously. They find application in printers, plotters, robots,
etc. Stepper motors are excited by pulses, to get incremental displacements. The
common step size of stepper motors ranges from 0.9° to 30°. Stepper motors are
made of permanent magnet rotors with stator field excitation. Two-phase excitation
and four-phase excitation are common. A four-phase stepper motor has four stator
poles that are excited by pulses. Each pole winding can be excited such that the
pole can be made either a north pole or a south pole. The number of teeth or the
number of poles in the rotor will decide the minimum incremental step angle when
a particular phase is excited. In this arrangement, the poles should be properly
excited in a particular sequence so that the rotor rotates in the desired direction.
If the excitation sequence is reversed, the rotor rotates in the reverse direction. A
typical stepper motor has a step angle of 1.8°, 50 teeth on the rotor, and eight poles
on the stator. The connections for interfacing a four-phase stepper motor to the
8085 through the 8255 are given in Fig. 7.22.
The stepper motor has six terminals—four terminals A, B, C, and D for
excitation and two more for power supply. Figure 7.22 shows the four terminals
Fig. 7.22 Interfacing of a stepper motor using the 8255
A, B, C, and D connected to the 8255 port pins through the transistor drivers. The
transistor drivers or buffers are essential as the port pins cannot directly source
the current required for the motor drive. As explained earlier, the motor terminals
have to be excited in the proper sequence so that rotor rotates continuously in one
direction. Two types of excitation are possible with a four-phase motor—one-
phase excitation and two-phase excitation. In one-phase excitation, only one phase
of the stepper motor is excited at a time. In two-phase excitation, two phases
are excited at a time. The excitation sequence is fixed for rotation in a particular
direction. The excitation sequence for one-phase excitation (for the interface
diagram in Fig. 7.22) is given in Table 7.18. The single phase excitation results in
low current through the motor windings. This is also called wave mode.
Table 7.18 Switching sequence: one-phase excitation (wave mode)
PA3 PA2 PA1 PAO Clockwise Anti-clockwise Hex value
0 0 0 1 1 4 01
0 0 1 0 2 3 02
0 1 0 0 3 2 04
1 0 0 0 4 1 08
The excitation sequence for two-phase excitation is given in Table 7.19. In two-
phase excitation, the excitation current through the motor winding is high. So it is
also called high torque excitation. Tables 7.18 and 7.19 also list the corresponding
hexadecimal byte values to be given to port A, assuming the higher-order four bits
to be zero.
Table 7.19 Switching sequence: two-phase excitation (hi-torque excitation)
PA3 PA2 PA1 PAO Clockwise Anti-clockwise Hex value

0 0 1 1 1 4 03
0 1 1 0 2 3 06
1 1 0 0 3 2 OC
1 0 0 1 4 1 09
The program for driving a stepper motor mainly consists of providing excitation
signals in the proper sequence to the port A terminals of the 8255. An appropriate
delay can be inserted between excitations to control the speed of rotation of the
motor. A minimum delay must be maintained so that the motor coils are properly
excited. This minimum delay also sets the maximum speed of operation of the
stepper motor.
Examples 7.9 and 7.10 explain the procedure for running the stepper motor
under various conditions.
Example 7.9:
Write a program to drive the stepper motor continuously at 60 rpm using the
interface diagram in Fig. 7.22.
It is assumed that a stepper motor with 1.8° step angle is used in Fig. 7.22.
If the time delay for each step is controlled, the speed of the motor can be
controlled. Let us assume that the required speed is N rpm. Then the speed
in rps (revolutions per second) is N/60. If N/60 is the number of rotations in
one second, the time taken for one rotation is 60/N. So the time taken for 1.8°
rotation is 60 x 1.8/(N x 360), which is equivalent to 0.3/Ns. If the time delay
introduced for each 1.8° rotation is 0.3/Ns, the speed of continuous rotation will
be N rpm. Here, the required speed N is 60 rpm. So the necessary time delay is
0.3/60, i.e., 5 ms.
The program given in Table 7.20 is used for continuous rotation of the stepper
motor. The count in the delay routine must be calculated to produce the required
time delay. The program first initializes the control word for the IC 8255. Then
a counter with an initial value of 04H is set up to indicate that the switching
sequence needs four steps, which are to be repeated continuously. A memory
pointer is then initialized to load the switching or excitation data to be given to
port A of the 8255. The switching data are stored initially in the memory locations.
The program shows four sets of switching tables stored in different locations. For
example, to excite the stepper motor coils in one-phase excitation method and
in clockwise direction, the memory pointer must be initialized with the memory
location 9008H. Then the program gives these switching data to the port A pins ot
the 8255, one after another, with a particular delay.
Table 7.20 Program for rotating a stepper motor at 60 rpm
9000: DB 03, 06, 0C, 09 ; Store excitation values for biphase

clockwise rotation.
9004: DB 09, 0C, 06, 03 ; Store excitation values for biphase
anti-clockwise rotation.
9008: DB 01, 02, 04, 08 ; Store excitation values for one-phase
clockwise rotation.
900C: DB 08, 04, 02, 01 ; Store excitation values for one-phase
accumulator.
OUT CONTROLJREG ; Move it to the control register.
LOOP: MVI C, 04H ; Initialize the counter with initial value =
4 (number of excitations).
LXI H, 9000H ; Initialize the memory pointer (9000H,
9004H, 9008H, or 900CH).
RPT: MOV A, M ; Get the excitation value from the
memory.
CALL DELAY ; Call the delay subroutine for proper
excitation of the motor coils.
INXH ; Increment the pointer to the next memory
location.
JNZ RPT ; If it is not zero, get the next data.
JMP LOOP ; Loop again for continuous rotation,
initializing the memory pointer and
counter again.
JNZ RPT ; Repeat decrement until required time
delay is achieved.
RET ; If required time delay is achieved, return
from subroutine.
Example 7.10:
Write a program to rotate a stepper motor by 180° using the interface diagram in
Fig. 7.22.
In most stepper motor applications, the stepper motor is not rotated continuously.
The angle by which the stepper motor rotates needs to be controlled. In this
example, the stepper motor shaft has to be rotated by exactly 180°. This can be
done by stopping the motor excitation when the motor shaft has rotated by 180°.
This is possible because each switching state of the motor coils rotates the shaft
by exactly the step angle, i.e., 1.8°. For 180° rotation, the number of switching
steps required is 180/1.8 = 100. These 100 steps are produced by repeating the
sequence of four excitations. So a count of 100/4 = 25 is needed. This count of
25 is used for exciting the motor coils with four complete step sequences. Then
the excitation is stopped and the motor rotation is halted. The program given in
Table 7.21 implements this by adding another loop with register D as a counter.
The program uses the same logic and the instructions used in Example 7.9.
Table 7.21 Program for rotating a stepper motor by 180°
9000: DB 03, 06, 0C, 09 ; Store excitation values for biphase clockwise
rotation.
9004: DB 09, 0C, 06, 03 ; Store excitation values for biphase
9008: DB 01, 02, 04, 08 ; Store excitation values for one-phase
clockwise rotation.
900C: DB 08, 04, 02, 01 ; Store excitation values for one-phase
accumulator.
MVI D, 19H ; Initialize a counter with 19H or 25D for 180°
rotation.
LOOP: MVI C, 04H ; Initialize a counter with 04H for excitation
sequences.
LXI H, 9000H ; Initialize the memory pointer (9000H,
9004H, 9008H, or 900CH).
MOV A, M ; Get the excitation value from the memory.
RPT: OUT PORTA ; Send it to port A.
CALL DELAY ; Call the delay subroutine for proper
INXH ; Increment the pointer to the next memory
location.
JNZ RPT ; If it is not zero, get the next data.
(Contd)
Table 7.21 Program for rotating a stepper motor by 180° (Contd)

DCRD ; Decrement the outer counter (for 180°
rotation).
JNZ LOOP ; If the motor has not rotated 180°, repeat the
process.
HLT ; If it has, terminate program execution.
JNZ RPT ; Repeat decrement until required time delay
is achieved.
RET ; If time delay is achieved, return from
subroutine.
7.8 INTERFACING INTELLIGENT LCDs

Many alphanumeric liquid crystal displays are available in the market. These
displays have a built-in controller IC and a display section. These displays can be
interfaced to any microprocessor or microcontroller. The data displayed in LCDs
can be easily controlled and changed.
Liquid crystal displays are created by placing a thin layer of liquid crystal fluid
between two glass plates. Transparent electrically conductive films are pasted on
the front and back glass plates in the shape of the character to be displayed. When a
voltage is applied between these two films, the electric field changes the behaviour
of the liquid crystal. So the light is either transmitted through it or reflected by it.
Hence, the required display becomes visible.
Modem LCDs come with a controller IC and related control inputs. They get
the ASCII code of the data to be displayed and display the character in the exact
location. The LCD displays come with many options such as 8-80 characters
' display, one-line, two-line, or four-line display, etc. Almost all these devices have
14 pins for interfacing with the microprocessor or microcontroller. The functions
of these 14 pins are listed in Table 7.22. Three pins E, R/W, and RS are used for
control and handshake signals. Eight pins are used for transferring data to the
display and can be connected to the data bus of the system. Two pins are allotted
for supply and ground and one pin is used for adjusting the contrast of display. The
voltage applied to this pin can be varied to adjust the contrast.
LCDs contain internal RAM for storing the data to be displayed. The control
signal RS given as input to the LCD indicates whether the data lines are carrying
a command or a data for display. RS is made zero to indicate that a command to
LCD is being sent on the data lines. It is made high to indicate that the data lines
contain display data to be read or written. R/W is also an input control signal given
to the LCD to indicate the direction of data transfer. Enable is the control input to
the LCD and must be pulsed to perform the read/write operation with the LCD. A
transition from 1 to 0 on this line enables the corresponding operation, which is

decided by the other control inputs.
Table 7.22 LCD pin configuration
Pin no. Symbol Level I/O Function

1 V ss — — Power supply (GND)
2 V cc — — Power supply (+5 V)
3 V ee — — Contrast adjust (V )
4 RS 0/1 I Command or data register select line
0 = Instruction input
1 = Data input
5 R/W 0/1 I 0 = Write to LCD module
1 = Read from LCD module
6 E 1 toO I Enable signal
7 DBO 0/1 I/O Data bus line 0 (LSB)
8 DB1 0/1 I/O Data bus line 1
14 DB7 0/1 I/O Data bus line 7 (MSB)
The common commands that are used in LCD units are given in Table 7.23.
The display can be cleared by issuing a command with LSB alone as 1. Similarly,
cursor control, display position control, and display method control can be done
using appropriate control words.
Table 7.23 LCD display command words
Code
Instruction Description
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
Clear 0000000 00 1 Clears display and returns
display cursor to the home position
(address 0)
Cursor 0000000 0 1 x Returns cursor to home position
home (address 0). Display RAM
contents remain unchanged
Entry 0000000 1 I/D S Sets cursor move direction
mode set (I/D) and specifies whether
to shift the display (S). These
operations are performed
during data read/write.
For I/D, 1 = increment;
0 = decrement (Contd)
Table 7.23 LCD display command words (Contd)
Code
Display 0 0 0 0 0 0 1 D C B Sets on/off position of all
on/off displays (D) and cursors (C)
control and blink of character at cursor
position (B)
Cursor/ 0 0 0 0 0 1 S/C R/L x X Sets move cursor—0 or
display shift display—1(S/C), shifts
shift direction (R/L) left—0 or
right—1
DDRAM contents remain
unchanged.
Function 0 0 0 0 1 DL N F x X Sets interface data length
set (DL)—1 for 8-bit data and 0 for
4-bit data, number of display
lines (N)—0 for one-line and
1 for two-line display, and
character font (F)—1 for 5 x 10
dot and 0 for 5 x 7 dot font
Set 0 0 0 1 CGRAM address Sets the CGRAM address;
CGRAM CGRAM data is sent and
address received after this setting.
Set 0 0 1 DDRAM address Sets the DDRAM address;
DDRAM DDRAM data is sent and
Read busy 0 1 BF CGRAM/DDRAM address Reads busy flag (BF), which
flag and indicates that internal operation
address is being performed and reads
counter CGRAM or DDRAM address
counter contents (depending on
previous instruction).
Write to 1 0 Write data Writes data into CGRAM or
CGRAM DDRAM
or
DDRAM
Read from 1 1 Read data Reads data from CGRAM or
CGRAM DDRAM
or
DDRAM
Note: x denotes don't care condition.
The interfacing of an LCD using the 8255 is shown in Fig. 7.23. The 8255 is
in turn interfaced to the 8085, as shown in Fig- 7.7. Port A is connected to the data
lines of the LCD and port C is connected to the control lines. PC2 is connected to
Fig. 7.23 LCD interfacing through the 8255
the enable (EN) line of the LCD. RS signal is connected to the LSB of port C. PCI
is connected to the R/W control signal.
The characters displayed for various ASCII data are given in Fig. 7.24.
Higher-order
LoweX^rbte 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
order four bits\^
CGRAM • :•••. ..... ...
■ •""" ■ ‘s!
XXXXOOOO (0) “J :...:
XXXX0001 (1) •
•
.....
aaaaa
a
:...s I
■ ■ a -a ::: a a
■
XXXX0010 (2)
■ ■ aaaaa a"’
XXXX0011 (3) • -...’
’...- ....! !..." .*"■
■■■•S ■
BM
8.'.*
•■a a.
1.4
■ • J ’..J
XXXX0100 (4) ■ ■ ■ • ... .a a a aa aa
iL
;—! ; Zu:. ■aa.a aa I."
XXXX0101 (5) :: s...! ... M ■ a aaa aa a
XXXX0110 (6) « ■ a ■ a ■ a ,5 J
a.a
:...’ S
aaaaa
(7)
• ■ ■
! hI
s"'i :. j
aâ
aaaaa .■•■s
XXXX0111
L.i !•”: s'! S 8 !* *
XXXX1000 (0) ■ ! sf! ■

1
■ ■ . • ■ a. a a
aZaa. • a a a. a a a
XXXX1001 (1) ••• ■ ••• • ■ •* aa s’J 1

_ • _ aa aaaaa a a>
XXXX1010 (2) » :■ ■
I ..... K t t:::i 5J
aaaaa aaaaa
XXXX1011 (3) 8 L ."’8 :...!
a” 1 : aaaaa
a*""l
J. ! aaaa .•5:. ’j”!
(4) J8 "a
XXXX1100 a.a
t"‘s ..........
a....
f»’I 1
! ! ! jHi
’x*
■■■a
a
a*.
a J
t.
XXXX1101 (5) J!!. ..........
T: ’’j’
•T* • !•.! ’ s.". ..h. j”j
S':::!
■
XXXX1110 (6) :: : ■! ■ • ’ ■ 1
.... SU tit:
u
s'"i Hi
XXXX1111 (7) ■
u....
....4
| 18 i • B
lili
in;
1£
Fig. 7.24 ASCII codes and corresponding display patterns

The LCD works with its own internal clock pulses. So any command or data
written to the LCD must be enabled with the EN signal. This EN signal must be
applied for a predefined duration. Each command and data requires between 40 ps
and 1.6 ps, depending on the type of LCD and its clock frequency. So a separate
subroutine is written to give proper control signals for the predefined delay time.
Here, two subroutines—COMMAND and DISP—are used to write a command
word and a data for display, respectively. These two subroutines use a common
delay routine.
The first step in the program is to clear the display, set the cursor to home
position, and start display from there. The simple program given in Table 7.24 is
written to display an array of characters stored in memory locations starting from
9000H. The number of characters displayed is NUM_CHAR; it is initialized as a
count in register C. All the characters are displayed continuously.
Table 7.24 Program for displaying data in an LCD
START: MVIA,01H ; Load the control word for clearing the

LCD display in the accumulator.
CALL COMMAND ; Call the subroutine to issue this command
to the LCD.
MVI A, 02H ; Load the control word for initializing the
cursor to home position to start displaying
data from there.
CALL COMMAND ; Call the subroutine to issue this command
to the LCD.
MVI C, NUM.CHAR ; Initialize a counter to the number of
characters to display.
NEXT: MOV A, M ; Load the the display data in the
accumulator.
CALL DISP ; Call the subroutine to issue this data to the
LCD.
INXH ; Increment the pointer so that it points to
the next data for display.
JNZ NEXT ; If it is not zero, loop again.
COMMAND: OUT PORTA ; Give the control word to the data lines of
the LCD.
MVI A, 04H ; Make E = 1, R/W = 0 (write), and RS = 0

(command).
(Contd)
Table 7.24 Program for displaying data in an LCD (Contd)

OUT PORTC ; Output it to the port C pins PC2, PC 1, and
PCO.
MVI A, OOH ; Make the E signal (PC2) zero.
OUT PORTC ; Output this data to port C.
CALL DELAY ; Call the DELAY subroutine to produce a
predefined time delay.
DISP: OUT PORTA ; Give the data to the data lines of the LCD.
MVI A, 05H ; Make E = 1, R/W = 0 (write), and RS = 1
(data).
OUT PORTC ; Output it to the port C pins PC2, PCI, and
PCO.
MVI A, OOH ; Make the E signal (PC2) zero.
OUT PORTC ; Output this data to port C.
CALL DELAY ; Call the DELAY subroutine to produce a
predefined time delay.
JNZ RPT ; Repeat decrement until required time
delay is achieved.
RET ; If time delay is achieved, return from
subroutine.
7.9 KEYBOARD AND DISPLAY INTERFACE IC 8279

The interfacing of keys and displays with the Intel 8085 processor has already
been discussed. It is seen that for displaying data, an external IC like the 8255 is
necessary. Similarly, for key interfacing, a port is necessary and the processor needs
to check the inputs from the keys for identifying whether a key has been pressed
or not. Moreover, these simple interface circuits become more complicated when
multiple display units and switches are interfaced to the processor. To reduce the
hardware for large keyboard interfacing, the matrix keyboard concept is used. To
interface multiple displays, the multiplexed display concept is used. This section
introduces the matrix keyboard and the multiplexed display concepts. These circuits
require large amounts of processing time. To reduce processor involvement, Intel
has produced a dedicated IC 8279. This IC relieves the processor from keyboard
and multiplexed display scanning. We shall discuss the hardware details and
programming of this IC in this section.
7.9.1 Matrix Keyboard

The interfacing of a single key switch to the 8085 through the 8255 has been
discussed in Chapter 6. The limitation of this interface is that each switch must
be allotted a separate port pin. The hardware complexity increases when multiple
switches are interfaced. The solution to this problem is to use a matrix keyboard.
The matrix keypad has switches connected in matrix form, as shown in Fig.
7.25. The figure shows a 4 x 4 key matrix. The rows of the keyboard matrix are
connected to four output port lines. The column lines are connected to four port
lines of an input port.
When no key is pressed, the column lines are connected to the (+5 V) Vcc line.
So the data in all the input port pins will be 1. If an output port pin is made low (i.e.,
logic 0) and if any switch in that row is pressed, the data bit in the corresponding
column becomes logic 0; the data bits in the other columns remain at logic 1. For
example, assume that DO of the output port is made 0, while the other bits are at
logic 1. If key 3 is pressed the input to D3 bit of the input port becomes zero, while
D0-D2 input bits are at logic 1. So by making DO output line 0, the key that has
been pressed in that row can be detected.
To check the entire keyboard for a key press, the following technique can be
used. One of the rows is made logic 0 and the input lines along the columns are
checked for occurrence of Os. If there is none, the next row is made logic 0 and the
procedure is repeated until the key that was pressed is identified.
Once a key is pressed, steps must be taken to remove the contact bounce
problem. Mechanical switches have a problem called contact bounce because of
their construction. Pressing a mechanical switch must produce a single pulse output.
Practically, instead of producing a single clean pulse output, the switches generate
a series of pulses because the switch contacts do not come to rest immediately.
As the microprocessor is faster than manual key pressing, the single key pressed
will be registered as multiple key presses. This is the main disadvantage of key
bouncing. The signal from keys falls and rises a few times within a period of about
5 ms as the contact bounces. So the signal from the key must be made free from
key bouncing transients. This technique is called de-bouncing of key.
Keyboard de-bouncing can be accomplished using hardware or software.
The bouncing of the key occurs within 5 ms. Since a human cannot press and
release a switch in less than 20 ms, the logic employed for de-bouncing checks the
signal after 20 ms and identifies whether a key is pressed or not. This logic can
be implemented both in hardware or software. The hardware techniques employ
set-reset flip-flops, non-inverting CMOS gates, or integrating de-bouncer. The
software techniques use the wait-and-see method. When a signal is sensed from a
switch, the program waits for 10 ms and checks the key again. If the signal from
the switch still indicates a key press, the program decides that the user has pressed
the key. Otherwise, the signal received is rejected as noise.
The software for identifying a key pressed in a keyboard matrix requires the
scanning of the rows and columns. Even after identifying the key, the key bouncing
problem must be overcome. If these tasks are accomplished using software, the
time taken is high and the processor may be held up for a long time in the process
of scanning the keyboard. To overcome this problem, Intel has produced IC 8279.
This IC can scan the keyboard, identify the key that has been pressed, and also
take care of the key bouncing problem.
Example 7.11:
Interface a 64-key matrix keyboard to the 8085 microprocessor using the 8255.
Write an 8085 assembly language program to initialize the 8255 and to read the
key code.
Figure 7.25 shows a matrix keyboard with 16 keys, connected to the 8085
microprocessor using the 8255. A matrix keyboard with 64 keys uses similar
hardware. However, eight bits instead of four are used in each port. In this example,
port A is assumed as the output port; port B lines are scanned for the occurrence
of 0, to check for a key press.
Figures 7.26 (a) and 7.26 (b) show the algorithm for the program and the delay
subroutine. This algorithm uses a routine called KEY. It keeps track of the keys
pressed in the same sequence in which they are scanned, and stores them in the
L register. When any key press is detected, the code corresponding to that key is
loaded in the accumulator and processed further. If necessary, a look-up table may
be used to convert the key detected into its corresponding ASCII code.
Fig. 7.26 (a) Algorithm for interfacing a matrix keyboard with the 8085
Fig. 7.26 (b) Algorithm for producing delay
Source program:
Table 7.25 gives the program for interfacing the matrix keyboard with the 8085.
Table 7.25 Program for interfacing a matrix keyboard with the 8085
MVI A, 1000001OB ; Set port A as the output port and port B as the
input port.
OUTCR ; Initialize the control register of the 8255.
START: MVI A, OOH ; Make all the scan data zero.
OUT PA ; Output to port A.
BACK: INPB ; Get data from port B.
CPI FF ; Check for key press.
JZ BACK ; If no key has been pressed, jump to BACK
and check for key press again.
CALL DELAY ; If a key has been pressed, wait for key de
bounce.
MVI L, OOH ; Initialize a key counter.
MVI C, 04H ; Initialize a column counter for four columns.
MVI B, 11111 HOB ; Make one column low.
NEXTCOL: MOV A, B ; Move the content of register B to the
accumulator.
OUT PA ; Output it to port A.
MVI D, 04H ; Initialize a row counter for four rows.
IN PB ; Read the return line status.
(Contd)
Table 7.25 Program for interfacing a matrix keyboard with the 8085 (Contd)
NEXTROW: RRC ; Check one row for key press.

JNC KEY ; If it is zero, jump to the subroutine KEY.
INRL ; If not, increment the key counter.
DCRD ; Decrement the row counter.
JNZ NEXTROW ; Jump to NEXTROW and check the next row.
MOV A, B ; Move the content of register B to the
accumulator.
RLC ; Select the next column.
MOV B, A ; Move the content of the accumulator to
register B.
DCRC ; Decrement the column counter.
JNZ NEXTCOL ; If it is not zero, jump to NEXTCOL.
JMP START ; If it is zero, jump to START.
KEY: MOV A, L ; Load the key code available in the register L.
... ; Proceed to process it.
Delay
subroutine:
DELAY: LXI D, Count ; Load the value of Count in the DE register
pair.
BACK: DCXD ; Decrement the DE register pair.
MOV A, D ; Move the content of register D to the
accumulator.
ORAE ; Logically OR the content of the accumulator
with the content of register E.
RET ; If it is zero, return to main program.
7.9.2 Multiplexed Display

The seven-segment display discussed in Section 7.3 uses individual port pins for
each display. This requires one port for each seven-segment display. To reduce
the hardware complexity for multiple display devices, the matrix display method
is used. Here, with two ports, as many as eight display units can be interfaced. An
arrangement with four display units is shown in Fig. 7.27.
The data pins of all the display devices are connected to one port pin. One
display unit alone is selected using another port pin, through the driver transistor.
This selection is done by using an active low pin output in the corresponding port.
However, the user must see the output on all the display units simultaneously. This
5V
Fig. 7.27 Multiplexed display arrangements
is done by displaying the data in quick succession in all the display units. Due to
the persistence of vision, the human eye holds the display image in it and the user
sees all the display units illuminated simultaneously. As long as the displays are
turned on and off fast enough, the eye will perceive them as being illuminated all
at the same time.
The program involves outputting data to one display unit and repeating the
same procedure for all the other display units in quick succession. The timer can
be used to control the rate at which data is displayed and refreshed. This consumes
a considerable amount of processor time. To overcome this problem, IC 8279 can
be used.
Example 7.12:
Write a program routine to scan and display the data available in the series of
memory locations starting at 9000H in four seven-segment displays connected to
the 8085 through the 8255. Assume that the data for display is connected to port A
of the 8255 and digit selection is done through the port B lines.
The port A lines are connected to the eight LEDs of the common anode seven
segment display. So the data to be sent is active low, meaning that logic 0 has to
be sent to light an LED segment. The common anode is driven by a PNP transistor.
The logic 0 connected to the base of the PNP transistor will switch it on and make
the corresponding segment display a digit. Here, the least significant four bits
of port B are assumed to be connected to the four transistor drivers. The 8255 is
assumed to have addresses as follows: port A—80H, port B—81H, port C—82H,
and control register—83H. The program given in Table 7.26 assumes that the
display data for the four digits is available in the memory locations 9000H-9003H.
A software lime delay is used to display the devices in a multiplexed manner.
Table 7.26 Program for displaying data in four seven-segment displays

MVI A, 80H ; Initialize the control word in the accumulator.
OUT 83H ; Load it in the control register of the 8255.
DISPLAY: LXI H, 9000H ; Initialize the memory pointer.
; Initialize register B with data for digit
MVIB, 11111110B
selection.
MVI C, 04H ; Initialize count for four digits.
LOOP; MOV A, M ; Get the display data.
OUT 80H ; Load it in port A.
MOV A, B ; Select a digit.
OUT81H ; Load it in port B.
; Introduce a delay by calling the subroutine
CALL DELAY
DELAY.
; Move the content of register B to the
MOV A, B
accumulator.
RLC ; Rotate it to select the next digit.
MOV B, A ; Store it again in register B.
INXH ; Point to the next display data.
DCRC ; Decrement count.
JNZ LOOP ; If it is not zero, jump to LOOP.
; If it is zero, initialize and repeat the display of
JMP DISPLAY
all digits again.
Delay subroutine:
DELAY: T VT ; Load the value of Count in the DE register
LXI D, Count
pair.
BACK: DCX D ; Decrement the DE register pair.
; Move the content of register D to the
MOV A, D
accumulator.
; Logically OR the content of register E with the
ORAE
accumulator.
RET ; If the result is zero, return from subroutine.
The delay in this routine must be such that within the time period of persistence
of vision, the first digit is displayed again after displaying other digits. Note that
this routine will be in a continuous loop. For multiplexed display, the display must
be continuously refreshed. The delay used here is a software delay routine. So
processor time is wasted, since no other processing of data is done by the processor
during this time. This disadvantage can be overcome by using a dedicated 8279 IC
(keyboard and display interface IC), which will update the displays.
7.9.3 Features, Block Diagram, and Pin Details of 8279

IC 8279 is a programmable keyboard and display interface controller, designed
by Intel for use with Intel microprocessors. The major features of this IC are as
follows:
(i) Supports keyboard of size up to 64-key matrix with 2-key lockout and n-
key rollover options
(ii) Supports display interface of up to 16 digits with many options
(iii) Simultaneous keyboard and display operations
(iv) 8-character FIFO memory to store the codes of keys pressed
(v) 16-byte display RAM corresponding to 16 digits of display
The block diagram of the 8279 is given in Fig. 7.28.
CLK RESET DB0-DB7 RD WR CS AO
] Keyboard section
' I
Fig. 7.28 Internal block diagram of IC 8279
IC 8279 has the following three sections:

(i) Display section with its own display RAM
(ii) Keyboard scan section with FIFO registers
(iii) Control logic with signals for interfacing with the processor
The control section consists of a data bus buffer for interfacing with the
processor. This VO section uses control signals such as AO, CS, RD, and WR.
The active low control signal CS is used to select the IC. Similarly, the active low
control signals RD and WR are used to indicate the direction of data transfer on
the data bus (DB0-DB7). The signal AO is used to select a data or control register.
A logic 1 on the AO line means that the content of the data bus is a command or
status. A logic 0 on the line means that the content of the data bus is data for the IC.
The control and timing registers store the keyboard and display modes and other
operating conditions.
Although there are many control and data registers, the 8279 uses only two
addresses—one with AO = 0 and the other with AO = 1. This is done using a
unique control word for each operation. For example, two different control words
are available for accessing the display RAM and the keyboard FIFO. For every
operation, the corresponding control word is written, the necessary register is
accessed, and then the operation is carried out.
SL0-SL3 are the four scan lines of the 8279. There are two programmable
options for the scan lines—encoded mode and decoded mode. In encoded mode,
the SL0-SL3 lines are binary counter outputs and need to be decoded externally
for scanning keyboards and displays. In decoded mode, the SL3-SL0 outputs are
decoded; one of the four lines has an active low output. The scan lines SL0-SL3
are common to both keyboards and displays. RL0-RL7 are the eight return lines
and are used as inputs to sense a key press in the keyboard matrix.
The other signals available in the 8279 are as follows:
(i) BD: Active low output signal, used to blank all displays
(ii) CLK: Clock input to be given to the 8279, for proper operation of internal
circuits
(iii) CNTL/STB: Control or strobe signal, given as input from the control key in
the keyboard
(iv) Shift: Input to the 8279 RL2 E 1 40 Vcc □
from the shift key of the RL3 E 2 39 RL1 □
keyboard CLK E 3 38 RLO □
(v) IRQ: Interrupt request IRQ E 4 37 □
CNTL/STB
sent to the processor from RL4 E 5 36 SHIFT □
the 8279 to indicate a key RL5 E 6 35 SL3 □
press RL6 E 34 SL2 □
(vi) OUT A0-A3 and OUT RL7 E 8 33 SL1 □
B0-B3: Data output lines RESET E 9 8279 32 ^3 SLO
for the display units RD E 10 31 OUT BO□
(vii) Reset: Input to the 8279 WR E 11 30 OUTB1 □
and connected to the DBO E 12 29 El OUTB2
processor RESET OUT DB1 E 13 28 OUT B3□
DB2 E 14 27 El OUT AO
The pin diagram of the 8279 is
DB3 E 15 26 El OUTA1
given in Fig. 7.29.
DB4 □ 16 25□ OUTA2
DB5 C 17 24 El OUT A3
7.9.4 Programming of 8279 DB6 E 18 23 El BD
IC 8279 can be programmed to DB7 C 19 22 El CS
select the number of displays, V8S E 21 E] AO
the type of key scan, the memory
to write the display data into, a Fig. 7.29 Pin diagram of IC 8279
blank display, and the key code read option, and to control the interrupt request
signal. All these operations or commands are written into the 8279 through the
data bus, with logic 1 on the AO line. The most significant three bits of the control
word differentiate the operations. The first three bits of the byte sent to the control
port select one of eight control words, which are listed in Table 7.27.
Table 7.27 Control word selection using the most significant three bits
D7 D6 D5 Function Purpose
0 0 0 Mode set Control word to select the number of displays,

display position, and type of key scan
0 0 1 Clock Control word to program the internal clock and set
the scan and de-bounce times
0 1 0 Read FIFO Control word to be written before reading the key
code from FIFO
0 1 1 Read display Control word written before reading the display
RAM
1 0 0 Write display Control word written in the control register before
writing data to the display RAM
1 0 1 Display write Control word to blank half-bytes.
inhibit
1 1 0 Clear Control word to clear the display and FIFO
1 1 1 End interrupt Control word to clear the IRQ signal to the
microprocessor
7.9.4.1 Keyboard/Display Mode Set Control Word

The mode set control word is used to set the basic control modes for display and
keyboard interfacing. As mentioned in Table 7.27, the most significant three bits
of this control word are made 0. The next two bits correspond to the display mode
and the least significant three bits correspond to the keyboard mode. The format of
the mode set control word is given in Table 7.28.
Table 7.28 Mode set control word format
D7 D6 D5 D4 D3 D2 D1 DO
GOOD D K K K
00—8-digit display 000—Encoded keyboard with 2-key lockout

with left entry 001 —Decoded keyboard with 2-key lockout
01—16-digit display 010—Encoded keyboard with n-key rollover
with left entry Oil—Decoded keyboard with n-key rollover
10—8-digit display 100—Encoded sensor matrix
with right entry 101—Decoded sensor matrix
11—16-digit display 110—Strobed keyboard; encoded display scan
with right entry 111—Strobed keyboard; decoded display scan
The display control word bits DD produce four options—8 bits or 16 bits, with
calculatorlike right entry or typewriterlike left entry.
The lines SL0-SL3 provide encoded and decoded output options for the
keyboard interface. In the case of encoded output option, SL0-SL3 outputs will
have active high outputs in binary form. To select a single row in the keyboard
and to select a single display digit, the encoded binary outputs must be decoded
externally with a decoder IC. In the case of decoded output option, the lines SLO-
SL3 will have only one active low output at a time. An external decoder in not
needed now. However, only four rows of the keyboard can be scanned with these
four lines, i.e., only one of four display digits can be selected.
In the keyboard matrix scan mode, there are two options—2-key lockout and
n-key rollover. In 2-key lockout mode, if two keys are pressed simultaneously, the
key that is released last is considered as the key pressed; the other key is neglected.
In the case of n-key rollover, if two or more keys are pressed simultaneously, all
the keys are sensed and stored in the FIFO in the sequence in which the keys are
recognized by the logic. In sensor matrix mode, the de-bounce logic is suppressed;
any key press sensed in the matrix is directly stored in the sensor RAM.
7.9.4.2 Clock Signal Programming Command Word
The clock command word programs the internal clock driver. The code PPPPP
shown in Fig. 7.30 corresponds to the binary code by which the input clock signal
must be divided to achieve the desired operating frequency. With the five bits
D0-D4, division is possible by any number from two to 31. For example, for an
operating frequency of 100 kHz and a clock input of 1 MHz, the count should be
0101 OB (i.e., 10D). This control word decides the time taken for scanning and the
de-bouncing.
D7 D6 D5 D4 D3 D2 D1 DO
0 0 1 P P P P P
Fig. 7.30 Clock signal programming word format
7.9.4.3 Read FIFO Sensor RAM Command Word

The read FIFO control word selects the address (AAA) of a keystroke from the
FIFO buffer (000-111). The bit AI shown in Fig. 7.31 selects auto-increment for
the address. If AI is set to 1, the address will be incremented after every read
operation. So data is fetched continuously, one after another, from the FIFO to the
processor. In the scan keyboard mode, the AAA and AI bits become irrelevant. All
data from the FIFO are read consecutively in the same order in which they were
entered into the FIFO.
D7 D6 D5 D4 D3 D2 D1 DO
0 1 0 AI 0 A A A
Fig. 7.31 Read FIFO command word format

7.9.4.4 Write Display RAM Command Word

Writing the above command into the command register programs the 8279 to get
and store the data to be displayed in the display RAM. If AI is set to 1, the auto
increment option is implemented and the address of the RAM is incremented
automatically after every write operation. Data written with 0 in the address line
AO are written into subsequent RAM addresses, automatically incrementing them.
The write display RAM control word format is shown in Fig. 7.32.
D7 D6 D5 D4 D3 D2 D1 DO
1 0 0 AI A A A A
Set to 1 for auto Address of the 16-byte display 6
increment option RAM in four bits
Fig. 7.32 Write display RAM command word format
7.9.4.5 Other Command Words

Other commands like reading display RAM, blanking display, clearing the display
or FIFO, and clearing the IRQ signal to the microprocessor may not be necessary
for basic interfacing of a keyboard/display. So a summary of these commands is
given below. More details about these commands are available in the datasheet of
the 8279.
Read display RAM command word The display RAM read control word (Fig.
7.33) selects the address of one of the display RAM positions. A subsequent read
operation using AO = 0 will read data in that display RAM address.
D7 D6 D5 D4 D3 D2 D1 DO
0 1 1 AI A A A A
Fig. 7.33 Read display RAM command word
Display inhibit/mask command word The display write inhibit control word
(Fig. 7.34) is used in applications where separate 4-bit display ports are used.
Examples include displays that use a BCD decoder. This control word is used to
inhibit either the leftmost four bits of the display or the rightmost 4 bits, using the
I-I bits. With this command word, it is possible to write a nibble into the display
RAM without affecting the other digits being displayed. The masking of bits MM
is similar in operation to inhibit, but these bits will selectively blank either the
leftmost or rightmost display.
D7 D6 D5 D4 D3 D2 D1 DO
1 0 1 0 I I M M
Fig. 7.34 Display inhibit/mask command word
Clear display command word The clear display control word (Fig. 7.35) can
clear the display RAM using the CD bits. This command word has the option of
making the display RAM all Os (D3 and D2 = 0) or all Is (D3 and D2 = 1). Setting
CF bit is used to clear the keyboard FIFO RAM. Setting CA bit is used to clear
both the display RAM and the FIFO RAM.
Fig. 7.35 Clear display command word
End interrupt command word The end interrupt command (Fig. 7.36) is issued
to clear the IRQ pin in sensor matrix mode.
D7 D6 D5 D4 D3 D2 D1 DO
1 1 1 E 0 0 0 0
Fig. 7.36 End interrupt command word
7.9.4.6 Keyboard Status Word Format

To determine if a character has been typed, the FIFO status register is checked. The
keyboard status word contains the status of FIFO, error, and display availability.
This status word can be read from the 8279 when AO is high. The status word
format is given in Fig. 7.37. The least significant three bits are used to indicate the
number of keys pressed and stored in the FIFO. The next bit F is used to indicate
that the FIFO is full. Underrun error bit U is used to indicate a read attempt from
the empty FIFO. Overrun error bit O is used when an entry into a full FIFO is
attempted. S/E is used to indicate a multiple key press. The bit D is used to indicate
the unavailability of the display.
D7 D6 D5 D4 D3 D2 D1 DO
D S/E 0 U F N N N
Number of keys pressed
Fig. 7.37 Keyboard status word
7.9.4.7 Keyboard Code Word Format

In the scanned keyboard mode, the character entered into the FIFO corresponds to
the position of the switch in the key matrix and the status of the control and shift
keys. The data read from the FIFO RAM has the format shown in Fig. 7.38. The
MSB corresponds to the status of the control key while the next bit corresponds
to that of the shift key. The next three bits are from the scan counter and indicate
the row in which the key press was identified. The least significant three bits
correspond to the column lines in which the key press was identified.
D7 D6 D5 D4 D3 D2 D1 DO
CTRL SHIFT s2 s. So *2 R. Ro
Encoded row position Encoded column position

"X'. W =$ $' - - - - - z-—z-z^-v
Fig. 7.38 Format of data read from FIFO RAM
7.9.5 Display Interface using 8279

IC 8279 can be used to interface a maximum of 16 characters. The lines A0-A3
and B0-B3 are used to give the display data to the devices. The scan lines are used
to select a display device. Figure 7.39 shows the interfacing of seven-segment
LEDs with the 8085 using the 8279.
The number of display devices used in this scheme is six. The seven-segment
displays are all common anode type and a transistor driver is used with each display
device. A PNP transistor drive, similar to those used in Fig. 7.27 is used to switch
between the common anode and +5V supply. A logic low is required to turn on
the transistor driver; it is generated using the decoder IC. Common decoder ICs
such as IC 74138 can be used as these ICs can give an active low signal on any of
their outputs. The segments of the display devices are all connected together on a
common bus and connected to the A0-A3 and B0-B3 outputs of the 8279. As the
displays are all of common anode type, the data output for illuminating the LEDs
must be logic low. This means that a logic 1 in the data lines A0-A3 and B0-B3
blanks the display and a logic 0 displays all the segments.
The program given in Table 7.29 initializes the 8279 with the control word for
encoded output and eight-digit display. The writing of data in the display RAM
of the 8279 is enough to display data. The 8279 automatically scans and refreshes
the display. As shown in Fig. 7.39, the program assumes that a six-digit display is
interfaced to the 8085 using the 8279. The program given uses programmed and
polled method of data transfer.
Table 7.29 Program for interfacing seven-segment displays using the 8279
START: MVI A, OOH ; Load the mode set command word in the
accumulator.
OUT COMMAND PORT ; Output it to the command port.
MVI A, 11010000B ; Load the clear display command word in
the accumulator.
MVI A, 90H ; Load the write display RAM command
word in the accumulator.
MVI A, DATA1 ; Load the first data in the accumulator.
OUT DATAPORT ; Output it to the seven-segment display.
MVI A, DATA2 ; Load the second data in the accumulator.
MVI A, DATA3 ; Load the third data in the accumulator.
MVI A, DATA4 ; Load the fourth data in the accumulator.
MVI A, DATA5 ; Load the fifth data in the accumulator.
MVI A, DATA6 ; Load the sixth data in the accumulator.
7.9.6 Keyboard Interface using 8279

The matrix keyboard can be interfaced with the 8085 processor through the 8279.
The size of the matrix keyboard can be anything between 2x2 and 16x8. For
matrices with more than four rows, only encoded scan mode can be used; the
lines SL0-SL3 need an external decoder. Column selection is done by the lines
RL0-RL7. These lines have internal pull-up resistors and so do not need external
resistors.
The 8279 does the three keyboard scan tasks—placing a low in a scan line, checking
for a low on the return lines, and detecting and de-bouncing the key pressed.
Figure 7.40 shows a keyboard matrix of size 8x8 connected to the 8279. Three
row select lines SL0-SL2 are used to apply a low on one of the eight row lines and
consecutively scan all the row lines. A key press can be sensed by a low on any one
Fig. 7.40 Interfacing matrix keyboard using IC 8279
of the eight return lines, RL0-RL7. The 8279 does this scanning automatically and
stores the key code into the FIFO RAM. In this figure, the CNTL and SHIFT lines
are not used and are connected to logic low.
The program for interfacing a matrix keyboard with the 8085 using the 8279
is given in Table 7.30. Initially, the mode set command word is written into the
command port. Here, the encoded scan keyboard mode with 2-key lock out is
used. After writing the command word, IC 8279 starts scanning the key presses.
Any key press can be sensed by reading the status word from 8279 and checking
the least significant three bits. The following program checks for a single key press
and reads the key code from the FIFO.
Table 7.30 Program for identifying a key press using IC 8279
START: MVI A, OOH ; Load the mode set command word in the
accumulator.
LOOP: IN COMMAND PORT ; Read the status word from the 8279.
ANI 07H ; Mask the most significant five bits.
JZ LOOP ; If no key is pressed, loop again to read
the status word.
MVI A, 50H ; If a key has been pressed, load the read
FIFO RAM command word in the
accumulator.
IN DATA_PORT ; Read the FIFO RAM data from the data port.
STA KEY_CODE ; Store the key code in a memory location.
The program in Table 7.30 uses the polling method of data transfer to transfr
data from the 8279 FIFO to the processor, by reading the status word. To save
processor time and to avoid the reading and checking of the status register, the
IRQ line of the 8279 can be used to interrupt the processor. The IRQ signal is
activated by the IC 8279 whenever a key press is sensed and its code is loaded
into the FIFO RAM. This interrupt request line can be tied to any of the interrupt
signals of the processor and the corresponding interrupt service routine can be
used to read the key code from FIFO RAM.
7.10 INTEL TIMER IC 8253

In programming the 8085, we have seen that a delay subroutine can be used to
introduce a predefined time delay. The delay is achieved by decrementing a count
value in a register using appropriate instructions. The disadvantage of this software
approach is that the processor is locked in the delay loop and processor time is
lost in counting. This can be overcome by using hardware timer and interrupts.
IC 555 can be used to generate timing signals, but only at fixed time intervals.
However, it cannot be easily interfaced with the microprocessor. So Intel has
produced programmable timer devices, IC 8253 and IC 8254. These devices can
be programmed to generate different types of delay signals and also count external
signals. Other counter/timer functions that are commonly implemented with the
8253 are programmable frequency square wave generator, event counter, real
time clock, digital one-shot, and complex motor controller.
7.10.1 Features of IC 8253

Timer ICs 8253 and 8254 have been manufactured by Intel with similar
operating functions. The 8254 can be operated at a frequency of up to 8 MHz,
whereas the 8253 can be operated only up to a maximum frequency of 2.6 MHz.
The following is the list of major features of IC 8253:
(i) Generation of accurate time delay
(ii) Three independent 16-bit down counters called channels
(iii) Six different programmable operating modes
(iv) Timer or counter operation
(v) Counting in binary or BCD
(vi) Capability to interrupt the processor
(vii) Single+5 V supply
(viii) Operation in both DC and AC (up to 2.6 MHz)
7.10.2 Block Diagram of IC 8253 and Pin Details

The internal block diagram of IC 8253 (Fig. 7.41) shows the three independent
16-bit timers—counters 0, 1, and 2. These counters are programmer-controlled;
the programmer can initialize the count value and start the counting process. The
initialization is done through the data bus of the system. Counting can be started
and stopped using software instructions written into the control register. The
count value in the counter can be read by the programmer at any time, using the
appropriate command word, through the data bus of the system.
CLKO
GATEO
OUTO
CLK1
GATE1
OUT1
CLK2
GATE 2
OUT 2
Fig. 7.41 Internal block diagram of IC 8253
The pins of IC 8253 are shown in Fig. 7.42.

Each counter has two pins, CLK (clock input) and GATE, for input and one
pin, OUT, for output. The control input line GATE is used to start or stop the
counting operation. The Out signal from each counter can be used to indicate
the completion of required counting
or timing operation and also to D7 1 □ 24 □ v
*cc
interrupt the processor.
D6 2 23 WR □
An 8-bit data bus is available
in the 8253 to interface the IC with
D5 3 RD □
D4 4 21 CS I
s
the microprocessor. The control
D3 5 20 A1
signal CS is used to select the
chip. This active low signal can be
D2 6 8253 19 AO □
activated using the address lines and
D1 7 □ 18 CLK 2
DO 8 17 OUT 2
the decoder. In addition, the 8253
requires two address lines AO and Al
CLKO 9 □ 16 □
GATE 2
I
OUTO C 10 15 CLK1
to be issued from the 8085 hardware.
These address lines are used to select
GATEO C 11 14 □
GATE1 I
one of four registers (three counters GND E12 13 OUT1 □

and one control register) in the 8253.
The RD and WR control signals are Fig. 7.42 Pin details of IC 8253
issued by the processor to indicate
whether it is reading from or writing into the 8253 registers. Table 7.31 shows the
control signals applied to the pins of the 8253 for various operations.
Table 7.31 Control signals and operation in IC 8253
cs RD WR A1 AO Operation
0 1 0 0 0 Load count value in counter 0

0 1 0 1 1 Write control word
0 0 1 0 0 Read counter value from counter 0
0 0 1 1 1 No operation
0 1 1 X X No operation
1 X X X X Disable chip
7.10.3 Operating Modes and Control Word of IC 8253

The complete operation of the 8253 is programmed by the systems software or the
programmer. The programmer configures the 8253 to match his/her requirements.
A set of control words must be sent out by the programmer to initialize each counter
of the 8253. These control words program the mode, loading sequence, and mode
of counting (binary or BCD). Then the programmer initializes one of the counters
of the 8253 with the desired quantity. When the appropriate command or control
word is given, the 8253 will count-out the delay and interrupt the CPU when it
has completed its tasks. It is easy to see that the software overhead is minimal and
that multiple delays can easily be maintained by assignment of interrupt priority
levels.
The normal procedure for software control of the 8253 has the following four
main steps:
(i) Write the control word into the control register of the 8253 for each
counter used.
(ii) Write the initial count value into the counter register.
(iii) Apply clock pulses to the counter.
(iv) Check for the desired count value, the interrupt signal from the counter, or
check for the hardware signal Out from the counter. After checking for the
required time delay, execute the next operation.
Each counter of the 8253 is individually programmed by writing a control
word into the control word register. The control word format is shown in Table
7.32. The LSB DO is used to select the counting mode—binary or BCD. The next
three bits M0-M2 decide the operating mode for the counter selected. RLO and
RL1 bits decide whether read or load operation is to be performed on the counter.
The counter can be made to count continuously, but the programmer can read the
count value at any time by writing a control word to latch the count value and then
read it. Similarly, initial setup can define whether an 8-bit value or a 16-bit value
is loaded into the counter. The most significant two bits SCO and SCI are used to
select the counter.
Table 7.32 Control word format of the 8253
Name SC1 SCO RL1 RLO M2 M1 MO Binary/BCD

Explanation Select counter Read/Load option Mode selection 0—Binary
00—Counter 0 00—Latch count bits counter
01—Counter 1 01—Load LS 000—Mode 0 1—BCD
10—Counter 2 byte only 001—Mode 1 counter
11—Illegal 10—Load MS X10—Mode 2
byte only XI1—Mode 3
11—Load LSB 100—Mode 4
and then 101—Mode 5
MSB
The six operating modes of the timer IC 8253 along with the function of the
gate pin are listed in Table 7.33.
Table 7.33 Operating modes of the 8253
M2 M1 M0 Operating modes GATE control Reloading of

Count value
Interrupt on 0—Disables counting

0 0 0 Mode 0 No
terminal count 1—Enables counting
Programmable 0 to 1 transition Yes, if
0 0 1 Mode 1
one-shot initiates counting triggered
0—Disables counting
Rate generator. 1—Enables counting
X 1 0 Mode 2 Divide-by-n 0 to 1 transition Yes
counter reloads counter and
initiates counting
1—Enables counting
Square wave
X 1 1 Mode 3 0 to 1 transition Yes
rate generator
reloads counter and
initiates counting
Software-
1 0 0 Mode 4 triggered No
1—Enables counting
strobe
Hardware- Yes, if gate
0 to 1 transition
1 0 1 Mode 5 triggered input goes
initiates counting
strobe from 0 to 1
7.10.3.1 Mode 0: Interrupt on Terminal Count

In mode 0, the counter is used to issue an output after counting up to the pre
initialized value. The initial count value is loaded into the counter and gets
decremented every clock pulse. The Gate signal input also controls the counting
operation. The output line OUT is made high from low, when the count value
becomes 0. The Out signal becomes low when the counter is loaded with the next
count value.
This mode 0 operation is a one-time operation and the Out signal indicates
the terminal condition of the required count operation. The Gate input signal of
the corresponding counter either enables or disables the counting operation. The
waveforms for counter operation in mode 0 are given in Fig. 7.43.
Clock
WRn
Output (interrupt)
WRm
Gate
Output (interrupt)
A+B=m
Fig. 7.43 Waveforms for counter operation in mode 0
7.10.3.2 Mode 1: Hardware-triggered One-shot

Mode 1 is similar to mode 0, but has a minor difference. The similarity between
the modes is that the output becomes low while counting down and becomes high
once the count value reaches zero. The first difference between the modes 0 and
1 is that in mode 1, the counting is started/triggered whenever the Gate input
becomes high. The second difference is that in mode 1, the count value is reloaded
if in the middle of the count the Gate goes low and becomes high again. This
operation of the counter is similar to that of a monostable multivibrator, with the
Gate input signal acting as the trigger input to the multivibrator. The duration of
low output is the quasi-stable state of the multivibrator and is decided by the count
value loaded initially.
The waveforms for counter operation in mode 1 are shown in Fig. 7.44.
7.10.3.3 Mode 2: Rate Generator
In mode 2, the counter generates continuous signals in the output line. The down
counting starts once the counter is loaded with the count value. In this mode, the
output signal becomes high once the counting starts. The output becomes low,
only during the last clock cycle of the count. After this, the count becomes zero.
Then the count value is reloaded and decremented every clock pulse. As only
one low pulse is generated during the entire count cycle, this mode is called rate
generator or frequency divider. The divided output frequency is given by the
following formula:
Output frequency = (Input clock frequency)/(Count value loaded)
This mode is commonly used to generate a real-time clock interrupt. The output
can be used as an interrupt signal to interrupt the processor during every output
period of the counter.
The Gate input in this mode acts as Reset input. If it becomes 0, counting is
disabled. When it becomes 1, the count value is reloaded and counting starts again.
The waveforms for counter operation in mode 2 are given in Fig. 7.45.
7.10.3.4 Mode 3: Square Wave Generator

The operation of modes 3 and 2 are similar, except that the output is a square wave
with equal low and high periods in mode 3. If the count value is loaded with n,
the output will be low for n/2 clock periods and high for n/2 clock periods. If n is
odd, the output will be high for a (n + l)/2 clock periods and low for a (n - l)/2
clock periods. The counting will be reinitialized once the count value reaches zero.
Thus, the square wave will be generated continuously. The frequency of the output
256 microprocessors and microcontrollers
square waveform will be given by the input clock frequency divided by the count
value. The waveforms for counter operation in mode 3 are given in Fig. 7.46.
7.10.3.5 Mode 4: Software-triggered Strobe

In mode 4, the down-counting in the counter is initiated by writing the count value
in the counter. The output will be low during the last clock period of every count
cycle. The Gate input controls the counting and will reinitialize the count value, as
shown in Fig. 7.47. An input of 0 on the Gate input pin inhibits the counting.
Clock —I I—I I—I I—I I—i I—I I—I I—I I_ I I_ I LJ I I U I_

WR | n =4 |
4 3 2 1 0
Output | |
Load n WR | n=4 |
Gate | |
________________ 4______________ 4 3 2 1 0
Output
/ ...... .......
7.10.3.6 Mode 5: Hardware-triggered Strobe

Mode 5 of the timer IC 8253 is similar to mode 4, with the difference that the
counting is triggered by the Gate input signal and not by the writing of the count
value by the software. The output is high once the count value is loaded. Counting
starts on the rising edge of the gate pulse. The output is low during the last count
of the counter.
The waveforms for counter operation in mode 5 are given in Fig. 7.48.

7.10. 4 Interfacing IC 8253 with 8085

The timer IC 8253 can be interfaced with the 8085 as an input and an output device.
The first step in interfacing is to allot the addresses for the devices and design the
address decoding logic. In an 8085-based system, the I/O devices require an 8-bit
address. So four consecutive 8-bit addresses are allotted to the 8253, for accessing
the three counters and one control register. The AO and Al address lines can be used
to select one of three counters and the control register. The lower-order address bus
and the data bus must be de-multiplexed using a latch and ALE signal, like in any
8085 system. The 8085 processor places the 8-bit I/O addresses on both the higher-
and lower-order address buses. So the higher-order address lines A8-A15 can be
used for address decoding, along with the IO/M signal, as shown in Fig. 7.49. The
RD and WR signals from the 8085 are connected to the 8253 for proper reading and
writing of the count value and the control word. For operating the counters, they
must be given proper signals on the input pins CLK and GATE.
Fig. 7.49 Interfacing the 8253 to the 8085
7.10. 5 Application Examples

Example 7.13: Timer interface using polling method
Assume that a timer IC 8253 is interfaced to the 8085 processor at the addresses
30H, 31H, 32H, and 33H. The system has another IC 8255 interfaced to it at the
addresses 40H, 41H, 42H, and 43H. Two seven-segment displays are interfaced
to port A of the 8255. Design a timer interface and program such that the seven
segment displays in the system will count in decimal from 00 to 99 with a 1 second
delay between counts. (This type of interface can be developed as a stop watch by
adding a set of switches on a port.)
The counters are interfaced to the 8085 at the addresses 30H-33H. So 33H
is the address of the control word. Here, the software polling method is used.
So the counter must be run and the program has to check whether the count is
completed for the predetermined period (here, 1 second). As the display has to
be incremented every second, a counter mode which has auto reload of the count
value has to be selected. So modes 2 or 3 can be used for this application. Counter
0 is selected and a 16-bit count value has to be loaded for the binary counter. The
mode 2 control word for the above configuration is given in Fig. 7.50.
Name SCI SCO RL1 RL0 M2 Ml M0 Binary/BCD
Value (34H) 0 0 1 1 0 1 0 0
Fig. 7.50 Control word value (Example 7.13)
The next step is to form the count value. The count value should be such that
the counter becomes 0 after counting the predetermined count value in 1 second.
So if the clock frequency for the counter operation is selected as 1 kHz, the counter
is decremented after every clock, i.e., after every 1 ms. So the count value of 1000
results in a delay of 1 second, when the counter becomes 0 after 1000 counts.
If the counter is designed to count in binary, then the count value 1000 must be
converted to binary and loaded into the counter as 3E8 (in hexadecimal form). If
the counter is designed to count in BCD, then the count value can be loaded in
BCD format as 1000.
The program consists of three parts. The first part is initializing the counter and
the count value. The clock signal must be applied to the selected counter’s clock
input pin. Here, the counter is operated in mode 2. So the count value need not be
loaded repeatedly after the count is over. The count value is reloaded automatically
after it becomes zero. The second part is checking whether the counter value has
become 0 using the software polling technique. In the software polling method,
the counter is first latched with a latch counter command control word. Then the
count value is read from the counter. After the 16-bit count value is loaded in the
processor registers, it is checked for occurrence of zero. This is done by performing
an OR operation on the two bytes. The third part is incrementing the display on the
seven-segment displays at port A of 8255. The program is given in Table 7.34.
Table 7.34 Program for interfacing the 8253 with the 8085 using polling method
OUT 43H ; Send it to the 8255 control register.
MVI A, OOH ; Load the initial data for the seven-segment
displays in the accumulator.
OUT 40H ; Send it to port A of the 8255.
STA 88OOH ; Store the displayed data in the memory.
MVI A, 34H ; Load the control word for the timer IC 8253 in the
accumulator.
MVI A, 0E8H ; Load the lower-order count value in the
accumulator.
(Contd)
Table 7.34 Program for interfacing the 8253 with the 8085 using polling method (Contd)

OUT 30H ; Output it to counter 0.
MVI A, 03H ; Load the higher-order count value in the
accumulator.
CHECK: MVI A, 04H ; Load the control word to latch the count value.
IN 30H ; Read the lower-order count value.
MOV B, A ; Store it in register B.
IN30H ; Read the higher-order count value.
GRAB ; Using OR operation, check whether the count
value has become 0.
JNZ CHECK ; If the count has not become 0, repeat latching and
reading of count value.
LDA 88OOH ; If the count value is 0, load the display data in the
accumulator.
ADI 01H ; Increment by 1.
DAA ; Adjust it to decimal value.
OUT 40H ; Send the incremented display data to port A of the
8255.
STA 8800H ; Save the display data in the memory.
JMP CHECK ; Loop back to check count value.
Example 7.14: Timer interface using interrupt method

The application given in Example 7.13 is to be repeated with the interrupt method.
Here, the counter is initialized and the counter starts counting. In mode 2, the
counter gives a logic 0 pulse for one clock period after the count is over. This
clock pulse is used as an interrupt signal for the 8085 processor. It is assumed
that the timer IC 8253 is interfaced to the 8085 at the addresses 3OH-33H and IC
8255 is interfaced at the addresses 40H-43H with two seven-segment displays
interfaced to the port A.
This interface uses the interrupt feature of the 8085 to increment the count
value in the displays at port A of the 8255. The timer IC is programmed to give an
interrupt signal every second. To achieve this, the 8253 is programmed to operate
in mode 2 and generate an Out signal after every second. In the interrupt service
routine, the display is incremented. In this example, the Out signal from the 8253
is connected to the RST 5.5 interrupt line of the 8085 as shown in Fig. 7.51. The
RST 5.5 requires an active high signal. However, the 8253 gives out an active low
signal whenever the counting is over in mode 2. So an inverter is connected to
provide an active high signal. The clock frequency applied at CLKO is selected as
1 kHz signal. GATEO is connected to logic 1.
Fig. 7.51 Interfacing 8253 timer 0 in interrupt driven mode
The program for interfacing the 8253 with the 8085 using the interrupt method
Table 7.35 Program for interfacing the 8253 with the 8085 using interrupt method

accumulator.
MVI A, OOH ; Load the initial data for the seven-segment
displays in the accumulator.
OUT 40H ; Send it to port A of the 8255.
STA 8800H ; Store the displayed data in the memory.
MVIA, 34H ; Load the control word for the timer IC 8253
in the accumulator.
OUT 33H ; Send it to the control register of the 8253.
MVI A, 0E8H ; Load the lower-order count value in the
accumulator.
MVI A, 03H ; Load the higher-order count value in the
accumulator.
; Main program continues.
RST5.5 ISR LDA 8800H ; Load the display data in the accumulator.
ADI01H ; Increment it by 1.
(Contd)
Table 7.35 Program for interfacing the 8253 with the 8085 using interrupt method (Contd)

DAA ; Adjust it to decimal value.
OUT 40H ; Send the incremented display data to port A
of the 8255.
STA 8800H ; Store the displayed data in the memory.
EI ; Enable interrupts again.
RET ; Return from the interrupt.
7.11 INTRODUCTION TO SERIAL COMMUNICATION

Serial communication is the process of sending and receiving information bit by
bit. For short-range communication, parallel data transfer is preferable as it is
the fastest means. When used over long distances, parallel communication needs
numerous wires and complex error handling/data recovery mechanisms. Moreover,
for parallel data transmission of n bits, both the receiver- and the transmitter-
side equipments need n separate amplifiers and related hardware. This results in
complex circuitry and high cost. Thus, serial communication is preferred for long-
range communication. It can be easily implemented using a single wire or a pair
of wires.
As the microcomputer uses parallel data, it is converted to serial form and
then transmitted. On receiving serial data, it is converted to parallel form and then
transferred to the microcomputer.
The terms commonly used in serial data systems are simplex, half-duplex,
and full-duplex. In simplex data transmission, data can be transferred only in
one direction. Examples of this type of system are radio, television, etc. In half
duplex transmission, communication can take place in either direction between
two systems but only in one direction at a time. An example of half-duplex
transmission is a two-way radio system, where one user listens while the other
talks. This is possible by turning off the receiver circuitry during transmission.
In full-duplex communication, both the receiver and the transmitter can send and
receive data at the same time. A normal telephone conversation is an example of a
full-duplex system.
Serial data can be sent either in synchronous mode or asynchronous mode.
In synchronous transmission, data is sent in blocks at a constant rate, i.e., the
frequencies of transmission and reception are the same. Transmission and reception
take place simultaneously. The beginning and end of a block are identified with
specific bytes or bit patterns. In general, synchronous transmission is used for high
transmission speeds of more than 20 kbits/second. In asynchronous transmission,
each data character has a bit to identify its start and one or two bits to identify its
end. Here, each character is identified individually. The characters can be sent
at any time, without checking the receiver. Reception and transmission are not
synchronized.
Figure 7.52 shows the bit format used for transmitting the asynchronous serial
data.
This format is also called frame. When no data is being sent, the signal line is
in a constant high level. The first data character is indicated by the line going low
for one bit duration and is usually called start bit. The data bits are then sent out
on the line one after another. Here, the least significant bit is sent out first. The
data bit is followed by an optional parity bit, which is used to check for errors in
received data. After the data bits and the parity bit, the signal bit is made high for
at least one bit duration to identify the end of character. This is referred to as stop
bit. Some systems may use two stop bits also.
Baud rate is the rate at which serial data is being transferred and in general
measured in bits/second. Baud rate = l/(Time between signal transitions). If
the signal is changing every 6.3 ms, then baud rate is 1/(6.3 x 10~3) or 600 Bd.
Common baud rates are 300, 600, 1200, 2400, 4800, 9600, and 19,200.
RS-232C is a standard that describes the function of the signal and handshake
pins for serial data transfer. A major problem with RS-232C is that it can transmit
data reliably for only about 50 ft (16.4 m) at its maximum rate of 20,000 Bd. If
longer lines are used, the transmission rate has to be drastically reduced. This
limitation is caused by the open signal lines with a single common ground that are
used in RS-232C.
The Electronics Industries Association (EIA) has a standard named RS-423A,
which is an improvement over RS-232C. This standard specifies a low-impedance
single-ended signal that can be sent over a 50 Q coaxial cable. Logic high in this
standard is represented by the signal line being between 4 V and 6 V negative
with respect to the ground and logic low is represented by the signal line being
from 4 V to 6 V positive with respect to the ground. The RS-423 standard allows a
maximum data range of 100,000 Bd on a 40-foot line or a maximum baud rate of
1000 Bd on a 4000-foot line.
RS-422A, another new standard for serial data transfer, specifies that each
signal will be sent differentially over two adjacent wires in a ribbon cable or a
twisted pair of wires. The term differential used in this standard means that the
signal voltage is developed between the two signal lines rather than between the
signal line and ground as in RS-232C and RS-423. In RS-422A, logic high is
transmitted by making the ‘b’ line more positive than the ‘a’ line. A logic low
is transmitted by making the ‘a’ line more positive than the ‘b’ line. The voltage
difference between the two lines must be greater than 0.4 V but less than 12 V.
Modem is a modulator and demodulator that sends digital Is and 0s as
modulated tones over standard phone lines. A modem is essential for transmitting
a signal over long distances. In the United States, modem standards are handled
by the Telecommunications Industry Association, which works closely with

the Comite Consultatif Internationale Telephonique et Telegraphique (CCITT),
which is part of the International Telecommunications Union. CCITT standards
that relate to modems start with ‘V’. Examples are V.22bis, which is a 2400-
bit/s modem standard, and the V.29, which is a 9600-bit/s modem standard.
The major modulation techniques used in modems are amplitude modulation,
frequency shift keying, phase shift keying, and multiple carrier modulation.
Modems can be directly connected to the microcomputer buses for establishing
serial communication between two systems.
Serial port transmission involves several technical terms and protocols. This
section focuses on the basic serial port IC Intel 8251 that can be interfaced with
any processor for data transmission and reception in serial manner.
7.11.1 Features and Details of 8251 USART

The 8251 is a universal synchronous asynchronous receiver transmitter (USART)
used for serial data communication. As a peripheral device in a microcomputer
system, the 8251 receives parallel data from the CPU and transmits them in serial
form. This device also receives serial data from outside, converts them into parallel
data, and sends them to the CPU. The 8251 can support both synchronous and
asynchronous transmission formats and is programmable. It supports full-duplex
serial transmission and reception and variable baud rates.
Figure 7.53 shows the internal block diagram of the 8251. It consists of a
parallel-to-serial shift register for transmission over the TXD line from the buffer
Fig. 7.53 Block diagram of the 8251 USART

and a serial-to-parallel converter for data received on the RXD line. A separate
control unit is available to determine the operation of the IC according to the control
word written into it. A modem control unit is present for interfacing a modem with
the 8251. In addition to these units, IC 8251 has an I/O port that can be used for
interfacing with any processor along with its read and write control logic. The
8251 requires clock and reset signals for working in a synchronized manner with
the processor. It has a 16-bit control register with which it can be programmed.
The status of operation of the 8251 can be read from the status register. These two
registers can be accessed by the processor by making C/D pin of the 8251 logic 1.
The data register can be accessed by making the C/D pin logic 0. Read operation
is used to read the serial data received and write operation is used to write the data
to be transmitted. The address line AO can be used as the C/D signal. So the 8251
uses two addresses—one for control and status and the other for data.
The basic operations of the 8251 are shown in Table 7.36.
Table 7.36 Basic operations of the 8251 and related control signals
CS C/D RD WR Function
1 X X X Chip not selected; data bus in high impedance state
0 X 1 1 Data bus in high impedance state
0 1 0 1 Status word read by CPU
0 1 1 0 Control word written into 8251 by CPU
0 0 0 1 Data read by CPU from 8251
0 0 1 0 Data written into 8251 by CPU
The 8251 has 28 pins. The details and functions of these pins are listed here.
(i) Data bus (D0-D7): A group of bidirectional lines that are used for data and
control word transfer between the CPU and the 8251
(ii) Reset: An active high signal applied to reset IC 8251. After resetting, the IC
has to be initialized again starting from the mode word.
(iii) CLK: The input signal used to apply a clock frequency to IC 8251. This
signal is used for the internal timing of all operations. This CLK frequency
must be higher than the transmit and receive clock frequency.
(iv) WR: Active low input signal, used to write data or command into IC 8251
(v) RD: Active low input signal, used to read data or status from IC 8251
(vi) C/D: Input signal used to select command/status or data. Input of 0 indicates
command/status; input of 1 indicates data.
(vii) CS: Active low input signal, used to select IC 8251. Any operation with the
IC can be done only when the CS signal is active low.
(viii) TXD: Transmit data line, used to send data out from the 8251
(ix) TXRDY (Transmit ready): Active high signal sent by the 8251 to the
processor, indicating that it is ready to accept a byte of data for transfer.
(x) TXEMPTY (Transmit buffer empty): Active high output signal, used to
indicate that the output register for transmitting data is empty.
(xi) TXC (Transmitter clock): Input clock signal used for transmitting or shifting
data to TXD line. The frequency of this signal decides the transmit baud rate.
(xii) RXD: Receive data line, used to receive data from another USART
(xiii) RXRDY (Receiver ready): Active high output signal to the processor,
indicating that it is ready with the received data.
(xiv) RXC (Receiver clock): Input clock signal, used for receiving and shifting
data on the RXD to the buffer. The frequency of this signal decides the
receive baud rate.
(xv) SYNDET/BD: Active high output. In asynchronous mode, it is used to
indicate a data break. In synchronous mode, it is used to indicate the correct
receipt of synchronous characters and the next data to be received.
The following signals are used with a modem for handshaking and establishing
connection:
(i) DTR: Active low output signal sent out by the 8251 to the modem, to
indicate that it is ready for communication
(ii) DSR: Active low input signal sent by the modem to indicate that it is ready
to transmit or receive
(iii) RTS: Active low output signal to the modem by the 8251, indicating that it
is ready to send data
(iv) CTS: Active low input signal sent by the modem, indicating that it can
accept data for transmission
7.11.2 Control Words

The 8251 operations should be initialized after resetting, but before using it. To
initialize it, the programmer must send the mode word and then the command word
to the control register address. There are two types of control word. One is mode
instruction (setting of function) and other is command (setting of operation).
7.11.2.1 Mode Command Word
The mode command word is written in the command port of the 8251 after
resetting. The first word written in the command port should follow the mode
command format. The mode command word (given in Table 7.37) is used to select
the operational functions of the 8251 such as synchronous or asynchronous mode,
number of data bits, number of stop bits, parity bit, baud rate, synchronization
methods, and synchronization characters.
Table 7.37 Mode instruction (asynchronous) bit configuration
D7 D6 D5 D4 D3 D2 D1 DO
S1 SO EP PEN L1 LO B1 BO
Frame control Parity check Character Baud rate select bits
stop bit length X0—Disable length 00—SYN mode
00—Inhibit 01—Odd parity 00—5 bits 01—IX clock
01—1 stop bit 10—Even 01—6 bits 10—16X clock
10—1.5 stop bits parity 10—7 bits 11—64X clock
11—2 bits 11—8 bits
For synchronous mode, it is necessary to write the synchronization characters

also. Therefore, more than one byte is required for the mode command. The mode
command word given in Table 7.37 is applicable if DI and DO bits are not 0. If DI
and DO are both 0, the mode command format in Table 7.38 is used.
Table 7.38 Mode instruction (synchronous) bit configuration
D7 D6 D5 - D4 D3 D2 D1 DO
SCS ESD EP PEN L1 LO 0 0
Number Synchronous Parity check Character length

of sync mode X0—Disable 00—5 bits
characters 0—Internal 01—Odd parity 01—6 bits
0—2 synchronization 10—Even parity 10—7 bits
characters 1—External 11—8 bits
1—1 character synchronization
7.11.2.2 Serial Command Word

It is necessary to write the serial command word after writing the mode command.
The serial command word is used to set functions such as transmit and receive
enable or disable, internal reset, error flag reset, and sending of break characters.
Figure 7.54 shows the various bit configurations for the 8251 command word.
Fig. 7.54 Command word bit configuration

7.11.2.3 Status Word

It is possible to identify the internal status of the 8251 by reading a status word.
The bit configuration of the status word is shown in Table 7.39. The programmer
can read the status information such as parity error, overrun error, framing error,
and the signal on the selected pins.
Table 7.39 Status word bit configuration
D7 D6 D5 D4 D3 D2 D1 DO
DSR SYNDET/BD FE OE PE TXEMPTY RXRDY TXRDY
Data set Same as in 1— 1—Overrun 1— Parity Same as Same Same
ready I/O pin Framing error error in I/O as in as in
0—DSR = 1 error pin I/O I/O pin
1—DSR = 0 pin
7.11.3 Interfacing 8251 with 8085

The interfacing of the serial port IC 8251 with the 8085 processor is shown in Fig.
7.55.
Fig. 7.55 Interfacing the 8251 with the 8085
The data bus lines D0-D7 are connected to the data lines of the 8251. The
higher-order address lines are used for address decoding and selection. The chip
selection signal CS is generated using an address decoder. The AO line is connected
to the C/D line of the 8251 to select either a control word or a data word. The
read and write control signals are connected to the corresponding signals of the
8251. The reset and clock output signals from the 8085 are connected to reset and
clock inputs of the 8251. In addition, the 8251 needs separate clock signals for
transmission and reception. These RXC and TXC clock signals can be obtained by
dividing the clock output from the 8085. This is not shown in Fig. 7.55.
Normally, two systems are interconnected using the serial port. For serial
communication, the TXD signal of one system is connected to RXD line of the
other system and vice versa. Care must be taken to ensure that the frequency of the
transmit clock of the transmitting computer is the same as that of the receive clock
of the receiving computer.
Programming the 8251 involves initializing the 8251 and then using it for data
transmission and reception. Initialization of the 8251 implies writing the mode
command word immediately after reset. The mode control word for synchronous
operation must be followed by the corresponding sync characters. Then the
command word for setting the parameters of the serial port is written into the
control register. Once the initialization is over, the 8251 is ready for transmission
and reception of data if proper clock signals are applied to it.
The serial data received is stored in the serial data buffer and the processor is
informed about the reception of data using the RXRDY signal. This signal may be
connected to an interrupt request in the 8085 and the corresponding interrupt service
routine can read the received data from the 8251. Programmers can also use the
status word read from the 8251 for checking whether data has been received or not.
Serial transmission is started by writing the data to be transmitted into the
data register of the 8251. The serial shifting of data into the TXD line starts
immediately. Once the transmission of data is over, the 8251 asserts the TXRDY
signal informing the processor that the 8251 is ready for transmission of the next
data. Programmers can also read the status word for checking whether data can be
written or not.
7.12 8259 PROGRAMMABLE INTERRUPT CONTROLLER

In a system, interrupts are used to handle routines such as reading ASCII characters
from a keyboard on interrupt basis, and detecting and performing emergency
operations such as sounding a fire alarm. For this purpose, the processor has
maskable and non-maskable interrupts. However, the processor has a limited
number of hardware interrupts. For applications that use interrupts from multiple
sources, the hardware can use an external device called Programmable Interrupt
Controller or Priority Interrupt Controller.
The Intel 8259 is a PIC designed and developed for use with the Intel 8085 and
Intel 8086 microprocessors. Although the 8259 family originally consisted of the
8259, 8259A, and 8259B PICs, a wide range of compatible chips are manufactured
today.
7.12.1 Features and Architecture of 8259

The basic operation of the interrupt mechanism lies in calling a subroutine whenever
a hardware interrupt signal is activated. When multiple interrupt sources are
present, the process of calling the interrupt subroutine involves priority resolving
and checking masks. The main purpose of using the 8259 interrupt controller is to
do the task of calling the interrupt service routine based on the interrupt priority
and masks. The 8259 acts as a multiplexer as it combines multiple interrupt input
sources into a single interrupt request.
The main features of the 8259 are as follows:
(i) It supports eight interrupts inputs from the peripherals and issues a single
interrupt signal to the processor.
(ii) It supports cascading of eight 8259 ICs and multiplexes 64 interrupt sources
into one.
(iii) It can set priorities for the interrupts, mask the interrupt sources, and provide
different interrupt vector addresses.
IC 8259 receives interrupts from different sources, resolves their priorities and
masking, and then passes the interrupt to the processor along with the interrupt
vector address.
In 8085-based systems, the interrupt vector address is provided by a three-byte
CALL instruction. In 8086-based systems, it is provided by an 8-bit vector number.
It can be operated in polled and vectored mode. The starting address of the ISR or
vector number is programmable. No clock is required for the IC.
Using the read/write logic, the 8259 is interfaced with the processor. The data
bus lines D0-D7 are connected to the data lines of the processor. The 8259 chip
is selected using the CS line. The address line AO is used to select the control
word or the data word. If AO is low, the controller selects the writing a command
word/reading a status option. If AO is high, the controller selects another register
for writing the initialization words.
The control logic has the signals INT and INTA. The INT output pin is used
to interrupt the CPU. The 8259 receives the interrupt acknowledge pulse from the
CPU through its INTA input. The 8259 can receive interrupt signals from eight
different sources on the lines IR0-IR7. When these lines go high, the requests are
stored in the interrupt request register (IRR). The interrupt service register (ISR)
stores all the levels that are currently being serviced. The interrupt mask register
(IMR) stores the masking bits of the interrupt lines to be masked. The priority
resolver examines the interrupt registers and determines whether the INT signal
should be sent to the microprocessor or not. The internal block diagram of the
interrupt controller is shown in Fig. 7.56.
The 8259 can be used in cascaded mode. The cascade buffer or comparator is
Fig. 7.56 8259 internal block diagram

used to expand the number of interrupt levels by cascading two or more 8259s. It
can cascade a maximum of eight ICs.
The following three registers are used to program and control the operation of
IC 8259:
(i) Interrupt mask register (IMR)
(ii) Interrupt request register (IRR)
(iii) In-service register (ISR)
The interrupt mask register is used to program the masking of external interrupt
sources. This register is written into by the programmer. The interrupt request
register is used to store the interrupts that have been sensed by the 8259 at its
inputs. The in-service register maintains the list of interrupts that are currently
being serviced and the corresponding service routine that is being executed.
7.12.2 Pin Diagram and Details of 8259

The main signals in the 8259 are as follows:
(i) Eight external interrupt request input lines—IR0-IR7
(ii) An interrupt request output line INT to be connected to the processor
(iii) Interrupt acknowledgment input INTA from the processor
(iv) Bidirectional data bus lines D0-D7 for data or commands from the
processor
(v) Control signals CAS0-CAS2 for cascading 8259s
(vi) Active low read control signal RD
(vii) Active low write control signal WR
(viii) Select line AO to select the control registers
(ix) Active low chip select line CS
(x) Select line SP/EN to
1 28 □
make the 8259 aslave cs Vcc
or a master wr 2□ 27 AO □
3 26 INTA
Figure 7.57 shows the pin RD
diagram of the 8259. D7 □ 4 25 IR7
7.12.3 Initialization of 8259

□ 5 24 IR6
D5 6 23 IR5
To service the interrupt
D4 7 22 IR4
requests, the interrupt controller 8259
8 21 IR3
should be initialized by writing D3 i
20 IR2 t
control words in the control D2 9
register. It requires two types of di 10 19 IR1
control words—initialization
command words (ICWs) and
D0 □ 11 18 IRO
12 17 INT
operational command words 16 SP/EN
13
(OCWs). The ICWs are used
15 CAS2
to set up the appropriate initial GND
conditions and specify the
restart vector location. The Fig 7.57 Pin diagram of the 8259
OCWs are used for masking interrupts, setting up status read operations, etc. The
8259 can be initialized with four ICWs, of which the first two are essential and other
two are optional, based on the modes being used. These words must be issued in a
given sequence. Once initialized, the interrupt controller can be set up to operate
in various modes using three different operational command words. Figure 7.58
shows the sequence in which the IC 8259 must be initialized. Operation command
words can be written into the 8259 at any time to perform specific functions.
Fig. 7.58 Sequence for 8259 initialization
7.12.3.1 Format of ICW1 (Initialization Command Word 1)

ICW1 is the first initialization command word that should be written into the 8259,
with AO = 0. This should be followed by ICW2. The 8-bit data has the format
shown in Table 7.40. The D2 bit ADI is used to set the address interval in the
interrupt vector table. It is used only in the 8085 and not in the 8086. If it is 1, the
ISR addresses are 4 bytes apart (0200, 0204, etc.). If it is 0, the ISR addresses are
8 bytes apart (0200, 0208, etc.). The D3 bit LTIM is used to indicate details about
the hardware signal used in the IRQ lines. It is used to select whether the signal is
level-triggered or edge-triggered. D4—D7 bits are used to specify the higher-order
bits of the lower byte of the ISR vector address. The higher-order bits are A7, A6,
and A5 if ADI = 1, and A7 and A6 only if ADI = 0. The remaining bits A4-A0 (or
A5-A0) are set by the 8259. This is applicable to the 8085 only.
Table 7.40 Format of ICW1
D7 D6 D5 D4 D3 D2 D1 DO
A7 A6 A5 1 LTIM ADI SNGL ICW4
Address lines Requirement
Level-triggered Address interval 1—Single
A5-A7 of for ICW4
interrupt mode 1—4 bytes apart PIC
interrupt vector 0—No ICW4
1 —Level-triggered 0—8 bytes apart 0—Cascaded
address 1—ICW4
0—Edge-triggered (For 8085 only) PIC
(For 8085 only) required
7.12.3.2 Format oflCW2 (Initialization Command Word 2)

In the 8085, ICW2 is used to set the higher-order eight bits of the interrupt vector
addresses. In the 8086, it defines the 8-bit vector address. This initialization word
is written into the 8259 with AO = 1.

ICW3 is required only when the 8259 is connected in cascaded mode, i.e., more
than one 8259 is connected in the system. This initialization word is written into
the 8259 with AO = 1. The format of ICW3 is given in Fig. 7.59.
D7 D6 D5 D4 D3 D2 D1 DO
Master S7 S6 S5 S4 S3 S2 SI SO
Slave 0 0 0 0 0 ID2 ID1 IDO
Fig. 7.59 Format of ICW3
There are two different ICW3 formats—one for the master and the other for the
slave.
(i) For the master mode, ICW3 is used to indicate whether a slave 8259 is
connected in the interrupt request line IRQ or not. If a bit is 1, it indicates
that slave is present on that interrupt request line. A 0 in a bit position
indicates it is a direct interrupt request from an external device.
(ii) For the slave mode, ICW3 assigns the slave a specific ID, using the three
least significant bits. ID0-ID2 is the slave ID number. For example, slave 4
has ICW3 = 04H (00000100).

ICW4 is necessary only when its requirement is mentioned in ICW1. It is used to
indicate whether the 8085 or the 8086 is being used in the system. It also indicates
the usage of end of interrupt mode, buffered/non-buffered mode, and special fully
nested mode. The format of ICW4 is given in Table 7.41. This initialization word
is written into the 8259 with A0 = 1.
Table 7.41 Format of ICW4
D7 D6 D5 D4 D3 D2
D1 DO
SFNM AEOI
1—Special fully BUF M/S 1—Auto end Mode
0 0 0 nested mode 0—Non-buffered 1—Master of interrupt 0—8085
0—Not special 1—Buffered 0—Slave 0—Normal 1—8086
fully nested mode mode
7.12.3.5 0CIV7 (Operational Command Word 1)

OCW1 is written into the 8259 with AO = 1. This word is used to mask the
interrupt requests IR0-IR7. The eight bits of the OCW1 are used to mask the
eight interrupts, with the LSB DO masking IRO and the MSB D7 masking IR7. A
particular interrupt IRn is masked by setting the corresponding bit Mn to 1; the
mask is cleared by setting the corresponding bit Mn to 0 (where n is the number of
the bit and ranges from 0 to 7). The format of OCW1 is given in Fig. 7.60.
D7 D6 D5 D4 D3 D2 D1 DO
M7 M6 M5 M4 M3 M2 Ml M0
Fig. 7.60 Format of 0CW1
7.12.3.6 0CW2 (Operational Command Word 2)

OCW2 is written into the 8259 with AO = 1. This word is used to specify priorities
of interrupts and issue of end of interrupt commands. OCW2 is usually written
to reset the bit in the in-service register. Normally, a bit is set in the in-service
register when the corresponding interrupt is being serviced. OCW2 is generally
written at the end of the interrupt service routine. The OCW2 can be programmed
for non-specific end of interrupt mode with the data 0010 0000 to automatically
reset the in-service register (ISR) bit. The programmer can also use OCW2 to reset
a specific ISR bit and rotate the priorities of the interrupts. Figure 7.61 shows the
bit format of 0CW2.
D7 D6 D5 D4 D3 D2 D1 DO
R SL EOI 0 0 L3 L2 LI
Fig. 7.61 Format of 0CW2
Table 7.42 lists the functions of the individual bits in OCW2.
Table 7.42 Function of 0CW2 bits
D7-D5 R SL EOI Action

EOI 0 0 1 Non-specific EOI (L3L2L1 = 000); reset all
bits of the in-service register
0 1 1 Specific EOI command—Clear the bits
encoded by L3, L2, and LI in the in-service
regis,er (Contd)
Table 7.42 Function of 0CW2 bits (Contd)
D7-D5 R SL EOI Action

Auto rotation of 1 0 1 Rotate priorities on non-specific EOI command
priorities 0 Set—Rotate priorities in auto EOI mode set
1 0
(L3L2L1 =000)
0 0 0 Clear—Rotate priorities in auto EOI mode
Specific rotation of 1 1 1 Rotate priority on specific EOI command (reset
priorities (lowest current ISR bit)
priority ISR = L3L2L1)
1 1 0 Set priority (does not reset current ISR bit)
0 1 0 No operation
7.12.3.7 0CW3 (Operational Command Word 3)

0CW3 is used to specify special masking of interrupts. The format of 0CW3 is
given in Table 7.43. More information about this command can be obtained from
the .Intel datasheet.
Table 7.43 Format of 0CW3
D7 D6 D5 D4 D3 D2 D1 DO
0 ESMM SMM 0 1 P RR RIS
OX—No effect
OX—No effect 10—Read IR register
0—Polling
10—Reset special mask on next read
1—No Polling
11—Set special mask 11—Read IS register
on next read
7.12.4 Operation of 8259

The following steps show how interrupt handling is done when an external device
places an interrupt request on the IR lines of the 8259. It is assumed that the
system has a single 8259 chip.
(i) One or more of the IR lines may go high.
(ii) Corresponding IRR bit is set.
(iii) The 8259 evaluates the request based on masking and priority.
(iv) The 8259 sends the interrupt request INT to the CPU.
(v) The CPU sends INTA.
(vi) The highest priority ISR is set and IRR is reset.
(vii) The 8259 releases the CALL instruction on the data bus.
(viii) The CALL instruction causes the CPU to initiate two more INTAs. The
processor sends the two interrupt acknowledge pulses on its INTA pin to
the INTA pin of the 8259. The INTA pulses tell the 8259 to send the desired
interrupt type to the processor. The 8259 releases the subroutine address,
first the lower-order byte and then the higher-order byte. The interrupt
service routine is executed in the processor with the following steps.
(a) The flags are pushed onto the stack.

(b) The interrupt and trap flags of the processor are cleared.
(c) The return address is pushed onto the stack.
(d) The inteiTupt vector address is loaded in the program counter/instruction
pointer.
(e) The interrupt service routine is executed.
(f) ISR bit is reset depending on the mode in the 8259.
7.12.5 Interfacing 8259 with 8085

Figure 7.62 shows the connection diagram for interfacing 8259 with the 8-bit
processor 8085.
The 8259 requires two addresses, with AO being 0 and 1. The AO line from the
address bus is connected to the AO line in the 8259. The higher-order address bus
is used to select a particular chip using an address decoder. The read and write
control signals of the 8085 are connected to the corresponding signals of the 8259.
The data lines of the 8259 are connected to the multiplexed lower-order address
and data buses of the 8085. The multi-purpose SP/EN pin is tied to logic high
because only one 8259 is used in the system. The interrupt request line INT of the
8259 is connected to the 8085’s interrupt line INTR. The INTA line of the 8085 is
connected to the INTA line of the 8259. When only one 8259 is used in a system,
the cascade lines (CASO, CAS1, CAS2) can be left open. The eight IR inputs of
the 8259 can be connected to the interrupt sources from various external devices
such as A/D converter, keyboard, and printer. Unused IR inputs must be tied to the
ground in order to avoid noise being recognized as an interrupt signal.
Initializing the 8259 involves writing the initialization command words in
proper sequence, as shown in Fig. 7.58. After initialization, the operation command
words can be written as and when required.
7.13 8237 DMA CONTROLLER

Programmed data transfers involve moving data from the memory into the
accumulator, and then from the accumulator to the output ports. A program has to
be written to transfer data from a device to the memory. Thus, programmed data
transfer is a slow process. This causes a problem while transferring large amounts
of data.
DMA stands for direct memory access. It is one of the ways to accomplish
high-speed data transfer directly between the memory and peripheral devices,
without the intervention of the microprocessor. This method is often used when a
large block of data is to be transferred.
DMA data transfer is controlled using a separate DMA controller. The
microprocessor must be disabled during the DMA data transfer process. To start
the DMA process, the microprocessor loads an external register in the DMA
controller with the data file’s starting address and the terminal count register
with the total number of bytes to be transferred. The microprocessor disables the
address and data buses and gives memory system control to the DMA controller.
The DMA controller places sequential addresses on the microprocessor’s memory
bus and issues the read-write pulses. As each byte is transferred, the terminal
count register is decremented. When the register is decremented to 0, it tells the
external device that the data transfer is complete.
As this is a limited application, a special-purpose hardware controller can do
it very quickly. DMA transfers take place with speeds close to the memory cycle
time. Once the DMA controller has finished transferring data into or out of memory,
the DMA controller gives control back to the microprocessor. The microprocessor
cannot accomplish any other function when a DMA transfer is taking place. This
is due to two reasons. First, the microprocessor’s memory is being used for a data
transfer. It is not available to supply program instructions or receive the results of
computations. Second, the typical DMA process requires that the microprocessor
place its memory address bus and data bus in a high impedance condition. This
high impedance condition allows the DMA controller and the memory system to
control the bus, but prevents the microprocessor from providing any bus control.
Thus, the DMA controller temporarily borrows the address bus, data bus, and
control bus from the microprocessor and transfers the data bytes directly from the
external peripheral devices to a series of memory locations. Since the data transfer
is done by hardware means, it is much faster than it would be if done by program
instructions. In this section, we shall discuss Intel’s DMA controller chip 8237 in
detail.
7.13.1 Features, Pin Details, and Architecture of 8237

The main features of the 8237 are as follows:
(i) Four independent DMA channels
(ii) Enable and disable control of individual requests
(iii) Possibility of memory-to-memory transfer
(iv) Address increment or decrement
(v) Cascading to expand to any number of DMA channels
Figure 7.63 shows the block diagram of the 8237.
The data bus buffer, timing and control block, DMA channels, corresponding
priority block, read/write control logic, and internal registers are the main
components of the 8237. The data bus consists of eight tri-state pins DB0-DB7.
Fig. 7.63 Block diagram of the 8237
Figure 7.64 shows the pin details of the 8237.
IOR □ ~40 □ A7
low □ 2 39 □ A6
V<x ^ss
MEMR □ 3 38 □ A5
MEMW □ 4 37 □ A4 A0-A3
NC □ 5 36 L EOP A4-A7
DB0-DB7
READY □ 6 35 E A3
DMA
34 E A2 handshake
HLDA e ADSTB signals
33 E A1
ADSTB □ 8 AEN <^DRQ(P-DRQ3
Control
32 E AO
AEN E 9 8237 signals MEMR
DMA requests
I Vcc
from
31 for the four
HRQ □ 10 and to MEMW 8237
DBO memory channels
CS □ 11 30 E
Control IOW
29 E DB1
CLK □ 12 signals
EOP DACK0-DACK3
DB2 from
RESET c 13 28 E and to DMA
DB3 peripherals READY acknowledge
DACK2 □ 14 27 E
-------- >HR0
26 E DB4 RESET
DACK3 □ 15 •HLDA
25 E DACKO CLK
DREQ3 □ 16
DREQ2 17 24 E DACK1
23 E DB5
DREQ1 □ 18 ▼
22 DB6 CS
DREQO 19
21 E DB7
(GND)VU □ 20
fig. 7.64 Pin details of the 8237

These pins are connected to the system data bus. The programming of the 8237
is done through this data bus. A0-A3 pins are used to select one of the internal
registers when the 8237 is in the slave mode under the control of the processor.
A4-A7 lines, along with the A0-A3 lines, are used to send the higher-order 8-bit
addresses when the 8237 is acting as master and doing DMA data transfer. The
timing and control block derives internal timing from clock input and generates
external control signals. The 8237 has four separate DMA channels and each
channel includes two 16-bit registers, a DMA register, and a count register.
DRQ0-DRQ3 are the four DMA request signals input to the 8237 by external
peripheral devices. These four requests can be prioritized. The priority encoder
block resolves priority contention between DMA channels requesting service
simultaneously. The details of the 8237 pins are as follows:
(i) DB0-DB7 (I/O data bus): The data bus lines are bidirectional three-state
signals connected to the system data bus, which carries data.
(ii) CLK (clock input): The clock input is used to generate the timing signals
that control 82C37A operations. This input may be driven from DC to 12.5
MHz for the 82C37A-12, from DC to 8 MHz for the 82C37A, and from DC
to 5 MHz for the 82C37A-5. The clock may be stopped either in 1 state or
in 0 state for standby operation.
(iii) CS (Chip Select): Chip Select is an active low input used to enable the
controller.
(iv) Reset: This is an active high input which clears the command, status,
request, and temporary registers, the first/last flip-flop, and the mode register
counter. The mask register is set to ignore requests. Following a reset, the
controller is in an idle cycle.
(v) Ready: This signal can be used to extend the memory read and write pulses
from the 8237 to accommodate slow memories or I/O devices.
(vi) HLDA (Hold Acknowledge): The active high Hold Acknowledge from the
CPU indicates that it has handed over control of the system buses.
(vii) DREQ0-DREQ3 (DMA request): The DMA request (DREQ) lines are
individual asynchronous channel request inputs used by peripheral circuits
to obtain DMA service. In fixed priority mode, DREQO has the highest
priority and DREQ3 has the lowest priority. A request can be generated
by activating the DREQ line of a channel. The polarity of the DREQ is
programmable. Reset signal initializes these lines to active high. The DREQ
must be maintained until the corresponding DACK goes active. It will not
be recognized while the clock is stopped.
(viii) IOR (I/O read): I/O read is a bidirectional active low three-state line. In the idle
or slave mode, it is an input control signal used by the CPU to read the control
registers. In the active or master mode, it is an output control signal used by the
8237 to access data from the peripheral during a DMA write transfer.
(ix) IOW (I/O write): I/O write is a bidirectional active low three-state line. In the
idle cycle, it is an input control signal used by the CPU to load information
into the 8237. In the active cycle, it is an output control signal used by the
8237 to load data in the peripheral during a DMA read transfer.
(x) EOP (endof process): EOP is an active low bidirectional signal. Information
concerning the completion of DMA services is available at the bidirectional
EOP pin. A pulse is generated by the 8237 when terminal count (TC) for
any channel is reached, except for channel 0 in memory-to-memory mode.
(xi) A0-A3 (I/O address): The four least significant address lines are bidirectional
three-state signals. In the idle cycle, they are inputs and are used by the
8237 to address the control register to be loaded or read. In the active cycle,
they are outputs and provide the lower four bits of the output address.
(xii) A4-A7 (address): The four most significant address lines are three-state
outputs and provide four bits of address. These lines are enabled only during
the DMA service.
(xiii) HRQ (Hold Request): The Hold Request (HRQ) output is used to request
control of the system bus. When a DREQ occurs and the corresponding
mask bit is clear, or a software DMA request is made, the 82C37A issues
HRQ. The HLDA signal then informs the controller when access to the
system buses is permitted.
(xiv) DACK0-DACK3 (DMA Acknowledge): DMA Acknowledge is used to
notify the individual peripherals when one has been granted a DMA cycle.
DACK acknowledges the recognition of a DREQ signal.
(xv) AEN (Address Enable): The address enable signal is an active high signal
used to indicate the availability of the higher-order 8-bit address. It can be
used by the latch to store the address. AEN can also be used to disable other
system bus drivers during DMA transfers. AEN is an active high signal.
(xvi) ADSTB (Address Strobe): This is an active high signal used to control
latching of the upper address byte.
(xvii) MEMR (Memory Read): The Memory Read signal is an active low three-
state output used to access data from the selected memory location during a
DMA read or a memory-to-memory transfer.
(xviii) MEMW (Memory Write): The Memory Write signal is an active low three-
state output used to write data to the selected memory location during a
DMA write or a memory-to-memory transfer.
Table 7.44 lists the names and sizes of the internal registers of the 8237.
Table 7.44 Internal registers in the 8237
Name Size
Base address registers 16 bits
Base word count registers 16 bits
Current address registers 16 bits
Current word count registers 16 bits
Temporary address register 16 bits
Temporary word count register 16 bits
Status register 8 bits
Command register 8 bits
Temporary register 8 bits
Mode registers 6 bits
Mask register 4 bits
Request register 4 bits
The internal registers of the 8237 are explained in this section.

Current address register Each channel has a 16-bit current address register.
This register holds the value of the address used during DMA transfers. The
address is automatically incremented or decremented (by one) after each transfer
and the values of the addresses are stored in the current address register during
the transfer. This register is written into or read from by the microprocessor in
successive 8-bit bytes.
Current word count register Each channel has a 16-bit current word count
register. This register determines the number of transfers to be performed. The
actual number of transfers is one more than the number programmed in the current
word count register (i.e., programming a count of 50 will result in 51 transfers).
The word count is decremented after each transfer. When the value in the register
goes from 0000H to FFFFH, a terminal count (TC) is generated. This register is
loaded or read in successive 8-bit bytes by the microprocessor in the program
condition.
Base address and base word count registers Each channel has a pair of base
address and base word count registers. These 16-bit registers store the original
value of their associated current registers. These registers cannot be read by the
microprocessor.
Command register This 8-bit register controls the operation of the 8237. It
is programmed by the microprocessor and is cleared by the reset or master clear
instruction. Figure 7.65 lists the function of the command register bits.
Mode register Each channel has a mode register associated with it. When the
register is being written into by the microprocessor in the program condition, the
least significant bits 0 and 1 determine which channel is chosen. Figure 7.66 lists
the details of the mode register bits.
Bit number
00—Select channel 0
XX—Readback
00—Verify transfer
01—Write transfer
10—Read transfer
11—Illegal
XX—If bits 6 and 7 = 11
0—Auto initialization disable

1—Auto initialization enable
0—Address increment select

1—Address decrement select
00—Demand mode select

01—Single mode select
10—Block mode select
11—Cascade mode select
Fig, 7.66 Mode register
Request register The 8237 can respond to requests for DMA service that are
initiated by software or by DREQ input. Each channel has a request bit associated
with it in the 4-bit request register. These are non-maskable and subject to
prioritization by the priority encoder network. Each register bit is set or reset
separately under software control. The entire register is cleared by a reset or
master clear instruction. Figure 7.67 shows the format of the request register and
its address coding. A software request for DMA operation can be made in block
mode or single mode. While reading the request register, bits 4-7 will always
read as Is, and bits 0-3 will display the request bits of channels 0-3, respectively.
Figure 7.67 shows the request register bits.
1—Set request bit

Fig. 7.67 Request register
Mask register Each channel has a mask bit associated with it that can be set
to disable an incoming DREQ. Each mask bit is set when its associated channel
produces an EOP, if the channel is not programmed to auto-initialize. Each bit of

the 4-bit mask register may also be set or cleared separately or simultaneously
under software control. The entire register is also set by a reset or master clear.
This disables all hardware DMA requests until a clear mask register instruction
allows them to occur. Figures 7.68 (a) and 7.68 (b) show the mask register format.
While reading the mask register, bits 4-7 will always read as Is, and bits 0 to 3 will
display the mask bits of channels 0 to 3, respectively. The four bits of the mask
register may be cleared simultaneously by using the clear mask register command.
All four bits of the mask register may also be written with a single command.
Bit number
00—Select channel 0 mask bit
0—Clear mask bit

1—Set mask bit
(b)
Fig. 7.68 (a) Mask register (format 1) (b) Mask register (format 2)
Status register The status register contains information about the status of the
devices, to be read by the processor at any time. The format of status register is
shown in Fig. 7.69. This information includes which channels have reached a
terminal count and which channels have pending DMA requests. Bits 0-3 are set
every time a TC is reached by that channel or an external EOP is applied. These
bits are cleared upon reset, master clear, and each status read operation. Bits 4-7
are set when their corresponding channels request service, irrespective of the mask
bit state. If the mask bits are set software can poll the status register to determine
which channels have DREQs, and selectively clear a mask bit, thus allowing user
defined service priority. Status bits 4-7 are updated while the clock is high. They
are cleared upon reset or master clear.
Temporary register The temporary register is used to hold data during
memory-to-memory transfers. The temporary register always contains the last
byte transferred in the previous memory-to-memory operation, if not cleared by a
reset or master clear.
Fig. 7.69 Status register
7.13.2 DMA Initialization and Operation

Initializing the 8237 requires a large number of bytes to be written into the
registers mentioned in Section 7.13.1.1. The 8237 is connected as I/O port with
the processor. In the idle cycle or idle mode, the 8237 A0-A3 lines are used to
program the internal registers and operation of the DMA controller. As discussed
earlier, the 8237 has four channels for DMA request. So it has separate registers
to hold the base memory address, current memory address, and the count register
in each channel. In general, Al and A2 are used to select one of the four DMA
channel registers and AO is used to select the memory address or count register.
The DMA channel registers are accessed when A3 = 0. If A3 = 1, the other control
registers are accessed as shown in Table 7.45.
Table 7.45 Selection of control registers using control signals
Operation A3 A2 A1 AO IOR IOW
Read status register 1 0 0 0 0 1

Write command register 1 0 0 0 1 0
Read request register 1 0 0 10 1
Write request register 1 0 0 110
Read command register 1 0 10 0 1
Write single mask bit 1 0 10 10
Read mode register 1 0 110 1
Write mode register 1 0 1110
Set first/last F/F 1 1 0 0 0 1
Clear first/last F/F 1 10 0 1 0
Read temporary register 1 10 10 1
(Contd)
Table 7.45 Selection of control registers using control signals (Contd)
Operation A3 A2 A1 AO IOR IOW
Clear mode register counter 1 1 1 0 0 1
Clear mask register 1 1 1 0 1 0
Read all mask bits 1 1 1 1 0 1

Write all mask bits 1 1 1 1 1 0
The DMA controller operates in two major cycles, active and idle. After being
programmed, the controller is normally idle until a DMA request occurs on an
unmasked channel or a software request is given. The 8237 will then request control
of the system buses and enter the active cycle. The active cycle is composed of
several internal states, depending on what options have been selected and what
type of operation has been requested.
7.13.2.1 Idle Cycle
When no channel is requesting service, the 8237 enters the idle cycle. In this
cycle, the 8237 samples the DREQ lines on the falling edge of every clock cycle
to determine if any channel is requesting a DMA service.
7.13.2.2 Active Cycle
When the 8237 is in the idle cycle, and a software request or an unmasked
channel requests a DMA service, the device issues a hold request (HRQ) to the
microprocessor and enters the active cycle. It is in this cycle that the DMA service
takes place, in one of the following four modes:
Single transfer mode In single transfer mode, the device is programmed to make
one transfer only. The word count is decremented and the address decremented or
incremented following each transfer. When the word count rolls over from 0000H
to FFFFH, a terminal count bit in the status register is set and an EOP pulse is
generated. DREQ must be held active until DACK becomes active. If DREQ is
held active throughout the single transfer, HRQ becomes inactive and releases
the bus to the system. It becomes active again and upon receipt of a new HLDA,
another single transfer is performed. An exception to this occurs when a higher
priority channel takes over.
Block transfer mode In block transfer mode, the device is activated by DREQ
or a software request and continues making transfers until a TC, caused by the
word count going to FFFFH, or an external end of process (EOP) is encountered.
DREQ need only be held active until DACK becomes active.
Demand transfer mode In demand transfer mode the device continues making
transfers until aTC or an external EOP is encountered, or until DREQ goes inactive.
The data transfer continues until the I/O device has exhausted its data capacity.
Higher priority channels may intervene in the demand process, once DREQ has
gone inactive. EOP is generated either by a TC or by an external signal.
Cascade mode This mode is used to cascade more than one 8237 for simple
system expansion. The HRQ and HLDA signals from the additional 8237 are
connected to the DREQ and DACK signals, respectively, of a channel for the initial
8237. This allows the DMA requests of the additional device to propagate through
the priority network circuitry of the preceding device. Figure 7.70 shows two
additional devices cascaded with an initial device using two of the initial device’s
channels. This forms a two-level DMA system. More 8237s could be added at the
second level using the remaining channels of the first level. Additional devices can
also be added by cascading into the channels of the second level devices, forming
a third level.
Second level
Additional devices
Fig. 7.70 Cascaded 8237s
7.13.3 Operation of 8237 with 8085

The block diagram in Fig. 7.71 shows how DMA transfer takes place between a
memory and I/O device with the help of a DMA controller. Here, the microprocessor
and the DMA controller timeshare the address, data, and control buses. The DMA
controller can control the system bus after issuing a Hold signal to the processor.
However, when the processor is controlling the bus, the DMA controller pins are
in high impedance state. When the DMA controller is active, the processor bus
enters into high impedance state. During the active period of DMA controller, the
8237 can drive the buses and issue the control signals.
When the system is first turned on, the buses are connected from the
microprocessor to the system memory and peripherals. Then, all the programmable
devices in the system are initialized and the routine programs are executed until
there is a need for data transfer.
The operation performed by activating one of the four DMA request inputs has
to be programmed first into the controller via the command, mode, address, and
word count registers. The sequence of operations involved in the DMA method of
data transfer is explained in Fig. 7.72.
Fig. 7.71 Interfacing the DMA controller with the processor
Fig. 7.72 Sequence of operations in direct memory access
The following sequence explains the DMA method of data transfer in detail.
j) The DMA controller is initialized by writing the proper control words, the
data count (i.e., amount of data to be transferred), and the starting address
for data transfer in the address registers.
ii) The mode register is programmed for proper data transfer.
ii) The appropriate bits are selected to enable the DMA operation.
(iv) When the peripheral device has the first byte of data ready, it sends a DMA
request, i.e., DREQ signal, to the DMA controller.
(v) If the input (channel) of the DMA controller is unmasked, the DMA
controller sends a hold request, i.e., HRQ signal to the microprocessor
HOLD input.
(vi) The microprocessor responds to this input by floating its buses and sends a
hold acknowledge signal to the DMA controller.
(vii) When the DMA controller receives the HLDA signal, it sends out a control
signal, disconnects the processor from the buses, and connects the DMA
controller to the buses.
(viii) When the DMA controller gets control of the buses, it sends out the
memory address where the first byte of data from the peripheral device is to
be written.
(ix) Then the DMA controller sends a DMA acknowledge, i.e., DACKO signal
to the peripheral device to tell it to get ready for the byte.
(x) Finally, the DMA controller asserts both the MEMW and the IOR lines on
the control bus.
(xi) Asserting the MEMW signal enables the addressed memory to accept data
written into it.
(xii) Asserting the IOR signal enables the disk controller to output the byte of
data from the disk to the data bus.
(xiii) The byte of data is then transferred directly from the peripheral device to the
memory location without passing through the CPU or the DMA controller.
(xiv) When the data transfer is complete, the DMA controller resets its hold
request signal to the processor and releases the buses. This lets the processor
take over the buses again until another DMA transfer is needed.
(xv) The processor continues executing from where it left off in the program.
POINTS TO REMEMBER
• The Intel processor IC 8085 needs additional slave chips like programmable peripheral
interfaces, keyboard/display interfaces, serial ports, timers, interrupt controllers, and
DMA controllers.
• Intel IC 8255 is a general-purpose programmable peripheral interface and can be used
to interface other devices like seven-segment displays, switches, ADCs, DACs, etc.
• Multiplexed displays and matrix keyboards reduce hardware complexity and can be
easily implemented using the slave IC Intel 8279.
• Serial data transmission can be easily done by the processor by interfacing the USART
8251 IC.
• The timing of various events can be controlled by the programmer by interfacing timer
ICs such as 8253 with the processor and connecting a clock to it.
• There is a need for a programmable interrupt controller if the number of peripherals
interfaced using the interrupt driven I/O method is higher than the interrupt capability
of the processor. Intel provides the programmable interrupt controller IC 8259 for such
applications.
• High speed data transfer between I/O devices and the processor can be achieved using a
technique called direct memory access. The DMA controller IC 8237 can be interfaced
with the processor to achieve direct memory access of memory by I/O devices.
Active cycle This is the cycle during which DMA service takes place.
Analog-to-digital converter The ADC converts the input analog voltage levels to
corresponding discrete digital signals.
Asynchronous transmission It is the method of serial data transfer done without a
common clock but at a common baud rate; it is character-oriented.
Baud rate The rate at which serial data is being transferred is called baud rate.
Bit set-reset mode The BSR mode is applied to port C of the 8255 for setting and
resetting individual port C bits.
Block transfer mode This is the mode in which the device that is activated by DREQ or
software request continues making transfers during the service until a TC caused by word
count going to FFFFH, or an external end of process (EOP) is encountered.
Cascade mode This is the mode in which the system is constructed using more than one
8237 cascaded for simple system expansion.
Cascading It is a method of connecting more than one 8259 in a microcomputer system,
to increase the number of interrupt sources.
Command instruction It is used for setting the operation features of the 8251.
Control word It contains information such as mode, bit set, and bit reset, that initializes
the functional configuration of the 8255.
Control words These are used to initialize each counter of the 8253. They program the
mode, loading sequence, and mode of counting (binary or BCD).
Counting This is the process of counting pulses applied at a random period and time.
Demand transfer mode This is the mode in which the device continues making transfers
until a TC or external EOP is encountered, or until DREQ goes inactive.
Digital-to-analog converter The DAC is used to get a proportional analog voltage or
current for the digital data given out by the microprocessor.
Display RAM It is a sequence of RAM locations in the 8279 to store the character data
to be used for display.
DMA Acknowledge This signal is used to notify the individual peripherals when one
has been granted a DMA cycle.
DMA request (DREQ) lines These are individual asynchronous channel request inputs
used by peripheral circuits to obtain DMA service.
DMA It is a method of data transfer between the memory and I/O devices, done without
the intervention of the microprocessor.
FIFO RAM It is a sequence of RAM locations in the 8279 to store the key code pressed
in a matrix keyboard interface.
I/O mode This mode applied to ports A, B, and C of the 8255 for programming the data
transfer and direction of data transfer.
Idle cycle This is the state of the system when no channel is requesting service.
Initialization command words These are used to set up appropriate initial conditions
and specify the restart vector location
Interrupt mask register This register stores the masking bits of the interrupt lines to be
masked.
Interrupt service register This register stores all the levels that are currently being
serviced.
Key board de-bouncing This is the process of removing switch transient voltages and
detecting an actual key press.
Matrix keyboard It is an arrangement of switches in matrix wiring so that they can be
interfaced with the processor with minimum hardware and scanning requirements.
Mode instruction It is used for setting the function of the 8251.
Modem It is a modulator and demodulator that sends digital Is and Os as modulated
tones over standard phone lines.
Multiplexed display This is a method of interfacing many display devices with a
processor and using scanning method to display digits, with one digit being displayed at
a time.
Operational command words (OCWs) These are used for masking interrupts, setting
up status read operations, etc.
Priority resolver It examines the interrupt registers to determine whether the INT request
should be sent to the microprocessor or not.
Programmable timer A device in which the initial count value can be loaded using the
data from the data bus, and counting can be started and stopped using software instructions
written to the control register is called programmable timer.
Rate generator The frequency output of this mode is equal to the input frequency
divided by n.
Serial communication This term refers to the process of sending and receiving
information bit by bit.
Single transfer mode This is the mode in which the device is programmed to make one
transfer only.
Synchronous transfer It is the method of serial transfer in which the transmission and
reception of data is done simultaneously with a common clock.
Timing This is the prrocess of counting using a precise clock pulse at fixed frequency.
REVIEW GUESTIONS
1. Name the registers available in the 8255.

2. Write the control word format for the I/O mode of the 8255.
3. Write a brief note on the I/O modes of the 8255.
4. Write the BSR mode control word format of the 8255.
5. List the components needed to interface seven-segment displays with the 8085.
6. Find the data direction and modes of operation of the ports of the 8255, if the control
word written into it is 80H.
7. Describe the function of EOC in the ADC interface with the 8085.
8. How can the frequency of a waveform generated using DAC be changed?
9. Why is a driver circuit needed for interfacing an LED to a port pin?
10. With encoded scan keyboard mode, the total number of keys that can be connected to
the 8279 is 128. Justify this statement.
11. Describe the block diagram of the 8279 keyboard/display interface.
12. What are the functions performed by the 8279?
13. Describe the different modes of operation of the keyboard interface with the 8279.
14. What are the different formats of display possible with the 8279?
15. What are the different control words of the 8279? Explain the function of each
command.
16. Name some applications of the 8253.
17. What is the difference between the 8253 and the 8254?
18. Explain how to configure a timer/counter using software.
19. List the various operating modes of the 8253.
20. How is the output frequency of the 8253 determined in rate generator mode?
21. What is the difference between hardware triggered strobe and software triggered
strobe?
22. What are the basic programming requirements to interface the 8253 with the 8085?
23. Compare serial and parallel communication.
24. Compare simplex and duplex transmission.
25. What is the difference between synchronous and asynchronous serial data transfer?
26. What is a modem?
27. Compare RS 232, RS 422, and RS 432 standards.
28. Draw the block diagram and explain the operations of the 8251 serial communication
interface.
29. Write and explain the mode word, command word, and status word formats of the
8251.
30. List the features modified by the mode instruction of the 8251.
31. Name the features modified by the command instruction of the 8251.
32. The synchronous mode of the 8251 is used for very high rate of data transfer. Is this
statement true or false? Justify your answer.
33. The order of instructions used to initialize the 8279 is important. Is this statement true
or false? Justify your answer.
34. Explain how data can be transferred using 8251 US ART at different baud rates.
35. What is the need for interrupt controller?
36. Compare maskable and non-maskable interrupts.
37. What is priority resolver?
38. List the internal registers of the 8259.
39. Write a note on cascaded mode of operation in the 8259.
40. What is EOI?
41. Explain the initialization process of the 8259.
42. Explain how the 8259 communicates with the 8085. Explain the different functions
available in the priority interrupt controller.
43. Draw the block diagram of the 8259 and explain how it can be used for increasing the
interrupt capabilities of the 8085.
44. How is DMA better than programmed data transfer?

45. Give examples of I/O devices that can be interfaced with DMA.
46. Write the sequence of operations carried out in DMA.
47. List the internal registers of the 8237.
48. Explain how data is transferred between the RAM and an I/O device using DMA.
49. Discuss the different modes of operation in the 8237.
50. Write a note on cascaded mode of operation of the 8237.
51. Describe in detail how the 8237 can be interfaced with the processor.
NUMERICAL/DESIGN-BASED EXERCISES
1. Form the control word for setting port C’s fourth pin.
2. Configure the ports of the 8255 (PPI) as follows: port A = output, port B = input, port
C higher = output, port C lower = input. (Assume that the 8255 PPI is located at 20H-
23H.)
3. Write the handshaking signals and their functions if port A of the 8255 is set up as an
input port in mode 1.
4. Design an interface using the 8279 for interfacing six seven-segment displays and a
matrix hexadecimal keypad to work with the 8085 processor. Explain the software
needed for the interfacing.
5. Write a program to set up the 8253 as a square wave generator with a period of 1 sec.
(Assume that the input frequency to the 8253 is 1 MHz.)
6. Write a program using the 8253 to generate a PWM signal whose frequency and pulse
width can be changed. (Hint: You can use two timers—one in programmable one-shot
mode to generate variable pulse width and the other in rate generator mode to trigger the
one-shot mode counter at desired frequency.)
7. Write an ALP to initialize the 8251 USART and receive data on polled basis, given the
following parameters: Baud rate factor = 64, character length = 8 bits, no parity check,
and 1 stop bit. Assume port address 50H for data and 51H for control/status.
PROGRAMMING EXERCISES
1. Draw and explain a typical stepper motor interface. Further, write an ALP to rotate the
shaft of a four-phase stepper motor five times in the clockwise direction.
2. Write an ALP to generate a square wave using the 8255.
3. Show how you would interface a keyboard with the 8085 processor using the 8255.
Write an ALP to generate a key code for the key pressed.
4. Interface a set of eight simple switches and eight simple LEDS with the 8085 using a
8255 PPI chip. The 8255 should be selected for the following memory addresses: port
A—0740 H, port B—0742H, port C—0744H, and CWR: 0746H. Write a program to
indicate the status of the switches on LEDs.
5. Assume that a key matrix with the keys 0-9, *, -, /, and + are interfaced with the 8085
through the 8279. Eight single-digit display units are interfaced with the same 8279.
Develop a software for using the display and the keyboard as a calculator.
CHAPTERO j
A COMPLETE 8085-BASED SYSTEM

LEARNING OUTCOMES
• Requirements of an 8085-based microcomputer system
• Design of an 8085-based system
• Interfacing of the peripherals in a system
8.1 INTRODUCTION
In the previous chapters, we have dealt with the basic architecture, instruction
set, programming, and interfacing of peripherals with the Intel 8085 processor.
Interfacing of memory chips and peripherals (such as LEDs, seven-segment
displays, ADCs, DACs, stepper motors, LCD displays, and timers) were considered
separately. However, when we want to build a complete system, the required
amount and type of memory and peripherals have to be simultaneously interfaced
with the processor. All these devices must be able to work in synchronism with
the processor without affecting one another. This chapter discusses the nuances of
interfacing all these devices to the 8085 to make a complete system and to execute
programs in the desired manner.
8.2 SYSTEM OVERVIEW

The block diagram of an 8085-based system design is given in Fig. 8.1. The system
consists of the 8085 processor chip, memory chips, input device, and output
device. The connecting wires between these parts are called buses. There are three
different buses in the system—the address bus, the data bus, and the control bus.
The address bus is used to transfer addresses from the processor to the memory
and I/O ports. The CPU can select any memory location or I/O device by sending
the corresponding address on these address lines. As the 8085 processor has 16
address lines, it can address 216 bytes (64 KB) of addresses/memory locations.
However, since it uses only 8-bit addresses for I/O ports, only 28 = 256 ports
can be addressed. The contents of the lower-order and higher-order address buses
are the same during I/O port access in the 8085 address bus. Only the CPU can
send addresses to select the peripherals or memory. Therefore, the address bus is
unidirectional, i.e., from the CPU to the peripherals.
The data bus is used to transfer data between the peripherals and the CPU. It
is bidirectional as data can flow in two directions. All parts of the system transfer
data through the data bus, under the control of the CPU. The CPU, through its
control bus, ensures that only one peripheral or memory chip transfers data through
A COMPLETE 8085-BASED SYSTEM 293
Fig. 8.1 Block diagram of an 8085-based system
the data bus at a time. The devices that are not using the data bus must float
their individual data buses. This means that these devices must have their data
buses in the high impedance state. In this state, the devices can neither source nor
sink current. So the data bus is not affected, even though the device is physically
connected to it.
The control bus carries various control signals from the processor to the
peripherals and the memory. These control signals are responsible for selecting the
direction of data transfer. The memory and I/O device selection is also done using
control signals. The peripherals obey the control signals given by the processor.
Some control signals are given by the peripherals to the CPU. An example of such
a signal is the Ready signal. This is a signal given by a slow peripheral to the CPU.
If this signal is low, the processor waits until it is made high by the peripheral.
The sequence of instructions or programs for execution is stored as binary
numbers or codes in successive memory locations. The memory in a system
must be of at least two types. Read only memory (ROM) must be present in a
system because the start-up code, which is executed when the power is turned on,
must be resident in the memory permanently. Every system has some programs
stored permanently in the ROM. These programs are called firmware. To store the
temporary data during program execution, random access memory or read/write
memory (RAM) is necessary. Hence, a system must have at least one ROM and
one RAM chip. The addressing of memory locations is very important; so is the
selection of addresses for the ROM and RAM chips.
8.3 ADDRESS MAP OF GENERAL 8085 SYSTEM

Memory in any microprocessor-based system is organized as a linear address space.
In the 8085, the memory is organized from the address 0000H to the address FFFFH.
in general, a program is organized as modules. Programmers write programs in
different modules/subroutines, each with a specific function. The simplest method
to organize these programs is to write different subroutines or modules and then call
them from the main program.

So any microprocessor-based
system will use a memory
organization similar to that
given in Fig. 8.2.
Normally, Reset is a
hardware signal applied to the
microprocessor system for it
to power on properly. Every
system must be powered on
with this signal. Upon applying
the Reset signal, the hardware
resets itself and makes the CPU
execute the instructions present
Fig. 8.2 Memory organization in a microprocessor system
at predefined locations. The
user must take control of the processor execution and so, must store the start-up
program in the memory. This program must be stored in the ROM, so that it can
be executed every time the processor is powered on. Therefore, at the reset address
of the processor, an instruction to jump to the user start-up program is placed. The
first few addresses are reserved for storing interrupt vector addresses. So all these
locations contain jump instructions. A ROM chip is used for storing the interrupt
vector addresses and the main program.
Some locations in the address map are reserved for the RAM chip. In addition
to data, the RAM should be used for storing return addresses during interrupt and
subroutine calls. Therefore, some amount of RAM should be allocated for the
stack. An example address map for an 8085-based system is shown in Table 8.1. It
can be seen that the system does not require all the possible 64 KB of memory. The
amount of memory is decided by the designers, depending upon the application of
the system.
Table 8.1 A typical address map
Address range Type of memory Program/Data Possible chip
0000H-3FFFH ROM/EPROM Program 27128

8000H-FFFFH RAM Data, Stack 62256
8.4 GENERAL MICROCOMPUTER SYSTEM USING 8085

The general 8085-based system shown in Fig. 8.3 consists of a standard memory
and a standard I/O port interfaced with the 8085 processor. The 8085 processor
operates on a single power supply of +5 V and ground, applied between Vcc and
Vss. The 8085 processor has an internal clock generator. Therefore, it is enough
to connect a crystal between the pins XI and X2. The lower-order address bus and
the data bus are multiplexed inside the 8085 processor. For the external devices to
access the address bus and data bus separately, these buses must be de-multiplexed.
This is done by connecting a latch to the multiplexed address and data bus.
Fig. 8.3 A general 8085-based system

The Address Latch Enable (ALE) is the signal given by the processor to tell the
latch that the address has been sent out by the processor and has to be stored onto
the latch.
The Reset signal should be applied to the processor when it is switched on.
Hence, a power-on reset circuitry, as shown in Fig. 8.3, must be connected to the
active low RESET input pin of the processor. The capacitor voltage during power-
on is zero. Therefore, an active low Reset signal is applied to the processor. The
Reset signal should be applied long enough for the reset action to be completed
by the processor. The typical values of R and C are 75 kQ and 1 pF, respectively.
During normal operation, the capacitor will be charged to the Vcc supply voltage
and so the Reset signal will not be applied to the processor. A push button connected
to the RC network is used to apply the Reset signal manually. The value selected
for RI is comparatively low so that when the RESET push button is pressed, the
capacitor is discharged and an active low signal is applied to RESET IN.
The control signals IO/M, RD, and WR are used for data transfer between the
peripherals and the processor. The peripheral addressed by the processor is selected
using an address decoder. The higher-order address Unes are used by the address
decoder to select the
desired chip of memory
or an I/O port.
The address
decoding is done
using the higher-
order address lines
A14 and A15 and the
control signal IO/M.
The decoder IC 74139
can be used for this
purpose. IC 74139 is a
dual 2-4 decoder. The Fig. 8.4 Address decoding using decoder for the address map in
Table 8.1
inputs to the IC are the
higher-order address lines A14 and A15. The four outputs are active low outputs. The
enable input E is called gate input G1 and is an active low signal. So, this chip is
enabled for memory access when the IO/M signal is low. For the address map shown
in Table 8.1, the YO output is used as the active low Chip Select for the ROM chip.
The outputs Y2 and Y3 must be combined using an AND gate to form the active low
Chip Select for the RAM chip. The circuit diagram for this is given in Fig. 8.4.
A general 8085-based system needs at least two I/O ports—one port for an
input device and the other for an output device. The commonly used input device
is the keyboard matrix discussed in Chapter 7; the commonly used output device is
the multiplexed seven-segment display. These two devices can be interfaced with
the processor using a single support chip, the keyboard and display Controller
IC 8279, provided by Intel. So the system needs one 8279 chip. In addition, the
system needs to interface with digital input and output ports. This is supported
by Intel’s programmable peripheral interface chip IC 8255. The timing of events
is an important issue in any microcomputer system and that necessitates the use
of a timer IC such as IC 8253. As an example, three slave ICs—8279, 8255, and
8253—are considered for interfacing with the 8085.
To start with the interfacing design, Tab|e g 2 Address map for |;Q devices
it is necessary to fix the address map for
the devices to be interfaced. Table 8.2 Chip Address range MSBs
gives the address map assumed for the A7 A6
three devices. Remember that the 8085 $279 OOH, 01H 0 0
processor uses only eight bits for I/O §255 40H, 41H, 42H, 43H 0 1
device accesses. Here, 8-bit addresses are §253 80H. 81H. 82H, 83H 1 0
assumed for the peripheral devices. The
most significant two bits vary from one chip to another. The 8279 uses only two
addresses, whereas the 8255 and 8253 use four addresses each. The interfacing of
these devices has been discussed in detail in Chapter 7.
The interfacing diagram for these three chips with the addresses assumed
is shown in Fig. 8.5. Chip selection is done using IC 74LS139, which is a
2-4 decoder. The two higher-order address lines A7 and A6 are used for address
decoding, i.e., device selection. This chip has to be selected only for I/O device
addresses. So the active low Chip Enable of the 74139 is connected to the inverted
IO/M control signal given by the processor. The VO chips under consideration are
selected only for VO accesses. The chips require a binary low signal as they have
an active low Chip Select. For memory accesses, the CS inputs will be high and so
these chips will not be selected. The lines have been connected such that the chip
8279 is selected when the higher-order address lines are 00. Similarly, the 8255
chip is selected when the higher-order address lines are 01 and the 8253 when
74LS139
Data bus
Fig. 8.5 Address decoding and interfacing I/O devices for the address map in Table 8.2
the lines are 10. If necessary, another peripheral IC chip can be connected to the
system with the Y3 output of 74139 as Chip Select.
Note that the data bus is common to all the devices since the individual data
buses of all devices are connected together. The data bus of only the device that is
selected is made active. Other devices that are not selected by a proper Chip Select
signal assign their data buses to the high impedance state. In this high impedance
state, the device data bus does not source or sink current.
In general, Figs 8.3-8.5 when combined form a complete 8085-based system.
To this system, additional devices such as ADCs, DACs, LEDs, switches, and
LCD displays can be connected, as explained in Chapter 7. Additional memory
chips can be interfaced by adjusting the address map, as explained in Chapter 6.
8.5 OTHER SUPPORTING DEVICES

Intel supplies several additional support slave ICs, as listed in Table 8.3. These
slave ICs improve the functionality of the microprocessor system and ease the
programming requirements. These devices are popular as they can be used not
only with the 8085, but also with several other microprocessors. Intel’s 16-bit
processors also support the interfacing of these devices. Table 8.3 gives only the
basic functions of these support chips. Details about the operation, interfacing, and
programming can be obtained from the datasheet of these chips.
Table 8.3 Intel’s supporting devices
Chip no. Function
8155 RAM + three I/O ports + timer, programmable 14-bit timer/counter

8156 RAM + three I/O ports + timer, 2048-bit (256 x 8) static RAM with two
8-bit I/O ports, one 6-bit I/O port, and 14-bit timer/counter
8185 1024 x 8-bit static RAM
8202 Dynamic RAM controller—Provides the signals necessary for controlling
the 2117 and 2118 dynamic memory chips. 8202A-1 and 8202A-3 support
an internal crystal oscillator.
8203 Dynamic RAM controller—Controls 2164, 2117, and 2118 dynamic
memory chips. 8203A-1 and 8203A-3 support an internal crystal oscillator.
8210 TTL to MOS shifter and high voltage clock driver
8212 8-bit I/O port
8216 4-bit parallel bidirectional bus driver
8222 Dynamic RAM refresh controller
8226 4-bit parallel bidirectional bus driver
8231 Arithmetic processing unit
8232 Floating point processor
8237 DMA Controller—Transfer rate is up to 1.6 MB/s in the 8237A-5. 8237A
operates at 3 MHz, 8237A-4 at 4 MHz, and 8237A-5 at 5 MHz.
8251 Communication controller—Asynchronous and synchronous operation
8253 Programmable interval timer—Contains three 16-bit programmable
timers/counters
(Contd)
Table 8.3 Intel’s supporting devices (Contd)
Chip no. Function
8254 Programmable interval timer

8255 Programmable peripheral interface—Contains 24 programmable I/O pins.
8257 DMA controller—Programmable four-channel DMA controller
8259 Programmable interrupt controller—eight-level priority controller, which
is expandable to 64 levels
8271 Programmable floppy disk controller
8272 Single/Double density floppy disk controller
8274 Multi-protocol serial controller—Contains four DMA channels
and two full-duplex transmitters and receivers of speeds up to 880 kbaud
8275 CRT controller
8276 Small system CRT controller
8278 Programmable keyboard interface
8279 Keyboard/Display controller
8282 8-bit non-inverting latch with output buffer
8283 8-bit inverting latch with output buffer
8295 Dot matrix printer controller
8355 16,384-bit (2,048 x 8) ROM with I/O
8604 4,096-bit (512x8) PROM
8702 2,048-bit (256 x 8) PROM
8755 EPROM + two I/O ports
POINTS TO REMEMBER
• The 8085 processor requires at least one ROM and one RAM chip to make it a complete
microcomputer system.
• The system requires at least one input device and one output device.
• The address map for the memory and I/O devices used must be finalized before designing
the address decoder.
• Decoder chips such as 74138 and 74139 can be used for address decoding in a micro
computer system.
• The decoder for the system must consider whether the Chip Select signals are active low
or active high.
• The data bus is common and connected to all the devices in the system.
REVIEW QUESTIONS
1. Draw and explain the general 8085-based system.

2. Explain the design of an 8085-based system using the minimum number of chips.
Design an 8085-based system to read data from a temperature sensor and display the
temperature in a seven-segment display. Assume the relevant data.
Part 3
o--------------------- AAAA--------------------
INTEL 8051
MICROCONTROLLERS
Chapter 9: Introduction to 8051 Microcontrollers
Chapter 10: 8051 Instruction Set and Programming
Chapter 11: Hardware Features of 8051
Chapter 12: 8051 Interface Examples

CHAPTER? 1
INTRODUCTION TO 8051
MICROCONTROLLERS
LEARNING OUTCOMES
• Differences between microprocessors and microcontrollers
• Description and features of Intel MCS-51 series microcontrollers
• Intel 8051 microcontroller architecture and features
• Power control modes of the 8051
• Stack operation in the 8051
9.1 INTRODUCTION
The microprocessor is a programmable chip that forms the CPU of a computer.
Nowadays, many microprocessor chips are available in the market for users to select
from depending on the application. In general, processor chips can be classified as
general-purpose microprocessors, microcontrollers, and DSP processors.
A general-purpose microprocessor is the CPU of a digital computer and
needs external components such as memory, input devices, output devices, and
decoders to function as a microcomputer system. These chips can be used to suit
any general-purpose application and can be configured by the user. Examples of
8-bit processors are Intel’s 8085, Zilog 80, and Motorola 6800. Examples of 16-
bit processors are Intel’s 8086 and 8088 and Motorola’s 68000 and examples of
32-bit processors are Intel’s 80186, 80286, and 80386, and Motorola’s 68030. In
general, these microprocessor-based systems get data from mass storage devices,
perform calculations, and store the results in storage devices. General-purpose
microprocessors use external memory and a lot of processor time is involved in
data transfer between the external memory and the processor.
Microcontrollers are processor chips that generally have memory, input ports,
and output ports within the chip itself. Therefore, they can also be called single
chip computers, computer-on-a-chip, or system-on-a-chip. Microcontrollers are
used in machine control applications, where there is no need to change the program.
Equipments that use microcontrollers include computer printers, plotters, fax
machines, Xerox machines, telephones, automotive engine control mechanisms,
and electronic instruments such as oscilloscopes, multimeters, planimeters, IC
testers, etc. The major difference between microprocessors and microcontrollers is
that microcontrollers are comparatively faster because of reduced external memory
accessing. Intel’s 8031, 8051, and 8096 and Motorola’s 68HC11 are examples of
microcontrollers.
DSP processors are processing chips that have flexibility in hardware and
software, to implement signal-processing algorithms. These processors have an
extended arithmetic and logic unit for operation on floating or fixed point number
formats. Like microcontrollers, DSP processors also have on-chip memory, I/O
ports, A/D converters, and serial ports. They are used in mobile phones, digital
cameras, PBX systems, and smart card readers.
Chapters 9-12 give a complete idea about the Intel 8-bit microcontroller’s
architecture, instruction set, programming, and hardware interfacing. Readers of
these chapters are expected to know the fundamentals of microprocessors, memory
structures, and assembly language programming.
9.2 INTEL’S MCS-51 SERIES MICROCONTROLLERS

Intel Corporation has many microcontrollers in both 8-bit and 16-bit configurations.
The 8-bit microcontrollers are available in many part numbers, with MCS-51 as
the family name. Figure 9.1 shows the various microcontrollers in the MCS-51
series, with their constituent differences. For example, 8XC51RD comes with an
internal ROM of 64 KB, while 8XC51FC comes with only a 32 KB ROM.
64 KB
32 KB
8 KB 16 KB ROM
ROM
ROM ROM
4 KB ROM
8XC51 8XC52 8XC51FB 8XC51FC 8XC51RD

8XC51FA 8XC51RB 8XC51RC
8XC51RA
Fig. 9.1 Microcontrollers in Intel’s MCS-51 series
Table 9.1 lists the features of the 8051 family of microcontrollers.

Table 9.1 Features of the 8051 family of microcontrollers
Device number Data bus width (bits) RAM capacity (bytes) ROM capacity
8031 8 128 Nil

8051 8 128 4 KB
8751H 8 128 4 KB EPROM
8052AH 8 256 8 KB
8752BH 8 256 8 KB EPROM
All the microcontroller chips listed in Table 9.1 have the same basic ar chitecture.
The Intel 8051 is considered for further discussion in the topics that deal with
instruction set, and software and hardware interfacing in Chapters 9-12.
9.3 INTEL 8051 ARCHITECTURE

The main features available in the 8051 chips are as follows:
(i) 8-bit CPU (ii) 4 KB of on-chip program memory
INTRODUCTION TO 8051 MICROCONTROLLERS 305
(iii) 128 bytes of on-chip data RAM (iv) four ports of eight bits each
(v) two 16-bit timers (vi) full-duplex serial port
(vii) on-chip clock oscillator
Figures 9.2 (a) and 9.2 (b) show the architecture and block diagram of the
8051, respectively.
In addition to these features, the 8051 provides Boolean processing, six
interrupt capabilities, and an 8-bit CPU for control applications.
The 8051 is an 8-bit microcontroller, i.e., the data bus within and outside the
chip is eight bits wide. The address bus of the 8051 is 16 bits wide. So it can
address 64 KB of memory. The lower-order address bus is multiplexed with the
data bus, as in the 8085 processor. The port 0 and port 2 pins of the 8051 form the
multiplexed address and data bus.
The 8051 is a 40-pin chip. The power supply +VCC and Vss takes two pins
and the built-in clock oscillator requires two pins (-XTAL1 and XTAL2) for
connecting the crystal.
The four control signal pins of the 8051 are PSEN, ALE, EA, and RST as
shown in Fig. 9.3 on page 307. RST is an active-high reset signal used to restart
the controller chip. The 8051 responds to an RST high input only if the RST is held
high for at least two machine cycles. A machine cycle is the period taken by any
processor to fetch and execute one instruction. In the 8051, the maximum number of
clock cycles taken for a machine cycle is 12. So the RST pin must be high for at least
16-bit address bus
Internal RAM SFR area
Fig. 9.2 (a) 8051 architecture

PO 0-P0 7 P2 0-P2 7
AAAAAAAA AAAAAAAA
Port 0 drivers Port 2 drivers
RAM Port 0 latch Port 2 latch ROM
ACC Stack pointer

Buffer
PCON SCON TMOD TCON
T2CON THO TLO TH1
TMP2 TMP1 TL1 PC
B register incrementer
SBUF IE IP
Interrupt serial ports
and timer blocks
PSW
PSEN Timing
and
control
RST
Port 1 latch Port 3 latch
Port 1 drivers
-XtAL1 XTAL2
P1 0-P1 7 P3 Q-P3 7
Fig. 9.2(b) 8051 internal block diagram
24 clock periods. PSEN, ALE, and EA are the signals used in conjunction with
the external memory access of the 8051. They are discussed in detail in Chapters
11 and 12.
9.4 MEMORY ORGANIZATION

In the 8051, the memory is organized logically into program memory and data
memory separately. The program memory is read-only type; the data memory is
organized as read-write memory. Again, both program and data memories can
be within the chip or outside. Figure 9.4 shows the various options available for
memory organization in the 8051.
The Intel 8051 has 128 bytes of RAM and 4 KB of ROM within the chip. The
address bus of the 8051 is 16 bits wide. So it can access 64 KB of memory. As the
memory is organized separately as program memory and data memory, the 8051
T2/P1.0 e1 40 □ Vcc
T2EX/P1.1 □2 39 □ P0.0/AD0
ECI/P1.2 e3 38 □ P0.1/AD1
CEX0/P1.3 e4 37 □ P0.2/AD2
CEX1/P1.4 □5 36 □ P0.3/AD3
CEX2/P1.5 □6 35 □ P0.4/AD4
CEX3/P1.6 □7 34 □ P0.5/AD5
CEX4/P1.7 □ 8' 33 □ P0.6/AD6
RST □ 9' 32 □ P0.7/AD7
8061
RXD/P3.0 □ 10 31 3 EA/VPP
Dual in-line
TXD/P3.1 □ 11 package 30 □ ALE
INT0/P3.2 E 12 29 □ PSEN
iNT1/P3.3 E 13 28 □ P2.7/A15
T0/P3.4 E 14 27 □ P2.6/A14
T1/P3.5 E 15 26 □ P2.5/A13
WR/P3.6 E 16 25 □ P2.4/A12
RD/P3.7 E 17 24 □ P2.3/A11
XTAL2 E 18 23 □ P2.2/A10
XTAL1 E 19 22 □ P2.1/A9
Vss E 20 21 □ P2.0/A8
Fig. 9.3 Pin details of 8051 DIP IC
Memory
I-------------- J I •
Program memory Data memory
I
Internal (4 KB)
I ■
External (64 KB)
I
Internal (128 bytes)
1
External (64 KB)
. t ... • ’ ' . , . - ' t
Fig. 9.4 Memory organization in the 8051
microcontroller can access 64 KB of program memory and 64 KB of data memory.

The user can configure the entire program memory outside the chip or use 4 KB
inside and 60 KB outside the chip. The internal data memory is accessed with 8-bit
addresses and the external data memory with 16-bit addresses. So the maximum
data memory that can be connected to the 8051 system is 64 KB.
9.5 INTERNAL RAM STRUCTURE

The 8051 has 128 bytes of internal data RAM, which is accessible as bytes or
sometimes as bits. The mapping of the internal RAM is shown in Fig. 9.5.
The address of the internal RAM starts at OOH and occupies space up to
7FH. The RAM space is divided into three blocks—the register banks, the bit-
addressable memory, and the scratch pad memory.
The 8051-has four register banks of eight registers each, with addresses from
OOH to 1FH. In assembly language, they are addressed by the names R0-R7. The
Fig. 9.5 8051 internal RAM map
register banks are identified with two bits in the processor status word (PSW). The
PSW has two bits for identifying the register bank, i.e., 00 represents bank 0, 01
represents bank 1,10 represents bank 2, and 11 represents bank 3.
In the 8051, bitwise operations are also possible with special instructions using
the bit addresses. The bit-addressable memory is both bit-addressable (from OOH
to 7FH) and byte-addressable (from 20H to 2FH). Bit operations are helpful in
many control algorithms.
Using general-purpose scratch pad memory, programmers can read and write
data at any time for any purpose. This memory ranges from the byte address 30H
to the address 7FH.
9.5.1 Special Function Registers

Special function registers (SFRs), which occupy the upper 128 bytes of the internal
memory, are the registers that control the entire processor. They can be accessed
only by direct addressing. The common SFRs are listed in Table 9.2.
The registers available in the 8051 are as follows:
(i) Accumulators—A and B
(ii) Processor status word—PSW
(iii) I/O port registers—PO, Pl, P2, and P3
(iv) Data pointers—DPH and DPL
(v) Serial data buffer register—SBUF
(vi) Stack pointer—SP
(vii) Timer registers—THO, TH1 and TLO, TL1
(viii) Timer control registers—TCON and TMOD
(ix) Power and port control—PCON and SCON
(x) Interrupt control registers—IP and IE
Programmers should not use the addresses in the range 80H-FFH (other than
the SFRs), as they are used by Intel Corporation for expanding the functions of the
8051. The 8051 has two accumulators—registers A and B. Register B forms the
accumulator for multiplication and division instructions; for other instructions it
can be accessed as a general-purpose register.
The stack in the 8051 is organized within the internal RAM area. The stack
pointer is eight bits wide and has to be initialized with an address in the RAM area.
When the 8051 is reset, the stack pointer is by default set to 07H. The stack pointer
is incremented before storing a data in the stack. Similarly, while reading data
from the stack, the data is read first and then the stack pointer is decremented.
Table 9.2 Special function registers of 8051
Direct addressed SFR Direct addressed SFR

memory address memory address
80 P0 90 Pl
81 SP 98 SCON
82 DPL 99 SBUF
83 DPH A0 P2
88 TCON A8 IE
89 TMOD B0 P3
8A TLO B8 IP
8B TL1 DO PSW
8C THO E0 ACC
8D TH1 F0 B
9.5.2 Processor Status Word

The PSW contains all the flags of the 8051 and is eight bits wide. The bit pattern
of this flag register is given in Table 9.3. From the table, it can be seen that there
are seven flag bits in the PSW of the 8051. The PSW is accessible fully as an 8-
bit register, with the address DOH. Meanwhile, individual bits of the PSW can be
accessed with the bit addresses given in Table 9.3. The contents of the PSW upon
reset are given in the third row.
Table 9.3 PSW format of 8051
PSW CY AC FO RSI RSO OV P
Bit address D7H D6H D5H D4H D3H D2H D1H DOH
Contents upon reset 0 0 0 0 0 0 X 0
Parity bit (P) It is set to 1 if the accumulator contains an odd number of is, after
an arithmetic or logical operation.
Overflow flag (OV) This flag is set during ALU operations, to indicate overflow
in the result. It is set to 1 if there is a carry out of either the D7 bit or the D6 bit of
the accumulator. Overflow flag is set when arithmetic operations such as add and
subtract result in sign conflict.
The conditions under which the OV flag is set are as follows:
Positive + Positive = Negative
Negative + Negative = Positive
Positive - Negative = Negative
Negative - Positive = Positive
Register bank select bits (RSO and RSI) These bits are user-programmable.
They can be set by the programmer to point to the correct register banks. The
register bank selection in the programs can be changed using these two bits.
Table 9.4 explains how these bits can be changed to select the appropriate
register bank.
Table 9.4 Register bank selection using PSW
RS1 RSO Selected bank Address range
0 0 BankO 00H-07H
0 1 Bank 1 08H-OFH
1 0 Bank 2 10H-17H
1 1 Bank 3 18H-1FH
General-purpose flag (FO) This is a user-programmable flag; the user can

program and store any bit of his/her choice in this flag, using the bit address.
Auxiliary carry flag (AC) It is used in association with BCD arithmetic. This
flag is set when there is a carry out of the D3 bit of the accumulator.
Carry flag (CY) This flag is used to indicate the carry generated after arithmetic
operations. It can also be used as an accumulator, to store one of the data bits for
bit-related Boolean instructions’.
The 8051 supports bit manipulation instructions. This means that in addition
to the byte operations, bit operations can also be done using bit data. For this
purpose, the contents of the PSW are bit-addressable. Similarly, the contents of
the accumulator and register B are also bit-addressable. The bit addresses of all the
bits of the accumulator and register B are given in Tables 9.5 (a) and 9.5 (b).
Table 9.5 (a) Addresses and contents of accumulator bits
Accumulator bits ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.l ACC.O
Bit address E7 E6 E5 E4 E3 E2 El E0
Contents upon reset 0 0 0 0 0 0 0 0

_____ •‘_____ ___
Table 9.5 (b) Addresses and contents of register B bits
Register B bits B.7 B.6 B.5 B.4 B.3 B.2 B.l B.O
Bit address F7 F6 F5 F4 F3 F2 Fl F0
Contents upon reset 0 0 0 0 0 0 0 0

....... ......
9.6 POWER CONTROL IN 8051

The 8051 has various power control modes, which are used to control the power
consumed by the microcontroller chip. Some of these modes let the microcontroller
go into a ‘sleep’ mode, which makes it consume lesser power than during normal
operation. The power control modes are selected through the Special Function
Register PCON. Table 9.6 gives the bit pattern of the PCON register (87H).
Table 9.6 Bit pattern for PCON (87H) register
Bit Name Function
7 SMOD Serial port baud rate set bit

6 - , Reserved
5 - Reserved
4 - Reserved
3 GF1 General-purpose flag 1
2 GFO General-purpose flag 0
1 PD Power down mode set bit
0 IPL Idle mode set bit
9.6.1 Idle Mode

The microcontroller enters the idle mode whenever the PCON.O bit is set to 1. In
the idle mode, the clock pulses applied to the CPU are masked, while all other
units such as interrupt controllers, etc. are kept active. The contents of the CPU
are not affected in the idle mode. The processor can be revoked from the idle mode
by applying either a hardware interrupt or a hardware reset signal. These two
actions will reset PCON.O and processor execution will resume at the instruction
following the instruction that set the idle mode.
9.6.2 Power Down Mode

The power down mode is initiated by making PCON.l bit 1. In this mode, the
clock generator is switched off and only the internal memory is active. The supply
voltage Vcc can be reduced to 2 V and the power consumption can be reduced. The
only way to revoke the processor from power down mode is to reset the system.
9.7 STACK OPERATION

In the 8051, the stack is configured as a series of memory locations following the
Last-In First-Out (LIFO) pattern. In general, the stack is initialized in the internal
RAM area. Any 8-bit data can be stored and retrieved from the stack using PUSH
and POP instructions, with the help of the stack pointer.
The stack pointer (SP) is an 8-bit register within the SFR area, with the address
81H. This register can hold one 8-bit address at a time, which is actually the
memory location at top of the stack. A push operation in the 8051 is used to store
an 8-bit data in the stack. The PUSH instruction first increments the value of SP and
then stores the data mentioned in the instruction in the memory location pointed
to by SP. Similarly, the POP instruction stores the value from the top of the stack
in the register mentioned in the instruction and then decrements the value of SP.
The stack pointer is initialized to the value 07H when the 8051 microcontroller is
reset. The other instructions of the 8051 that affect the stack and the stack pointer
are ACALL, LCALL, RET, and RETI. The stack pointer can be initialized to any
internal RAM address by the programmer, by writing the required address in the
SP SFR address 81H.
POINTS TO REMEMBER
• Intel MCS-51 is a family of microcontrollers and 8051 is the familiar IC in the

family. Different versions of the basic 8051 are available from Intel and other chip
manufacturers.
• The 8051 is an 8-bit microcontroller with built-in RAM, I/O ports, timers, and interrupt
facility.
• The functioning of the microcontroller is controlled using a set of registers called special
function registers (SFRs).
• The 8051 can itself act as an independent system, with all memory and ports inside it.
If necessary, memory and I/O ports can be added externally.
• The processor supports many operating modes such as power down mode, idle mode,
etc.
KEY TERMS
Data memory It is a read and write memory, which is used to store data.
Flags These are the bits used to indicate the status of the results after arithmetic and
logical operations.
Processor Status Word (PSW) It is the register containing the various flags that are
used to indicate the status of the results after arithmetic and logical operations.
Program memory It is a read only memory, which is used to store programs.
Special Function Registers (SFRs) These are part of the internal memory and are used
for specific functions and control of various functional blocks in the 8051.
REVIEW QUESTIONS
1. Differentiate between microprocessors and microcontrollers.

2. Why are microcontrollers often called single-chip computers?
3. How does the 8031 differ from the 8051?
4. Write the format of the 8051 PSW.
5. What is a special function register?
6. Which port of the 8051 is used as address/data bus?
7. What is the function of RSO and RSI bits in the PSW of the 8051?
8. What is the address range of the bit-addressable internal memory of the 8051?
9. Write a note on memory organization in the 8051.
10. Draw and explain the architectural details of the 8051.
11. How can you put the 8051 in idle mode?
12. Explain the stack operation in the 8051.
THINK AND ANSWER
1. Find the contents of the flags in the 8051 after adding the binary numbers 01011100B
and 11000101B.
2. Write the binary word to be written into the PSW of the 8051, to select the register
bank 2 in the internal RAM.
3. Give at least two examples of situations in which the overflow flag is set.
4. What does a ‘0’ in the zero flag after an arithmetic operation mean?
CHAPTER 10
8051 INSTRUCTION SET AND

PROGRAMMING
LEARNING OUTCOMES
• Addressing modes of the 8051, their need and uses
■
• Classification of 8051 instructions based on their operation
• Various instructions of the 8051 and their execution
• Effects of instruction execution on the flag register
• Developing programs using the assembly language instructions of the 8051
• Using the 8051 instruction set and the internal RAM
• Program execution control and branching
• Data manipulation and calculations
■ '............ ....................
10.1 INTRODUCTION
With a basic idea about the architecture and the memory organization of the 8051,
it is easy to study the instruction set and its flexibility for control applications.
Unlike the 8085 instruction set, the 8051 instruction set has instructions for bit
manipulations. In addition, the 8051 instruction set supports addressing modes
such as indexed addressing and relative addressing.
10.2 ADDRESSING MODES OF 8051

The way in which data is specified in an instruction is called addressing mode. The
data fetched for execution depends on the addressing mode. The instruction set of
the 8051 supports five addressing modes.
10.2.1 Immediate Addressing

In this addressing mode, the data to be manipulated is given in the instruction
itself. The data is preceded by the ‘#’ symbol.
Example:
ADD A, #80H
This instruction adds the data 80H to the contents of the accumulator and the result
is stored in the accumulator itself. This addressing mode is used when the data for
the arithmetic and logical operation is needed only once and is a constant.
10.2.2 Register Direct Addressing

In this addressing mode, the register that contains the data to be manipulated is
8051 INSTRUCTION SET AND PROGRAMMING 315
specified in the instruction.

Example:
ADD A, RO
This instruction adds the contents stored in register RO to the accumulator contents
and stores the result in the accumulator. The registers A, DPTR (data pointer
register), and R0-R7 are used in register direct addressing. This addressing mode
uses temporary registers, which hold the data for the operation.
10.2.3 Memory Direct Addressing

The memory address that contains the data to be operated on is specified in the
instruction.
Example:
ADD A, 74H
This instruction adds the data in the accumulator to that stored in the memory
address 74H. All internal RAM addresses, including that of the special function
registers, can be used in memory direct addressing instructions. This addressing
mode is used when the data stored in memory is to be used in arithmetic and logical
instructions. The data in the memory, which is used in memory direct addressing,
can be changed at any point in the program.
10.2.4 Memory Indirect Addressing

The register that contains the memory address of the data is specified in the
instruction. The register specified is preceded by the ‘ @ ’ symbol in the assembly
language format.
Example:
ADD A. @R0
The value stored in the register RO is now the address of the memory location
of the data to be fetched. From this memory location, the data is fetched and
the instruction is executed. The DPTR is used to access the data in the external
memory with 16-bit addresses. The indirect addressing mode is very useful for
accessing data that are stored in consecutive memory locations and accessed
serially in the program.
10.2.5 Indexed Addressing

In this type of addressing, the instruction consists of two parts — a base address
and an offset. This type of addressing is useful in relative memory accessing and
relative jumping. The base address is stored in the DPTR or any other register. The
offset value is stored in the accumulator.
Example:
MOVC A. @A + DPTR
This instruction adds the contents of the accumulator to the contents of the data
pointer and the result forms the actual address from where data is to be fetched.
This data is moved to the accumulator.
The indexed addressing mode is useful in accessing data structures similar to

look-up tables. The base address holds the address of the starting point of the table
and the offset points to a particular entry in the table.

The instructions supported by the 8051 can be classified into different types
depending on their operational functions. The complete instruction set is given
in Appendix B. The different types of 8051 instructions are discussed in Sections
10.3.1-10.3.5.

As the name indicates, instructions in this set are used to transfer data. Data can be
transferred from or to the external RAM or within the internal memory itself. The
list of data transfer instructions is given in Table 10.1.
Table 10.1 Data transfer instructions
Mnemonic Operation Addressing modes

Direct Indirect Register Immediate
MOV A, <src> A = <src> yf yf yf yf

MOV <dest>, A <dest> = A yf yf yf
MOV <dest>, <dest> = <src> yf yf yf
<src>
MOV DPTR, # DPTR = 16-bit immediate data
data 16
PUSH <src> INC SP: yf
MOV ‘@SP’, <src>
POP <dest> MOV <dest>, ‘@SP’: yf
DEC SP
XCH A, <byte> ACC and <byte> exchange data yf yf yf
XCHD A, @Ri ACC and @Ri exchange lower- yf
order nibbles
MOVX A, @Ri Copy 8-bit data from the Only indirect addressing mode
external RAM location pointed
to by Ri to register A
MOVX @Ri, A Copy 8-bit data from register A Only indirect addressing mode
to the external RAM location
pointed to by Ri
MOVX A, @ Copy 8-bit data from the Only indirect addressing mode
DPTR external RAM location pointed
to by the 16-bit DPTR to register
A
MOVX @DPTR, Copy 8-bit data from register A Only indirect addressing mode
A to the external RAM location
pointed to by the 16-bit DPTR
MOVC A, @A Read program memory at (A + Only indexed addressing mode
+ PC PC)
The instruction MOV is used to transfer data between internal registers/memory.

The general format is ‘MOV Reg. destination, Reg. source’. The source and
destination registers within the 8051 chip can be addressed using any addressing
mode other than indexed addressing.
The instructions with the mnemonic MOVX are used to access data from external
memory locations using indirect addressing only. MOVX instruction must use the
accumulator (A) register as either the destination or the source; the other operand
is indirectly accessed external memory. MOVX can be used with both 8-bit and
16-bit external memory addresses. Note that the external memory can be interfaced
with the 8051 with either 8-bit or 16-bit addresses. If 8-bit addresses are used, an
internal register (any location in the internal RAM) is used to hold the address of the
memory. If 16-bit addresses are used, the DPTR is used to hold the address.
The instructions MOVC A, @A + DPTR and MOVC A, @A + PC are the two
instructions that mean ‘MOVE CODE MEMORY’ and are used to transfer data
from the program memory or code memory to the accumulator using indexed
addressing. Note that program memory addressing using MOVC instruction
needs a 16-bit address. So, the DPTR and program counter (PC) are used as base
registers in these instructions. Data can only be read from the program memory
and not written into because the program memory is generally ROM.
The PUSH instruction is used to copy data from an internal RAM location to
the stack. The POP instruction is used to copy data from the top of the stack to the
RAM location specified in the instruction.
XCHD is used to transfer only the lower-order nibble between the accumulator
and the indirectly addressed internal RAM. XCH is used to exchange the contents
of the accumulator and a register or the internal memory of the 8051.

These instructions are used to do arithmetic operations. The common arithmetic
operations such as addition, subtraction, multiplication, and division are possible
with the 8051. They are shown in Table 10.2. All the data used in arithmetic
instructions must be available inside the controller, i.e., in the internal RAM area.
Table 10.2 Arithmetic instructions
Mnemonics Operation Addressing modes

ADD A, <byte> A = A + <byte> a/ a/ a/
ADDC A, <byte> A = A + <byte> + carry a/ V a/
SUBB A, <byte> A = A - <byte> - carry a/ a/
INCA A = A+ 1 Accumulator only

DECA A = A- 1 Accumulator only
INC <byte> <byte> = <byte> + 1 V a/ • a/
DEC <byte> <byte> = <byte> - 1 a/
MULAB B:A = B x A Accumulator only

DIV AB A = Int [A/B]; B = Mod [A/B] Accumulator only
DAA Decimal adjust accumulator Accumulator only
The ADD instruction is used to add 8-bit data with the accumulator and the
result is stored in the accumulator (A) register. The carry generated (if any) is
stored in the carry flag of the processor status word PSW. The ADDC instruction
is used to add 8-bit data with the accumulator, along with the carry bit. The SUBB
instruction is used to subtract the contents of a register and the carry bit from the
contents of the accumulator. For the ADD and SUBB instructions, one of the data
must be in accumulator; the other data can be immediate or in any direct addressed
or indirect addressed internal memory location.
In addition to the ADD, ADDC, and SUBB instructions, there are two
more instructions—MUL and DIV. The register B is used exclusively for these
two instructions. The operands should be stored in the registers A and B. The
MUL instruction multiplies the contents of registers A and B and stores the 16-bit
result in both the registers. The lower-order byte of the result is stored in register
A and the higher-order byte in register B. The DIV instruction upon execution
divides the contents of register A by the contents of register B. The quotient of the
result is stored in register A and the remainder in register B. Division by 0, i.e., a
‘0’ in register B before the execution of the instruction DIV AB sets the overflow
flag (OV) to 1.
The DAA instruction is used to convert the binary sum obtained after adding
two BCD numbers into a BCD number.

In addition to the logical AND, OR, and XRL operations, the 8051 has instructions
such as CLR and CPL, as shown in Table 10.3. All the data for the logical
instructions must be available in the internal RAM.
The instruction CLR A is used to clear the contents of register A, CPL is used
to complement or logically invert the contents of register A, and SWAP is used to
swap the nibbles of register A.
The 8051 supports four rotate operations, with options to rotate left or right and
through the carry.
Table 10.3 Logical instructions

ANL A, <byte> A = A AND <byte> y[ yj yf yf

ANL <byte>, A <byte> = <byte> AND A y/
ANL <byte>, #data <byte> = <byte> AND data yf
ORL A, <byte> A = A OR <byte> y/ yf yf yf
ORL <byte>, A <byte> = <byte> OR A yf
ORL <byte>, #data <byte> = <byte> OR data yf
XRL A, <byte> A = A XOR <byte> yf yf yf yf
XRL <byte>, A <byte> = <byte> XOR A yf
XRL <byte>, #data <byte> = <byte> XOR data yf
(Contd)
Table 10.3 Logical instructions (Contd)

CLR A A = 00H Accumulator only

CPLA A = NOT A Accumulator only
RL A Rotate ACC left one bit Accumulator only
RLC A Rotate ACC left through carry Accumulator only
RR A Rotate ACC right one bit Accumulator only
RRC A Rotate right through carry Accumulator only

The 8051 supports unconditional jumping and subroutine calling in three
ways—absolute jump (AJMP and ACALL), long jump (LJMP and LCALL),
and short jump (SJMP). These unconditional branching instructions are listed in
Table 10.4.
Table 10.4 Unconditional branching instructions
Mnemonics Operation
SJMP rel_addr Jump to (PC) + 8-bit rel_addr.

AJMP 11-bit addr Jump to PC:addr.
LJMP addr Jump to addr.
JMP @A + DPTR Jump to A + DPTR.
ACALL 11-bit addr Call subroutine at PC:addr.
LCALL addr Call subroutine at addr.
RET Return from subroutine.
RETI Return from interrupt.
NOP No operation
Table 10.5 lists the conditional branching instructions of the 8051.

Table 10.5 Conditional branching instructions

CJNE A, <byte>, rel Jump if A <byte> yf yf

CJNE <byte>, #data, rel Jump if <byte> #data yf yf
DJNZ <byte>, rel Decrement byte and jump yf yf
if not zero
JZrel Jump if A = 0 Accumulator only
JNZ rel Jump if A 0 Accumulator only
The syntax for short jump instruction is ‘SJMP 8-bit address’ and can be explained
as follows:
(i) This 8-bit address is a relative address, relative to the program counter.
(ii) The branching address is calculated by adding the address given in the
instruction with the program counter content.
(iii) The 8-bit address is a 2’s complement number, i.e., the most significant bit
stands for the + or - sign. The remaining seven bits are used to specify the
address. Thus, using SJMP the user can branch to anywhere between 127
bytes after the program counter content and 128 bytes before it, i.e., from
(PC - 128) bytes to (PC + 127) bytes.
Example:
8800: SJMP 06H
This instruction shifts the execution to the location 8808H. The program counter
content after fetching the two-byte SJMP instruction is 8802H. So, adding 06H to
8802H results in 8808H.
The syntax for LJMP instruction is ‘LJMP 16-bit address’.
After execution of this instruction, the program counter is loaded with the
16-bit address in the instruction and execution shifts to that location.
The syntax for AJMP instruction is ‘AJMP 11-bit jump address’.
The destination branching address for this absolute jumping instruction is
calculated by keeping the most significant five bits of the program counter and
changing the least significant 11 bits as given in the instruction.
Example:
8800: AJMP 7F0H
This instruction branches the execution to the address 8FF0H. After fetching
this instruction, the program counter content will be 8802H. Keeping the most
significant five bits of the PC (10001) and changing the least significant 11 bits as
given in the instruction (111 1111 0000) results in the branching address 8FF0H.
The 8051 has a single instruction (DJNZ) for counter operation, i.e., to
decrement the destination data and branch according to the result of decrement
operation. This instruction is useful in looping using a counter, similar to the ‘for’
loop in high-level languages.
Similarly, jumping after checking the result of a comparison can be done by
the instruction CJNE. This instruction is useful in looping of instruction execution
based on a condition. This instruction can be used in programming constructs,
similar to the ‘do-while’ condition in high-level languages.
10.3.5 Bit Manipulation Instructions

A special feature of the 8051 microcontroller is that it can handle bit data as well
as byte data. The internal data memory map of the 8051 has a bit-addressable area
also. The special function registers that have 0 or 8 as the last digit in their hex
address are also bit-addressable.
The bit manipulation instructions include logical instructions and conditional
branching instructions, as listed in Table 10.6.
Table 10.6 Bit manipulation instructions
Mnemonics Operation
ANL C, bit C = C AND bit

ANL C, /bit C = C AND (NOT bit)
ORL C, bit C = C OR bit
ORL C, /bit C = C OR (NOT bit)
MOV C, bit C = bit
MOV bit, C bit = C
CLR C C=0
CLR bit bit = 0
SETB C C= 1
SETB bit bit = 1
CPLC C = NOT C
CPL bit bit = NOT bit
JC rel Jump if C = 1
JNCrel Jump if C = 0
JB bit, rel Jump if bit = 1
JNB bit, rel Jump if bit = 0
JBC bit, rel Jump if bit = 1; CLR bit
The logical instructions include ANL and ORL. Conditional branching includes
JC, JNC, JB, JNB, and JBC.
The other instructions available in this category include CLR, SETB, CPL, and
MOV.
Note that there are no instructions for halting machine execution.
Table 10.7 shows the flag bits affected by the various instructions. Note that
the increment and decrement instructions do not affect the flag register.
Table 10.7 Instructions that affect flag bits
Instruction Flags affected

C OV AC
ADD yf yf
ADDC yf yf yf
SUB B yf yf yf
MUL 0 yf
DIV 0 yf
DA yf
RRC yf
RLC yf
SETB C 1
CLR C 0
CPLC yj
(Contd)
Table 10.7 Instructions that affect flag bits (Contd)
Instruction Flags affected

C OV AC
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
CJNE
10.4 SOME ASSEMBLER DIRECTIVES

Assembler directives are special instructions to the assembler program and are
used to define specific operations. These directives are not part of the executable
program. Some of the most frequently used assembler directives are as follows:
(i) ORG—ORiGinate; defines the starting address for the program in program
(code) memory
(ii) EQU—EQUate; assigns a numeric value to a symbol identifier so as to
make the program more readable
(iii) DB—Define a Byte; puts a byte constant (8-bit number) at the memory
location specified
(iv) DW—Define a Word; puts a word constant (16-bit number) at the memory
location specified
(v) DBIT—Define a BIT; defines a bit constant, which is stored in the bit-
addressable section of the internal RAM
(vi) END—This is the last statement in the source file and is used to advise the
assembler to stop the assembly process.
10.5 PROGRAMMING EXAMPLES USING 8051 INSTRUCTION SET

Example 10.1:
Fill a block of memory in the internal RAM with a specific data.
The following assembly language program is used to fill a block of internal
data memory with a particular data. The number of memory locations to be filled
is given by the variable COUNT in the program. This program uses indirect
addressing.
Program:
START: MOV RI.tfCOUNT ; Load number count.
MOV RO, #30 ; Load the starting address of the memory.
LOOP: MOV @R0, #DATA : Load data in the memory location pointed to
by R0.
INC R0 ; Point to the next memory location.
DJNZ RI, LOOP ; Check for count after decrementing and loop
if not 0.
The following program uses direct addressing for achieving the same programming
objective, using the memory locations 30H-34H.
MOV 30, #DATA

MOV 31, #DATA
MOV 32, #DATA
MOV 33, #DATA
MOV 34, #DATA
Example 10.2:
Add three 8-bit numbers.
The following program is developed assuming that the numbers are in memory
locations 3OH, 31H, and 32H of the internal data RAM. The result is stored in
memory locations 50H and 51H of the internal RAM.
Algorithm:
(i) The first byte is moved to the accumulator and the second byte is added
to it.
(ii) If the carry flag is set, register RI is incremented.
(iii) The third byte is added to the intermediate result.
(iv) If the carry flag is set, register RI is again incremented.
(v) The accumulator forms the least significant byte of the result and register
RI forms the most significant byte of the result.
Program:
START: MOV RI, #00H ; Set a register for storing the MSB of the
result.
MOV RO, #30H ; Set the starting address for the memory
locations with stored data.
MOV A, @R0 Get the first data.
INC RO Point to the next memory location.
ADD A, @R0 Add the data.
JNC LI Check for carry.
INC RI If a carry is present, increment the MSB of
the result.
LI: INC RO Point to the next memory location.
ADD A, @R0 Add the third data.
JNC L2 Check for carry.
INC RI If a carry is present, increment the MSB of
the result.
L2: MOV 50H, A Save the result.
MOV 51H, RI
Example 10.3:
Add two BCD numbers.
The following program is developed assuming that the BCD numbers are in
memory locations 30H and 31H of the internal data RAM. The result is stored in
memory locations 50H and 51H of the internal RAM, with the lower-order sum in
50H and the carry (if any) in 51H.
Algorithm:
(i) The first byte is moved to the accumulator and added to the second byte.
(ii) The accumulator is now decimal adjusted.
(iii) The value OOH is moved to the accumulator and added to the carry.
(iv) The result is stored in memory locations 50H and 51H.
Program:
MOV A, 30H ; Get the first data.
ADD A, 31H ; Add the. second data.
DAA ; Convert the surirto a BCD number.
MOV SOH, A ; Save the sum.
MOV A, #00H ; Move OOH to the accumulator.
ADDO A, #00H ; Load the carry of the sum in register A using ADDC
MOV 51H, A ; Save the result.
Example 10.4:
Add two 16-bit data.
In this example, the data are assumed to be initially stored in external memory
locations. The first data is stored in locations 4000H and 4001H, while the second
is stored in locations 4002H and 4003H.
Program:
MOV DPTR, #4000H ; Point to the first data.
MOVX A, @DPTR ; Bring the data pointed to by DPTR to the
accumulator.
MOV RO, A ; Move the LSB of the first data to RO.
INC DPTR ; Point to the MSB of the first data.
MOVX A, @DPTR ; Bring it to the accumulator.
MOV RI, A ; Move the MSB of the first data to RI.
INC DPTR ; Point to the next data.
MOVX A,@DPTR ; Move the LSB of the second data to the
accumulator.
ADD A, RO ; Add the LSBs of the two data.
MOV RO, A ; Store the sum in register RO.
INC DPTR ; Point to the MSB of the second data.
MOVX A, @DPTR ; Move the MSB of the second data to the
accumulator.
ADDC A, RI ; Add the MSBs of the data along with carry
from the previous addition.
MOV RI, A ; Store the MSB of the sum in register RI.
The sum is stored in registers RO and Rl, at the end of the execution of this
program.
Example 10.5:
Shift a 4-digit BCD number left by one digit. Assume that the data is stored in
30H and 31H.
Algorithm:
(i) The value OOH is stored in memory location 35H.
(ii) The least significant two digits (byte) are moved to the accumulator.
(iii) The nibbles of the accumulator are reversed and the least significant nibble
is exchanged with the value stored in memory location 35H.
(iv) The result is stored in memory location 50H.
(v) The same process is repeated for the next byte and the result is stored in
memory locations 51H and 52H.
Program:
MOV 35H, #00H ; Initialize the intermediate storage register.
MOV RO, #35H ; Initialize the memory pointer.
MOV A, 30H ; Move the least significant two digits of the data
to the accumulator.
SWAP A ; Exchange the two digits (nibbles) within the data.
XCHD A, @R0 ; Move the tens digit to the memory.
MOV 50H, A ; Register A has units digit of BCD data in the
upper nibble and 0 in the lower nibble and this is
stored in memory.
MOV A, 31H ; Move the higher-order data to register A.
SWAP A ; Exchange the lower-order and higher-order nibbles.
XCHD A, @R0 ; Move the thousands digit to the memory and
the tens digit to register A.
MOV 51H, A ; Save the shifted data in the memory.
MOV 52H, @R0 ; Save the thousands digit.
Example 10.6:
Read a byte from port 0 and depending on which bit is set, jump to one of eight
different locations.
Algorithm:
(i) First, the byte is moved from port 0 to one of the bit-addressable bytes (i.e.,
within 20H-27H of the SFR).
(ii) Then, depending on which bit is set, control is transferred to one of eight
different locations.
(iii) Control is returned to the start of the program to read the next data in the
port.
Program:
LOOP: MOV 20H, PORT 0 ; Get the data from port 0 to internal RAM 20H.
JB 00, LI ; Check the LSB using the bit address and
if set, jump to the relative address LI
JB 01, L2
JB 02, L3
JB 03, L4
JB 04, L5
JB 05, L6
JB 06, L7
JB 07, L8
LJMP LOOP
In this program, L1-L8 are the 8-bit relative addresses to which the branching has
to take place. The 8-bit relative address is assumed to be a 2’s complement number
and branching takes place above or below the main program.
Example 10.7:
Reverse the bits in a byte.
Algorithm:
(i) Assume that the byte to be reversed is stored in register RO.
(ii) Register RI is initialized with OOH and register R2 with 08H for use as
counter.
(iii) The byte from register RO is loaded in the accumulator.
(iv) The accumulator is shifted left through the carry and exchanged with
register RI. Now, the LSB of the data is moved to the carry and the shifted
data is moved to RI.
(v) The accumulator is shifted right through the carry and exchanged again
with register RI. Now, the LSB in the carry is shifted into register RI.
(After subsequent shifts, it is moved into the MSB of RI.)
(vi) The value stored in register R2 is decremented and if it is not zero, execution
is transferred to step 4.
Program:
MOV R0,#data ; Initialize RO with data.
MOV RI, #00H : Initialize RI with zero, to store the result
MOV R2, #08H ; Initialize the counter.
MOV A, RO : Get the data.
LOOP: RLC A : Bring one bit to the carry.
XCH A, RI : Bring RI to register A.
RRC A ; Move the bit in the carry flag in reverse
order into RI.
XCH A, RI ; Bring the shifted data to the accumulator,
for shifting the next bit.
DJNZ R2, LOOP : Check if all eight bits have been reversed.
If not, repeat the process for the next bit
MOV 30H, RI ; Store the result from register RI in the
internal RAM location 30H.
WAIT: SJMP WAIT ; Loop indefinitely here.
Example 10.8:
Find the biggest number in a block of data stored in the memory locations 70H-
7FH.
Algorithm:
(i) A memory pointer is initialized to point to the starting address of the series
of memory locations.
(ii) A counter is initialized for the number of data.

(iii) The first byte stored in the block is assumed to be the biggest number and is
stored in register RI.
(iv) The next data is compared with the data in RI.
(v) If the data in RI is smaller, the data in the block is stored as the biggest
number in register RI.
(vi) This process is repeated for all the data in the block.
Program:
MOV RI, #00H ; Initialize RI to store the biggest
number.
MOV RO, #70H : Initialize the memory pointer.
MOV 30H, @R0 : Store the first data as the biggest,
in register 30H.
MOV RI, 30H ; Store it in register RI also.
LOOP: INC RO ; Point to the next location.
MOV A, RI : Bring the biggest data to the
accumulator.
SUBB A, @R0 : Compare by subtracting the next data
from the biggest.
JNC NEXT : If there is no carry, the data is
smaller. So, jump to NEXT.
MOV 30H, @R0 ; If the compared data is bigger, bring
it to register 30H as the biggest
data.
MOV RI, 30H ; Store it in register RI also.
NEXT: CJNE RO, #80H, LOOP ; Repeat these steps for all the data
in the memory up to the address 7FH.
The programs in this section illustrate only the basic instructions of the 8051.
In general, the instruction set of the 8051 is very flexible. Therefore, readers are
recommended to go through all the 8051 instructions.
POINTS TO REMEMBER
• Intel 8051 supports data types such as integer, signed integer, and bits. There are
instructions to support these data types.
• The Intel 8051 instructions are classified based on their operations as data transfer,
arithmetic, logical, and branching instructions.
• Intel 8051 supports immediate, direct, indirect, indexed, and relative addressing
modes.
• Some instructions support only specific addressing modes.
• The flag register plays an important role in conditional jumping instructions.
• Relative jumping instructions use an 8-bit signed number as the offset to be added to the
program counter contents, to get the branching address.
KEY TERMS
Absolute jump This refers to jumping using the 11-bit address mentioned in the
instruction, keeping the most significant five bits the same as in the PC.
Long jump This refers to jumping using the 16-bit address in the instruction.
Short jump This refers to jumping using the 8-bit relative address added to the contents
of the PC.
REVIEW QUESTIONS
1. Where are the registers R0-R7 located in the 8051 microcontroller?

2. What is the need for bit addressing?
3. How do you classify the 8051 instructions based on (i) length of the instruction,
(ii) addressing mode, and (iii) functions performed. Give two examples for each.
4. Give one example each for one-byte, two-byte, and three-byte instructions of the
8051.
5. Write the instruction that is used to clear the accumulator content.
6. What is the function of the instruction XCHD?
7. What type of addressing is used to move data from the external memory to the
accumulator?
8. Which instruction can be used to access the I/O ports of the 8051 ?
9. Name the programming constructs where CJNE can be used.
10. When is the instruction DJNZ useful?
11. Differentiate between the execution of the instructions ADD and ADDC. When is
ADDC used?
PROGRAMMING EXERCISESl
1. Write a program to multiply two 8-bit numbers in the internal RAM and store the result
in the external RAM. [Hint: Use MOVX instruction to access external memory.]
2. Write a program to divide a number in the internal RAM location 40H by the number
in the location 41H. Store the quotient in 50H and the remainder in 51H.
3. Write a program to search for a particular data in a block of internal RAM. Identify and
store the memory location of that data.
4. Write a program to arrange a block of binary numbers in ascending order.
THINK AND ANSWER
1. Find the address to which program execution is transferred after the execution of the
instruction SJMP FOH, if it is stored in the address 8811H.
2. Find the relative address to be used in the SJMP instruction, so that the same SJMP
instruction is executed after jumping.
3. Explain the difference between the following instructions:
JB 30H, 4EH
JBC 30H, 4EH
CHAPTER 11
HARDWARE FEATURES OF 8051

LEARNING OUTCOMES
• Structure, addresses, and operation of 8051 ports
• External memory interfacing in the 8051
• Features, operation, and programming of 8051 timers
• Interrupts in the 8051, their sources, priorities, and timing
• Features, operation, and programming of 8051 serial port
11.1 INTRODUCTION
The major benefit of microcontrollers lies in their built-in parallel ports. The
parallel ports can be used to interface all data converters (ADCs, DACs, etc.) and
display devices (LEDs, LCDs, etc.).
Any microcontroller-based system needs to transfer data between the external
peripherals and the microcontroller. The microcontroller needs to read data fed
by the user from the external interface, process it, and give the output to the
peripherals or to the user again. To communicate data with the external world, the
microcontroller needs ports. The ports may support either parallel or serial data
transfer.
11.2 PARALLEL PORTS IN 8051

The 8051 has four I/O ports—port 0, port 1, port 2, and port 3. The major constraint
in microcontroller chips is the number of pins. To reduce the number of pins, the
pins allotted for parallel ports are assigned some alternative functions as well.
Out of the four parallel ports available in the 8051, port 1 is used exclusively for
input and output functions. The other port pins have functions other than input and
output. So, the 24 pins of ports 0, 2, and 3 perform functions other than parallel
data transfer. These functions are decided by the hardware interfaced and the
instructions being executed.
All the four ports are bidirectional, i.e., they can be programmed to perform
input or output operation. The eight port pins are connected through eight D-type
port latches. A D-type latch connects the data in it to a port pin, when the port is
used as an output port.
The user can access all the four ports using their addresses mapped in the
special function register (SFR) area. Tables 11.1 (a) and 11.1 (b) list the SFR
addresses of the parallel ports and the addresses of the individual parallel port
pins, respectively. Note that it is possible to address individual bits of all the four
ports by their bit addresses. Using these bit addresses, individual bits can be read
or changed.
Table 11.1 (a) Addresses of parallel ports of 8051
Port Byte address Port Byte address
Port 0 80 Port 2 A0
Port 1 90 Port 3 B0
Table 11.1 (b) Addresses of parallel port pins of 8051
Port pins Bit address Port pins Bit address
Port 0.0 80 Port 2.0 A0

Port 0.1 81 Port 2.1 Al
Port 0.2 82 Port 2.2 A2
Port 0.3 83 Port 2.3 A3
Port 0.4 84 Port 2.4 A4
Port 0.5 85 Port 2.5 A5
Port 0.6 86 Port 2.6 A6
Port 0.7 87 Port 2.7 A7
Port 1.0 90 Port 3.0 B0
Port 1.1 91 Port 3.1 Bl
Port 1.2 92 Port 3.2 B2
Port 1.3 93 Port 3.3 B3
Port 1.4 94 Port 3.4 B4
Port 1.5 95 Port 3.5 B5
Port 1.6 96 Port 3.6 B6
Port 1.7 97 Port 3.7 B7
Figure 11.1 shows the parallel ports in the 8051 and their pins.
11.2.1 Structure of Port 1

Port 1 is the only port in the 8051 that is used exclusively for input and output
operations. The structure of port 1 is shown in Fig. 11.2. The output of the port
latch is connected to the port pin through a transistor driver with an internal pull-
up resistor. The port can be operated as an input port after writing the data ‘1’ in
all the bits of the port 1 latch.
The 8051 ports are organized such that most instructions read the data from the
pin for the read operation and some read the data from the latch. So, to distinguish
between these instructions, the input buffer contains the select logic and the related
control signals—Read latch and Read pin.
HARDWARE FEATURES OF 8051 331
+5V
40
30 39
ALE P0.0/AD0
31 38
EA P0.1/AD1
29 37
PSEN P0.2/AD2
9 36
C2 RST P0.3/AD3
35
P0.4/AD4
h n33PF 34
P0.5/AD5
18 33
XTAL2 P0.6/AD6
19 32
XTAL1 P0.7/AD7
X1
1 21
P1.0 P2.0/AD8
Ld U33pf 2 P1 1 P2.1/AD9
22
C1 3 23
P1.2 8051 P2.2/AD10
4 24
P1.3 P2.3/AD11
5 25
P1.4 P2.4/AD12
6 26
P1.5 P2.5/AD13
7 27
P1.6 P2.6/AD14
8 28
P1.7 P2.7/AD15
10
P3.0/RXD
11
P3.irrxD
12
P3.2/INT0
13
P3.3/INT1
U
P3.4/T0
15
P3.5/T1
j6
P3.6/WR
17
P3.7/RD
Fig. 11.1 Parallel ports and port pins of 8051
Read latch
Internal bus
Write to latch
Read pin
Input buffer Latch Output driver
Fig. 11.2 Internal structure of port 1
11.2.2 Structure of Ports 0 and 2

Pins of ports 0 and 2 can be used as input port pins if a ‘1’ is written in the
corresponding port latches by the programmer. For using the pins of ports 0 and
2 as output pins, a pull-up resistor may have to be connected to the corresponding

port pins. The internal structure of port 0 is shown in Fig- 11-3.
Fig.11.3 Internal structure of port 0
Besides input and output, ports 0 and 2 have an alternative function—they can
be used as address/data bus when external memory or I/O devices are accessed.
Port 0 acts as the lower-order address bus and port 2 acts as the higher-order
address bus. The drivers of ports 0 and 2 have an internal multiplexer for this
purpose. The internal structure of port 2 is shown in Fig. 11.4.
Read latch
Internal bus
Write to latch
Read pin
Input buffer Latch Output driver
Fig. 11.4 Internal structure of port 2
11.2.3 Structure of Port 3

Port 3 is different from the other ports in the aspect that its individual port pins
can be programmed for input and output operations. Each pin of port 3 can be
programmed separately for input operation, output operation, or other alternative
functions. The alternative functions allotted to each port 3 pin are given in
Table 11.2. All the port 3 pins serve an alternative function, based on the hardware
signals and interfacing.
Table 11.2 Alternative functions of port 3 pins
Port pin Alternative function

P3.0 RXD—Serial input data line
P3.1 TXD—Transmit data line
P3.2 INTO—External interrupt 0
P3.3 INTI—External interrupt 1
P3.4 TO—Timer 0 external input
P3.5 T1—Timer 1 external input
P3.6 WR—External data memory write strobe
P3.7 RD—External data memory read enable
The internal structure of the port 3 pins is shown in Fig. 11.5. From the figure
it can be understood that the alternative functions can be activated only if the
data ‘1’ is written in the port 3 bits.
Fig.11.5 Internal structure of port 3
With respect to port access, there are two possibilities for the read operation.
The read instruction for a port can read either the port latch or the port pins. This
difference is made in the internal hardware of the 8051, to avoid misinterpretation
of the voltage level at the pins. Some of the instructions read a port, modify the
data, and write the data back into the port. These instructions read the data from the
latches and not the pins. All other instructions accessing the ports read the data from
the port pins only. Examples of instructions that read the port latch are as follows:
ANL Pl, A
ORL P2, A
XRL P3, A
INC P0
DEC Pl
JBC Pl.l, DELAY
CPL P3.0
DJNZ P3, LABEL

CLR P3.1
SETB Pl.2
MOV P2.2, C
Note that these instructions read the port, modify the contents, and then write
the data back into the port. Hence, the port latches are read and not the pins.
11.3 EXTERNAL MEMORY INTERFACING IN 8051

External memory interfaced with the 8051 can be of two types—external program
memory and external data memory. External memory accesses are accomplished
with ports 0 and 2 of the 8051, as they serve as the multiplexed address/data buses.
The external memory in the 8051 is always accessed with 16-bit addresses. The
8051 outputs the ALE (address latch enable) signal to de-multiplex the lower-order
address and data bus. In addition, the microcontroller sends the control signals on
the port 3 lines.
11.3.1 Program Memory Interfacing

In addition to the internal program memory, additional program memory can
be placed outside the chip. In another method, the entire program memory can be
placed outside the chip, neglecting the internal program memory. Applying the
proper voltage level on the input line EA of the 8051 can select one of these two
methods.
Connecting EA to the ground will disable the internal program memory; only the
external program memory will be accessible. The Read strobe signal given by the
microcontroller is PSEN. This active low signal is connected to the Read selection
line of the memory chips. Figure 11.6 shows the hardware signal connections for
such a memory interface to the 8051.
Fig. 11.6 Interfacing external program memory to 8051

Connecting the EA pin of the 8051 to logic 1 or +5V will program the
microcontroller to use the internal program memory for the addresses starting
at 0000H. After the available internal memory is used completely, the external
memory is accessed.
If EA = 0, the internal program memory is not accessed.
If EA = 1, the internal program memory is accessed for the address range 0000H-
OFFFH (or the available range) and the external program memory is accessed for
addresses greater than OFFFH.
Example 11.1:
Design an interface circuit to connect a 16 KB EPROM IC 27128 to the 8051.
Solution:
As the 27128 has 16 KB of memory registers, 14 address lines are required to
select one memory location. The first step in interfacing is to select or fix the
address range for the chips to be used. So, the address map of the 27128 is fixed
as 0000H-3FFFH. The most significant bits A14 and A15 are used to decode and
select the chip. For decoding purposes, a 2-to-4 decoder chip, the 74139, is used.
The 74139 has a dual 2-to-4 decoder and one of them is used for selecting the
EPROM chip. The connection diagram is shown in Fig. 11.7. The 8-bit latch or
register IC 74373 is used to de-multiplex the lower-order address and data bus.
OE is the data read enable line of the 27128 and is connected to the PSEN signal
output of the 8051.
Fig. 11.7 Interfacing EPROM IC 27128 to 8051

11.3.2 Data Memory Interfacing

The data memory in the system should be random access memory, as it should
facilitate both read and write operations on data. The external data memory is
interfaced in the same way as the program memory, as shown in Fig. 11.8. The
major difference between data memory and program memory is that read and
write operations can be done in random access data memory, whereas only read
operation is possible in program memory. The control signals for reading from
and writing into data memory are obtained from the port 3 pins. P3.6 pin sends the
data memory write enable signal and P3.7 pin sends the RAM read enable signal.
A decoder logic circuit is necessary to select the RAM chip, based on the higher-
order address lines.
Fig. 11.8 Interfacing external data memory to 8051

Example 11.2:
Design an interface circuit to connect an 8 KB RAM IC 6264 to the 8051.
Solution:
IC 6264 has 8 KB of static RAM. So, 13 address lines are required to select a
memory location. The first step in interfacing is to select the address range for
the chip to be used. The address range for the RAM chip is selected as C000H-
DFFFH. The most significant bits A14 and Al5 are used to decode and select the
chip. Bits Al4 and Al5 are at logic 1 for the address range selected. So a 2-to-4
decoder chip, the 74139, is used and the Y3 output is made active low when the
A14 and Al5 lines are at logic high. This Y3 signal is used as the active low chip
select input of the IC 6264. The connection diagram is shown in Fig. 11.9. The
data read enable line of the 6264 is OE, which is connected to the P3.7 port output
'of the 8051. Similarly, the write enable input 6264 is connected to the port line
P3.6 of the 8051. The 8-bit latch or register IC 74373 is used to de-multiplex the
lower-order address and data bus.
11.3.3 Timing Diagram for External Program and Data Memory Access
The timing diagram for the 8051 program memory access is given in
Fig. 11.10 (a). As discussed earlier, port 0 is used for the lower-order address as
well as for data. Port 2 is used for the higher-order address. Program memory
selection is done by the active low PSEN signal.
During the first state, the lower-order address from the program counter is
placed on the port 0 lines. To de-multiplex the lower-order address bus and the
data bus, an active high signal is sent on the ALE line. This signal is used by
the external latch to hold the lower-order address. The PSEN signal is used as a
Read signal for the memory. During the second state, the microcontroller sends the
higher-order contents of the program counter on the port 2 lines. During the fourth
state of the machine cycle, the data (or the opcode in this case) is placed on the
port 0 lines by the program memory, which is read by the microcontroller. The last
two states or four clock cycles in a machine cycle can be used for the next memory
access. So, in 8051 microcontrollers, during one machine cycle, two memory read
operations are possible, using the ALE signal twice. If the instruction read is a
one-byte instruction, the second byte read is discarded.
The timing diagram for signals related to external data memory write operation
is given in Fig. 11.10 (b). The external data memory, with 16-bit addresses, is
accessed using the MOVX instruction; the data pointer DPTR is used to hold
the address of the data memory. Port 0 sends the lower-order byte of DPTR and
One machine cycle
Clock
signal
ALE
WR
Port 2
PortO
Fig. 11.10 (a) Timing diagram for external program memory access (b) Timing diagram for
external data memory access—write operation
port 2 sends the higher-order byte. The active low Write signal is sent by the
microcontroller on the line P3.6. As seen in the program memory access timing
diagram in Fig. 11.10 (a), the memory access for the data memory can be started
in the fifth state, S5, of a machine cycle and completed in the fourth state, S4, of
the next machine cycle.
The external memory read access also follows the timing diagram given in
Fig. 11.10 (b) with the control signal WR replaced with RD. The data is transferred
from the memory devices to the microcontroller. The active low RD signal is sent
out through the P3.7 line.
11.4 8051 TIMERS

The basic Intel 8051 has two 16-bit timers. These timers are accessible to the
programmer through the corresponding SFR registers. They can be initialized,
run, read, and controlled by these registers. The 8051 timers have three general
functions:
(i) Producing a delay for a definite time and then issuing an interrupt request
(ii) Counting the transitions on an external pin
(iii) Generating baud rates for the serial port
Basically, timers are digital counters that are incremented when a pulse is given
to them. They can be controlled to do any of their functions, using four SFRs—
TMOD, TCON, TH0/TL0, and TH1/TL1. A timer overflows when it counts to
the highest value and resets to 0 on next count. The overflow in the timers sets
the two bits in the TCON SFR. This overflow can be programmed to interrupt the
microcontroller execution and execute a predefined subroutine.
If the timer registers are incremented by the internal clock pulses from the
microcontroller, the operation is called timing. If the timer registers get their clock
pulses from an external device through the port 3 pins of the 8051, the operation
is called counting. Timer 0 external input pin P3.4 (TO) is used to give clock input
to timer 0 to act as a counter. Timer 1 external input pin P3.5 (Tl) is used to give
clock input to timer 1.
11.4.1 Timer SFRs

The 8051 has two timers, both of which have similar operations and functions.
The timer in the 8051 is basically a 16-bit register, which can be incremented
based on the clock pulses applied to it. These timer registers are configured as
SFRs. One timer is Timer 0 and the other is Timer 1. Each timer has two 8-bit
SFRs. TH0 and TL0 form the higher- and lower-order bytes of Timer 0; TH1
and TL1 form the higher- and lower-order bytes of Timer 1. These SFRs, at any
time, have the timer/counter register content. So, the timers can be stopped at any
time and the contents can be read from these registers. As the timers have 16 bits,
the timer content/count value can vary from 0 to 65,535. The timer content will
become 0 after counting up to 65,535. This is called as overflow. The overflow
will be indicated by the setting of the timer overflow interrupt flag.
The two timers share two SFRs for control—the TMOD and TCON registers.
Table 11.3 shows the timer-related SFRs and their addresses.
Table 11.3 SFRs related to timers
SFR name Description SFR address

THO Timer 0 higher-order byte 8CH
TLO Timer 0 lower-order byte 8AH
TH1 Timer 1 higher-order byte 8DH
TL1 Timer 1 lower-order byte 8BH
TCON Timer control 88H
TMOD Timer mode 89H
TMOD SFR
The TMOD SFR in the 8051 controls the timer operation. The TMOD register bits
are used to select the timer operating modes, counting or timing operation, and
gate control. The higher-order four bits are used for Timer 1 and the lower-order
four bits are used for Timer 0. The individual bits of TMOD have the functions
shown in Table 11.4.
Table 11.4 Bit patterns for TMOD (89H) SFR
D7 D6 D5 D4 D3 D2 D1 DO
T1 T1 TO TO
GATE1 C/Tl GATE0 C/T0
Ml MO Ml M0
1—count 1— count Mode set 1—count 1— Mode set
only if pulses on 00— 13-bit only if INTO count 00—13-bit
INTI pin the pin T1 timer pin (P3.2) pulses timer
(P3.3) (P3.5) input is high on the
input is 01—16-bit pin 01—16-bit
high 0—count timer 0—count T0(P3.4) timer
on every regardless of
0—count machine 10—8-bit INTO pin 0— 10—8-bit
regardless cycle auto reload count auto reload
of INTI mode on every mode
pin machine
11—Split cycle 11—Split
timer mode timer mode
For each timer, two bits are used to specify the mode of operation. So each timer
can be operated in any one of four modes.
TCON SFR
The SFR that controls the two timers and provides valuable information about
them is TCON. The TCON SFR bit pattern is given in Table 11.5.
Table 11.5 Bit patterns for SFR TCON (88H) SFR
Bit Name Bit Explanation of function Timer

address
D7 TF1 8FH Timer 1 overflow—The microcontroller sets 1

this bit when Timer 1 overflows.
D6 TRI 8EH Timer 1 run—The microcontroller turns on 1
Timer 1 when this bit is set. When this bit is
cleared, Timer 1 is turned off.
D5 TF0 8DH Timer 0 overflow—The microcontroller sets 0
this bit when Timer 0 overflows.
D4 TRO 8CH Timer 0 run—The microcontroller turns on 0
Timer 0 when this bit is set. When this bit is
cleared, Timer 0 is turned off.
The higher-order four bits of the TCON SFR are described in Table 11.5. The
lower-order four bits are related to interrupts and are explained in Section 11.5.
Note that the individual bits of TCON register can be addressed separately by their
bit addresses. This allows the programmer to run the timers using bit-addressable
instructions and check the overflow independently.
11.4.2 Timer Operating Modes

The two 16-bit timers of the 8051 can be operated in any one of four modes. Mode
selection can be done by setting the proper bits in the TMOD SFR. The basic
modes of operation are tabulated in Table 11.6.
Table 11.6 Operating modes of 8051 timers
TxM1 TxMO Timer mode Description of mode
0 0 0 13-bit timer
0 1 1 16-bit timer
1 0 2 8-bit auto reload
1 1 3 Split timer mode
Mode 0—13-bit Timer Mode

Timer mode 0 is a 13-bit timer. Of the 16 bits available for the timer, only 13 bits
are used. Five bits of the lower-order byte and eight bits of the higher-order byte
are used in mode 0. The lower-order byte TL0/1 counts from 0 to 31. When TL0/1
is incremented from 31, it resets to 0 and increments TH0/1. So the timer can only
contain 8192 values from 0 to 8191.
Figure 11.11 shows how the timer of the 8051 is operated in mode 0. As
explained earlier, the timer can be operated as a timer with internal clock pulses or
as a counter with external clock pulses. This selection is done by D2 bit of TMOD
for Timer 0 and D6 bit of TMOD for Timer 1, as shown in Table 11.4.
Fig. 11,11 Mode 0 operation of Timer 1 of 8051
The clock pulses selected by D2 and D6 bits of TMOD are then controlled by
programmer setting and connected to the timer registers. The control is done by
three different means. The first is the Timer Run control bits D4 and D6 of the
TCON register. The timer will run only when the Timer Run control bits are set
to 1. Other controls for the timer are through the GATE control bits D4 and D7 of
TMOD and the external inputs for the timer. Setting GATE to 1 allows the timer
to count only if the external control input INTO or INTI is set to 1. Setting GATE
to 0 will disable the corresponding external timer control inputs INTO and INTI.
Setting the timer to mode 0 will make it overflow back to zero, after 8192
counts. This will set the TF1 and TFO bits for Timer 1 and Timer 0, respectively.
Mode 1—16-bit Timer Mode
In timer mode 1 of the 8051, each timer is operated as a 16-bit timer. This is a
very commonly used mode. It functions just like mode 0, except that all 16 bits are
used. As mode 1 uses 16 bits, the counter will count from 0 to 65,535. The clock
pulses are applied to the lower-order eight bits and the overflow from this lower-
order byte will be counted by the higher-order byte.
Timer operation in mode 1 and control of its gating are similar to mode 0, as
shown in Fig. 11.12.
Fig. 11.12 Mode 1 operation of Timer 1 of 8051
Mode 2—8-bit Timer Auto Reload Mode

Timer mode 2 is an 8-bit auto reload mode. When a timer is in mode 2, TH0/1
holds the ‘reload value’ and TL0/1 is used as the timer. Thus, TL0/1 starts counting
up. Overflow from TL0/1 after counting up to 255 sets the bits TFO/1 in TCON
register and also reloads the timer register TL0/1 with the contents of THO/1. The
reload does not affect THO/1 and leaves it unchanged.
For example, let us say THO holds the value FDH and TLO holds the value
FEH. At the next counting pulse, TLO will be incremented to FFFI. Then for the
next pulse, the TLO will overflow and will become OOH. As it is in reload mode, the
TLO will be loaded with the value in THO, i.e., FDH. The value of THO will never
change. THO/1 is set to a known value and TL0/1 is the SFR that is constantly
incremented. The auto reload mode is very commonly used for establishing a baud
rate for serial communications.
Timer operation in mode 1 and control of its gating are similar to mode 0, and
are shown in Fig. 11.13.
Mode 3—Split Timer Mode

The operation of the timers in mode 3 is shown in Fig. 11.14. Mode 3 of the 8051
timer is a split timer mode and is applicable only for Timer 0. When Timer 0 is
operated in mode 3, it essentially becomes two separate 8-bit timers, i.e., Timer 0
is TLO and Timer 1 is THO. Both timers count from 0 to 255 and overflow back
to 0.
Fig. 11.14 Mode 3 operation of Timer 0 of 8051
In mode 3, all the bits that are related to the real Timer 1 simply hold their
count and do not run. The situation is similar to maintaining TRI at 0. In split
timer mode of Timer 0, the real Timer 1 (i.e., TH1 and TL1) cannot be started or
stopped, since the related control bits are now linked to THO. The real Timer 1, in
this case, will be incremented every machine cycle.
When two separate timers, in addition to a baud rate generator, are required in
an application, the real Timer 1 can be used as a baud rate generator and THO/TLO
can be used as two separate timers in mode 3.
11.4.3 Timer Control and Operation

For timer operation (C/T = 0 in TMOD), the timer register counts the divided-
down clock. The timer register is incremented once every (FOSC/12) in standard
mode. If the clock frequency is 1,10,59,000kHz, the counter will be incremented
at the rate of (l,10,59,000kHz/12) = 9,21,583kHz. This means the counter will
be incremented 921,583 times in a second. Thus, to produce a delay of, say, 0.1
seconds, the counter must be initialized to the count value (0.1 x 921,583) =
92158.
For counter operation (C/T = 1), the timer register counts the negative transitions
on the T0/T1 external input pin (alternative function of port 3). The external input
is sampled every clock cycle. When the sample is high in one cycle and low in the
next, the counter is incremented. Since it takes two cycles to recognize a negative
transition, the maximum count rate is (FOSC/24) in standard mode.
The following steps describe the algorithm to initialize and use a timer in the
8051. The algorithm is shown in the form of a flowchart in Fig. 11.15.
(i) Decide what mode the timer should be in.
(ii) Initialize the TMOD SFR.
(iii) Write the timer value into the timer
register.
(iv) Start the timer by setting the TR0/1 bit
in the TCON register.
(v) Check for TF0/1 bit or program to
handle timer overflow as an interrupt
and execute interrupt subroutine.
To set the bit TRI of TCON (D6 bit), any one

of the following two commands can be used:
MOV TCON, #40H or SETB TRI
As TRI is a bit-addressable location, SETB
instruction is used. This has the benefit of
setting the TRI bit of TCON without changing
the value of any other bit of the SFR.
There are two common ways of reading the
value of a 16-bit timer:
(i) Read the actual value of the timer as
a 16-bit number from THO/TLO or
Fig. 11.15 Steps in timer control
TH1/TL1.
(ii) Detect when the timer has overflowed, from the TF0/1 bits of TCON. If
TF0 is set, it means that Timer 0 has overflowed; if TF1 is set, it means
that Timer 1 has overflowed. This overflow can act as an interrupt and can
directly run an interrupt service routine, if enabled properly.
11.4. 4 Using Timers as Counters

Timers in the 8051 can be programmed to count pulses from external devices. In
practice, these pulses can be due to any event. For example, a sensor placed along
a conveyor belt can give one pulse for every object moving on the conveyor. This
pulse can be counted by the 8051 timer in counter mode. The pulses from the
sensor can be given as an external input to a timer and programmed to count. The
timer can be programmed to produce an interrupt after a predefined count value.
For example, after counting 12 objects in the conveyor or after counting 12 pulses
in the timer, an interrupt may be given to the 8051 system to produce a signal for
another action such as packing the 12 items. Example 11.5 explains this concept.
The 8051 microcontroller timers when operated as counters, can count pulses
applied on the external pin P3.4 in Timer 0 and on pin P3.5 in Timer 1. The
microcontroller will scan the voltage levels on these pins after every machine
cycle, i.e., every 12 clock cycles. To detect the rise and fall on these pins as a
pulse input, the microcontroller requires 24 clock cycles or two machine cycles.
So, the maximum frequency of the external pulses that can be counted by the
microcontroller is 1/24 of the system clock frequency. For the 12 MHz clock, the
maximum frequency that can be counted is 5,00,000 pulses per second. For higher
frequencies, the microcontroller cannot count accurately.
11.4. 5 Programming Examples

In this section, we shall discuss some programs involving 8051 timers.
Example 11.3:
Write a program to generate a square wave of frequency 2 kHz on any one of the
port pins, using Timer 0, assuming that the clock frequency of the 8051 system is
12 MHz.
Solution:
As a continuous square wave has to be generated, the 8-bit timer auto reload mode
is selected for this operation. Since the clock frequency is 12 MHz, after dividing
by 12, the counter will get the clock pulses at the rate of 1 MHz. So, the counter
will be incremented after every 1 ps.
To generate a square wave of 2 kHz, the period should be set to 500 ps
(1/2kHz). This means that the program must give an output of logic 1 for
250ps and logic 0 for another 250 ps, so that a square wave of 500 ps period can
be generated. Here, as the counter is incremented after every microsecond, the
counter has to count up to 250. The counter will overflow after every 250 counts.
During an overflow, the logic output on the pin will be inverted. By doing this
continuously, a square wave can be generated.
This program uses the polled method to check whether the timer overflow has
occurred. The LSB of port 1 is used to generate the square wave.
MOV TMOD, #000000106 ; Set Timer 0 in mode 2.
CLR TFO ; Clear Timer 0 overflow flag.
CLR P1.0 ; Output logic 0 on the LSB of port 0.

MOV THO, #050 ; Initialize Timer 0 with (2550 - 2500) so that
it will overflow after 250 ps.
SETB TRO : Start or run Timer 0 by setting the TRO bit.
LOOP: JNB TFO, LOOP ; Read, check, and loop until the overflow
bit TFO in TCON register is set.
CLR TFO : Clear the overflow flag.
CPL P1.0 ; Complement Pl bit 0.
LJMP LOOP ; Jump back for polling the overflow bit.
Example 11.4:
Write a program to generate a square wave of frequency 1 kHz on any one of the
port pins, using Timer 0, assuming that the clock frequency of the 8051 system is
12 MHz.
Solution:
Example 11.4 is similar to Example 11.3. However, to generate a square wave of
1kHz, the period should be set to lOOOps (1/1 kHz). So, the 8-bit counter mode
cannot be used, as the count value will exceed 255.
The clock frequency is 12 MHz after dividing by 12; the counter will get the
clock pulses at the 1 MHz rate. So, the counter will be incremented every 1 ps. The
program must give an output of logic 1 for 500 ps and logic 0 for another 500 ps,
so that a square wave period of 1000 ps can be generated.
The program uses 16-bit counter mode. As there is no auto reload option with
the 16-bit timer mode, the user or the programmer has to reload the count value
every time in the program. The timer should produce a delay of 500 ps. So, the
16-bit counter must be initialized to 65,035 (i.e., 65,535 - 500). The hexadecimal
equivalent of this decimal value is FE0B. Therefore, the lower-order eight bits of
the timer are initialized to 0BH and the higher-order eight bits to FEH.
The following program uses the polled method to check whether the timer
overflow has occurred. The LSB of port 1 is used to generate the square wave.
MOV TMOD, #00000001B ; Set Timer 0 in mode 1 (16-bit operation).
CLR TFO ; Clear the Timer 0 overflow flag.
CLR P1.0 ; Output logic 0 on the LSB of port 0.
LOOP: MOV THO, #OFEH ; Initialize the 16 bits of Timer 0 with the
appropriate value.
MOV TLO, #OBH
SETB TRO ; Start or run Timer 0 by setting the TRO bit.
WAIT: JNB TFO, WAIT ; Read, check, and loop until the overflow bit
TFO in TCON register is set.
CLR TRO
CLR TFO ; Clear the overflow flag.
CPL P1.0 ; Complement Pl bit 0.
LJMP LOOP ; Jump again for loading and starting the
counter.
Example 11.5:
Write a program to count 10,000 objects on a conveyor belt, assuming that a sensor
gives a pulse for every object moving on the conveyor belt. Generate an interrupt
after that. Use the ISR to give a logic 1 output on any port pin.
Solution:
To count the external pulses, Timer 1 is initialized as a counter by setting the D6
bit of TMOD. Mode 1 of Timer 1 is used in this example, as 10,000 objects are to
be counted and this can be accomplished by the 16-bit timer mode only. Timer 1
is loaded with the value 55,535 (i.e., 65,535 - 10,000), which in hexadecimal form
is D8EF. This gives an interrupt after 10,000 counts.
The program is written in two parts. The main program initializes the timer and
runs it. After that, the main program does nothing. Detecting the count value of
10,000 is done automatically by running the timer and generating an interrupt at
every overflow. Then the interrupt service routine is used to give a logic 1 output
on the port pin.
Main program:
MAIN: MOV TMOD. #01010000B Set Timer 1 in mode 1 (counter
operati on).
MOV TH1, #0D8H Load the Timer 1 highe r-order byte
MOV TL1, #OEFH Load the Timer 1 lower -order byte.
MOV IE, #10001000B Enable Timer/Counter 1 i nterrupt.
SETB TRI Start Timer/Counter 1.
LOOP: LJMP LOOP Loop and do nothing.
(Refer Section 11.5 for 8051 interrupts)

Interrupt service routine:
ISR_TIMER1: CLR TRI ; Stop Timer 1 temporarily.
SETB Pl.0 : Set the LSB of Pl.
RETI ; Return from interrupt.
11.5 8051 INTERRUPTS

Interrupt is a mechanism that makes the microcontroller interrupt the current
program execution and execute another program. The program that is executed
upon interrupt is called interrupt service routine (ISR). These routines are
considered high-priority routines, in comparison with the main program.
11.5.1 Interrupt Sources and Interrupt Vector Addresses

The 8051 has the following five interrupt sources, i.e., any of the following events
will make the 8051 execute an interrupt service routine.
(i) Timer 0 overflow
(ii) Timer 1 overflow
(iii) Reception/transmission of serial character
(iv) External hardware interrupt 0
(v) External hardware interrupt 1
The different interrupt sources have to be distinguished and the 8051 must
execute different subroutines depending on which interrupt was triggered. This
is accomplished by jumping to or calling a fixed address, when a given interrupt
occurs. These addresses are called interrupt vector addresses or interrupt handler
addresses. Table 11.7 lists the interrupt vector addresses for the five interrupts.
Table 11.7 Interrupts and their vector addresses
Interrupt Flag Interrupt vector address
External 0 IE0 0003H
Timer 0 TFO 000BH
External 1 IE1 0013H
Timer 1 TF1 001BH

Serial RI/TI 0023H
Whenever Timer 0 overflows (i.e., the TFO bit is set), the main program is
suspended temporarily and control is transferred to 000BH. It is assumed that the
service routine at address 000BH handles the Timer 0 overflow.
11.5.2 Enabling and Disabling of Interrupts

When the microcontroller is turned on, all interrupts are disabled by default. This
means that even if, for example, the TFO bit is set, the 8051 will not execute the
interrupt. Programming must be done specifically to enable interrupts.
The interrupt enable special function register IE SFR at the address A8H is used
to enable and disable interrupts by modifying its bits. Table 11.8 gives the various
bit patterns for enabling the interrupts, individually and globally. Interrupts can
be enabled individually by using the bit addresses of the individual bits of the IE
register. Table 11.8 also gives the bit addresses of the bits of the IE register.
Table 11.8 Bit patterns for IE (A8H) SFR
Bit position D7 D6 D5 D4 D3 D2 DI DO
Bit address AF AC AB AA A9 A8
Name EA - - ES ET1 EXI ETO EXO
Explanation Global Undefined Undefined Enable Enable Enable Enable Enable

interrupt serial Timer 1 External Timer 0 External
enable/ interrupt interrupt 1 interrupt 0
disable interrupt interrupt
Each 8051 interrupt has its own bit in the IE SFR. A particular interrupt can
be enabled by setting the corresponding bit. For example, to enable the Timer 1
interrupt, one of the following instructions can be executed: MOV IE, #08H or
SETB ET1.
However, before the Timer 1 interrupt (or any other interrupt) is truly enabled,
bit 7 of the IE SFR must also be set. Bit 7, which is the global interrupt enable/
disable, enables or disables all interrupts at the same time, i.e., if bit 7 is cleared,
no interrupts occur, even if all the other bits of the IE SFR are set. Setting bit 7
enables all the interrupts that have been selected, by setting other bits in the IE
SFR.
11.5.3 Interrupt Priorities and Polling Sequence

After every instruction, the 8051 automatically evaluates whether an interrupt
should occur. Interrupt conditions are checked for in the following order:
(i) External 0 interrupt
(ii) Timer 0 interrupt
(iii) External 1 interrupt
(iv) Timer 1 interrupt
(v) Serial interrupt
This list also gives the priority of the interrupts. So, whenever the External 0
interrupt and Timer 1 interrupt occur at the same instant, the 8051 microcontroller
executes the interrupt service routine corresponding to External 0 interrupt first.
Then the 8051 returns to the main program, executes one instruction, and then
executes the interrupt service routine corresponding to the Timer 1 interrupt.
This also means that if a serial interrupt occurs at the same instant that an
External 0 interrupt occurs, the External 0 interrupt routine is executed first and
then the serial intermpt routine is executed.
There are two levels of intermpt priority in the 8051—high and low. Using
intermpt priorities, the above intermpts can be divided into two separate interrupt
priority categories.
Interrupt priorities are controlled by the IP SFR (B8H), which has the format
shown in Table 11.9. For example, if the serial intermpt is more important than
the Timer 0 interrupt, the Intermpt Priority register IP SFR at the address B8H
can be programmed to set the priority appropriately. This can be accomplished by
assigning a high priority to the serial intermpt and a low priority to the Timer 0
intermpt. By setting the D4 bit to 1, the serial intermpt will be set to higher priority
and by making the DI bit 0, the Timer 0 intermpt will be set to lower priority. Note
that the priority can be set individually by using the bit addresses of the IP register.
For example, the Timer 0 intermpt priority can be made high by setting the DI bit
of the IP SFR. So, the following instructions can be used: SETB PT0, SETB B9H,
and MOV IP, #82H.
Table 11.9 Bit patterns for IP (B8H) SFR
Bit address BC BB BA B9 B8
Name EA — — PS PT1 PX1 PT0 PX0
Explanation Enable Undefined Undefined Serial Timer 1 External Timer 0 External
Interrupts— interrupt interrupt 1 interrupt 0
Made 0 to priority priority interrupt priority interrupt
disable all priority priority
• interrupts
Based on the two-level priority set by the IP register, interrupt subroutines are
executed as follows under various conditions:
(i) When a high-priority interrupt and a low-priority interrupt appear at the

same time, the high-priority interrupt will be serviced first.
(ii) When a high-priority interrupt appears during the execution of a low-
priority interrupt service routine, the high-priority interrupt will be serviced
after suspending the low-priority service routine.
(iii) A low-priority interrupt cannot interrupt a high-priority interrupt.
If there is more than one high-priority interrupt and if any two of them appear
at the same time, the priority among these two will be decided by the order in
which the interrupt conditions are checked by the hardware.
The complete structure ofthe 8051 interrupts can be understood well by referring
to Fig. 11.16. The five interrupt sources are first passed through the IE register,
which decides the enabling and disabling of interrupts. The global interrupt enable
signal is also shown in the figure. The IP register sets two priority levels among
the available interrupts. This is shown in the figure as the high priority and low
priority blocks. The bits ITO and IT1 can be set by the TCON SFR; they are used
to decide whether the hardware interrupt is level-triggered or edge-triggered.
enable
Fig. 11.16 Structure of 8051 interrupts
11.5. 4 Timing of Interrupts

The 8051 microcontroller samples the hardware signal level on its pins once in
every machine cycle. A machine cycle is the time taken by the controller to access
one memory location or I/O device. As the 8051 takes 12 clock cycles to complete
one machine cycle, the interrupt signal applied at the pins of the 8051 must be
available for at least 12 clock periods.
External interrupts are applied at the pins INTO and INTI. The sensing of the
voltage level applied to this pin can also be programmed in the 8051. The interrupts
can be either level-triggered or edge-triggered, as set by the ITO and IT1 bits of
the SFR TCON, as shown in Table 11.10. A ‘0’ in these bit positions will make
both the hardware interrupts level-triggered. When an interrupt is level-triggered,
a low-level voltage on the interrupt pin will activate the interrupt.
Table 11.10 Bit patterns for the TCON (88H) SFR
Bit address 8F 8E 8D 8C 8B 8A 89 88
Name TF1 TRI TF0 TRO LEI IT1 IE0 ITO
Interrupt Interrupt
1 type 0 type
control. control.
Timer Timer
Set to Set to
1 run 0 run
External 1 by External 1 by
Timer 1 control Timer 0 control
interrupt software interrupt software
Explanation overflow bit. Set overflow bit. Set
1 edge for edge- 0 edge for edge-
flag to 1 by flag to 1 by
detect bit triggering detect bit triggering
software software
and and
to run. to run.
cleared cleared
for level- for level-
triggering triggering
A ‘1’ on the ITO and IT1 bits of the SFR TCON will program the hardware
interrupts as edge-triggered. When an interrupt is edge-triggered, a change of
voltage from a high state to a low state will activate the interrupt.
When an interrupt is triggered, the microcontroller performs the following actions
automatically:
(i) The lower-order byte of the program counter is stored in the location
pointed to by the stack pointer and the higher-order byte is stored in the
next consecutive location.
(ii) The priority among all the interrupts received is resolved, the lower-order
priorities are blocked, and only one interrupt is considered for execution.
(iii) If the interrupt selected is a timer or an external interrupt, the corresponding
interrupt flags are cleared.
(iv) The corresponding interrupt vector address is loaded into the program
counter. This results in the execution of the interrupt service routine.
(v) The RETI instruction at the end of the interrupt service routine transfers the
execution to the main program by popping the return address from the stack
to the program counter.
The internal architecture of the 8051 is such that the external hardware
interrupts will be cleared automatically when the interrupt service routine is
executed, only if the interrupts are programmed to be edge- or transition-triggered.

If the interrupts are level-triggered, the programmer will have to reset the interrupt
enable corresponding to this interrupt, using the IP SFR.
If the interrupt being handled is a timer or external interrupt, the microcontroller
automatically clears the interrupt flag before passing control to the interrupt handler
routine. This means it is not necessary to clear the bit in the program.
11.5. 5 Programming Examples

Example 11.6:
Write a program to generate a square wave of 10kHz on the LSB of port 1, i.e.,
P1.0, using a timer.
Solution:
In this example, the timer is initialized in mode 2. This is the 8-bit auto reload
mode. The clock frequency applied to the counter is assumed to be 1 MHz. So, the
counter is incremented every 1 ps. To generate a square wave of 10kHz, the port
pin is toggled after every 1/ (2x10,000) s. This time is calculated to be 50 ps. So,
the counter is loaded with the count value of 50 to generate a delay of 50 ps.
The LSB of port 1 is toggled in the interrupt service routine. The timer will
give an interrupt after every 5Ops.
ORG OOOBH ; Timer 0 interrupt vector
OOOBH: CPL P1.0 jToggle the port bit.
RETI
Main program:
MOV TMOD, #02H ; Initialize Timer 0 in mode 2.
MOV THO. #-50 ; Initialize the reload value with 50, to
produce 50ps delay.
SETB TRO : Start Timer 0.
MOV IE, #82H ; Enable Timer 0 interrupt.
Loop: SJMP Loop ; Loop and do nothing.
Example 11.7:
Construct a digital clock, using an 8051 system employing a 12 MHz clock. Use
timer and interrupt.
Solution:
To implement the digital clock, Timer 0 is used in this example. The timer is
initialized in mode 1 and is programmed in timer mode (C/T0 = 0) in the TMOD
register. The priority for the timer 0 interrupt is made high in the IP register and
all other interrupts are set to low priority. To enable the Timer 0 interrupts, the
appropriate control word is written into the IE register.
The timer will be incremented every 1 ps. To produce clock operation, an
interrupt is needed every 1 s. So, it has been designed to give one interrupt every
(1 /60)01 of a second, i.e., every 16.67 ms. So, the Timer 0 must be made to count up
to 16,667, to give an interrupt every (l/60)lh of a second. So, the timer is initialized
to 48869 (i.e., 65536 - 16667) in decimal form or BEE5 in hexadecimal form.
Four registers—RO, RI, R2, and R3—are used to store time values, the values
of (l/60)lh of a second, seconds, minutes, and hours, respectively. These registers
are incremented in the interrupt service routine. If these register contents exceed
their maximum value, the registers are reset to their initial values. Care must be
taken to avoid using the registers RO to R3 in the main program.
Algorithm:
(i) Program the timer to produce an interrupt every (l/60)Ih of a second.
(ii) In the ISR, increment the seconds register.
(iii) If it is greater than 59, increment the minutes register and reset the seconds
register.
(iv) If the minutes register is greater than 59, increment the hours register and
reset the minutes register.
Control word setting:

The control word setting, which uses the TMOD, TCON, IP, and IE registers, is
given in Tables 11.11 (a), 11.11 (b), 11.11 (c), and 11.11 (d), respectively.
Table 11.11 (a) TMOD register bit pattern
Name GATE1 C/Tl T1M1 TIMO GATEO C/TO TOMI TOMO
Data 0 0 0 0 0 0 0 1
= 01H
Table 11.11(b) TCON register bit pattern
Name TF1 TRI TFO TRO IE1 IT1 IE0 ITO
Data 0 0 0 •1 0 0 0 0
= 10H
Table 11.11(c) IP register bit pattern
Name EA — — PS PT1 PX1 PTO PXO
Data 0 0 0 0 0 0 1 0
— 02H
Table 11.11 (d) IE register bit pattern
Name EA — — ES ET1 EXI ETO EXO
Data 1 0 0 0 0 0 1 0
= 82H
Main program:
MOV TMOD, #01H Initialize the TMOD register.
MOV THO, #BEH
MOV TLO, #E5H Load the count for (l/60)th of a second in the THO
and TLO registers.
MOV RO, #00H Initialize the (l/60)th of a second register.
MOV RI, #00H Initialize the seconds register.
MOV R2, #00H Initialize the minutes register.
MOV R3, #00H Initialize the hours register.
MOV IP, #02H Initialize the Interrupt Priority register.
MOV IE, #82H Initialize the Interrupt Enable register.
SETB TRO Start Timer 0 and run it.
Interrupt service routine:

OOBH: CLR TRO 9 Clear TRO and stop Timer 0 temporarily.
MOV A, RO
ADD A, #01 9 Increment the (l/60)th of a second register.
DA A
MOV RO, A
CJNE RO, #60D, END ; Compare with 60 and return if not equal to 60.
MOV RO, #00H 9 Reset the (1/60) seconds register.
MOV A, RI
ADD A, #01H 9 Increment the seconds register.
DA A
MOV RI, A
CJNE RI, 7/6OD, END ; Compare the seconds register with 60 and
return if not equal to 60.
MOV RI, #00H 9 Reset the seconds register.
MOV A, R2
ADD A, #01H 9 Increment the minutes register.
DA A
MOV R2, A
CJNE R2, #60D, END ; Compare the minutes register with 60 and
return if not equal to 60.
MOV R2, #00H 9 Reset the minutes register.
MOV A, R3
ADD A, #01H 9 Increment the hours register.
DA A
MOV R3, A
CJNE R3, #24D. END ; Compare the hours register with 24 and return
if not equal to 24.
MOV R3, #00H ; Reset the hours register.

MOV THO. #BEH ; Load the count for (l/60)th of a second In the
THO and TLO registers.
MOV TLO, #E5H
END: SETB TRO ; Start Timer 0 again and run it.
RETI ; Return to the main program.
11.6 8051 SERIAL PORTS

One of the 8051’ s many powerful features is its integrated Universal Asynchronous
Receiver Transmitter (UART), otherwise known as serial port. With the integrated
serial port of the 8051, data can be transmitted and received easily by reading it
from and writing it to the serial port registers. The features of the 8051 serial ports
are as follows:
(i) Full-duplex operation
(ii) Receive-buffered
(iii) Access using single double-buffered register SBUF
(iv) Four different modes of operation
(v) Option to use fixed or programmable baud rate
A full-duplex serial port can transmit and receive data simultaneously.

Transmission is initiated by writing a data to the SBUF SFR register. Received
data can be read from the SBUF register. The same address SBUF actually points
to two different registers, one while reading and the other while writing. This
technique of having the same address for two different registers is called double
buffering. The receive operation is buffered through another register. This means
that the reception of the next byte can be started even when the previously received
byte is available in the SBUF register. However, when the second byte reception
is complete, the data received will be written to SBUF and the previous byte will
be lost if it is has not already been read from SBUF.
11.6.1 Serial Port Control SFRs

The serial port of the 8051 is controlled by two registers in the SFR area, as shown
in Table 11.12. The two registers are serial port control register SCON and serial
port buffer register SBUF.
Table 11.12 SFRs related to serial port
SFR name Description SFR address
SCON Serial port control register 98H

SBUF Serial port buffer register 99H
In addition to these two registers, the MSB of the PCON register (the SMOD
bit) is used to double the baud rate of serial transmission and reception. If the
SMOD bit is set to 1, the baud rate is doubled.
The individual bits of SCON have the functions shown in Table 11.13. As the
SCON register has many individual status bits, the individual bits of this register
are bit-addressable. The bit address is also given in Table 11.13. The programmer
can use these bit addresses to check the status of the serial port and set the mode
individually.
Table 11.13 Bit patterns for SCON (98H) SFR
Bit Name Bit address Explanation of function
D7 SMO 9FH
Serial port mode select bits
D6 SMI 9EH
D5 SM2 9DH Multiprocessor communications enable bit
Receiver enable—this bit must be set, to receive
D4 REN 9CH
characters
Transmit bit 8—the 9th bit to be transmitted in modes
D3 TB8 9BH
2 and 3
D2 RB8 9AH Receive bit 8—the 9th bit received in modes 2 and 3
Transmit Interrupt flag—set when a byte has been
DI TI 99H
completely transmitted
Receive Interrupt flag—set when a byte has been
DO PT
I\1 98H
completely received
The D7 and D6 bits of the SCON register define the operating modes of the
serial port; the basic operating modes are given in Table 11.14. The SMO and SMI
bits can select any one of the four operating modes described in Section 11.6.2.
Table 11.14 Definition of bits SMO and SM1 in SCON SFR
SMO SM1 Serial mode Explanation Baud rate
0 0 0 8-bit shift register FOSC/12

0 1 1 8-bit UART Variable
1 0 2 9-bit UART FOSC/64 or FOSC/32
1 1 3 9-bit UART Variable
The next bit, SM2, is a flag used for enabling ‘multiprocessor communication’
in modes 2 and 3. When SM2 is set to 1 in modes 2 and 3, the ‘Receive Interrupt’
RI flag will not be activated if the 9th data bit received is 0. When SM2 is set in
mode 1, the RI flag will not be activated if a valid stop bit is not received. This
is useful in certain advanced serial applications. For now, it can assumed that the
SM2 bit has to be cleared so that the RI flag will be set when any character is
received.
The next bit, REN, is ‘Receiver Enable’. This bit is set in order to receive the
characters from the receive data line of the serial port.
The TB8 and RB8 bits are used in modes 2 and 3. In these modes, nine data
bits are transmitted and received. The programmer must store the ninth bit to be
transmitted in TB8; RB8 holds the ninth bit received.
TI stands for ‘Transmit Interrupt’. When a program writes a data to the serial
port buffer SBUF, the serial port will start shifting this data in the serial transmit
line bit by bit at the predefined clock speed or baud rate. The 8051 will give the TI
signal to the programmer, after sending the data completely. Upon sensing that the
TI bit is set to 1, the programmer can write the next data for transmission. When
the TI bit is set, the programmer may assume that the serial port is free and ready
to transmit the next byte.
The RI bit stands for ‘Receive Interrupt’. Whenever a data is received on the
receive data line of the serial port, it is shifted to a buffer and then stored in the
SBUF register. Setting of the RI bit indicates that a byte has been received. Upon
sensing that the RI bit is set to 1, the programmer may read the data from the
SBUF.
11.6.2 Operating Modes

Bits SMO and SMI are used to select one serial port mode from the four possible
operating modes. The operating mode basically selects the number of bits to be
transmitted and received and the baud rate to be used. The four operating modes
and their differences are explained in this section. The basic operation of the serial
port of the 8051 can be understood well from Fig. 11.17.
TXD RXD
Internal data bus
Fig. 11.17 Block diagram of 8051 serial port
As mentioned earlier, SBUF is physically two registers with the same address.
When data to be transmitted is written into the SBUF register, it will be shifted bit
by bit into the TXD line of the 8051. The port 3 pin 3.1 acts as the TXD line. The
shifting is done by the transmit clock, which determines the baud rate.
Similarly, when data bits are received on the RXD line (pin 3.0 of port 3), the
bits are shifted serially into the shift register in synchronization with the receiver
clock. After the reception is complete, the data received will be placed on SBUF,
from where it can be read by the programmer through the internal bus.
Mode 0: In this mode, serial data enters and exits through the RXD pin. So, in
mode 0, full-duplex is not possible, i.e., both transmission and reception cannot
take place simultaneously. The TXD pin is used to output the shift clock in this
mode. Eight bits are transmitted/received (LSB first). The baud rate is fixed at
(l/12)th the oscillator frequency. Transmission is started by writing a data byte
into the SBUF register and once the transmission is complete, the TI flag is set.
Figure 11.18 shows the transmission of data on the RXD line.
RXD (Data out) \ pp
RXD (Shift dock) I
TI_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Fig. 11.18 Mode 0 signal transmission pattern
Similarly, reception is started by enabling REN in the SCON register. Once the
data reception is complete, the RI flag is set as shown in Fig. 11.19. The baud rate
in mode 0 is fixed at (l/12)th the clock frequency.
, Write to SCON (Clear RI)_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Fig. 11.19 Mode 0 signal reception pattern
Mode 1: In this mode, 10 bits are transmitted through TXD and simultaneously,
10 bits can be received through RXD. The 10 bits include a start bit (0), eight data
bits (LSB first), and a stop bit (1). On completion of reception, the stop bit goes
into RB8 in the SFR SCON. The baud rate is variable and is set by the Timer 1
overflow rate. The baud rates for mode 1 are fixed as follows:
Baud rate = (Timer 1 overflow rate/16) if SMOD bit in PCON SFR is set to 1.
Note that PCON is a SFR (described in Section 9.6). The MSB of the PCON
register can be set or reset by the programmer. The baud rate can be doubled by
setting the MSB of PCON. To generate the baud rate clock from Timer 1, Timer 1
can be configured in auto reload mode with the Timer 1 interrupt disabled.
As in mode 0, transmission is initiated by writing a data into the SBUF register.
Reception is enabled when REN of the SCON SFR is 1; data reception is initiated
by a 1 -to-0 transition on the RXD line.
Mode 2: In this mode, 11 bits are transmitted through TXD or received through
RXD. The 11 bits include one start bit (always 0), eight data bits (LSB first), a
programmable 9th data bit, and a stop bit (always 1). The ninth data bit transmitted
is the same as the TB8 bit in the SCON SFR. It can be assigned the values 0 or
1 by the programmer. For example, the parity bit (P in the PSW) could be moved
into TB8 for transmission as the ninth bit. On reception, the ninth data bit will go
into RB8 in the SCON SFR, while the stop bit will be ignored. The baud rate is
programmable to either 1/32 or 1/64 of the oscillator clock frequency.
Baud rate = (Clock frequency/32) if SMOD bit in PCON SFR is set to 1.
Baud rate = (Clock frequency/64) if SMOD bit in PCON SFR is set to 0.
Mode 3: In this mode, 11 bits are transmitted through TXD and simultaneously,
11 bits are received through RXD. The 11 bits include a start bit (0), eight data
bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, mode 3 is
the same as mode 2 in all respects, except the baud rate. The baud rate in mode 3
is variable.
The baud rates for mode 3 are fixed as follows, similar to mode 1:
In general, serial transmission in the 8051 starts immediately after a data is
written into the SBUF register, after initializing the serial port. Similarly, serial
data reception is possible if the REN bit of the SCON register is set. In addition,
for mode 0, the RI bit must be 0 for data reception.
11.6.3 Programming the Serial Port

The flowchart in Fig. 11.20 shows the steps in programming the serial port of the
8051. These steps are detailed in Sections 11.6.3.1-11.6.3.3.
Fig. 11.20 Flowchart for programming serial port of 8051
11.6.3.1 Initializing Serial Port

Once the serial port mode has been selected, the programmer must configure the
serial port’s baud rate. The baud rates are programmable only in serial port modes
1 and 3. In modes 0 and 2, the baud rates are determined based on the oscillator’s
frequency.
The baud rate in mode 0 is fixed at the shift clock frequency of (system clock
frequency)/12. This results in a baud rate of 9,21,583 for a system clock frequency
of 11.059 MHz. Similarly, the baud rate for mode 2 is fixed at (clock frequency)/64.
This results in a baud rate of 1,72,797 for a system frequency of 11.059 MHz.
The baud rate for the modes 1 and 3 is fixed by the Timer 1 overflow frequency.
Timer 1 can be programmed to overflow at regular intervals in the 8-bit auto reload
mode. The reload value loaded into the TH1 register will decide the baud rate.
The relation between the baud rate and the TH1 timer reload value is given in the
following equations.
TH1 = 256 - ((Clock frequency/384)/Baud) if SMOD in PCON SFR is 0.
TH1 = 256 - ((Clock frequency/192)/Baud) if SMOD in PCON SFR is 1.
Table 11.15 gives the commonly used baud rates and the corresponding reload
value for the timer in mode 2, assuming that the clock frequency is 11.059 MHz
and that SMOD is reset.
Table 11.15 Timer values for different baud rates
Baud rate Timer value TH1

300 A0H
1200 DOH
2400 FAH
9600 FDH
The following set of instructions will set the timer for a baud rate of 9600.
MOV TMOD, #001000006 ; Set Timer/Counter 1 set in mode 2
(8-bit timer operation)
M0V.TH1, #OFDH ; Time the Timer/Counter 1 for 9600 baud.
SETB TRI ; Enable the Timer/Counter 1 for free run.
For initializing the serial port for mode 3 operation, the following instruction can
be used:
MOV SCON, #110100006
11.6.3. 2 Transmitting and Receiving Data using Serial Port
Once the serial port is properly configured, it is ready to send and receive data.
To write a byte to the serial port, one must write the value to be transmitted in
the SBUF (99H) SFR. For example, to send the letter ‘A’ to the serial port, the
following instruction can be written:
MOV SBUF, #‘A’
Upon execution of this instruction, the 8051 will begin transmitting the
character through the serial port. Once the transmission is complete, the serial port
transmit interrupt flag TI is set. Since the 8051 does not have a serial output buffer,
a character cannot be written to SBUF before the previously written character is
completely transmitted. The completion of data transmission can be detected by
checking the TI flag. This flag is set after data is written into the SBUF register.
Reading data received by the serial port is also easy. To read a byte from the
serial port one must read the value stored in the SBUF (99H) SFR, after the 8051
has automatically set the RI flag in the SCON register.
11.6.3. 3 Programming Examples

In this section, we shall discuss some programs involving the 8051 serial port.
Example 11.8:
Write a program to transmit the ASCII character ‘A’ continuously using the 8051
serial port. Use 9-bit data at 9600 baud. Use polled operation.
Solution:
MAIN: ; Set up Timer/Counter 1 to drive baud rate
of 9600.
MOV TMOD. #001000006 : Set Timer/Counter 1 in mode 2 (8-bit timer).
MOV TH1, #OFDH : Time the Timer/Counter 1 for 9600 baud.
SETB TRI : Enable Timer/Counter 1 for free run.
MOV SCON, #110100006 ; Initialize serial port for mode 3 operation.
SEND: MOV SBUF, #41H ; Move the ASCII character ‘A’ to SBUF.
LOOP: JNB TI, LOOP : Test TI flag to check whether data has
been sent.
CLR TI : Clear TI.
LJMP SEND ; Loop back and send ‘A’ again.
END
Example 11.9:
Write a program to receive a character from the serial port and save this character
in R7. Use 9-bit data at 9600 baud. The parity bit can be ignored. Use polled
operation.
I
Solution:
MAIN: : Set up Timer/Counter 1 to drive baud rate
of 9600.
MOV TMOD, #001000006 ; Set Timer/Counter 1 in mode 2 (8-bit timer).
MOV TH1, #OFDH ; Time Timer/Counter 1 for 9600 baud.
LOOP: JNB RI, LOOP ; Test RI to check whether data has been
recei ved.
CLR RI ; Clear RI.
MOV R7, SBUF ; Move data from SBUF to R7.
END
Example 11.10:
Write a program to receive a character from the serial port using interrupt driven
method and save this character in R7. Use 9-bit data at 9600 baud. The parity bit
can be ignored.
Solution:
When a character is received from the serial port, the ISR saves the received
character in R7. The initialization of the ISR vector address is done in the following
manner:
ORG 23H ; Vect r address of serial port interrupt
LJMP ISR_SERIAL
The main program and tl e ISR follows:
MAIN: ; Set up Timer/Counter 1 to drive baud rate
of 9600 baud rate.
MOV TMOD, #00100000B : Set Timer/Counter 1 in mode 2 (8-bit timer).
MOV TH1, #OFDH ; Time Timer/Counter 1 for 9600 baud.
MOV IE, #10010000B ; Enable the serial port interrupt.
LOOP: LJMP LOOP ; Loop and do nothing.
; ISR—SERIAL
ISR_SERI AL: ; TI or RI will cause a serial port interrupt.
This routine, upon setting RI, reads the
received character and saves it in R7.
JNB RI, RETURN ; Return if RI is not set (TI caused the
i nterrupt).
MOV R7, SBUF ; Move data from SBUF to R7.
CLR RI : Clear RI.
RETURN:
RETI ; Return from interrupt.
END
Example 11.11:
Write a program to transmit the block of data stored from the internal memory
address 40H onwards continuously, using the 8051 serial port. Use 8-bit data at
2400 baud. Use polled operation.
Solution:
MAIN: Set up Timer 1 to drive baud rate of 2400.
MOV TMOD, #001000006 Set Timer 1 in mode 2 (8-bit timer).
MOV TH1, #OFAH Time Timer 1 for 2400 baud.
SETB TRI Enable Timer 1 for free run.
MOV SCON, #010000006 Initialize serial port for mode 1 operation.
MOV RO, #40H Initialize memory pointer.
MOV RI, //COUNT Initialize a counter for the number of data
in the block.
SEND: MOV SBUF,@RO Get the data from memory and send it to SBUF
for transmission.
LOOP: JNB TI, LOOP Test TI flag to check whether data has been
sent.
CLR TI Clear TI.
INC RO Point to the next data.
DJNZ RI, SENO Loop again to send data, if not completed.
END
POINTS TO REMEMBER
• The 8051 microcontroller has four parallel ports of eight bits each. These ports have
alternative functions, in addition to parallel I/O.
• The ports read differently for reading from pin and for reading from port registers for
certain specific instructions.
• The ports are used for external memory interfacing.
• The 8051 has two timers of 16 bits each, both of which can be operated in four different
modes.
• The timers can be accessed using polled method or interrupt driven method.
• The 8051 has five different sources of interrupts and can be masked, prioritized, and
vectored using the related SFRs.
• The serial port of the 8051 is duplex and can be programmed using the internal SFRs
to operate in different modes. The baud rate clock can be either supplied externally or
can be generated using timers. The serial data transfer can be either polled or interrupt
driven.
KEY TERMS
Baud rate It is the rate or frequency at which the serial data is shifted onto the transmission
lines
EA It is external memory access signal, an input signal to 8051.
IE SFR This interrupt enable register in the 8051 SFR area, used to enable or disable a
particular interrupt
Interrupt It is a signal to a microcontroller to execute a high priority program.
Interrupt priority It is the sequence in which the interrupts will be serviced when all the
interrupt signals appear at the same time.
Interrupt vector address It is the address of the memory location from where the
program will be executed upon sensing a particular interrupt.
IP SFR This interrupt priority register is in the 8051, used to set two levels of priority,
high and low, among the available interrupt sources.
Operating modes of serial port These are modes that decide the number of bits
transmitted or received and the baud rate used.
PSEN It is the program memory Read strobe signal given by 8051.
SBUF It is the serial port register from where the data is transmitted; register in which
received data is stored.
SCON It is the serial port control register, used to select the modes and control the serial
port.
Structure of port This refers to internal circuit organization and connection of various
signals to the ports
TCON This SFR is used by programmers to control the running of the timer and to read
the timer overflow status.
Timer It is a register which acts as a counter and is incremented for every clock pulse
Timer operating modes These are the different methods available for programming and
using the timers.
Timer overflow It is the condition in which the timer content becomes all 1 s and becomes
all Os upon next count. This overflow will set the timer overflow flag in the TCON SFR.
TMOD This SFR is used to set the modes of operation of the 8051 timers.
UART It is the universal asynchronous receiver transmitter, the serial data reception and
transmission mechanism in microprocessor technology.
REVIEW QUESTIONS
1. How many I/O ports are available in the 8051 ?

2. How many ports in the 8051 are available for I/O purposes, if external memory is
connected to the 8051 ?
3. Why only memory mapped I/O port address is used in 8051?
4. Which I/O port of the 8051 has no alternative function?
5. What is meant by multiplexed lower-order address and data bus?
6. What circuit configuration allows the ports to use their pins for both input and
output?
7. What are the instructions that read the port latches?
8. What are the instructions that read the port pins?
9. What should be done to make a port an input port?
10. How many timers are available in the 8051 ?
11. What are the SFR registers associated with the 8051 timers?
12. Explain mode 0 operation of the 8051 timers.
13. What is the difference between mode 0 and mode 1 operation of the 8051 timers?
14. What is the function of IF0/1 bit in the TCON register of the 8051?
15. Explain software and hardware methods to start and stop timers in the 8051.
16. Define interrupt priority.
17. Write the vector addresses and the priority sequence of the 8051 interrupts.
18. What are the ways to mask an interrupt in the 8051?
19. When does the 8051 check for an interrupt signal?
20. For how long must an 8051 hardware interrupt be applied for it to be sensed?
21. Explain the execution of the instruction RETI.
22. List the features of the 8051 serial port.
23. Differentiate between parallel and serial interfaces.
24. How many operating modes are available in the serial port of the 8051? Explain the
differences among them.
25. How will you double the baud rate in the 8051?
26. Write steps to program the 8051 for serial data transfer.
27. What is the function of the SM2 bit in the SCON register of the 8051 ?
28. Define double-buffered register.
Show the circuit connections for interfacing 16 K of EPROM IC 27158 and 8 K of RAM
IC 6264 with the 8051.
THINK AND ANSWER
1. What are the conditions for external memory access in the 8051?
2. What is the purpose of multiplexing the lower-order address bus with the data bus for
external memory access?
3. What are the advantages of separate data and program memory (Harvard architecture)?
4. Write a delay routine for 1ms using Timer 0 of the 8051, for 12 MHz crystal
frequency.
5. Write a routine using a timer of the 8051 to count the cars moving on a road and to
give a signal when the count value reaches 100.
6. Write the interrupt priority word so that the following settings will be implemented in
the 8051: The serial port interrupts and external interrupt 1 are high-priority interrupts;
the other interrupts are low-priority ones.
7. Write the control word for masking external interrupts in an 8051-based system.
8. Write the control word format for setting the serial port in mode 1.
9. Calculate the reload value of Timer 1 for achieving a baud rate of 4800 in the 8051,
for a crystal frequency of 11.0592 MHz.
10. Write an 8051 ALP to transmit ‘Hello World’ serially at 9600 baud for a crystal
frequency of 11.0592 MHz.
CHAPTER 12
8051 INTERFACE EXAMPLES

LEARNING OUTCOMES
• Interfacing of the programmable interface IC 8255, switches, and LEDs with the 8051
• Interfacing of analog-to-digital and digital-to-analog converters
• Interfacing of LCD interfaces, matrix keyboards, and motors
• 8051 application examples
12.1 INTERFACING 8255 WITH 8051

When the 8051 is connected to external memory, port 0 (P0) is used for the lower-
order address and data bus and port 2 (P2) is used for the higher-order address
bus. Since the port 3 pins have an alternative function, the net result is that only
Pl is left for input and output operation. One way to expand the number of I/O
ports is to connect the 8255 programmable peripheral interface with the 8051. The
details of the Intel 8255 IC and its interfacing with the 8085 have been explained
in Chapter 7. This section explains the interfacing of the 8255 with the 8051.
The interfacing of the 8255 with the 8051 is done assuming the 8255 as a
memory location, because the 8051 supports only memory-mapped I/O. For
accessing the external memory in the 8051, the MOVX instruction is used. The
lower-order address bus and the data bus are multiplexed and are available in the
port 0 pins. This is de-multiplexed using a latch and the ALE signal.
Figure 12.1 shows the interfacing of the 8255 with the 8051. The first step in the
general interfacing method is to decide the addresses for the port. The 8051 uses
16-bit addresses and the most significant address lines are used for decoding and
selecting the device. Here, the higher-order address bus from port 2 is given to a
decoder logic circuit. From the decoder, the 8255 chip select signal is generated.
The 8255 needs four addresses for interfacing with any processor—three for the
ports A, B, and C and one for the control register. The lower-order address lines
A0 and Al are connected to select one of these four registers. The read and write
control signals are available from the port 3 pins P3.7 and P3.6.
Example 12.1:
Assume that the 8255 is interfaced to the 8051 at the addresses 8000H-8003H.
Write a program to read the content of port A and write it in other ports.
Solution:
The first step in programming is to finalize the control word to be written in
the control register of the 8255. Here, port A is initialized as the input port in
8051 INTERFACE EXAMPLES 367
Port A
PortC
mode 0. Ports B and C are initialized as output ports in mode 0. For this initialization,
the control word is 10010000B or 90H (refer to Chapter 7). The addresses for the
port access are stored in the data pointer register of the 8051, in the following
program.
MOV A, #90H ; Initialize the control word.
MOV DPTR, #8003H ; Initialize the data pointer to the control
regi ster.
MOVX @DPTR, A ; Write the control word in the control
regi ster.
MOV DPTR, #8000H ; Load the address of port A in the data
pointer.
MOVX A, @DPTR ; Move data from port A to the accumulator.
INC DPTR ; Increment the data pointer so that it
points to port B.
MOVX @DPTR, A ; Write the data in port B.
INC DPTR ; Increment the data pointer so that it points
to port C.
MOVX @DPTR, A ; Write the data in port C.
12.2 INTERFACING OF PUSH BUTTON SWITCHES AND LEDS

The simplest input devices and output devices that can be interfaced to any
microprocessor are push button switches and light emitting diodes (LEDs),
respectively. We shall consider the example of four push button switches interfaced
to one port of the 8051, and four LEDs connected to another port.
Each switch is connected in such a way that when it is open, it connects a
logic 0, i.e., OV to the port, and when it is closed,

it connects a logic 1, i.e., 5 V. Figure 12.2 shows a
circuit designed in such a way that it would not source
over cun-ent or be destroyed, as a consequence. This
ensures safe operation of the ports and switches.
The LED is illuminated when it is forward biased
and has enough current flowing through it. LED
indicators are easy to interface with microcontrollers
as they can function even at a current of about 10 mA.
A driver IC can be used for illuminating LEDs.
Figure 12.3 shows
Fig. 12.2 Interfacing of
a method of using switches to port pins
an inverter driver
for connecting ports to LEDs. When a logic 1 is
given to the port pin, it is inverted by the inverter
and connects ground (logic 0) to the cathode of
the LED. This forward biases the LED, thereby
illuminating it. The resistor R in the circuit
determines the current through the LED and
thereby decides its illumination.
Fig. 12.3 Interfacing LED with Figure 12.4 shows the interfacing of four
driver to port pins
switches to the port 3 pins and four LEDs to the
port 1 pins of the 8051.The inverter driver IC
74240 is used to drive the LEDs. Even though only four LEDs are shown, we
can connect eight LEDs as the 74240 has eight inverter drivers. The program for
displaying the contents of the four switches using the LEDs is as follows:
Start: MOV A, P3
MOV Pl, A
When logic 1 is sensed on the port 3 line, it is given as output to the port 1 lines.
This forward biases the LEDs, thereby illuminating them. When logic 0 is sensed
Fig.12.4 Interfacing four switches and four LEDs with the 8051
and sent as output to the port 1 lines, the LEDs are not illuminated since the circuit
is reverse biased.
12.3 INTERFACING OF SEVEN-SEGMENT DISPLAYS

Seven-segment displays consist of seven LED segments. The arrangement of the
seven segments and the display format of the digits are shown in Fig. 12.5. Seven
segment displays are available in a single dual in-line package. There is one pin
for each segment and these pins are named from a to f. A separate LED is used to
Fig. 12.5 Arrangement of LEDs and digit display format in seven-segment displays
display the decimal point. In addition to these eight pins, seven-segment displays
have one more pin, for power supply. Seven-segment displays come in two types,
common anode and common cathode.
In common anode display, the anodes of all the LEDs are connected together
to form a pin. To illuminate a segment, the common anode pin is connected to the
supply and the corresponding segment input is connected to a low-level voltage,
i.e., logic 0.
On the other hand, in common cathode display, the cathodes of all the LEDs
are connected together. So to illuminate a segment, the corresponding segment
input is connected to a high-level voltage, i.e., logic 1, and the common cathode is
connected to the ground. This forward biases the LEDs and illuminates them.
The interfacing of seven-segment displays with the 8051 microcontroller needs
a driver, as shown in Fig. 12.3. Here, the 74240 TTL inverter driver IC is used for
driving the seven-segment displays. The seven-segment display is assumed to be
of common anode type. The common anode is connected to the +5 V supply. The
interfacing diagram for displaying the BCD code read from the key connected
to P3 and displaying it in seven-segment display connected to port 1 is shown in
Fig. 12.6.
A segment can be illuminated when its pin is connected to a low-level voltage
or to ground. This is done by connecting the segment input to logic 0, through
the 74240. The 74240 IC inverts the inputs applied to it. This implies that if a
particular segment has to be illuminated, the corresponding output for that segment
has to be at logic 1. The data output for displaying decimal digits 0-9 is shown in
Table 12.1.
Fig. 12.6 Interfacing switches and seven-segment display with 8051
Table 12.1 Data format for displaying decimal numbers in seven-segment displays
Decimal D7 D6 D5 D4 D3 D2 D1 DO Data for

number display (hex)
dp g f e d c b a
0 0 0 1 1 1 1 1 1 3F
1 0 0 1 1 0 0 0 0 30
2 0 1 0 1 1 0 1 1 5B
3 0 1 0 0 1 1 1 1 4F
4 0 1 1 0 0 1 1 0 66
5 0 1 1 0 1 1 0 1 6D
6 0 1 1 1 1 1 0 1 7D
7 0 0 0 0 0 1 1 1 07
8 0 1 1 1 1 1 1 1 7F
9 0 1 1 0 1 1 1 1 6F
The program for getting data from port 3 and displaying it in port 1 is as
follows. In this program, the look-up table concept is used to select the display
code corresponding to each digit. The data in Table 12.1 is stored in a series of
memory locations starting at ‘TABLE’. Indexed addressing mode is used to access
this table.
MOV A, P3 Get data from port 3.
ANL A, OFH Mask the higher-order four bits.
GETCOOE: MOV DPTR. //TABLE Initialize the pointer to the table.
MOVC A, @A + DPTR Get the display code from the table.
MOV Pl. A ; Output it to port 1 to display in the

seven-segment display.
TABLE: DB 3FH,30H,5BH.4FH.66H. 6DH,7DH,07H,7FH,6FH
END
12.4 INTERFACING ADC CHIP

The analog-to-digital converter is an essential component in any microprocessor
or microcontroller system, for interfacing analog inputs. A brief introduction to
ADCs, given in Chapter 7, is reproduced here.
The specifications of an ADC are the range of analog input voltage, the number
of digital bits at the output, the resolution, the conversion time, and the number of
analog input channels. The analog input voltage can be either unipolar or bipolar.
Unipolar means that the input voltage can have only one polarity, e.g., (0 to +5 V)
or (0 to +10 V). Bipolar means that the input voltage can range from one polarity
to the other, e.g., (-5 V to +5 V) or (-10 V to +10 V). Most commercially available
ADC chips come with the option of selecting one of these voltage ranges using
the Vref input pin. ADC chips are available with different number of output binary
bits—8, 10, 12, or 16 bits. The number of bits will decide the number of voltage
levels sensed. For example, an 8-bit ADC will have 28 possible levels, i.e., 256
levels. The number of bits and the input voltage range will decide the resolution.
The resolution of an ADC is defined as the smallest change in input voltage that
can be sensed or detected at the output. It can be mathematically defined as the
range of input voltage divided by the number of levels at the output. For example,
an ADC with the input voltage range of (0 to +5 V) with 8 bits at the output will
have a resolution of (5/256), i.e., approximately 19.5 mV. The conversion time
of ADCs is decided by the type of the ADC and the clock frequency used in the
converter circuits.
Some ADC chips come with the option of having more than one analog input.
One of these analog input channels is selected using select lines and an analog
multiplexer circuit. ADC chips also have a sample-and-hold circuit. The sample-
and-hold circuit is used to maintain the analog input voltage constant when the
conversion is in progress.
There are two possible methods for interfacing ADC chips with the 8051. In
the first method, one can directly interface the ADC chip with the 8051 parallel
ports. In the second method, especially in the case of complex systems (involving
many external chips including the memory), an 8255 PPI chip may be interfaced
with the 8051 and the ADC chip can be interfaced with the 8051 through the 8255.
Figure 12.7 shows the direct interfacing of ADC 0808/0809 with the 8051.
ADC 0808/0809 is a commonly used ADC chip with eight analog input channels
and an 8-bit digital output. The eight analog inputs are multiplexed and selected
using the three select lines, A, B, and C. The select lines are connected to the least
significant three bits of port 0. The additional inputs +Vref, -VreP and CLK and
the supply inputs must be given to the ADC chip. The ALE and SC pins are tied
together and connected to the port pin P0.3. The OE pin is connected to another
port 0 pin, P0.4, and the end of conversion signal (EOC) is sensed through P0.5.
Fig. 12.7 Direct interfacing of ADC chip with 8051
The software part follows the flowchart shown in Fig- 12.8. The channel
selection signal is issued to the ADC chip, followed by the ALE/SC signal. Then,
Fig. 12.8 Flowchart for ADC conversion software

the conversion starts within the chip and the EOC signal is received at the end of
conversion. When the EOC signal is received, the program issues the OE signal
and then reads the data from the data lines connected to port 1.
The program for analog-to-digital conversion for the interface shown in
Fig. 12.7 is as follows:
ADCONVERT: MOV P1,#OFFH ; Make port 1 as the input port by writing
Is
MOV P0,#CH_NUM ; Select the channel number on port 0 LSB
3 1i nes.
SETB P0.3 Issue ALE/SC signal on P0.3 line.
NOP Wai t.
NOP Wait.
CLR P0.3 Remove the ALE/SC signal by making it 0.
CHECK: JNB P0.5, CHECK Read P0.5 to check EOC until it becomes 1
SETB P0.4 Make 0E signal high on P0.4.
MOV A,Pl Read the result data from port 1.
MOV ADC_RES,A Store it in a memory location ADC_res.
RET End of subroutine program.
12.5 INTERFACING DAC CHIP

Digital-to-analog converters are used to get a proportional analog voltage or
current for the digital data sent by the microprocessor.
Let us consider the common digital-to-analog converter chip DAC 0800 in
this interface example. This section will describe the interfacing of the DAC 0800
with the 8051 microcontroller. Any one port is enough to interface an 8-bit DAC
with the 8051. The interface diagram is shown in Fig. 12.9. The data lines of the
DAC chip are connected to the port 1 lines of the microcontroller. The port 1
Fig. 12.9 Interfacing DAC 0800 with 8051

lines should now be made output lines, to send digital output to the DAC. The
output from the DAC chip is a variable current and this is converted into a variable
voltage using a current-to-voltage converter.
The following section explains the programming for applications involving the
DAC. Four common applications—square wave generation, ramp wave generation,
staircase wave generation, and sine wave generation—are discussed.
12.5.1 Square Wave Generation

Write a program to generate a square waveform using the DAC chip.
The DAC chip interfaced with port 1 of the 8051, as shown in Fig. 12.9, is
considered. In this example, a square waveform is generated using the DAC chip.
The square waveform has 0 V output for half a period and a voltage of amplitude
Vt for another half.
The data for any particular voltage Vj is calculated using the following formula:
Equivalent value for voltage output Vj = [(2n - 1)/ Maximum output voltage] x Vp
where n is the number of binary bits in the input to the DAC.
For example, the equivalent value for a 3V output in a DAC with an 8-bit
binary input and a maximum output of 5 V, is [(28 - 1)/ 5] x 3 = 51 x 3 = 153 (in
decimal form). The same value (in hexadecimal form) will be 99H.
The following program can generate a square wave of amplitudes 3 V and 0 V,
with a predefined delay and hence a predefined frequency, according to the count
value.
START: MOV Pl. #00H ; Load the hexadecimal equi valent of OV in
port 1.
LCALL DELAY : Call the subrouti ne DELAY.
MOV Pl. V/-99H ; Load the hexadecimal equi valent of 3V in
port 1.
LCALL DELAY Call the subroutine DELAY.
SJMP START Loop again to get a continuous waveform.
DELAY: MOV RO, #COUNT Load a register with a count value.
RPT: DJNZ RO. RPT Decrement it and loop.
RET If the value of count becomes zero, retu
from subroutine.
12.5.2 Staircase Wave Generation

Write a program to generate a staircase waveform using the DAC chip.
The waveform to be generated is given in Fig. 12.10 and the hardware
is assumed to be the same as in Fig. 12.9. Three levels—Vp V , and V3—are
assumed in the output voltage waveform. The hexadecimal output to be given to
the port is calculated using the formula given in Section 12.5.1. The following
program assumes these three values as DATA1, DATA2, and DATA3. The fixed
time delay is used in all the three levels.
START: MOV P1.//DATA1 ; Load the hexadecimal equivalent of Vj in
port 1.
CALL DELAY : Call the subroutine DELAY.
MOV Pl. #DATA2 Load the hexadecimal equivalent of V2

in port 2.
CALL DELAY Call the subroutine DELAY.
MOV P1,#DATA3 Load the hexadecimal value of V3 in port 3
CALL DELAY Call the subroutine DELAY.
SJMP START Loop again to get a continuous waveform.
DELAY: MOV RO, #C0UNT Load a register with a count value.
RPT: DJNZ RO, RPT Decrement it and loop.
RET If the value of count becomes zero, return
from subroutine.
Fig. 12.10 Staircase waveform generated
12.5.3 Ramp Wave Generation

Write a program to generate a ramp waveform using a DAC chip.
Figure 12.11 shows the ramp waveform to be generated. Port 1 is given
gradually increasing values starting from 0. The hardware details are assumed to
be the same as in Fig. 12.9.
Fig. 12.11 Ramp waveform generated
The following program generates the ramp waveform shown in Fig. 12.11, with
V = 5 V. The delay calculation is slightly different from the previous examples.
Here, the voltage levels are increased from OOH to FFH, i.e., 0 to 255 in decimal
form. So within T seconds, there are 255 levels. Therefore, the delay for each
level will be T/255. The delay routine is then written to produce this delay of
T/255 seconds. The delay time should be as small as possible for ramp generation.
Otherwise, the waveform will look like a staircase waveform with 255 levels.
The following program involves incrementing the value given to port A from
OOH to FFH, with a time delay routine called at each level.
START: MOV R1,#OOH : Move the hexadecimal equivalent of
OV to register 1.
LOOP: MOV Pl, RI : Move the data in the register RI to
port 1, where the DAC is connected.
LCALL DELAY ; Call the subroutine DELAY.
INC RI : Increment register RI.
SJMP LOOP : Loop again to send the data to
the DAC.
DELAY: MOV RO, #COUNT ; Load a register with a count value.
RPT: DJNZ RO, RPT : Decrement it and loop.
RET ; If the value of count becomes zero,
return from subroutine.
12.5.4 Sine Wave Generation

Write a program to generate a sine wave using a DAC chip connected to the 8051
controller.
In this example, the voltage data to be given to port 1 are stored in the memory
locations 9000H-9024H. These data can correspond to any predefined waveform,
including a sine wave. In such cases, the entire wave is divided into many levels;
each level is converted into the corresponding digital value and stored in the
memory location. The time delay between the levels is fixed and is generated
using the delay routines.
START: MOV DPTR, #9000H ; Initialize the data pointer with the
starting address of the data table.
MOV RI, #24H ; Initialize a counter with the number
of entries in the table.
LOOP: MOV A, @DPTR ; Move the data from the table to the
accumulator.
MOV Pl, A ; Send it to port 1 where DAC is
connected.
LCALL DELAY : Call the subroutine DELAY.
INC DPTR ; Point to the next data in the table.
DJNZ RI, LOOP ; Check for the number of entries and
loop to send the next data to port 1.
SJMP START ; If all entries in table have been sent,
start again from the first entry.
DELAY: MOV RO, tfCOUNT ; Load a register with a count value.
RPT: DJNZ RO, RPT ; Decrement it and loop.
RET ; If the value of count becomes zero,
9000H: DB 128, 150, ; Table for decimal sine values in
172, 192, 210, 226, steps of 10° for OV to 10V.
239, 248, 254, 256,
254, 248, 239, 226,

210, 192, 172, 150,
128, 106, 84, 64, 46,
30, 17, 8, 2, 0, 2, 8,
17, 30, 45, 64, 84, 105
For sine wave generation, the sine wave is first converted into the corresponding
digital values at the sample intervals. To generate a sine wave, it is assumed that
the DAC gives an output voltage of 0V-10V. This voltage range can be easily
adjusted by changing the gain of the I-to-V converter at the output of the DAC
network. So the equation (5 + 5 x sin 0) is used to calculate the voltage required
at the output of the DAC network. This voltage waveform is shown in Fig. 12.12.
To find the digital values to be given at the input of the DAC network, we should
multiply the voltage value by 25.6. This is because for an 8-bit DAC, there are
256 levels with a full-scale output voltage of 10 V and so the per step value is
256/10. For reducing the number of levels, the sine wave is generated with values
for every 10° step. The decimal values to be given to the DAC network are given
in the program as the look-up table starting at 9000H. To get a more accurate
waveform, the table can be constructed with 1° steps.
Fig. 12.12 Sine wave generation
In the program given, the delay corresponds to 10° steps in the waveform,
as the sine values are stored in the look-up table for every 10°. For example, to
generate a 50 Hz sine wave, the delay for 10° should be (1/(50 x 36)), i.e., 0.55 ms.
If the count in the delay routine corresponds to 0.55 ms, the waveform generated
will be at 50 Hz.
12.6 INTERFACING MATRIX KEYPAD

The matrix keypad is organized as a matrix connection of switches. Mechanical
switches have a problem called contact bounce because of their construction. The
pressing of a mechanical switch must produce a single pulse output. Practically,
instead of producing a single clean pulse output, the switches generate a series
of pulses because the switch contacts do not come to rest immediately. As the
microprocessor is faster than a manual key press, the single key press will be
registered as multiple key presses. This is the main consequence of key bouncing.
The signal from the key falls and rises a few times within a period of about 5 ms,
as the contact bounces. So the signal from the key must be made free from key
bouncing transients. This technique is called key de-bouncing.
Key de-bouncing can be accomplished using hardware or software. The
bouncing of key signals occurs within 5 ms. A human cannot press and release a
switch in less than 20 ms. A de-bouncing logic will check the signal after 20 ms
and then recognize whether a key is pressed or not. This logic can be implemented
both in hardware and in software. The hardware techniques employ set-reset
flip-flops, non-inverting CMOS gates, or integrating de-bouncers. The software
technique uses the wait-and-see method. When a signal is sensed from a switch,
the program waits for 10 ms and checks the same key again. If the signal from the
switch still indicates the key press, the program decides that the user has pressed
the key. Otherwise, the signal received is rejected as noise. Figure 12.13 shows the
matrix keyboard interfaced with the 8051.
Fig. 12.13 Matrix keyboard interfaced with 8051

In the software, a column scan is done by giving an output of 0 on the lines

P1.0-P1.3 of port 1. A key press is detected by checking for the row (P2.0-P2.3
of port 2) in which the zero level appears. The scanning of a row is achieved by
applying 0 V to one port 1 pin and 5 V to the other three port 1 pins, then scanning
each individual port 2 pin to see if one of them is low. If it is, the key at the
junction between the row and column being scanned is the pressed key. An ASCII
code (0, 1, 2, 3, ... , 9, A, B, C, D, E, and F) can be assigned to each key. The
scan program uses the subroutine get_code, which in turn uses the look-up table
concept to find the ASCII value for the key pressed. It returns the code to register
R2. The routine includes a software delay routine of 20 ms to solve the keyboard
de-bouncing problem.
The procedure for finding a key press involves the following steps:
(i)Clear P1.0, set the other three bits (iii) Clear Pl.2, set the other three bits
(a) Scan P2.0 (a) Scan P2.0
(b)ScanP2.1 (b)ScanP2.1
(c) Scan P2.2 (c) Scan P2.2
(d) Scan P2.3 (d) Scan P2.3
(ii)Clear Pl. 1, set the other three bits (iv) Clear Pl.3, set the other three bits
(a) Scan P2.0 (a) Scan P2.0
(b)ScanP2.1 (b)ScanP2.1
(c) Scan P2.2 (c) Scan P2.2
(d) Scan P2.3 (d) Scan P2.3
The routine for the scan program is as follows:

SCAN: MOV Pl, #111111106 ; Clear P1.0 and set the other three bits.
JNB P2.0, keyO : Check P2.0; if it is 0, go to the subroutine
for de-bouncing and key reading.
scanl: JNB P2.1,keyl : Check P2.1 ; if it is 0, go to the subroutine
scan2: JNB P2.2,key2 ; Check P2.2; if it is 0, go to the subroutine
scan3: JNB P2.3, key3 ; Check P2.3; if it is 0, go to the subroutine
scan4: MOV Pl, #11111101B ; Clear Pl.l and set the other three bits.
JNB P2.0, key4 : Check P2.0; if it is 0, go to the subroutine
scan7: JNB P2.3, key7 ; Check P2.3: if it is 0, go to the subroutine
scan8: MOV Pl, #111110116 ; Clear Pl.2 and set the other three bits.
... (Continue scanning with other bits)
subroutine DELAY for key de-
keyO: LCALL DELAY_20ms ; Call the
bound ng.
JB P1.0, scanl : If the port 1.0 value is not 0, return to

scanl.
MOV A, #0 ; If it is 0, store the key value in register
A.
LJMP get_code ; Get the corresponding ASCII key code.
keyl: LCALL DELAY_20ms ; Call the subroutine DELAY for key de-
bounci ng.
JB Pl.l, scan2 ; If the port 1.1 value is not zero, return to
scan2.
MOV A, #1 ; If it is 0, store the key value in register
A.
LJMP get_code : Get the correspond!ng ASCII key code.
... (Continue for other keys.)
get_code: MOV DPTR,
#key_table ; Use the data pointer to point to the ASCII
code table.
MOVC A, @A+DPTR ; Get the ASCII value using indexed
addressing.
MOV R2, A ; Save the ASCII value in register R2.
RET : Return from subroutine.
key_table:
DB ‘0123456789ABCDEF' ; Table for the ASCII values of keys 0 to F.
END : Terminate program execution.
This software can also be modified and written using the ‘SETB bit’ and the
‘CLR bit’ instructions. A set of 16 flag bits in the bit-addressable internal RAM
region can be used to store bit information about which key was pressed, and this
can be used by the main software routine.
12.7 INTERFACING STEPPER MOTOR WITH 8051

Stepper motors are used for position control applications such as the control of
disk drives and in robotics.
The most common stepper motors have four stator windings, which are paired
with a centre-tapped common terminal.
While the conventional motor shaft runs freely, the stepper motor shaft moves
in a fixed repeatable increment, which allows one to move it to a precise position.
The typical stepper motor considered here has 50 teeth on the rotor and eight poles
on the stator for a 1.8° step angle. Table 12.2 shows the switching sequence for
single-phase excitation.
Table 12.2 Switching sequence: One-phase excitation (wave drive)
P0.3 P0.2 P0.1 PO.O Clockwise Anti-clockwise HEX value
0 0 0 1 1 4 01
0 0 1 0 2 3 02
(Contd)
Table 12.2 Switching sequence: One-phase excitation (wave drive) (Contd)
P0.3 P0.2 P0.1 PO.O Clockwise Anti-clockwise HEX value
0 1 0 0 3 2 04
1 0 0 0 4 1 08
Table 12.3 shows the switching sequence for two-phase excitation.

Table 12.3 Switching sequence: Two-phase excitation (high-torque excitation)
P0.3 P0.2 P0.1 PO.O Clockwise Anti-clockwise Hex value

0 0 1 1 1 4 03
0 1 1 0 2 3 06
1 1 0 0 3 2 OC
1 0 0 1 4 1 09
The interfacing of a four-phase stepper motor with the 8051 is given in

Fig. 12.14. The figure shows the four terminals A, B, C, and D of the motor
connected to the port 0 pins through the transistor drivers. The common terminal
of the motor is connected to the supply. The excitation sequence for the stepper
motor is given in Tables 12.2 and 12.3. The single-phase excitation results in low
current through the motor windings and is also called wave drive mode. In two-
phase excitation, the excitation current through the motor windings is high and so
it is called high-torque excitation mode.
The following program is used for continuous rotation of the stepper motor.
The value of count in the delay routine must be calculated to match the required
speed. A counter of 4 is set up to indicate that the switching sequence needs four
steps, which are to be repeated continuously. A memory pointer is then initialized
to load the switching or excitation data to be given to the port. The switching data
are stored initially in the memory locations.
START: MOV 30. #03H : Store the excitation values for bi-phase
clockwise rotation from the internal memory
location 30H.
MOV 31, #06H
MOV 32, #OCH
MOV 33, #09H
RPT: MOV RO, #30H : Initialize the memory pointer with the address
for excitation.
MOV RI, #04H : Initialize the counter for four steps of
excitation data.
LOOP: MOV PO,@RO : Get the excitation data and send it to
port 0.
LCALL DELAY : Call the subroutine DELAY for proper
INC RO ; Point to the next memory location.
DJNZ RI, LOOP : Decrement the counter. If it is not zero, get
the next data.
SJMP RPT : Loop again for continuous rotation.
DELAY: MOV R3, #count : Load register R3 with the count value.
HERE: DJNZ R3, HERE : Decrement and loop until it becomes zero.
To rotate the stepper motor in the reverse direction, the register RO can be
initialized with 33H and decremented. The stepper motor connections are such
that either A or B is excited and then, either C or D is excited. The connections are
also such that the port output can be rotated bit by bit for the rotation of the motor.
The following program rotates data, so as to excite the motor in sequence. Here,
the accumulator is initialized with 00010001B. The left-shifting of this data will
excite the required motor phases one by one. The most significant four bits are set
as 0001, so that the continuous rotation of this data will result in the continuous
rotation of the motor.
START: MOV A, #00010001B ; Initialize the accumulator with 1 in
the bit PO.O.
LOOP: MOV PO, A ; Get the excitation data and send it to

port 0.
RL A : Rotate the accumulator content for
excitation of the next phase.
LCALL DELAY : Call DELAY for proper excitation of
the motor coils.
SJMP LOOP ; Loop again for continuous rotation.
DELAY : MOV R3, //count : Load the value of count in R3.
HERE: DJNZ R3, HERE ; Decrement it until it becomes 0.
Example 12.2:
Write a program to rotate the stepper motor in Fig. 12.14—90° clockwise and 180°
anti-clockwise and then continuously repeat the same sequence.
Solution:
The stepper motor used is assumed to have a step angle of 1.8°. So for 90°
rotation, the number of excitation pulses required is 90/1.8, i.e., 50 in decimal
form and 32 in hexadecimal form. For 180° rotation, the number of excitation steps
required is 100 or 64H. If the single phase excitation data 0001000IB is rotated
left for clockwise motor rotation, the data is rotated right for anti-clockwise motor
rotation. The program is as follows:
START: MOV RO, #32H : Initialize the counter for 90s rotation.
MOV A, #00010016 : Initialize the accumulator with 1 in the
bit P0.0.
L00P1: MOV PO, A ; Get the excitation data and send it to port 0.
RL A ; Rotate the accumulator content left, to rotate
the motor clockwise.
LCALL DELAY ; Call DELAY for proper excitation of the
motor coils.
DJNZ RO, L00P1 ; Check for 90s rotation. If not, loop.
MOV RO, #64H ; Initialize the counter for 180Q rotation.
MOV A, #00010016 ; Initialize the accumulator with 1 in the
bit P0.0.
L00P2: MOV PO, A ; Get the excitation data and send it to port 0.
RR A ; Rotate for excitation in anti-clockwise
di rection.
LCALL DELAY : Call DELAY for proper excitation of the
motor coils.
DJNZ RO, L00P2 ; Check for 180e rotation. If not, loop.
SJMP START ; Loop for continuous operation.
DELAY: MOV R3, #count ; Load the value of count in R3.
HERE: DJNZ R3, HERE ; Decrement until the value becomes 0.
12.8 INTERFACING LCD WITH 8051

Modem LCD devices are becoming popular and are finding an increasing number
of applications. The main advantage of LCDs over seven-segment displays is their
ability to display numbers, characters, and graphics; the latter can display only
numbers and a limited set of characters. LCDs come with an internal controller
and refreshing circuit. So the CPU is relieved of the task of refreshing the display.
The programming of LCD devices is easier, since they have predefined control
words and addresses. The cost of LCDs is also declining.
General LCD devices have 14 pins, which are listed in Table 12.4.
Table 12.4 LCD display pin configuration
Pin number Symbol Level I/O Function

1 Vv ss — — Power supply (GND)
2 Vv cc — — Power supply (+5 V)
3 PF
vEE — - Contrast adjust (Vo)
4 RS 0/1 I Command or data register select line
0 = Instruction input
1 = Data input
5 R/W 0/1 I 0 = Write to LCD module
1 = Read from LCD module
6 E 1 to 0 I Enable signal
7 DBO 0/1 I/O Data bus line 0 (LSB)
14 DB7 0/1 I/O Data bus line 7 (MSB)
Eight data lines are used for interfacing the LCD with the processor. The three
control signals are RS, R/W, and E.
(i) RS is used to select a control register or a data register.
(ii) R/W indicates the direction of data flow between the processor and the
display.
(iii) The E signal is used to enable data transfer.
The three control signals and eight data lines are interfaced with the two ports
of the 8051. In the interface diagram shown in Fig. 12.15, the port 1 lines are used
to transfer data and the port 2 lines are used to issue the control signals from the
microcontroller to the LCD.
The LCD interface accepts a number of commands/instructions. A select list of
these commands is given in Table 12.5.
Vcc
Fig. 12.15 LCD interfaced with 8051
Table 12.5 Select LCD command codes
Hex code Instruction

01 Clear display and return cursor to home position
02 Return cursor to home position
04 Shift cursor left (Decrement)
06 Shift cursor right (Increment)
05 Shift display right
07 Shift display left
08 Display off and cursor off
0A Display off and cursor on
OC Display on and cursor off
0E Display on and cursor character not blinking
OF Display on and cursor character blinking
An exhaustive list of LCD command words is given in Table 12.6.

Table 12.6 LCD command words
Code
RS R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
Clear 0 0 0 0 0 0 0 0 0 1 Clears display and returns

display cursor to the home position
(address 0).
Cursor 0 0 0 0 0 0 0 0 1 * Returns cursor to home

home position (address 0). Returns
the rotating display to the
original position. DDRAM
contents remain unchanged.
(Contd)
Table 12.6 LCD command words (Contd)
Code
Entry 0 0 0 0 0 0 0 1 1/ S Sets the direction of
mode set D movement of the cursor (1/
D) and specifies whether to
shift the display (S). These
operations are performed
during data read/write.
I/D: 1—increment;
0—decrement.
Display 0 0 0 0 0 0 1 D C B Sets displays on/off (D),
on/off cursor on/off (C), and
control blinking of character at
cursor position (B).
Cursor/ 0 0 0 0 0 1 s/ R/ * * Sets move cursor—0 or shift
display c L display—1(S/C),
shift shift direction left—0;
right—1 (R/L).
DDRAM contents remain
unchanged.
Function 0 0 0 0 1 DL N F * * Sets interface data length (DL
set = 1 for 8-bit data and 0 for
4-bit data),
number of display lines
(N = 0 for one-line and 1 for
two-line display), and
character font (F = 1 for 5 x
10 dots and 0 for 5 x 7 dots
font).
Set 0 0 0 1 CGRAM address Sets the CGRAM address.
CGRAM CGRAM data is sent and
Set 0 0 1 DDRAM address Sets the DDRAM address.
DDRAM DDRAM data is sent and
Read busy 0 1 BF CGRAM/DDRAM address Reads busy flag (BF), which
flag and indicates whether an internal
address operation is being performed
counter and reads CGRAM or
DDRAM address counter
contents (depending on
previous instruction).
(Contd)
Table 12.6 LCD command words (Contd)
Code
Write to 1 0 Write data Writes data to CGRAM or
CGRAM DDRAM.
or
DDRAM
Read from 1 1 Read data Reads data from CGRAM or
CGRAM DDRAM.
or
DDRAM
Note: * in the table denotes don’t care.
The programming of the LCD is done with the appropriate initialization word
and command words. Every time a control or command word is written into the
LCD, the RS signal input must be made 0; R/W must be made 0 for the write
operation. After setting these two signals, the enable signal E must be applied as a
pulse for a duration of not less than 450 ns. Similarly, when data is written into the
LCD device, the RS signal must be made 1 and R/W must be made 0. To display
characters and numbers, the corresponding ASCII code is sent to the data registers
of the LCD display. The following program is used to display the 15-character
data available in the series of external memory locations starting at 9000H in the
LCD.
START: MOV A, #01H ; Load the control word to clear the display in
the LCD.
CALL COMMAND ; Call the subroutine to issue this command to
the LCD.
MOV A, #OEH ; Load the control word to initialize the cursor
to home position, and switch on the display and
the cursor.
CALL COMMAND ; Call the subroutine to issue this command to
the LCD.
MOV DPTR, #9000H ; Initialize the memory pointer.
MOV RO, #OFH ; Initialize the counter for the number of
characters to display.
NEXT: MOVX A, @DPTR ; Load the display data in the accumulator.
CALL DISP ; Call the subroutine to issue this data to
the LCD.
INC DPTR ; Point to the next data for display.
DJNZ RO, NEXT ; Decrement the count for the number of data to
be displayed. If it is not zero, loop again.
; Main program continues after this line.
Subroutines
COMMAND: MOV Pl,A ; Give the control word to the data lines of the LCD.
CLR P2.2 ; RS = 0 (command)

CLR P2.1 ; R/W = 0 (write)
SETB P2.0 ; E = 1 (apply a high pulse)
CLR P2.0 ; E = 0 (apply a low to E, so that there will
be a H-to-L pulse)
CALL DELAY ; Wait for a predefined time delay.
DISP: MOV Pl,A ; Give the data to the data lines of the LCD.
SETB P2.2 ; RS = 1 (data)
CLR P2.1 : R/W = 0 (write)
SETB P2.0 ; E = 1 (apply a high pulse)
CLR P2.0 ; E = 0 (apply a low to E, so that there will
be a H-to-L pulse)
CALL DELAY ; Wait for predefined time delay
DELAY: MOV RI, tfCOUNTl ; Load a register with a count value, COUNT1.
LOOP1: MOV R2, #COUNT2 ; Load another register with a count value, COUNT2,
for more delay.
LOOP2: DJNZ R2, L00P2 ; Decrement it.
DJNZ RI, LOOP1 ; Decrement until the required time
delay is obtained.
RET ; When the required time delay has been produced,
This program calls a delay subroutine to allow the LCD to take the command
or data into its registers. The delay is written with two registers. Instead of the
delay routine, the busy flag of the LCD can be checked to see whether the data or
command has been written into the LCD registers. The busy flag is available in the
D7 data line of the LCD. The following subroutine, READY, can be used instead
of the DELAY subroutine. This subroutine checks the busy flag from the LCD and
returns from the subroutine when the busy signal is removed by the LCD.
READY: SETB Pl.7 ; Pl.7 is made an input port by writing a 1 to it.
CLR P2.2 ; RS = 0 (command)
SETB P2.1 ; R/W = 1 (read command register)
RPT: SETB P2.0 ; E = 1
CLR P2.0 ; E = 0 (H-to-L pulse applied on the E signal)
JB Pl.7, RPT ; Check the busy flag and loop until it is 1.
12.9 INTERFACING DC MOTORS/SERVOMOTORS

An interfacing method for turning on and off a DC motor via a microcontroller is
5V
From microcontroller port pin o-
Fig. 12.16 Circuit diagram for interfacing 5V DC motor
This circuit will work only for a 5 V DC motor. When the output on the port pin
is logic 1, i.e., 5 V, the PNP transistor is off. This means that the current through
the motor is made zero and hence it is off. If the port pin output is at logic 0, the
PNP transistor is on. So the transistor allows the current through the motor and the
motor generates torque.
If the motor supply voltage is higher, the circuit shown in Fig. 12.17 is used.
This circuit uses two transistors—one PNP and the other, NPN. In the circuit, a
12 V DC motor is interfaced with a microcontroller pin.
5V 19V
Fig. 12.17 Circuit diagram for interfacing 12 V DC motor
When the port pin is set at 5 V, the PNP transistor is off. This means that the NPN
transistor is also off and there is no path for current through the motor. Therefore,
the motor is off. When the port pin is cleared, the PNP transistor is on. This turns
on the NPN transistor, which allows current to flow through the motor to the
ground; thus the motor is on. The value of R2 needs to be chosen such that it is
neither too high nor too low. A high value of R2 will make the current in the base
of the NPN transistor so low that it will not be enough to turn on the transistor.
A very low value of R2 will result in too much current through the motor.
Bidirectional DC Motor Control

A circuit diagram for interfacing a 12 V DC motor with a microcontroller, in a way
that allows the controller to not only turn on and off the motor but also to set the
direction in which the motor runs, is given in Fig. 12.18.
Fig. 12.18 Circuit diagram for driving 12 V bi-directional DC motor
The circuit is made up of a four-transistor H-bridge. To run the motor in one

direction, the transistors TI and T4 are turned on and T2 and T3 are turned off.
The left side of the motor is at 12 V and the right side is at ground. To reverse the
direction, the transistors T2 and T3 are turned on and the other two transistors
in the H-bridge are turned off. If T3 and T2 are on, the left side of the motor is
at ground and the right side is at 12 V. Therefore, the motor runs in the opposite
direction. If both terminals of the motor are at the same voltage, the motor is off.
So if TI and T3 are on, both sides of the motor are connected to 12 V and the
motor is off. If T2 and T4 are on, both sides of the motor are connected to the
ground and the motor is off.
The circuit is designed so that T1-T2 and T3-T4 cannot be on at the same
time. If TI and T2 were on at the same time, there would be a short circuit between
12 V and ground, and the transistors would bum out. The same is true for T3
and T4. The truth table for the circuit, with its two inputs, A and B, is given in
Table 12.7.
Table 12.7 Bidirectional motor control modes using two microcontroller pins
Mode Pin A PinB Motor

0 0 0 Off
1 0 1(5V) Reverse (T2, T3 ON)
2 1(5V) 0 Forward (Tp T4 ON)
3 1(5V) 1(5V) Off
The following is an explanation of the four entries in the table.

(i) Mode 0
(a) With A at 0 (i.e., ground), T5 is on, which turns on T2; the left side of the
motor is at ground. When A is at 0, it also means that T6 is off. Since there
is no path for current through R3 and R4, there is no voltage drop across
them, which in turn means that the base of TI is at 12 V. Hence TI is off.
(b) The right-hand side of the circuit is a mirror image of the left. Therefore,
with B at 0, T4 is on and T3 is off. Hence the right side of the motor is also
at ground. The motor is off.
(ii) Mode 1
(a) A is still at 0, which means TI is still off and T2 is still on; the left side of
the motor is at ground.
(b) With B at 5 V (i.e., logic 1 on the port pin, which is being used for B), T7 is
off, which means that T4 is off. However, T8 is on, which generates a path
for the current through T8 to ground and also through R9 to the base of T3.
There is a certain amount of voltage drop across R9, but the base of T3 is
close enough to ground for T3 to turn on; the right side of the motor is at
12V.
(c) Therefore, the motor is on and as the left side of the motor is grounded and
the right side is connected to 12 V, it would rotate in the opposite rotation.
(iii) Mode 2
(a) This is the mirror image of mode 1, resulting in TI being on, T2 off, T3 off,
and T4 on. Hence the left side of the motor is at 12 V and the right side is at
ground. The motor runs forward.
(iv) Mode 3
(a) As in mode 2, with A at 5 V, the left side of the motor is at 12 V.
(b) As in mode 1, with B at 5 V, the right side of the motor is at 12 V.
(c) Therefore, the motor is off.
12.10 MICROCONTROLLER APPLICATION EXAMPLE-STOPWATCH

Figure 12.19 shows the complete circuit diagram of a stopwatch. The circuit
basically consists of four sets of seven-segment LEDs connected through the BCD
to the seven-segment display code converter. This code converter (IC 7448) can
also act as a driver for the display segments. The other circuit arrangements are
for the power on, reset, and clock signals. The circuit with R and C has 0 V, when
the power is off. When the power is switched on, the capacitor starts charging
and gradually rises towards the supply voltage of 5 V. This applies a logic high
voltage of 5 V, which gradually decreases towards 0 V at the RST pin. The RST is
the active high reset signal and has to be applied for at least 24 clock periods. The
RC combination and the time constant ensure that the active high reset signal is
applied for at least 24 clock periods. The microcontroller chip has a built-in clock
oscillator. So it is enough to connect the crystal to the XTAL1 and XTAL2 pins.
The connection diagram for this is given in Fig. 12.19.
The circuit consists of four seven-segment displays. For displaying numerals
7448 BCD to
Seven-segment
decoder
a be d ef g a b c d e f g a b c d e f g a b c d e f g
f
7448 7448 7448 7448
D C B A D C B A D C B A D C B A
+5V +5V +5V +5V
+5V
LP1.0 Vcc
L- P1.1 PO.O
P1.2 P0.1
+5V P1.3 P0.2
P1.4 P0.3
P1.5 P0.4 I
10nF=±= P1.6 P0.5
P1.7 P0.6
RST _P0.7
,2K (RXD) P3.0 EAA/pp
(TXD) P3.1 ALE/PROG Vcc
(INTO) P3.2 +5V
PSEN
(INT1) P3.3 P2.7
(TO) P3.4 P2.6 Switch
(T1JP3.5 P2.5
30 pF (WR) P3.6 P2.4
(RD) P3.7 P2.3
XTAL2 P2.2
XTAL1 P2.1
I
30 pF GND P2.0 i
Fig. 12.19 Circuit diagram for timer/stopwatch operation
in the four displays, we have to connect the pins of two ports to the display code
converter. Here, the port pins of PO and Pl are used. The BCD data of the display
is given to the port pins.
For stopwatch operation, an additional switch is needed to switch on and off
counting in the stopwatch. A separate push-to-on switch is connected to the LSB
of port 2. The voltage on this pin can be sensed to control the counting and display
in the seven-segment displays.
The program for stopwatch operation involves a timer register, which is
incremented at regular intervals. The interval can be programmed to be either
(l/10)th of a second or 1 second. With the interval of (l/10),h of a second and a
4-digit display, the hardware arrangement can be used to count up to 999.9
seconds. With an interval of 1 second, the hardware arrangement can count up
to 9,999 seconds. The timer register can be programmed to generate an interrupt
after every interval.
The flowchart for the stopwatch example is given in Fig. 12.20. The program
involves first initializing the timer to the required time interval. The display is also
Fig. 12.20 Flowchart for stopwatch operation
initialized to display all zeros. Then the status of the switch is sensed from the
LSB of port 2. If the switch is pressed, the program moves to the next step, i.e.,
starting the timer and giving data output to the displays. Otherwise, the program
keeps looping in the status check on P2.0. After every timer overflow, the data for
display is incremented and converted into BCD form. New data is given to the
port pins by writing them to the port registers. Data in the display is incremented
as long as the switch on P2.0 is pressed.
The hardware, flowchart, and program can be improved further to include
additional features such as resetting the display, using separate switches to start and
stop the stopwatch, and using a press switch to switch on and off the stopwatch.
12.11 MICROCONTROLLER APPLICATION EXAMPLE

TRAFFIC LIGHT CONTROL
Figure 12.21 shows the basic traffic control signals at a four-road junction.
The following assumptions are made for designing the traffic light control. There
are free left turns in all the four directions. Traffic is allowed in the four sequences
shown in Figures 12.22 (a)-12.22 (d). Each sequence again has two combinations
of traffic signals—one for red and green and the other for red, green, and yellow.
Figures 12.22 (a)-12.22 (d) shows the traffic signals that are on. For example, in
Fig. 12.22 (a), the green light (WG) in the west direction is on and the red light is
on in all the other three directions. All other lights are off and they are not shown in
Fig. 12.22 (a).
Fig. 12.21 Traffic light controls at four road junction
Traffic light control using a microcontroller can be done easily with parallel ports.
The port pins can be connected to each light, LED, or group of LEDs through
a proper driver circuit. The data in the parallel ports can be changed using the
program, for turning on and off the lights. Figure 12.23 shows the connection
diagram for all the lights, which are assumed to be LEDs in this example. The port
pins of port 0 and port 1 are used. The least significant three bits of port 0 are used
for the west direction. The port 0 pins 3, 4, and 5 are used for the north direction.
Fig. 12.22 (a) Traffic light control sequence 1

Fig. 12.22 (b) Traffic light control sequence 2
Fig. 12.22 (c) Traffic light control sequence 3
Fig. 12.22 (d) Traffic light control sequence 4

Fig. 12.23 Hardware connection diagram for traffic lights
Similarly, the least significant three bits of port 1 are used for the lights in the east
direction and pins 3, 4, and 5 are used for the south direction.
Table 12.8 shows the data to be given to the port pins for the sequences shown
in Fig. 12.22. The other pins such as XTAL1, XTAL2, and RST in Fig. 12.23 can
be connected as shown in Fig. 12.19. The reset pins and clock inputs are connected
to the corresponding circuit.
Table 12.8 Data for port pins for traffic light control
SG SY SR EG EY ER NG NY NR WG WY
PortO Port 1 WR
Sequence
P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P0.5 P0.4 P0.3 P0.2 P0.1 PO.O Data Data
0 0 1 0 0 1 0 0 1 1 0 0 OCH 09H
Sequence 1
0 0 1 0 0 1 0 1 0 1 0 0 14H 09H
0 0 1 0 0 1 1 0 0 0 0 1 21H 09H
Sequence 2
0 0 1 0 1 0 1 0 0 0 0 1 21H OAH
0 0 1 1 0 0 0 0 1 0 0 1 09H OCH
Sequence 3
0 1 0 1 0 0 0 0 1 0 0 1 09H 14H
1 0 0 0 0 1 0 0 1 0 0 1 09H 21H
Sequence 4
1 0 0 0 0 1 0 0 1 0 1 0 OAH 21H
One of the advantages of this type of microcontroller-based traffic light control is

the ease of programming and the flexibility to change the operation of the traffic
lights. Another advantage is the programmability of different delays for the traffic
in different directions. This program is written using the look-up table concept. So
the same program can be used if LEDs are connected through the 8255 PPI port
pins.
START: MOV RO. #04H ; Initialize RO for four sequences.

MOV DPTR. #LED_DATA ; Use the data pointer to point to the LED
di splay data.
LOOP: MOVX A. @DPTR ; Get the hex data to be given to port 0.
MOV PO. A ; Give it to port 0.
MOVX A. @DPTR ; Get the data for port 1.
MOV Pl,A ; Output it to port 1.
LCALL DELAY1 ; Call the required time delay.
INC DPTR : Point to the next data.
MOVX A, @DPTR : Get the hex data to be given to port 0.
MOV P0,A ; Give it to port 0.
MOVX A, @DPTR ; Get the data for port 1.
MOV Pl, A ; Output it to port 1.
LCALL DELAY2 : Call the required time delay for the yellow
1i ght.
DJNZ RO, LOOP ; Decrement count: if it is not zero, loop for
the next sequence.
SJMP START : Loop again for continuous sequencing.
LED_DATA:DB 0C, 09,
14, 09,21, 09, 21,
0A, 09, 0C, 09, 14,
09, 21, OA, 21 : Table for the hex values for ports.
END ; Terminate program execution.
This program can be rewritten using the SETB and CLRB instructions, as all
the port pins are bit-addressable. However, the program becomes lengthy as each
LED has to be individually controlled.
12.12 MICROCONTROLLER APPLICATION EXAMPLE-THERMOMETER

Temperature measurement is one of the most common tasks in industries. The
thermistor (temperature-sensitive resistor) is an electrical component capable
of measuring temperature variations, relying on the change in its resistance
with changing temperature. Once calibrated against the thermistor equation, it
is possible to electronically determine the temperature around the thermistor by
measuring the change in voltage across it, as its resistance changes.
Thermistors operate in a limited temperature range (typically -80 °C to 150 °C).
The significant advantages of the thermistor as a tool for temperature measurement
are as follows:
(i) A large output signal that results in better precision

(ii) Greater stability, providing accurate performance for longer periods of time
(iii) Higher accuracy than thermocouples in mid-range temperatures
Most thermistors have a negative temperature coefficient (NTC), meaning that
the resistance goes up as the temperature goes down. Of all passive temperature
measurement sensors, thermistors have the highest sensitivity (resistance change per
degree of temperature
change). Thermistors
do not have a linear
temperature/resistance
curve. The nonlinear
curve of resistance
against temperature
is given in Fig. 12.24.
The figure shows the
normalized resistance
variation with reference
to resistance at 25 °C.
The Steinhart-Hart
equation is widely
used to approximate Fig. 12.24 Resistance variation of thermistor with temperature
the temperature, T, of a
thermistor, as a cubic function of the logarithm of its resistance, Rr It is written
as
i = a + b In RT + c (In Rr)3
where a, b, and c are physical constants depending on the system. Within the
small temperature range of 30 °C-100 °C, further linear approximation can be done
as follows:
In Rt = In Ro + Z"
or
= Ro exp —
T)
Figure 12.25 shows a simple circuit that could be used to allow a microprocessor
to measure the temperature using a thermistor. A resistor (Rj) pulls the thermistor
up to a reference voltage. This is typically the same as the ADC reference. So Vref
would be 5 V, if the ADC reference were 5 V. This thermistor used in the circuit
has a nominal resistance value of lOkQ at 25 °C, and varies from 330 kfi at -40 °C,
down to 200 Q at 150 °C, a range of 1650:1. Such a huge dynamic range in the
output resistance can make measurement difficult.
It is possible to perform a ‘good enough’ linearization by adding some very
inexpensive circuitry. One way is to incorporate the thermistor into a Wheatstone
bridge, as shown in Fig. 12.26. However, this arrangement provides an essentially
Fig. 12.25 Simple circuit to measure temperature using thermistor
linear output voltage in response to small changes in resistance. The linearity in

the desired range of temperature can be achieved by changing the value of R in the
bridge circuit.
Figure 12.26 shows the complete interfacing arrangement for temperature
measurement using a thermistor and an ADC with the 8051 microcontroller. The
ADC 0804 is used in this circuit. This is an ADC chip with a single analog input.
The commonly used pins alone are shown in the figure. The analog input can be
converted into its digital equivalent by providing a Start Conversion (SC) signal to
the ADC chip. The end of conversion can be sensed on a separate port pin. After
the end of conversion, the data on the DB0-DB7 lines can be read by applying
a Read signal to the RD pin of the ADC chip. The digital data received can be
converted into display data and given to the LCD screen.
The software part of this temperature measurement routine has the following
steps:
(i) Clear the display.
(ii) Give the Start Conversion signal.
(iii) Check for end of conversion.
(iv) Read data from the ADC.
(v) Convert to the corresponding display temperature using the look-up table.
(vi) Display the temperature.
This algorithm uses the simple I/O interface. The program can be made more
efficient using interrupts. The end of conversion (EOC) signal can be connected
to an interrupt input of the processor. At the end of every conversion, the program
can read and display temperature, and initiate the conversion process once again.
The circuit arrangement shown in Fig. 12.26 can be used for measurement of
Fig. 12.26 Circuit diagram for temperature measurement using microcontroller
any physical quantity. To measure quantities other than temperature, instead of

the thermistor and bridge arrangement, a circuit should be provided to convert the
physical quantity into a voltage.
12.13 RTC INTERFACING USING l2C STANDARD

There are a number of peripheral integrated circuits (ICs) in modern electronic
systems that have to communicate with one another and with the outside world.
To simplify the circuit design, Philips developed a simple bidirectional two-
wire, serial data (SDA) and serial clock (SCL) bus for inter-IC control. This is
called FC bus. The I2C bus supports chips manufactured by any IC fabrication
process (NMOS, CMOS, and bipolar) and also the extremely broad range of FC-
compatible chips from Philips and other suppliers. It has become the worldwide
industry standard proprietary control bus. Figure 12.27 shows the interconnection
of various devices using the I2C bus.
The basic FC bus, with a data transfer rate of up to 100 Kbits/s and 7-bit addressing,
was introduced twenty years ago. However, as data transfer rates and application
functionality rapidly increased, the FC bus specification was enhanced to include
Fig. 12.27 Interconnection of various devices using l2C bus
fast mode and 1 O-bit addressing, thereby satisfying the demand for higher speeds
and more address space. More recently, the high speed mode has been added in the
I2C bus, with speeds of up to 3.4 Mbits/s, which ensures that the I2C bus can support
existing and future high speed serial transfer rates for different applications.
12.13.1 Details of l2C Bus

In the I2C bus, two wires—serial data (SDA) and serial clock (SCL)—carry
information between devices such as the microcontroller, the LCD driver, and the
memory connected to the I2C bus. Each device is recognized by a unique address
and can operate either as a transmitter (such as a microcontroller, EEPROM, and
flash memory) with the capability to send and receive data or as a receiver (such
as an LCD driver). In addition to transmitters and receivers, devices can also
be considered as masters or slaves when performing data transfers, as shown in
Table 12.9. The table indicates the description of various terms used in the I2C
bus. A master is the device that initiates a data transfer on the bus and generates
the clock signals to permit that data transfer. During this time, any device that is
addressed by the master is considered a slave.
Table 12.9 Description of terms associated with the l2C bus
Term Description
Master The device that initiates a data transfer, generates clock signals, and
terminates a data transfer
Slave The device addressed by a master
Transmitter The device that sends data to the bus
Receiver The device that receives data from the bus
It is the responsibility of the master device to generate the clock signals on the
I2C bus. Each master generates its own clock signals when transferring data on the
I2C bus. Bus clock signals from a master can only be altered when they are stretched
by a slave that is operating slowly and holding down the clock line (i.e., keeping
the clock line in the low state) or by another master when arbitration occurs. The
timing diagram of the various conditions in the I2C bus, and the reading and writing
of data from and to the bus are explained in Sections 12.13.1.1-12.13.1.6.
12.13.1.1 Start and Stop Conditions
Any data transfer in the I2C bus must be initiated with a start (S) condition. After
the data transfer is completed, it must be terminated by a stop (P) condition.
Figure 12.28 shows the timing diagram for the start and stop conditions. A high-
to-low transition on the SDA line when SCL is high defines a start condition. A
low-to-high transition on the SDA line when SCL is high defines a stop condition.
The start and stop conditions are always generated by the master. The bus is
considered to be busy after the start condition is generated. The bus is considered
to be free again, a certain time after the stop condition is generated.
Fig. 12.28 Start (S) and stop (P) conditions in l2C bus
The bus stays busy if a ‘repeated start’ (Sr) is generated instead of a stop
condition. In this respect, the start (S) and repeated start (Sr) conditions are
functionally identical. Detection of start and stop conditions by the devices
connected to the I2C bus is simple if they incorporate the necessary interfacing
hardware. However, microcontrollers with no such interface have to sample the
SDA line at least twice per clock period to sense the transition.
12.13.1.2 Data Validity Condition
The data bit on the SDA line (high or low) must be stable during the high period
of the clock. The state of the data line can change only when the clock signal on
the SCL line is low, as shown in Fig. 12.29.
Fig. 12.29 Data bit transfer in the l2C bus
12.13.1.3 Data Transfer in Byte Format

The number of bytes that can be transmitted per data transfer in the I2C bus is
unrestricted. Each byte has to be followed by an Acknowledge (A) signal from
the slave. Data is transferred with the most significant bit (MSB) first, as shown in
Fig. 12.30. If a slave cannot receive or transmit another complete byte of data
since it is performing some other function (e.g., servicing an internal or external
interrupt), it can hold the clock line SCL in the low state to force the master into a
wait state. Data transfer then continues when the slave is ready for another byte of
data, with the slave releasing SCL to the high state.
SDA
Byte complete, interrupt

within slave
Clock line held low while
interrupts are serviced
SCL S or
Sr UU\ ACK ACK
START or STOP or
repeated START repeated START
condition condition
Fig. 12.30 Data transfer in byte format in the PC bus
12.13.1.4 Acknowledge (A) and Not-acknowledge (A)

Data transfer with acknowledge is mandatory in the FC bus. The acknowledge-
related clock pulse is generated by the master. The transmitter releases the SDA
line to the high state during the acknowledge clock pulse. The receiver must pull
down the SDA Une to the low state during the acknowledge clock pulse, as shown in
Fig. 12.31. The set-up and hold times must also be taken into account. Usually, a
receiver that has been addressed must generate an Acknowledge (A) signal after
(SDA)
Not-acknowledge
(SDA) Data“*ull»'
' ' receiver
Acknowledge
SCL from master
START condition Clock pulse for

acknowledgement
Fig. 12.31 Acknowledge (A) and Not-acknowledge (A) in the PC bus
each byte has been received. The master can then generate either a stop condition to
abort the data transfer or a repeated start condition to start a new data transfer. If a
master that is acting as a receiver is involved in a data transfer, it must signal the end
of data transfer to the slave transmitter by generating a Not-acknowledge signal (A)
on the last byte that was clocked out of the slave. The slave transmitter must release
the SDA line to allow the master to generate a stop or repeated start condition.
12.13.1.5 Writing Data to Slave Receiver by Master Transmitter
Figure 12.32 shows the format of the FC frame when a master transmitter writes
data to a slave receiver. The shaded portion indicates the transfer of data from
the master to the slave and the

unshaded portion indicates A Data |a/a| P
the transfer of data from the Data transferred (in —'
0 (Write)
slave to the master, which is bytes + Acknowledge)
Q From master to slave A = Acknowledge (SDA low)
the Acknowledgement signal A = Not-acknowledge (SDA high)
from the slave. The read/write Q From slave to master S = START condition
P = STOP condition
(R/W) bit is made 0 when
the master writes data to the Fig. 12.32 Master transmitter sending data to slave
slave. receiver in l2C bus
The following sequence is
used while a master transmitter writes data to a slave receiver:
(i) The master sends the start (S) condition.
(ii) The master sends the 7-bit slave address, with the read/write (R/W) bit
(which is 0) appended as the LSB. For example, if the master wants to write
in an EEPROM memory (slave) with the 7-bit address 40H (i.e., 1000000
in binary), the read/write R/ W bit is appended as the LSB to this 7-bit
address to get the resultant byte 80H (i.e., 10000000 in binary) and it is sent
to the slave.
(iii) The slave sends the Acknowledge (A) signal.
(iv) The master sends data bytes one by one to the slave and the slave sends
Acknowledge signal (A) for every byte transferred. For the last byte sent by
the master, the slave replies with a Not-acknowledge signal (A).
(v) The master sends the stop condition to end the data transfer.
Note: In the case of slaves such as EEPROM and RTC, which have sub-addresses
or pointers (i.e., address of internal registers or specific locations within the slave),
after sending the slave address, the first data byte that is sent by the master is the
sub-address of a specific location or internal register within the slave from where
the successive data bytes from the master will be written in the slave. The sub
address is used to initialize the internal address pointer in the slave to point to a
particular location or register.
12.13.1.6 Reading Data from Slave Transmitter by Master Receiver
While data is being read from a slave transmitter by a master receiver on the FC
bus, there are two different cases depending upon whether the addressed slave
has sub-addresses or not. The sub-address is usually needed to access data from
a serial EEPROM, RTC, etc. Figure 12.33 shows the transfer of data between a
master receiver and a slave transmitter that has sub-addresses.
• . — Data transferred (in -

(Write) ' ea ' bytes + acknowledge)
Q From master to slave 0 From slave to master SUB denotes sub-address
Fig. 12.33 Master receiver reading data from slave transmitter having sub-addresses
If the master wants to read data bytes from a specific location or internal
register in the slave successively, the sequence of operations done by the master is
as follows:
(which is 0) appended as the LSB. The slave sends the Acknowledge (A)
signal.
(iii) The master sends the sub-address of a particular location or register in the
slave from where it wants to read data. This is called dummy write. The
slave sends the Acknowledge (A) signal.
(iv) The master sends a repeated start condition (Sr).
(v) The master again sends the 7-bit slave address, with the read/write (R/W)
bit, which is set to 1 now, to indicate read operation.
(vi) The slave sends data bytes one by one to the master and the master sends an
Acknowledge signal (A) after each byte read. If it is the last byte to be read
from the slave then the master sends a Not-acknowledge signal (A).
(vii) The master sends a stop (P) condition to end the data transfer.
When data is being read from a slave transmitter with no sub-addresses (such
as an analog-to-digital converter) by a master receiver in the I2C bus, the following
sequence of operations has to be performed:
(which is 1) appended as the LSB. The slave sends the Acknowledge (A)
signal.
(iii) The slave sends data bytes one by one to the master and the master sends
an Acknowledge signal (A) after each byte read. If it is the last byte to be
read from the slave,
the master sends a Data
Not-acknowledge
— Data transferred
1 (Read)
signal (A). bytes + Acknowledge)
(iv) The master sends a [J From master to slave □ From slave to master
stop (P) condition to

end the data transfer. Fig. 12.34 Master receiver reading data from slave
transmitter having no sub-addresses
This is shown in Fig. 12.34.
12.13.2 8051 Subroutines used to Implement l2C Bus

We can implement the I2C bus by using any two pins of the 8051. The 8051
subroutines (written in assembly language programs), which are used to implement
various functions involved in the I2C bus are given here. Port pins P0.6 and P0.7 of
the 8051 are assumed to be used as the SDA line and the SCL line, respectively,
of the I2C bus.
: Ports used for FC bus
SDA EOU P0.6 : The symbol SDA corresponds to pin P0.6.
SCL EQU P0.7 ; The symbol SCL corresponds to pin P0.7.
406 MICROPROCESSORS and microcontrollers
; Initializing the PC bus

I2C-INIT:
SETB SDA ; Set SDA to 1.
SETB SCL ; Set SCL to 1.
RET ; Return
; Creating the start condition
I2C_start:
CLR SDA ; Set SDA to 0.
CLR SCL ; Set SCL to 0.
RET ; Return
; Creating the restart condition
I2C_REstart:
SETB SCL : Set SCL to 1.
RET ; Return
; Creating the stop condition
I2C_stop:
SETB. SDA ; Set SDA to 1.
RET ; Return
; Sending data in register A of the 8051 (master) to a slave
I2C_SEND:
MOV R6. #08 ; Load the number of bits in A (i.e., 8) in R6.
REP:
RLC A ; Rotate A left through the carry to transfer one bit
in A to the carry, starting from the MSB.
MOV SDA, C ; Move the bit in the carry flag t0 SDA.
DJNZ R6, REP ; Decrement R6 and go to REP, if is not 0 (to
transmit the next bit).
RET ; Return
; Sending the Acknowledge signal
I2C_ACK:
RET : Return
; Sending the Not-acknowledge signal
I2C_NACK:
RET ; Return
; Receiving data from a slave to register A of the 8051 (master
I2C_RECEIVE:
MOV R6, #08 ; Load the number of bits in A (i.e., 8) in R6.
REP2:
MOV C, SDA ; Move the bit SDA to the carry flag.
RLC A ; Rotate A left through the carry, to receive one bit
from the carry, starting from the MSB.
DJNZ R6, REP2 ; Decrement R6 and go to REP2, if R6 is not 0 (to
receive the next bit).
RET ; Return
12.13.3 DS1307—Serial PC Real-time Clock IC

The DS 1307 serial real-time clock (RTC) is a product of MAXIM and is a low
power, binary coded decimal (BCD) clock/calendar IC. It has 56 bytes of battery-
backed general-purpose SRAM. Address and data are transferred serially through
an I2C bidirectional bus. The clock/calendar provides seconds, minutes, hours,
day, date, month, and year information with leap year compensation valid up to
the year 2100. The end of the month date is automatically adjusted for months
with fewer than 31 days, including corrections for leap year. The clock operates in
either the 24-hour or 12-hour format with AM/PM indicator. Figure 12.35 shows
the pin diagram of DS 1307 (plastic DIP). The DS 1307 has a built-in power
sense circuit that detects power failures and automatically
switches to the backup supply provided by the battery
X1E Pvcc
connected to it. The timekeeping operation continues X2C □ SQW/OUT
while the DS 1307 operates from the backup supply. It VbatC 3 SCL
also has a programmable square-wave output signal and GNDE □ SDA
consumes less than 500 nA in battery-backup mode, with

the oscillator running. The DS 1307 has eight pins and is Fig. 12.35 Pin diagram
of DS1307
available in plastic dual in-line package (DIP) and small
outline (SO) form.
The functional block diagram is shown in Fig. 12.36.
It contains an oscillator circuit, power control circuit, FC interface circuit, 56
bytes of battery-backed SRAM, clock, calendar and control registers, 7 bytes of
user buffer, multiplexer/buffer to control a MOSFET for generating a square wave
output, and control logic.
Fig. 12.36 Functional block diagram of DS 1307
12.13.3.1 Pin Details ofDS1307

The pin details of DS 1307 are as follows:
XI and X2—These two pins provide connections for the standard 32.768kHz
quartz crystal. The internal oscillator circuitry of the DS 1307 is designed for
operation with a crystal having a specified load capacitance (CL) of 12.5 pF. XI is
the input to the internal oscillator and can optionally be connected to an external
32.768 kHz oscillator. The output of the internal oscillator (X2) is floated if an
external oscillator is connected to XI.
Vbat—This pin is the backup supply input for a standard 3 V lithium cell or
any other energy source. The battery voltage must be held between the minimum
(2 V) and maximum limits (3.5 V) for proper operation (typical value is 3 V). If a
backup supply is not required, VBAT must be grounded. The nominal power-fail
trip point (V ) voltage at which access to the RTC and user RAM is denied, is
set by the internal circuitry as 1.25 times VBAT. A lithium battery with 48 mAh or
greater will provide backup supply for the DS 1307 for more than 10 years in the
absence of power at +25 °C.
SDA—This pin is the serial data input/output for the FC serial interface. The
SDA pin is open-drain and requires an external pull-up resistor. The pull-up
voltage can be up to 5.5 V, regardless of the voltage on Vcc.
SCL—This pin is the serial clock input for the FC interface and is used to
synchronize data movement on the serial interface. The pull-up voltage can be up
to 5.5 V, regardless of the voltage on Vcc.
SQW/OUT—This is a square wave/output driver pin. When enabled (i.e., when
the SQWE bit in the control register is set to 1), the SQW/OUT pin outputs one of
four square wave frequencies (1Hz, 4 kHz, 8 kHz, and 32 kHz). The SQW/OUT
pin is open-drain and requires an external pull-up resistor. SQW/OUT operates

with either Vcc or VBAT. The pull-up voltage can be up to 5.5 V, regardless of the
voltage on Vcc. If not used, this pin can be left floating.
Vcc—This is the primary power supply pin. When a voltage is applied within
normal limits (a minimum of 4.5 V to a maximum of 5.5 V, with a typical value
of 5 V), the device is fully accessible and data can be written and read. When
a backup supply is connected to the device and Vcc is below VpF, reading and
writing are inhibited. However, the timekeeping function continues unaffected by
the lower input voltage.
12.13.3.2 Detailed Description ofDS1307
The DS 1307 operates as a slave device on the I2C bus. Access is obtained by
implementing a start condition and providing a device identification code, which
is 1101000 (in binary form) for the DS 1307, followed by a register address.
Subsequent registers can be accessed sequentially until a stop condition is
executed. When Vnn falls below 1.25 times of V., A„ the device terminates the
access in progress and resets the address counter in the DS 1307. Inputs to the
device will not be recognized at this time, so as to prevent erroneous data from
being written to the device from an out-of-tolerance system. When Vcc falls below
VBAT, the device switches to a low current battery-backup mode. Upon power-up,
the device switches from battery to Vcc when Vcc is greater than (VBAT + 0.2 V)
and recognizes inputs when Vcc is greater than 1.25 times VBAT.
Oscillator Circuit
The DS 1307 uses an external 32.768 kHz crystal. The oscillator circuit does not
require any external resistors or capacitors to operate. The crystal should have a
load capacitance (CL) of 12.5 pF. Figure 12.36 shows the functional schematic
of the oscillator circuit. Using a crystal with the specified characteristics ensures
that the start-up time is usually less than one second. The accuracy of the clock is
dependent upon the accuracy of the crystal and the accuracy of the match between
the capacitive load of the oscillator circuit and the capacitive load for which the
crystal was trimmed. Additional error will be added by crystal frequency drift
caused by temperature shifts. External circuit noise coupled into the oscillator
circuit may result in the clock running fast.
RTC and RAM Address Map

The time and calendar information is obtained by reading the appropriate register
bytes in the DS 1307. Table 12.10 shows the address map for the RTC registers
and RAM registers in the DS 1307. The RTC registers are located in the address
locations 00H-07H. The RAM registers are located in address locations 08H-
3FH. During a multi-byte access, when the address pointer reaches 3FH, which
is the end of the RAM space, it wraps around to the location OOH, which is the
beginning of the clock space. The Function column in Table 12.10 indicates
the type of information present in the registers and the Range column indicates the
minimum and maximum values that can be stored in the registers.
Table 12.10 Timekeeper registers
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BitO Function Range
OOH CH 10 seconds Seconds Seconds 00-59
01H 0 10 minutes Minutes Minutes 00-59
12 10 hour 1-12
02H 0 24 PM/ 10 hour Hours Hours +AM/PM
AM 00-23
03H 0 0 0 0 0 Day Day 01-07
04H 0 0 10 Date Date Date 01-31
05H 0 0 0 10 month Month Month 01-12
06H 10 year Year Year 00-99
07H OUT 0 0 SQWE 0 0 RSI RS0 Control
08H- RAM 00H-FFH
3FH 56 x 8
Note: 'O' in the table implies that the bit will be read as 0.
Clock and Calendar

Time and calendar information is obtained by reading the appropriate register
bytes in DS 1307. Table 12.10 shows the registers in the DS 1307. The time and
calendar are set or initialized by writing the appropriate register bytes. The contents
of the time and calendar registers are in BCD format. The day-of-week (DOW)
register increments at midnight. Values that correspond to the day of week are
user-defined, but must be sequential (i.e., if 1 equals Sunday, 2 equals Monday,
and so on). Illogical time and date entries result in undefined operations. Bit 7
of register 0, which is at address OOH, is the clock halt (CH) bit. When this bit
is set to 1, the oscillator is disabled. When CH is cleared to 0, the oscillator is
enabled. On first application of power to the DS 1307, the time and date registers
are typically reset to 01/01/00 01 00:00:00 (which corresponds to month/date/year
day-of-week hour:minute:second). The CH bit in the seconds register will be set
to 1, due to which the oscillator is disabled. The clock can be halted whenever the
timekeeping functions are not required. This minimizes the battery current.
The DS 1307 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours
register at address 02H is defined as the 12-hour or 24-hour mode-select bit. When
it is high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM
bit, with logic high used to represent PM. In the 24-hour mode, bit 5 is the second
10-hour bit (20-23 hours). The hour value must be re-entered whenever the 12/24-
hour mode bit is changed.
When reading from or writing into the time and date registers, user buffers
(i.e., secondary registers) are used to prevent errors when the internal registers
update. During this process, the secondary registers are synchronized to the
internal registers on any I2C start condition. The time information is read from
these secondary registers while the clock continues to run. This eliminates the
need to re-read the registers, in case the internal registers update during a read.
The internal divider chain in the DS 1307 is reset whenever the seconds register
is written. Write transfers occur on the FC acknowledge from the DS 1307. Once
the divider chain is reset, to avoid rollover issues, the remaining time and date
registers must be written within one second.
Control Register
The DS 1307 control register is used to control the operation of the SQW/OUT
pin. The bits in the control register and the function of different bits in the control
register are shown in Fig. 12.37.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BitO

OUT 0 0 SQWE 0 0 RSI RSO
Fig, 12.37 DS1307 control register bits
The different bits in the DS 1307 control register and their functions are as follows:
OUT—The output control bit controls the output level of the SQW/OUT pin
when the square wave output is disabled by clearing the SQWE bit. If SQWE is
0, the logic level on the SQW/OUT pin is 0 if OUT is 0, and it is 1 if OUT is 1,
as shown in Table 12.11. On initial application of power to the DS 1307, this bit is
typically set to 0.
Square wave enable (SQWE)—This bit, when set to logic 1, enables the
oscillator output to be available at the SQW/OUT pin. The frequency of the
square wave output depends upon the value of the RSO and RS 1 bits in the control
register, as shown in Table 12.11. With the square wave output set to 1 Hz, the
clock registers update on the falling edge of the square wave. On initial application
of power to the DS 1307, this bit is typically set to 0.
Table 12.11 Function of different bits in the control register
RS1 RSO SQW/OUT output SQWE OUT

0 0 1Hz 1 X
0 1 4.096 kHz 1 X
1 0 8.192 kHz 1 X
1 1 32.768 kHz 1 X
X X 0 0 0
X X 1 0 1
Rate select (RSl:RS0)—These bits control the frequency of the square wave
output when the square wave output has been enabled. Table 12.11 lists the square
wave frequencies that can be selected with the RS bits. On initial application of
power to the DS 1307, these bits are typically set to 1.
12.13.3.3 Data Transfer between Master and DS1307
The DS 1307 can operate in two modes—slave receiver mode (during which
data is written into the DS 1307 by a master such as a microcontroller) and slave
transmitter mode (during which data can be read from the DS 1307 by a master
such as a microcontroller). The two modes are discussed in detail in this section.
Slave Receiver Mode (Write Mode)

In this mode, a master transmitter such as a microcontroller sends data bytes to the
DS 1307, which acts as the slave receiver. Serial data and serial clock are received
through the SDA and SCL pins, respectively, of the DS 1307. After each byte is
received from the master, an Acknowledge bit (A) is transmitted by the DS 1307.
The start and stop conditions are recognized as the beginning and end of the serial
transfer. Figure 12.38 shows the data transfer in this mode. The slave address byte
is the first byte received after the master generates the start condition. The slave
address byte contains the DS1307’s 7-bit address, which is 1101000, followed by
the direction bit (R/W), which is 0 for a write. After receiving and decoding the
slave address byte, the DS 1307 outputs an Acknowledge signal (A) on the SDA
pin. Next, the master transmits a word address (i.e., sub-address) to the DS 1307.
This sets the register pointer on the DS 1307, with the DS 1307 acknowledging the
transfer. The master can then transmit zero or more bytes of data, with the DS 1307
acknowledging each byte received. The register pointer automatically increments
after each data byte is written. The master will generate a stop condition to
terminate the data write.
Slave address R/W Word address (n) Data(n) Data (n+1) Data (n+X)
A
s 1101000
2______ ts 0 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX P
S = Start Q From master to slave

Data transferred
A = Acknowledge (ACK)
(X+1) bytes + Acknowledge)
P = Stop Q From slave to master
Fig. 12.38 Data transfer in slave receiver mode—write mode
Slave Transmitter Mode (Read Mode)

In this mode, any master receiver such as a microcontroller receives data bytes
from the DS 1307, which acts as the slave transmitter. The diagram indicating the
data transfer in this mode is shown in Fig. 12.39. The first byte is received and
handled as in the slave receiver mode, except that the direction bit (R/W) is set to
1 to indicate read operation. The DS 1307 transmits serial data on the SDA pin,
while the serial clock is input on the SCL pin. The start and stop conditions are
recognized as the beginning and end of a serial transfer. The slave address byte is
the first byte received after the start condition is generated by the master. The slave
address byte contains the DS1307’s 7-bit address, which is 1101000, followed by
the direction bit (R/W), which is 1 for a read. After receiving and decoding the
Slave address R/W Data (n) Data (n + 1) Data (n + 2) Data (n + X)

S | 1101000 ~ p A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P
S = Start 0 From master to slave

Data transferred
A = Acknowledge (ACK)
P = Stop Q From slave to master
A ~ Not-acknowledge (NACK)
Fig. 12.39 Data transfer in slave transmitter mode—read mode

slave address, the DS13O7 outputs an Acknowledge signal (A) on the SDA pin.
The DS 1307 then begins to transmit the data, starting from the register whose
address is given by the register pointer. If the register pointer is not written into
before the initiation of a read mode, the first address that is read is the last one
stored in the register pointer. The register pointer automatically increments after
each byte is read. The DS 1307 must receive a Not-acknowledge signal (A) to end
a read.
When the DS 1307 is operating in the slave transmitter mode (read mode), if
the master receiver wants to access the data bytes starting at a specific internal
register or RAM location in the slave, after sending the slave address and (R/W)
bit (which is set to 0), the master receives an Acknowledge signal (A) from the
slave, as shown in Fig. 12.40. The master then sends the word address (i.e., sub
address or pointer) of the specific internal register or RAM location from where
reading has to be done in the slave, and receives the Acknowledge signal (A) from
the slave. Then, after a repeated start (Sr) condition, the master again sends the
slave address and the (R/W) bit (which is set to 1 now to indicate read operation)
and receives the Acknowledge signal (A) from the slave. Then the master reads
data bytes one by one from the desired internal registers or RAM locations of the
slave and generates an Acknowledge signal for each byte received. After the last
byte is received, the master sends a Not-acknowledge signal to the slave and the
slave terminates the transfer. The master sends the stop condition. Figure 12.40
shows the complete details of this data transfer.
Slave address R/W Word address (n) Slave address
S = Start 3 From master to slave

Data transferred
Sr = Repeated Start
A = Acknowledge (ACK) Q From slave to master
P = Stop
A = Not-acknowledge (NACK)
Fig. 12.40 Data read—slave receive and transmit
Figure 12.41 shows the interfacing of the 8051 with the DS 1307. Pins P0.6 and P0.7
of the 8051 act as the SDA and SCL, respectively, of the FC bus. Rpu represents
the pull-up resistance that is to be connected to the SDA and SCL pins. To get a
square wave (if needed), another pull-up resistance is connected to the SQW/OUT
pin. Using the 8051 subroutines written in an assembly language program, along
with the sequence mentioned for data read and write in the DS 1307, data can be
transferred between the 8051 and DS 1307.
Fig. 12.41 Interfacing 8051 with DS1307
POINTS TO REMEMBEfS
• The number of I/O ports in a microcontroller can be increased by interfacing the

programmable peripheral interface chip (8255) with the 8051.
• Different I/O devices such as LEDs, seven-segment displays, LCDs, ADCs, and DACs
can be interfaced with the 8051 microcontroller, either directly or through the 8255.
• A DAC interfaced with a microcontroller can be used for generating many waveforms.
• A multiplexed display can be used to reduce the hardware and thus reduce power
consumption. This is achieved at the cost of software overhead.
• A stepper motor or a DC motor can be precisely controlled, if interfaced and controlled
using a microcontroller.
• A microcontroller can be used for many industrial and domestic applications such as
traffic light control, temperature control, weighing machine control, and lighting control.
The readers can develop many more applications, using combinations of interfaces
discussed in this chapter.
REVIEW QUESTIONS
1. Discuss in detail the interfacing of the stepper motor with the 8051.
2. What is the need for the 8255 in a microcontroller-based system?
3. Explain the interfacing of push button switches and LEDs with the 8051
microcontroller.
4. Assume that an ADC and a DAC chip are interfaced with the 8051. Write a program
to read the data from the ADC and output it on the DAC line with a 1 ms delay.
5. Write a program to read the analog voltage through the ADC chip and display the
result in a two-digit seven-segment display. Draw the related interface diagram with
the 8051.
6. Describe with a schematic, the scanning of the matrix keyboard in an 8051-based
system and identifying the key pressed.
7. Assume that the speed of a stepper motor has to be controlled using an 8051
microcontroller. Design the required hardware and explain the required software.
8. Show how a low-voltage DC motor can be controlled using the 8051.
9. Explain with a neat diagram, the interfacing of an LCD with the 8051.
10. Explain traffic light control in a three-road junction using the 8051.
THINK AND ANSWER
1. Explain the interfacing of four seven-segment LED displays with the 8051, using the
multiplexed display concept.
2. Interface an ADC chip and an intelligent LCD with the 8051. Explain the algorithm
needed to read data from the ADC and display it in the LCD.
3. Interface a DC motor and two switches with the 8051 and explain the software needed
for controlling the direction of the DC motor using the switches.
N U M E RIC AL/D ESIG N-BASED EXERCISES
1. Design a microcontroller-based system for a weighing machine.

[Hint: Use a load cell or any other suitable transducer, instead of a thermistor, in the
example discussed.]
2. Design a microcontroller-based controller for turning on and off the lights in a building,
based on the movement of people in the building.
[Hint: Use an IR sensor to detect persons in the building and accordingly either turn on
or turn off the light, as done in the traffic light control example.]
Part 4
INTEL 8086—16-BIT
MICROPROCESSORS
Chapter 13: Intel 8086 Microprocessor

Architecture, Features, and Signals
Chapter 14: Addressing Modes, Instruction Set,

and Programming of 8086
Chapter 15: 8086 Interrupts
Chapter 16: Memory and I/O Interfacing
Chapter 17: Multiprocessor Configuration
Chapter 18: 8086-based Systems

CHAPTER 13
INTEL 8086 MICROPROCESSOR

ARCHITECTURE, FEATURES, AND
SIGNALS
LEARNING OUTCOMES
• Internal architecture of the 8086, which consists of an execution unit and a bus interface
unit
• Different general-purpose and segment registers and their functions
♦ Accessing of instructions and data from the memory using the segment and offset
addresses
• Pin details of the 8086
• Functions of the maximum mode and minimum mode signals
13.1 INTRODUCTION
In 1978, Intel released its first 16-bit microprocessor, the 8086, which executes the
instructions at 2.5 MIPS (million instructions per second). The execution time for
one instruction is 400 ns (= 1/MIPS = 1/(2.5 x 106)). The 8086 can address 1MB
(1 MB = 220 bytes) of memory, as it has a 20-bit address bus. The width of the data
bus in the 8086 is 16 bits. This higher execution speed and larger memory size
have enabled the 8086 to replace the smaller minicomputers in many applications.
Another feature in the 8086 is the presence of a small six-byte instruction queue
in which the instructions fetched from the memory are placed before they are
executed.
13.2 ARCHITECTURE OF 8086

The functional block diagram of the 8086 is shown in Fig. 13.1. It is subdivided
into the following two units:
(i) An execution unit (EU), which includes the ALU, eight 16-bit general-
purpose registers, a 16-bit flag register, and a control unit.
(ii) A bus interface unit (BIU), which includes an adder for address calculations,
four 16-bit segment registers (CS, DS, SS, and ES), a 16-bit instruction
pointer (IP), a six-byte instruction queue, and bus control logic.
13.2.1 Execution Unit

The EU consists of eight 16-bit general-purpose registers—AX, BX, CX, DX,
SP, BP, SI, and DI. Among these registers, AX, BX, CX, and DX can be further
Fig. 13.1 Functional block diagram of the 8086
divided into two 8-bit registers—AH and AL, BH and BL, CH and CL, and DH
and DL, respectively, as shown in Fig. 13.1. The general-purpose registers can
be used to store 8-bit or 16-bit data during program execution. In addition, each
register has the following special functions:
(i) AX/AL: AX or AL is used as the accumulator. It is used in the multiply,
divide, and input/output (I/O) operations, and in some decimal and ASCII
adjustment instructions.
(ii) BX: The BX register holds the offset address of a location in the memory.
It is also used to refer to the data in the memory using the look-up table
technique, with the help of the XLAT instruction.
(iii) CX/CL: CX is used to hold the count value while executing the repeated
string instructions (REP/REPE/REPNE) and the LOOP instruction. CL is
used to hold the count value while executing the shift/rotate instructions.
The count value indicates the number of times the same code has to be
executed when the LOOP instruction is used and the number of times the
data item has to be shifted/rotated when the shift/rotate instruction is used.
(iv) DX: DX is used to hold a part of the result during a multiplication operation
and a part of the dividend before a division operation. It is also used to hold
the I/O device address while executing the IN and OUT instructions.
(v) SP: The SP register or the stack pointer is used to hold the offset address of
INTEL 8086 MICROPROCESSOR ARCHITECTURE, FEATURES, AND SIGNALS 421
the data stored at the top of the stack segment. SP is used along with the SS
register to decide the address at which the data is to be pushed or popped,
during the execution of the PUSH or POP instruction, respectively.
(vi) BP: The BP register is called base pointer. It is also used to hold the offset
address of the data to be read from or written into the stack segment.
(vii) SI: The SI register is called source index register. It is used to hold the
offset address of the source data in the data segment, while executing string
instructions.
(viii) DI: The DI register is called destination index register. It is used to hold the
offset address of the destination data in the extra segment, while executing
string instructions.
Here, the term segment refers to a portion of the memory where the data, code,
or stack for a program is stored. In the 8086, the maximum size of a segment can
be 64 KB and the minimum size can be even 1 byte. A segment always begins at a
memory address divisible by 16. This means that the starting address of a segment
in the memory in hexadecimal form is XXXXOH. The reason for this is explained
in Section 13.2.2.
The flag register of the 8086 is shown in Fig. 13.2.
D15 D14 D13 D12 Dll D10 D9 D8 D7 D6 D5 D4 D3 D2 DI DO

— — — —< ■ • OF DF IF TF SF ZF — AF — PF — CF
Note: Bits marked —Intel-reserved bits (normally set to 0)
Fig. 13.2 Flag register of the 8086
The flags in the flag register can be classified into status flags and control flags.
The flags CF, PF, AF, ZF, SF, and OF are called status flags, as they indicate the
status of the result that is obtained after the execution of an arithmetic or logic
instruction. The flags DF, IF, and TF are called control flags, as they control the
operation of the CPU. The functions of the different flags are as follows:
(i) CF (carry flag): CF holds the carry after an 8-bit or 16-bit addition or the
borrow after an 8-bit or 16-bit subtraction operation.
(ii ) PF (parity flag): If the lower eight bits of the result have an odd parity (i.e.,
odd number of Is), PF is set to 0. Otherwise, it is set to 1.
(iii ) AF (auxiliary carry flag): AF holds the carry after addition or the borrow
after subtraction of the bits in the bit position 3 (the LSB is treated as bit
position 0). This flag is used by the DAA or the DAS instruction to adjust
the value in AL after a BCD addition or subtraction, respectively.
(iv) ZF (zero flag): ZF indicates that the result of an arithmetic or logic operation
is zero. If Z = 1, the result is zero and if Z = 0, the result is not zero.
(v) SF (sign flag): SF holds the arithmetic sign of the result after an arithmetic
or logic instruction is executed. If S - 0, the sign bit is 0 and the result is
positive.
(vi) TF (trap flag): TF is used to debug a program using the single-step
technique. If it is set (i.e., TF = 1), the 8086 gets interrupted (trap or single-
step interrupt) after the execution of each instruction in the program. If TF
is cleared (i.e., TF = 0), the trapping or debugging feature is disabled.
(vii ) DF (direction flag): DF selects either the increment or decrement mode for
the DI and/or SI register, during the execution of string instructions. If D
= 0, the registers are automatically incremented; if D = 1, the registers are
automatically decremented. This flag can be set and cleared using the STD
and CLD instructions, respectively.
(viii ) IF (interrupt flag): IF controls the operation of the INTR interrupt pin of
the 8086. If IF = 0, the INTR pin is disabled and if IF = 1, the INTR pin is
enabled. This flag can be set and cleared using the STI and CLI instructions,
respectively.
(ix) OF (overflow flag): Signed negative numbers are represented in the 2’s
complement form in the microprocessor. When signed numbers are added
or subtracted, an overflow may occur. An overflow indicates that the result
has exceeded the capacity of the machine. For example, if the 8-bit signed
data 7EH (= +126) is added with the 8-bit signed data 02H (= +2), the
result is 80H (= -128 in the 2’s complement form). This result indicates
an overflow condition and the overflow flag is set during the given signed
addition operation. In an 8-bit register, the minimum and maximum value
of the signed number that can be stored is -128 (= 80H) and +127 (= 7FH),
respectively. In a 16-bit register, the minimum and maximum value of
the signed number that can be stored is -32,768 (= 8000H) and +32,767
(= 7FFFH), respectively. For operations on unsigned data, OF is ignored.
13.2.2 Bus Interface Unit

There are four segment registers CS, DS, SS, and ES in the 8086. The function
of these registers is to indicate the starting or base address of the code segment,
data segment, stack segment, and extra segment, respectively, in the memory. The
code segment contains the instructions of a program and the data segment contains
data for the program. The stack segment holds the stack of the program, which
is needed while executing the CALL and RET instructions and also to handle
interrupts. The extra segment is an additional data segment that is used by some
string instructions.
The base address of any segment can be obtained by adding four binary 0s
to the farthest right portion of the content of the corresponding segment register,
which is the same as adding the hexadecimal digit 0. It is also equivalent to shifting
the content of the segment register left by four bits. Hence, a segment in the 8086
always starts at a memory address that is divisible by the decimal number 16 (also
known as 16-byte boundary). This is illustrated with an example as follows:
Example 13.1:
Let us assume that the segment registers have following values stored in them:
CS DS SS ES
2000H 4000H 6000H 8000H
The base address of the code segment

is obtained by adding four binary Os
(same as the hexadecimal digit 0)
to the content of CS. Therefore, the
base address is 20000H. Similarly,
the base address of the data segment,
stack segment, and extra segment
are 40000H, 60000H, and 80000H,
respectively. Figure 13.3 shows the
location of these segments in the 1MB
memory. Memory
If the size of two different segments

is less than 64 KB, it is possible that
the two segments may overlap (i.e.,
another segment may begin within
the 64 KB allocated to a segment).
For example, let a particular
application in the 8086 require a
code segment of size 1 KB and a data
segment of size 2KB. If the code
Fig. 13.3 Location of various segments
segment is stored in the memory
in memory
from the address 20000H, it will end
at the memory address 203FFH. The data segment can be stored from the address
20400H (which is the next immediate 16-byte boundary in the memory). The CS
and DS registers are loaded with the values 2000H and 2040H, respectively, for
running this application in the 8086.
13.3 ACCESSING MEMORY LOCATIONS

Each address in the physical memory (ROM/EPROM) is called a physical address.
To access an operand (either data or instruction) from a particular segment of the
memory, the 8086 has to first calculate the physical address of that operand. To
accomplish this task, the 8086 adds the base address of the corresponding segment
with an offset address, which may be the content of a register, an 8-bit or 16-
bit displacement given in the instruction, or a combination of both, depending
upon the addressing mode used by the instruction. The designers of the 8086 have
assigned certain register(s) as default offset register(s) for the segment registers,
as shown in Table
Table 13.1 Segment registers and default offset registers in the 8086
13.1. However, this
default assignment Segment registers Default offset registers
can be changed by
CS IP
using the segment
DS BX, SI, DI, 8- or 16-bit displacement
override prefix in the
instruction, which is SS SP and BP
explained in Chapter ES DI for string instructions
14 (Section 14.2).
Example 13.2:
The fetching of an instruction from the memory in the 8086 is explained in this
example.
Let us assume that the CS register has the value 3000H and the IP register has
the value 2000H. To fetch an instruction from the memory, the CPU calculates the
memory address from which the next instruction is to be fetched, as follows:
CS x 10H = 30000H—► Base address of the code segment
+ IP = 2000H —> Offset address
32000H—> Memory address from where the next instruction is taken
Example 13.3:
Let us see the fetching of data from the memory using the DS and BX registers,
with an example. Consider the execution of the instruction MOV AX, [BX].
The square bracket around BX in this instruction indicates that the data
specified by the BX register is in the memory; the BX register holds the offset
address of the data in the data segment. The data obtained from the memory is
moved to the AX register. Let us assume that DS and BX have the values 10000H
and 3000H, respectively. To calculate the memory address from where the data
has to be taken, the CPU does the following operation:
DS x 10H =10000H —> Base address of the data segment
+ BX = 3000H —> Offset address
13000H —> Memory address from where the data is taken
This is also explained in Fig. 13.4.
Memory Address
10000H
13000H
13001H
Fig. 13.4 Execution of the instruction MOV AX, [BX]
Example 13.4:
Let us see the pushing of data into the stack segment using the PUSH instruction,
with an example.
Assume that the SS and SP registers have the values 3000H and 0105H,
respectively. Consider the execution of the instruction PUSH AX by the 8086. The
steps carried out by the 8086 to execute the PUSH AX instruction are as follows:
(i) SP is decremented by 1 (i.e., SP = 0104H) and the content of the AH register
(upper byte of AX) is pushed into the offset address specified by SP in the
stack segment, as shown in Fig. 13.5 (a).
(ii) SP is again decremented by 1 (i.e., SP = 0103H) and the content of the AL
register (lower byte of AX) is pushed into the offset address specified by SP
in the stack segment, as shown in Fig. 13.5 (b).
Memory Address
30000H—Base address of
AH AL A stack segment (=SS X 10H)
3CH SP = 0104H
2BH
3CH 30104H—(SS X 10H + SP)
(a)
Memory Address
30000H—(SS X 10H)
30103H—(SSX10H + SP)
30104H
(b)
Fig. 13.5 PUSH AX: (a) pushing the first byte of AX onto the stack segment (b) pushing the
second byte of AX onto the stack segment
The instruction queue is six bytes long and stores the pre-fetched instructions
from the code segment. From there, the instruction is taken to the instruction
decoder, where it is decoded. The decoder passes the decoded information to the
timing and control circuit, which in turn generates the various control signals to
execute the instruction. Whenever this decoded instruction requires branching
(which arises when conditional or unconditional jump instructions are decoded),
the instruction queue is flushed and the instruction bytes from the branch address
are fetched into the queue. The BIU fetches the instruction bytes from the memory
whenever the EU is not using the address/data bus and puts them in the instruction
queue. Fetching and execution of instructions can take place simultaneously. Thus
the instruction queue reduces the execution time of a program.
The segment and offset mechanism for accessing the memory in the 8086 allows
the programmer to write relocatable programs or data structures. A relocatable
program or data structure is one that can be placed anywhere in the memory map
of the 8086 and executed without any modification. This is not possible in the 8085
microprocessor. In a relocatable program, the jump instructions use only relative
values (positive or negative) with respect to the program counter, using which the
jump address is calculated. In addition, in a relocatable data structure, the data is
referred to using the offset address in the data segment or the extra segment.
13.4 PIN DETAILS OF 8086

The 8086 can operate in any one of the following two modes—minimum mode and
maximum mode. In the minimum mode, all the control signals for the memory and
I/O are generated by the 8086. In the maximum mode, some control signals must
be externally generated. This requires the addition of an external bus controller
such as the 8288 to the 8086. Some pins in the 8086 have the same function in both
modes; other pins have different functions. Figure 13.6 shows the pin details of the
8086.
Max. mode (Min. mode)
GND 40 □
ADU E2 39 □ AD15
AD13 38 □ A16/S3
AD12 4 37 □ A17/S4
AD11 E 5 36 □ A18/S5
AD10 6 35 J A19/S6
AD9 7 34 □ BHE/S7
AD8 E 8 33 □ MN/MX
AD7 9 32 □ RD
8086
AD6 E 10 31 □ RQ/GTO (HOLD)
$
AD5 E 11 30 □ RQ/GT1 (HLDA)
AD4 12 29 □ LOCK (WR)
AD3 E 13 28 □ S2 (M/iO)
AD2 14 27 □ SI (DT/R)
AD1 E 15 26 □ SO (DEN)
ADO 16 25 J QSO (ALE)
NMI 17 24 □ QS1 (INTA)
INTR E 18 23 □ TEST
CLK 19 22 □ READY
GND
4 E 20 21 □ RESET
Fig. 13.6 Pin details of the 8086
13.4.1 Function of Pins Common to Minimum and Maximum Modes

The pins that have a common function in both the modes are as follows:
(i) AD15-AD0: These pins act as the multiplexed address and data bus of the
microprocessor. Whenever the ALE (address latch enable) pin is high (i.e.,
1), these pins carry the address, and when the ALE pin is low (i.e., 0), these
pins carry data. Using two external octal latches such as two 74373s along
with the ALE signal, these pins can be de-multiplexed into the address bus
(A15-A0) and data bus (D15-D0).
(ii) A19/S6-A16/S3: These pins (address/status bus) are multiplexed to provide
the address signals A 19-Al6 and the status bits S6-S3. When ALE = 1,
these pins carry the address and when ALE = 0, they carry the status lines.
Using one external octal latch (74373) along with the ALE signal, these
pins can be de-multiplexed into the address bus (A 19-Al6) and the status
bus (S6-S3). S3 and S4 indicate the segment accessed by the 8086 during
the current bus cycle. This is shown in Table 13.2.
Table 13.2 Function of status bits S4 and S3
S4 S3 Segment accessed
0 0 Extra segment
0 1 Stack segment
1 0 Code segment or no segment
1 1 Data segment
The status bit S5 indicates the condition of the IF bit; S6 always remains at logic
0.
(iii) NMI: The non-maskable interrupt (NMI) input is a hardware interrupt. It
cannot be disabled by software. It is a positive edge-triggered interrupt and
when it occurs, the type 2 interrupt occurs in the 8086.
(iv) INTR: The interrupt request (INTR) is a level-triggered hardware interrupt,
which depends on the status of IF. When IF = 1, if INTR is held high (i.e.,
logic 1), the 8086 gets interrupted. When IF = 0, INTR is disabled.
(v) CLK: The clock signal must have a duty cycle of 33% to provide proper
internal timing for the 8086. Its maximum frequency can be 5, 8, and
10 MHz for different versions of the 8086—the 8086, 8086-2, and 8086-1,
respectively.
(vi) Vcc: This power supply pin provides a +5 V signal to the 8086. The variation
allowed in the power supply input is ±10%.
(vii) BHE/S7: The bus high enable (BHE) pin is used in the 8086 to enable the
most significant data bus (D15-D8) during a read/write operation. The
state of the status line S7 is always logic 1.
(viii) MN/MX: The MN/MX pin is used to select either the minimum mode or
the maximum mode operation for the 8086. This is achieved by connecting
this pin to either +5 V directly (for minimum mode) or to the ground (for
maximum mode).
(ix) RD: Whenever the Read signal (RD) is at logic 0, the 8086 reads the data
from the memory or EO device through the data bus.
(x) TEST: The TEST pin is an input that is tested by the WAIT instruction. If
the TEST pin is at logic 0, the WAIT instruction functions as a NOP (no
operation) instruction. If the TEST pin is at logic 1, the WAIT instruction
waits for the TEST pin to become logic 0. This pin is often connected to
the BUSY pin of the 8087 (numeric coprocessor) to perform floating-point
operations.
(xi) READY: This input is used to insert wait states into the timing cycle of the
8086. If the READY pin is at logic 1, it has no effect on the operation of the
microprocessor. If it is at logic 0, the 8086 enters the wait state and remains
idle. This pin is used to interface the slowly operating peripherals with the
8086.
(xii) RESET: This input causes the 8086 to reset, if it is held at logic 1 for a
minimum of four clocking periods. Whenever the 8086 is reset, CS and IP
are initialized to FFFFH and 0000H, respectively, and all other registers are
initialized to 0000H. This causes the 8086 to begin executing instructions
from the memory address FFFF0H.
(xiii) GND: The GND connection is the return for the power supply (Vcc). The
8086 has two GND pins and both must be connected to ground for proper
operation.
13.4.2 Function of Pins used in Minimum Mode

The pins used in the minimum mode are as follows:
(i) M/IO: This pin indicates whether the 8086 is performing memory read/
write operation (M/IO = 1) or I/O read/write operation (M/IO = 0).
(ii) WR: The Write signal indicates that the 8086 is sending data to a memory
or I/O device. When WR is at logic 0, the data bus contains valid data for
the memory or I/O.
(iii) DT/R: The Data Transmit/Receive signal indicates that the 8086 data bus is
transmitting (DT/R = 1) or receiving (DT/R = 0) data. This signal is used to
control the data flow direction in external data bus buffers.
(iv) DEN: The Data Bus Enable signal activates external data bus buffers. When
data is transferred through the data bus of the 8086, this signal is at logic 0.
When DEN is high, no data flows in the data bus.
(v) ALE: When the Address Latch Enable (ALE) signal is high, it indicates
that the 8086 multiplexed address/data bus (AD15-AD0) and multiplexed
address/status bus (A19/S6-A16/S3) contain an address, which can be
either a memory address or an I/O port address.
(vi) INTA: The Interrupt Acknowledge signal is a response to the INTR input
pin. The INTA signal is used to place the interrupt type or vector number in
the data bus, in response to the INTR interrupt.
(vii) HOLD: The Hold input requests a direct memory access (DMA) and is
generated by the DMA controller. If the Hold signal is at logic 1, the 8086
completes the execution of the current instruction and places its address,
data, and control buses in the high impedance state. If the Hold signal is at
logic 0, the 8086 executes the instructions normally.
(viii) HLDA: The Hold Acknowledge signal indicates that the 8086 has entered
the hold state and is connected to the HLDA input of the DMA controller.
13.4.3 Function of Pins used in Maximum Mode

The pins used in the maximum mode are as follows:
(i) S2, ST, and SO: The status bits indicate the function of the current bus cycle.
These signals are normally decoded by the 8288 (bus controller). Table
13.3 shows the function of these three status bits in the maximum mode.
Table 13.3 Function of S2, S1, and SO pins
S2 S1 so Function
0 0 0 Interrupt acknowledge
0 0 1 I/O read
0 1 0 I/O write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive (inactive)
(ii) LOCK: The Lock output is used to lock peripherals off the system. This pin
is activated by using the LOCK prefix on any instruction.
(iii) RQ/GTO and RQ/GT1: The request/grant pins request DMA during the
maximum mode operation of the 8086. These lines are bidirectional and
are used to request and grant a DMA operation.
(iv) QS1 and QSO: The queue status bits show the status of the internal
instruction queue in the 8086. These pins are provided for access by the
numeric coprocessor (8087). Table 13.4 shows the function of the QS1 and
QSO bits.
Table 13.4 Function of QS1 and QSO pins
QS1 QSO Function
0 0 Queue is idle (or no operation).

0 1 First byte of opcode is read from the queue.
1 0 Queue is empty.
1 1 Subsequent byte of opcode is read from the queue.
POINTS TO REMEMBER
• The internal architecture of the 8086 mainly contains two units—the bus interface unit
(BIU) and the execution unit (EU).
• The BIU fetches instructions and data from the memory to the processor, using the
content of a segment register and an offset.
• There exists a six-byte instruction queue in the 8086, which is used to store the recently
fetched instructions in the CPU. This is used to speed up the execution of a program.
• There are four memory segments—code, data, stack, and extra segments in the 8086 and
their base address is indicated by adding four binary 0s to the right of the corresponding
segment register’s content. The maximum size of a memory segment is 64 KB.
• For fetching either an instruction byte or a data, the 8086 adds the base address of the
particular segment with an offset address present in a register, available as an 8- or 16-
bit displacement in the instruction, or obtained by a combination of both.
• The designers of the 8086 have fixed the default offset register(s) for every segment
register. However, this can be changed using the segment override prefix in the
instruction.
• The EU contains the ALU, general-purpose registers, and the flag register, which are
used during the execution of an instruction.
• The flag register contain different flags, which can be classified as status flags and
control flags. The status flags reflect the result of arithmetic and logical operations, and
the control flags control the operation during execution of instructions.
• The 8086 can be operated in minimum mode or maximum mode.
• In the 8086, the size of the address bus and data bus is 20 bits and 16 bits, respectively.
The 8086 can access a maximum memory size of 1 MB (= 220), as it has a 20-bit address
bus.
Bus interface unit This unit BIU includes an adder for address calculations, four 16-
bit segment registers (CS, DS, SS, and ES), a 16-bit instruction pointer (IP), a six-byte
instruction queue, and bus control logic. This unit is responsible for fetching the instructions
and data into the 8086 from the memory or I/O device.
Code segment This segment contains the instructions of a program.
Data segment This segment contains the data for a program.
Execution unit This unit includes the ALU, eight 16-bit general-purpose registers, a
16-bit flag register, and the control unit. This unit is responsible for executing instructions
in the 8086.
Extra segment This is an additional data segment used by some string instructions.
Flags These show information related to the result of the arithmetic or logic operation
performed in the ALU. Flags in the flag register can be classified as status flags and control
flags.
Instruction queue It is six bytes long in the 8086 and stores the pre-fetched instructions
from the memory. It is used to speed up the execution of a program.
Maximum mode operation In this mode, some control signals must be externally
generated, using a bus controller such as the 8288.
Minimum mode operation In this mode, all control signals for the memory and I/O are
generated by the microprocessor itself.
Offset This is a 16-bit number that is added to the base address of a segment, to select a
byte of instruction or data from the memory.
Relocatable program It is the one that can be placed anywhere in the memory map of
the 8086 and executed without any modification.
Segment register This register indicates the starting or base address of a segment in the
memory.
Stack segment This segment holds the stack of a program.
REVIEW QUESTIONS
1. What is the size of the address bus and data bus in the 8086?
2. What is meant by multiplexed address and data bus?
3. Draw the register organization of the 8086 and explain typical applications of each
register.
4. How is the 20-bit physical memory address calculated in the 8086 processor?
5. Write the different memory segments used in the 8086 and their functions.
6. List the segment registers and their default offset registers in the 8086.
7. What are the steps involved when PUSH BX is executed by the 8086?
8. Write the function of the DF, IF, and TF bits in the 8086.
9. The content of the different registers in the 8086 is CS = F000H, DS = 1000H,
SS = 2000H, and ES = 3000H. Find the base address of the different segments in the
memory.
10. If the current content of the CS and IP registers is FFFFH and 0000H, respectively,
from which memory location will the 8086 fetch the next instruction?
11. If the content of the DS and BX registers is 2500H and 1000H, respectively, from
which memory location will the 8086 fetch the data, while executing the instruction
MOV CX, [BX]?
12. If the content of the SS and SP registers is 5000H and 1000H, respectively, in which
memory location is the content of DX saved, when the 8086 executes the instruction
PUSH DX?
13. What is the difference between the minimum and maximum mode operation of the
8086?
14. What is the supply to be given to the Vcc input of the 8086?
15. What is the maximum frequency and duty cycle of the clock signal givento the 8086?
16. What is the function of the BHE and ALE signals in the 8086?
17. Which pins of the 8086 are used to enable and control the external data busbuffers?
18. What is the minimum time for which the Reset input must be activated for proper reset
of the 8086?
19. What are the contents of the CS and IP registers immediately after the reset of the
8086?
20. What is meant by DMA operation? Which pins of the 8086 are used to perform the
DMA operation in the minimum and maximum modes of the 8086?
21. What is the role of the status lines S4 and S3 in the 8086?
22. What is the function of the S2, SI, and SO signals in the maximum mode operation of
the 8086? _ ___
23. What is the role of the TEST pin in the 8086?
24. Explain the architecture of the 8086 with a neat functional block diagram.
25. Explain the function of the different flags in the 8086.
THINK AND ANSWER
1. How much memory, in terms of bytes, can be interfaced with the 8086? Why?
2. What is the minimum and maximum size of a segment in terms of bytes? Why?
3. Why is memory divided into segments in the 8086? What are its advantages?
4. How many 8K x 8 memory chips are required to construct a 1 MB memory?
5. Which pin of the 8086 determines the mode of operation? How?
6. What are the differences between NMI and INTR interrupts in the 8086?
7. Which pin of the 8086 is used to synchronize the slowly operating peripherals with the
8086? How?
8. Is it possible for a segment to begin at a memory address that is not divisible by 16
(i.e., the address that does not end with the digit OH) in the 8086? Why?
9. Is it possible for two segments to overlap in the 8086? Why?
10. Why is the stack segment said to be growing downwards in the 8086?
11. Mention the differences between 8085 and 8086 microprocessors.
CHAPTER 14
ADDRESSING MODES,
INSTRUCTION SET, AND
PROGRAMMING OF 8086
14.1 ADDRESSING MODES IN 8086

There are different addressing modes in the 8086. The addressing mode indicates
the way in which the operand or data for an instruction is accessed and the way
in which the microprocessor calculates the branch address for the jump, call, and
return instructions. We can classify the addressing modes in the 8086 under five
categories:
(i) Register addressing mode
(ii) Immediate addressing mode
(iii) Data memory addressing modes
(iv) Program memory addressing modes
(v) Stack memory addressing mode
Let us see each addressing mode in detail.
14.1. 1 Register Addressing Mode

In this addressing mode, the data present in the register is moved or manipulated
and the result is stored in the register.
Example:
(a) MOV AL, BL ; Move the content of BL to AL.
(b) MOV CX, BX ; Move the content of BX to CX.
(c) ADD CL, BL ; Add the contents of CL and BL and store the
result in CL.
(d) ADC BX, DX ; Add the contents of BX , the carry flag, and
DX, and store the result in BX.
ADDRESSING MODES, INSTRUCTION SET, AND PROGRAMMING OF 8086 4 33
14.1. 2 Immediate Addressing Mode

In this mode, the destination can be either a memory location or a register. The
data can be 8 bits or 16 bits wide and is directly given in the instruction.
Example:
(a) MOV AL, 50H ; Move the data 50H to AL.
(b) MOV BX, 23A0H ; Move the data 23A0H to BX.
(c) MOV [SI], 43C0H ; Move the data 43C0H to the memory at [SI].
In the last example, [SI] represents the memory location in the data segment at
the offset address specified by the SI register.
14.1. 3 Data Memory Addressing Modes

The term effective address (EA) represents the offset address of the data within a
segment, which is obtained by different methods, depending upon the addressing
mode that is used in the instruction. Let us assume that the various registers in
the 8086 have the following values (Table 14.1) stored in them, throughout the
discussion of data memory addressing modes.
Table 14.1 Values stored in different registers of the 8086
Register CS DS SS ES BX BP SI DI
Stored value 1000H 3000H 4000H 6000H 2000H 1000H 1000H 3OOOH
The different data memory addressing modes are as follows:

(i) Direct addressing: In this mode, the 16-bit offset address of the data within the
segment is directly given in the instruction.
Example:
(a) MOV AL, [1000H]
In this instruction, the effective address is 1000H. Since the destination is an 8-
bit register (i.e., AL), a byte is taken from the memory at the address given by
DS x 10H + EA (= 31000H) and stored in AL.
(b)MOV BX, [2000H]
EA = 2000H in this instruction. Since the destination is a 16-bit register (i.e., BX),
a word is taken from the memory address DS x 10H + EA (= 32OOOH) and stored
in BX. (Note: Since a word contains two bytes, the bytes present at the memory
addresses 32000H and 32001H are moved to BL and BH, respectively.)
(ii) Base addressing: In this mode, EA is the content of the BX or BP register.
When the BX register is present in the instruction, data is taken from the data
segment and when BP is present, data is taken from the stack segment.
Example:
(a)MOV CL, [BX]
EA = (BX) = 2000H
Memory address = DS x 10 4- (BX) = 32OOOH. The byte from the memory address
32OOOH is read and stored in CL.
(b)MOV DX, [BP]

EA = (BP) = 1OOOH
Memory address = SS x 10 + (BP) = 41000H. The word from the memory address
41000H is read and stored in DX.
(iii) Base relative addressing: In this mode, EA is obtained by adding the content of
the base register with an 8-bit or 16-bit displacement. The displacement is a signed
number with negative values represented in 2’s complement form. The 16-bit
displacement can have values from -32768 to +32767 and the 8-bit displacement
can have values from -128 to +127.
Example:
(a) MOV AX, [BX + 5]
EA = (BX) + 5
Memory address = DS x 10H + (BX) + 5
= 30000H + 2000H + 5 = 32005H
The word from the memory address 32005H is read and stored in AX.
(b)MOV CH,[BX - 100H]
EA = (BX) - 100H
Memory address = DS x 10H + (BX) - 100H
= 30000H + 2000H - 100H = 31F00H
The byte from the memory address 31F00H is read and stored in CH.
(iv) Index addressing: In this mode, EA is the content of the SI or DI register,
which is specified in the instruction. The data is taken from the data segment.
Example:
(a)MOV BL, [SI]
EA = (SI) = 1000H
Memory address = DS x 10H + SI
= 30000H + 1000H = 31000H
A byte from the memory address 31000H is read and stored in BL.
(b)MOV CX, [DI]
EA = (DI) = 3000H
Memory address = DS x 10H + (DI)
= 30000H + 3000H = 33000H
A word from the memory address 33OOOH is read and stored in CX.
(v) Index relative addressing: This mode is the same as the base relative addressing
mode, except that instead of the BP or BX register, the SI or DI register is used.
Example:
(a)MOV BX, [SI - 100H]
EA = (SI) - 100H
Memory address = DS x 10H + (SI) - 100H
= 30000H + 1000H - 100H = 30F00H
A word from the memory address 30F00H is read and stored in BX.
ADDRESSING MODES, INSTRUCTION SET, AND PROGRAMMING OF 8086 435
(b)MOV CL, [DI + 10H]

EA = (DI) + 1OH
Memory address = DS x 1OH + (DI) + 1OH
= 3OOOOH + 3OOOH + 1OH = 33O1OH
A byte from the memory address 3301 OH is read and stored in CL.
(vi) Base plus index addressing: In this mode, EA is obtained by adding the content
of a base register and an index register.
Example:
MOV AX, [BX + SI]
EA = (BX) + (SI)
Memory address = DS x 10H + (BX) + (SI)
= 30000H + 2000H + 1000H = 33000H
A word from the memory address 33OOOH is taken and stored in AX.
Base relative, index relative, and base plus index addressing modes are used to
access a byte or word type data one by one, from a table or an array of data stored
in the data segment.
(vii) Base relative plus index addressing: In this mode, EA is obtained by adding
the content of a base register, an index, and a displacement.
Example:
(a) MOV CX, [BX + SI + BOH]
EA = (BX) + (SI) + 50H
Memory address = DS x 10H + (BX) + (SI) + 50H
= 30000H + 2000H + 1000H + 50H
= 33050H
A word from the memory address 33050H is read and stored in CX.
Base relative plus index addressing is used to access a byte or a word in a particular
record of a specific file in the memory. An application program may process many
files stored in the data segment. Each file contains many records and a record
contains a few bytes or words of data. In base relative plus index addressing, the
base register may be used to hold the offset address of a particular file in the data
segment; the index register may be used to hold the offset address of a particular
record within that file; the relative value is used to indicate the offset address of
particular byte or word within that record.
14.1.4 Program Memory Addressing Modes

Program memory addressing modes are used with the JMP and CALL instructions
and consist of three distinct forms—direct, relative, and indirect.
(i) Direct addressing: Direct program memory addressing stores both the segment
and the offset address where the control has to be transferred with the opcode, as
shown in Fig. 14.1.
This instruction is equivalent to JMP 32000H. When it is executed, the 16-bit
offset value 2000H is loaded in the IP register and the 16-bit segment value 3000H
is loaded in CS. When the microprocessor calculates the memory address from
EAH OOH 20H OOH 30H

(Opcode) (IP—Lower-order byte) (IP—Higher-order byte) (CS—Lower-order byte) (CS—Higher-order byte)
mini11.1. i.ipt::.-'~~xr;Tij:t~r;g-rn; juiwi'IUiiimf™
Fig. 14.1 Format of JMP instruction (direct addressing)
where it has to fetch an instruction using the relation CS x 10H + IP, the address
32000H is obtained using the given CS and IP values.
This type of jump is known as intersegment jump, using which the
microprocessor can jump to any memory location within the memory system (i.e.,
within 1 MB). It is also known as far jump. The inter-segment or FAR CALL
instruction also uses direct program memory addressing. While using the assembler
to develop the 8086 program, the assembler directive FAR PTR is sometimes used
to indicate the inter-segment jump instruction.
Example:
(a) JMP FAR PTR COMPUTE
(b) JMP FAR PTR SIMULATE
In these examples, COMPUTE and SIMULATE are the labels of memory
locations that are present in code segments other than the ones in which these
instructions are present.
(ii) Relative addressing: The term relative here means relative to the instruction
pointer (IP). Relative JMP and CALL instructions contain either an 8-bit or a
16-bit signed displacement, which is added to the current instruction pointer.
Based on the new value of IP thus obtained, the address of the next instruction to
be executed is calculated using the relation CS x 10H + IP.
The 8-bit or 16-bit signed displacement allows a forward or a reverse memory
reference, depending on the sign of the displacement. If the displacement is positive,
PC is incremented by the displacement value and if it is negative, PC is decremented
by the magnitude of the displacement value. A one-byte displacement is used in the
short jump and call instructions, and a two-byte displacement is used in the near
jump and call instructions. Both types are considered intrasegmentjumps, since the
program control is transferred anywhere within the cunent code segment.
An 8-bit displacement has a jump range between +127 and -128 bytes from the
next instruction, while a 16-bit displacement has a jump range between -32,768
and +32,767 bytes from the instruction following the jump instruction in the
program. The opcode of the relative short jump and near jump instructions are
EBH and E9H, respectively.
While using an assembler to develop the 8086 program, the assembler
directives SHORT and NEAR PTR are used to indicate the short jump and near
jump instructions, respectively.
Example:
(a) JMP SHORT OVER
(b) JMP NEAR PTR FIND
In these examples, OVER and FIND are the labels of memory locations that
are present in the same code segment in which these instructions are present.
(iii) Indirect addressing: The indirect jump or CALL instructions use a 16-bit
register (AX, BX, CX, DX, SP, BP, SI, or DI), a relative register ([BP], [BX],
[DI], or [SI]), or a relative register with displacement. The opcode of the indirect
jump instruction is FFH. It can be either an inter-segment indirect jump or an
intra-segment indirect jump.
If a 16-bit register holds the jump address in an indirect JMP instruction, the
operation is a near jump. If the CX register contains 2000H and the JMP CX
instruction present in a code segment is executed, the microprocessor jumps to the
offset address 2000H in the current code segment to take the next instruction for
execution (this is done by loading the IP with the content of CX, without changing
the content of CS).
When the instruction JMP [DI] is executed, the microprocessor first reads a
word in the current data segment from the offset address specified by DI and
places that word in the IP register. Now, with this new value of IP, the 8086
calculates the address of the memory location to which it has to jump, using the
relation CS x 10H + IP.
Example:
Let us assume that the registers DS, DI, and CS have the values 1000H, 2000H,
and 3000H, respectively. When JMP [DI], present at the offset address 1500H
in the code segment 3000H is executed, the microprocessor reads a word from
the address given by DS x 10H + DI (= 12000H) in the memory, and loads
it in the instruction pointer (IP). Let us assume that the word that is stored
in the address 12000H is 4000H. Hence, the program counter will be loaded
with the value 4000H. Now, the microprocessor fetches the next instruction for
execution from the address given by CS x 10H + IP (= 3000H x 10H + 4000H
= 34000H).
14.1.5 Stack Memory Addressing Mode

The stack is used to hold data temporarily during program execution and also store
the return address for procedures and interrupt service routines. The stack memory
is a last-in, first-out (LIFO) memory. Data are placed into the stack using the
PUSH instruction and taken out using the POP instruction. The CALL instruction
uses the stack to hold the return address for procedures and the RET instruction is
used to remove the return address from the stack.
The stack segment is maintained by two registers—the stack pointer (SP) and
the stack segment (SS) register. Data is pushed into or popped from the stack as
words (16-bit data), since bytes (8-bit data) cannot be used with the PUSH and
POP instructions. Whenever a word of data is pushed into the stack, the higher-
order eight bits of the word are placed in the memory location specified by SP - 1
(i.e., at the address SS x 10H + SP - 1) and the lower-order eight bits of the word
are placed in the memory location specified by SP - 2 in the current stack segment
(i.e., at the address SS x 10H + SP - 2). SP is then decremented by 2. The data
pushed into the stack may be the content of a 16-bit register, a segment register, or
a 16-bit data in the memory.
Since SP gets decremented for every push operation, the stack segment is said
to be growing downwards, as for successive push operations, data are stored in the
lower memory addresses in the stack segment. Due to this, SP is initialized with
the highest offset address, according to the user’s requirement, at the beginning of
the program.
Example:
(a) PUSH AX ; Push the content of AX into the stack.
(b)PUSH DS ; Push the content of DS into the stack.
(c) PUSH [BX] ; Push the content of the memory location at
the offset address specified by BX in the
current data segment, into the stack.
The PUSHF instruction is used to push the flag register’s content into the
stack.
Whenever a word is popped from the stack, the lower-order eight bits of the
word are removed from the memory location specified by SP and the higher-order
eight bits of the word are removed from the memory location specified by SP + 1
in the current stack segment. SP is then incremented by two.
Example:
(a) POP BX : Pop the content of BX from the stack.
(b) POP ES ; Pop the content of ES from the stack.
(c) POP [BP] ; Pop the content of the memory 1 ocation at
the offset address specified by BP in the
current stack segment, from the stack.
The POPF instruction is used to pop a word stored in the stack and move it to
the flag register.
14.2 SEGMENT OVERRIDE PREFIX

The segment override prefix, which can be added to almost any instruction in
any memory related addressing mode, allows the programmer to deviate from the
default segment and offset register mechanism. The segment override prefix is
an additional byte that appears in at the beginning of an instruction, to select an
alternative segment register. The JMP and CALL instructions cannot be prefixed
with the segment override prefix, since they use only the code segment (CS)
register for address generation.
Example:
The MOV AX, [BP] instruction accesses data within the stack segment by default,
since BP is the offset register for the stack segment. However, if the programmer
wants to get data from the data segment using BP as the offset register in this
instruction, the instruction should be modified as MOV AX, DS: [BP].
Table 14.2 shows the instructions that address memory segments other than the
default ones.
Table 14.2 Instructions that include the segment override prefix
Instruction Default segment Accessed segment
MOV BX, ES:[BP] SS ES

MOV BX, SS:[DI] DS SS
MOV CX, ES:[BX] DS ES
MOV CX, ES:[SI] DS ES
MOV AX, CS:[BX] DS CS

The instructions of the 8086 are classified as data transfer, arithmetic, logical,
flag manipulation, control transfer, shift/rotate, string, and machine control
instructions.

The data transfer instructions include MOV, PUSH, POP, XCHG, XLAT, IN,
OUT, LEA, LDS, LES, LSS, LAHF, and SAHF. These instructions are discussed
here in detail:
(i) MOV: The MOV instruction copies a word or byte of data from a specified
source to a specified destination. The destination can be a register or a memory
location. The source can be a register, a memory location, or an immediate number.
The general format of the MOV instruction is MOV destination, source.
Example:
(a) MOV BL, 50H ; Move immediate data 50H to BL.
(b)MOV CX, [BX] ; Copy the word from the memory at [BX] to CX.
(c)MOV AX, CX ; Copy the contents of CX to AX.
Note: [BX] indicates the memory location at the offset address specified by BX in
the data segment.
(ii) PUSH: The PUSH instruction is used to store the word in a register or a
memory location into the stack, as explained in the stack addressing mode. SP is
decremented by two after the execution of PUSH.
Example:
(a)PUSH CX : PUSH the content of CX into the stack.
(b)PUSH DS ; PUSH the content of DS into the stack.
(c)PUSH [BX] ; PUSH the word in the memory at [BX] into
the stack.
(iii) POP: The POP instruction copies the top word from the stack to a destination
specified in the instruction. The destination can be a general-purpose register, a
segment register, or a memory location. After the word is copied to the specified
destination, SP is incremented by two.
Example:
(a) POP BX ; Pop the content of BX from the stack.
(b)POP DS : Pop the content of DS from the stack.
(c) POP [SI] : Pop a word from the stack and store it in
the memory at [SI],
Note: [SI] indicates the memory location in the data segment at the offset address
specified by SL
(iv) XCHG: The XCHG instruction exchanges the contents of a register with the
contents of a memory location. It cannot exchange the contents of two memory
locations directly. The source and destination must both be either words or bytes.
The segment registers cannot be used in this instruction.
Example:
(a) XCHG AL, BL : Exchanges the content of AL and BL.
(b)XCHG CX, BX : Exchanges the content of CX and BX.
(c) XCHG AX, [BX] ; Exchanges the content of AXwith the content
of the memory at [BX].
(v) XLAT: The XLAT instruction is used to translate a byte in AL from one code
to another code. The instruction replaces a byte in the AL register with a byte in
the memory at [BX], which is one of the data items present in a look-up table.
Before XLAT is executed, the look-up table containing the desired codes must
be put in the data segment and the offset address of the starting location of the
look-up table is stored in BX. The code byte to be translated is put in AL. When
XLAT is executed now, it adds the content of the AL with BX to find the offset
address of the data in the look-up table. Further, the byte in that offset address will
get copied to AL.
(vi) IN: The IN instruction copies data from a port to the AL or AX register. If an
8-bit port is read, the data is stored in AL and if a 16-bit port is read, the data is
stored in AX. The IN instruction has two formats—fixed port and variable port.
In the fixed port type IN instruction, the 8-bit address of a port is specified
directly in the instruction. With this form, any one of 256 possible ports can be
addressed.
Example:
IN AL, 80H : Input a byte from the port with address 80H to AL.
IN AX, 40H ; Input a word from the port with address 40H to AX.
For the variable port type IN instruction, the port address is loaded into the DX
register before the IN instruction. Since DX is a 16-bit register, the port address
can be any number between 0000H and FFFFH. Hence, we will be able to address
up to 65,536 ports in this mode. The following example shows a part of a program
having the IN instruction. The operations done when the instructions are executed
are given in the corresponding comment fields.
Example:
MOV DX, 0FE50H ; Initialize DX with the port address of FE50H.
IN AL, DX ; Input a byte from the 8-bit port with port

address FE50H into AL.
IN AX, DX ; Input a word from the 16-bit port with port
address FE50H into AX.
The drawback of the fixed port type IN instruction is that the port address
cannot be changed once the program is stored in the ROM. The variable port type
IN instruction has the advantage that the port address can be computed in the
program during execution, and by loading it in DX, the corresponding port can be
accessed using the IN instruction.
(vii) OUT: The OUT instruction transfers a byte from AL or a word from AX
to the specified port. Similar to the IN instruction, the OUT instruction has two
forms—fixed port and variable port.
Examples for fixed port OUT instruction:
(a)OUT 48H, AL ; Sends the content of AL to the port with
address 48H.
(b)OUT OFOH, AX ; Sends the content of AX to the port with
address FOH.
Examples for variable port OUT instruction:

The following example shows a part of a program having the OUT instruction.
MOV DX, 1234H ; Load the port address 1234H in DX.
OUT DX, AL ; Send the content of AL to the port with address
1234H.
OUT DX, AX ; Send the content of AX to the port with address
1234H.
(viii) LEA (load effective address): The general format of the LEA instruction is
LEA register, source. This instruction determines the offset address of the variable
or memory location called the source and puts this offset address in the indicated
16-bit register.
Example:
(a) LEA BX, COST ; Load BX with the offset address of COST in the
data segment, where COST is the name assigned
to a memory location in the data segment.
(b)LEA CX, [BX] [SI] ; Load CX with the value equal to (BX) + (SI),
where (BX) and (SI) represent the content of
BX and SI, respectively.
(ix) LDS: This instruction loads the register and DS with words from the memory.
The general form of this instruction is LDS register, memory address of first
word.
The LDS instruction copies a word from the memory location specified in the
instruction into the register, and then copies a word from the next memory location
into the DS register. LDS is useful in initializing the SI and DS registers at the start
of a string before using one of the string instructions.
Example:
LDS SI, E2000HJ ; Copy the content of the memory at the
offset address 2000H in the data segment to
the lower-order byte of SI, and the content
of 2001H to the higher-order byte of SI. Copy
the content at the offset address 2002H in
the data segment to the lower-order byte of
DS and the content of 2003H to the higher-
order byte of DS.
(x) LES and LSS: The LES and LSS instructions are similar to the LDS instruction,
except that instead of the DS register, the ES and SS registers, respectively, are
loaded, along with the register specified in the instruction.
(xi) LAHF: This instruction copies the lower-order byte of the flag register into
AH.
(xii) SAHF: This instruction stores the content of AH in the lower-order byte of
the flag register.
Except the SAHF and POPF instructions, no other data transfer instruction
affects the flag register.

The arithmetic instructions in the 8086 are used to perform addition, addition
with carry, subtraction, subtraction with borrow, increment, decrement, negation
(changing sign), comparison, multiplication, division, decimal-adjust after
addition, decimal-adjust after subtraction, and processing of ASCII data. Let us
now discuss each instruction in detail.
(i) ADD: The general format of the ADD instruction is ADD destination, source.
The data from the source and destination are added and the result is placed in
the destination. The source may be an immediate number, a register, or a memory
location. The destination can be a register or a memory location. However, the
source and destination cannot both be memory locations. The data from the source
and destination must be of the same type (either bytes or words).
Example:
(a) ADD BL, 80H : Add the immediate data 80H to BL.
(b)ADD CX, 12B0H ; Add the immediate data 12B0H to CX.
(c) ADD AX, CX ; Add the content of AX and CX and store the
result in AX.
(d)ADD AL, [BX] ; Add the content of AL and the byte from the
memory at [BX] and store the result in AL.
(e) ADD CX, [SI] ; Add the content of CX and the word from the
memory at [SI] and store the result in CX.
(f) ADD [BX] , DL ; Add the content of DL with the byte from the
memory at [BX] and store the result in the
memory at [BX].
The flags AF, CF, OF, PF, SF, and ZF are affected by the execution of the
ADD instruction.
(ii) ADC: This instruction adds the data in the source and destination with the
content of the carry flag and stores the result in the destination. The general format
of this instruction is ADC destination, source.
All the rules specified for ADD are applicable to the ADC instruction.
(iii) SUB: The general form of the subtract (SUB) instruction is SUB destination,
source. It subtracts the number in the source from the number in the destination
and stores the result in the destination. Like the ADD instruction, the source may
be an immediate number, a register, or a memory location. The destination can be
a register or a memory location. However, the source and destination cannot both
be memory locations. The data from the source and destination must be of the
same type (either bytes or words).
For subtraction, the carry flag (CF) functions as the borrow flag. If the result is
negative after subtraction, CF is set. Otherwise, it is reset. The flags AF, CF, OF,
PF, SF, and ZF are affected by the SUB instruction.
Example:
(a) SUB AL, BL Subtract BL from AL and store the result i n
AL.
(b)SUB CX, BX ; Subtract BX from CX and store the result i n
CX.
(c) SUB BX, [DI] ; Subtract thei word in the memory at [DI]
from BX and store the result in BX.
(d)SUB [BP] , DL ; Subtract DL from the byte in the memory at
[BP] and store the result in the memory at
[BP],
(iv) SBB: Subtract with borrow—The general form of this instruction is SBB
destination, source. The SBB instruction subtracts the content of the source
and the carry flag from the content of the destination and stores the result in the
destination. The rules for the source and the destination are same as that for the
SUB instruction. AF, CF, OF, PF, SF, and ZF are affected by this instruction.
(v) INC: The increment (INC) instruction adds 1 to the content of a specified
register or a memory location. The data incremented may be a byte or word. While
the carry flag is not affected by this instruction, the flags AF, OF, PF, SF, and ZF
are affected.
Example:
(a)INC CL : Increment the content of CL by 1.
(b)INC AX : Increment the content of AX by 1.
(c) INC BYTE PTR [BX] ; Increment the byte in the memory at [BX] by 1.
(d)INC WORD PTR [SI] ; Increment the word in the memory at [SI] by 1.
In these examples, the terms BYTE PTR and WORD PTR are assembler
directives, which are used to specify the type of data (byte or word) to be
incremented in the memory.
(vi) DEC: The decrement (DEC) instruction subtracts 1 from the content of a specified
register or memory location. The data decremented may be a byte or a word. CF is
not affected, but AF, OF, PF, SF, and ZF flags are affected by this instruction.
(vii) NEG: The negate (NEG) instruction replaces the byte or word in the specified
register or memory location by its 2’s complement (i.e., changes the sign of the
data). The CF, AF, SF, PF, ZF, and OF flags are affected by this instruction.
Example:
(a)NEG AL ; Take 2’s complement of the data in AL and
store it in AL.
(b)NEG CX ; Take 2’s complement of the data in CX and
store it in CX.
(c) NEG BYTE PTR [BX] ; Take 2’s complement of the byte in the memory
at [BX] and store the result in the same
pl ace.
(d)NEG WORD PTR [SI] ; Take 2’s complement of the word in the memory
at [SI] and store the result in the same place.
(viii) CMP: The general form of the compare (CMP) instruction is CMP
destination, source. This instruction compares a byte or word in the source with a
byte or word in the destination and affects only the flags, according to the result.
The content of the source and destination are not affected by the execution of this
instruction. The comparison is done by subtracting the content of the source from
that of the destination. The AF, OF, SF, ZF, PF, and CF flags are affected by the
instruction. The rules for the source and destination are the same as those for the
SUB instruction.
Example:
After the instruction CMP AX, DX is executed, the status of CF, ZF, and SF will
be as follows:
CF ZF SF
IfAX = DX 0 1 0
IfAX>DX 0 0 0
IfAX<DX 1 0 1
(ix) MUL: The multiply (MUL) instruction is used for multiplying two unsigned
bytes or words. The general form of the MUL instruction is MUL source. The
source can be a byte or a word from a register or memory location, which is
considered as the multiplier. The multiplicand is taken by default from AL and AX
for byte and word type data, respectively. The result of multiplication is stored in
AX and DX-AX (i.e., the most significant word of the result in DX and the least
significant word of the result in AX) for byte and word type data, respectively.
(Note: Multiplying two 8-bit data gives a 16-bit result and multiplying two 16-bit
data gives a 32-bit result.)
Example:
(a)MUL CH : Multiply AL and CH and store the result in
AX.
(b)MUL BX ; Multiply AX and BX and store the result in

DX-AX.
(c)MUL BYTE PTR [BX] ; Multiply AL with the byte in the memory at
[BX] and store the result in DX-AX.
If the most significant byte of the 16-bit result is OOH or the most significant
word of a 32-bit result is OOOOH, both CF and OF will be 0. Checking these flags
allows us to decide whether the leading Os in the result have to be discarded or
not. The AF, PF, SF, and ZF flags are undefined (i.e., a random number is stored
in these bits) after the execution of the MUL instruction.
(x) IMUL: The IMUL instruction is used for multiplying the signed byte or word
in a register or memory location with AL or AX, and store the result in AX or
DX-AX, respectively. If the magnitude of the result does not require all the bits of
the destination, the unused bits are filled with copies of the sign bit.
If the upper byte of a 16-bit result or the upper word of a 32-bit result contains
only copies of the sign bit (all Os or all Is), CF and OF will both be 0. Otherwise,
both will be 1. AF, PF, SF, and ZF are undefined after IMUL.
To multiply a signed byte by a signed word, the byte is moved into a word
location and the upper byte of the word is filled with copies of the sign bit. If the
byte is moved into AL, using the CBW (convert byte to word) instruction, the sign
bit in AL is extended into all the bits of AH. Thus, AX contains the 16-bit sign-
extended word.
Example:
(a) IMUL BL : Multiply AL with BL and store the
result in AX.
(b)IMUL AX : Multiply AX and AX and store the
result in DX-AX.
(c) IMUL BYTE PTR [BX] ; Multiply AL with the byte from the
memory at [BX] and store the result in
AX.
(d) IMUL WORD PTR [SI] ; Multiply AX with the word from the
memory at [SI] and store the result in
DX-AX.
(xi) DIV: The divide (DIV) instruction is used for dividing unsigned data. The
general form of the DIV instruction is DIV source, where ‘source’ is the divisor.
It can be a byte or word in a register or memory location. The dividend is taken by
default from AX and DX-AX for byte and word type data division, respectively.
Table 14.3 shows the complete details of the DIV instruction.
Table 14.3 Details of DIV instruction
Dividend (bits) Divisor (bits) Quotient (bits) Remainder (bits)

AX (16) Source (8) AL (8) AH (8)
DX-AX (32) Source (16) AX (16) DX(16)

If an attempt is made to divide by 0 or if the quotient is too large to fit in AL or AX

(i.e., if the result is greater than FFH in 8-bit division or FFFFH in 16-bit division),
the 8086 automatically generates a type 0 interrupt. All flags are undefined after a
DIV instruction.
Example:
(a)DIV DL ; Divide the word in AX by the byte in DL.
The quotient is stored in AL and the remainder
in AH.
(b)DIV CX ; Divide the double word (32 bits) in DX-AX by
the word in CX. The quotient is stored in AX
and the remainder in DX.
(c) DIV BYTE PTR [BX] ; Divide the word in AX by the byte from the
memory at [BX]. The quotient is stored in AL
and the remainder in AH.
(xii) IDIV: The IDIV instruction is used for dividing signed data. The general form
and the rules for the IDIV instruction are same as those for the DIV instruction.
The quotient is a signed number and the sign of the remainder is the same as the
sign of the dividend.
To divide a signed byte by a signed byte, the dividend byte is put in AL and
using the CBW (convert byte to word) instruction, the sign bit of the data in AL
is extended to AH. Thus, the byte in AL is converted to a signed word in AX. To
divide a signed word by a signed word, the dividend byte is put in AX and using
the CWD (convert word to double word) instruction, the sign bit of the data in AX
is extended to DX. Thus, the word in AX is converted to a signed double word in
DX-AX.
If an attempt is made to divide by 0 or if the quotient is too large or too small
to fit in AL and AX for 8- and 16-bit division, respectively (i.e., either the result is
greater than the decimal value +127 in 8-bit division or the decimal value +32,767
in 16-bit division, or the result is less than the decimal value -128 in 8-bit division
or the decimal value -32,767 in 16-bit division), the 8086 automatically generates
a type 0 interrupt. All flags are undefined after a DIV instruction.
(xiii) DAA: Decimal adjust AL after BCD addition—This instruction is used to
get the result of addition of two packed BCD numbers (in a packed BCD number,
two decimal digits are represented as eight bits) as a BCD number. The result of
addition must be in AL for DAA to work correctly. If the lower nibble (four bits)
in AL is greater than 9 after addition or if the AF flag is set by the addition, the
DAA instruction adds 6 to the lower nibble in AL. If the result in the upper nibble
of AL is now greater than 9 or if the carry flag is set by the addition, the DAA
instruction adds 60H to AL.
Example:
(a) Let AL = 01011000 = 58 BCD
CL = 00110101 =35 BCD
Consider the execution of the following instructions:
ADD AL, CL ; AL = 10001101 = 8DH and AF = 0 after execution
DAA : Add 0110 (decimal 6) to AL, since lower nibble in AL

is greater than 9
; AL = 10010011 = 93 BCD and CF = 0
Therefore, the result of addition is 93 BCD.
(b)Let AL = 10001000 = 88 BCD
CL = 01001001 =49 BCD
ADD AL, CL ; AL = 11010001 and AF = 1 after execution
DAA ; Add 0110 (decimal 6) to AL
: AL = 11010111 = D7H
; Upper nibble 1101 > 9. So add 60H (0110 0000) to AL.
; AL = 0011 0111 = 37 BCD and CF = 1
The final result is 137 BCD, taking into account the carry generated. The DAA
instruction affects AF, CF, PF, and ZF. OF is undefined after the DAA instruction
is executed.
(xiv) DAS: Decimal adjust after BCD subtraction—DAS is used to get the result
in packed BCD form after subtracting two packed BCD numbers. The result of
the subtraction must be in AL for DAS to work correctly. If the lower nibble in
AL after a subtraction is greater than 9 or if the AF is set by subtraction, the DAS
instruction subtracts 6 from the lower nibble of AL. If the result in the upper
nibble is now greater than 9 or if the carry flag is set, the DAS instruction subtracts
60H from AL.
Example:
(a) Let AL = 86 BCD = 10000110
CH = 57 BCD = 01010111
SUB AL, CH ; AL = 00101111 = 2FH and CF = 0 after execution
DAS ; Lower nibble of the result is 1111. So DAS subtracts
06H from AL to make AL = 00101001 = 29 BCD and CF =
0 to indicate that there is no borrow.
The result is 29 BCD.
b) Let AL = 49 BCD = 01001001
CH = 72 BCD = 01110010
SUB AL, CH ; AL = 1101 0111 = D7H and CF = 1 since result is
negati ve
DAS ; Subtract 0110 0000 (60H) from AL because upper nibble
in AL is greater than 9. This makes AL = 01110111 =
77 BCD and CF = 1, indicating that a borrow is
needed.
The answer is 77 BCD as 149 BCD - 72 BCD = 77 BCD. The value 149 BCD
is mentioned here, considering the borrow that is generated after the subtraction.
There are four arithmetic instructions that are used to perform operations
on unpacked BCD numbers. In an unpacked BCD number, one decimal digit is
represented as an 8-bit number in which the upper four bits are always zero. For
example, the decimal digit 3 is represented as 03H in unpacked BCD form.
(xv) AAA: The AAA (ASCII adjust after addition) instruction must always follow
the addition of two unpacked BCD operands in AL. When AAA is executed, the
content of AL is changed to a valid unpacked BCD number; the upper four bits of
AL are cleared. CF is set and AH is incremented if a decimal carry-out from AL
is generated.
Example:
Let AL = 05 (decimal) = 00000101
BH = 06 (decimal) = 00000110
AH = OOH
ADD AL, BH ; AL = 11 (decimal) and CF = 0
AAA : AL = 01 and AH = 01 and CF = 1
Addition of 5 and 6 gives a decimal result of 11, which is equal to 0101H in
unpacked BCD form. It is stored in AX. When this result is to be sent to the printer,
the ASCII code of each decimal digit is easily found by adding 30H to each byte.
(xvi) AAS: ASCII adjust after subtraction—This instruction always follows the
subtraction of one unpacked BCD operand from another in AL. It changes the
content of AL to a valid unpacked BCD number and clears the top four bits of AL.
CF is set and AH is decremented if a decimal borrow occurs.
Example:
(a) Let AL = 09 BCD = 00001001
CL = 05 BCD = 00000101
AH = OOH
SUB AL, CL ; AL = 04 BCD
AAS ; AL = 04 BCD and CF = 0
; AH = OOH
(b)Let AL = 05 BCD
CL = 09 BCD
AH = OOH
SUB AL, CL ; AL = -4 BCD (in 2’s complement form AL = FCH) and
CF = 1
AAS ; AL = 04 BCD
: CF = 1 indicating that a borrow is needed and
AH = FFH = 2’s complement of -1
AAA and AAS affect the AF and CF flags and OF, PF, SF, and ZF are left
undefined. Another salient feature of these two instructions is that it is possible
to take input data in the ASCII form of the unpacked decimal number, obtain
the result as an unpacked decimal number, and then convert it to ASCII form by
adding 30H to it.
(xvii) AAD: ASCII-adjust before the division instruction modifies the dividend in
AH and AL, to prepare for the division of two valid unpacked BCD operands. After
the execution of AAD, AH is cleared and AL contains the binary equivalent of the
original unpacked two-digit numbers. Initially, AH contains the most significant
unpacked digit and AL contains the least significant unpacked digit.
Example:
To perform the operation 32 (decimal)/08 (decimal)
Let AH = 03H ; Upper decimal digit in the dividend
AL = 02H ; Lower decimal digit in the dividend
CL = 08H ; Divisor
AAD ; AX = 0020H (binary equivalent of the decimal value
32 in 16-bit form)
DIV CL ; Divide AX by CL. AL contains the quotient and AH the
remainder.
AAD affects the PF, SF, and ZF flags. AF, CF, and OF are undefined after
execution of AAD.
(xviii) AAM: The AAM (ASCII adjust AX after multiplication) instruction corrects
the value obtained by multiplication of two valid unpacked decimal numbers. The
higher-order digit is placed in AH and the lower-order digit in AL.
Example:
Let AL = 05 (decimal)
CL = 09 (decimal)
MUL CH ; AX = 002DH = 45 (decimal)
AAM ; AH = 04 and AL = 05 (unpacked BCD form of the decimal
number 45)
OR AX, 3030H ; To get the ASCII code of the result In AH and AL
(Note: This instruction is used only when the result
is needed in ASCII form.)
AAM affects the same flags as AAD.

The logical instructions in the 8086 include AND, OR, XOR, NOT, and TEST.
Let us now discuss each instruction in detail.
(i) AND: The AND instruction performs a logical AND operation between
the corresponding bits in the source and destination and stores the result in the
destination. The source and the destination can be either bytes or words. The
general form of the AND instruction is AND destination, source.
The rules for the destination and source for the AND instruction are the same
as those for the ADD instruction. CF and OF are both 0, and PF, SF, and ZF are
updated after the AND instruction is executed. AF is undefined. PF is affected
only when the AND operation is performed on an 8-bit operand.
(ii) OR: The OR instruction performs a logical OR operation between

general form of the OR instruction is OR destination, source.
The rules for the source and destination and the way flags are affected are the
same as the AND instruction.
(iii) XOR: The XOR instruction performs a logical XOR operation between
general form of the XOR instruction is XOR destination, source.
The rules for the source and destination and the way flags are affected are the
same as the AND instruction.
(iv) NOT: The NOT instruction inverts each bit (i.e., performs l’s complement)
of the byte or word at a specified destination. The destination can be a register or
a memory location. The NOT instruction does not affect any flags.
Example:
(a) NOT AL : Take l’s complement of AL.
(b)NOT BX ; Take l’s complement of BX.
(c) NOT LSI] ; Take l’s complement of the data in the memory
at LSI].
(v) TEST: This instruction ANDs the content of a source byte or word with the
content of the specified destination byte or word. The flags are updated, but
neither operand is changed. The TEST instruction is often used to set flags before
a conditional jump instruction. The general form of TEST instruction is TEST
destination, source. The rules for the source and destination and the way flags are
affected are the same as the AND instruction.
Example:
Let AL = 0111 1111 =7FH
TEST AL, 80H ; AL = 7FH (unchanged)
ZF = 1 since (AL) AND (80H) = OOH; SF = 0; PF = 1
14.3.4 Flag Manipulation Instructions

The 8086 has a few instructions exclusively for performing operations on the flags
in the flag register. They are used to set or clear specific flags in the flag register,
to push or pop the flag register content into or from the stack, and to transfer the
lower-order byte of the flag register to the AH register and vice versa. Table 14.4
indicates the function of the different flag manipulation instructions in the 8086.
Table 14.4 Flag manipulation instructions
Mnemonics Function
LAHF Load the lower-order byte of the flag register in AH

SAHF Store AH in the lower-order byte of the flag register
(Contd)
Table 14.4 Flag manipulation instructions (Contd)
Mnemonics Function
PUSHF Push the flag register’s content onto the stack
POPF Pop the top word of the stack onto the flag register
CMC Complement the carry flag (CF = complement of CF)
CLC Clear the carry flag (CF = 0)
STC Set the carry flag (CF = 1)
CLD Clear the direction flag (DF = 0)
STD Set the direction flag (DF = 1)
CLI Clear the interrupt flag (IF = 0)
STI Set the interrupt flag (IF = 1)
14.3.5 Control Transfer Instructions

The control transfer instructions of the 8086 are used to call a subroutine, return
from a subroutine, and branch conditionally or unconditionally in a program. In
conditional branching, there are two categories depending on whether unsigned or
signed data is involved. The terms ‘above’ and ‘below’ are used when referring
to the magnitude of unsigned numbers. The binary number 10000000 (= 128 in
decimal form) is above the binary number 01000000 (= 64 in decimal form). The
terms ‘greater’ and ‘lesser’ are used when referring to the relationship between
two signed numbers. ‘Greater’ means more positive. The signed binary number
00001111 (= +15 in decimal form) is greater than the signed binary number
10000001 (= -127 in decimal form). The control transfer instructions of the 8086
are given in Table 14.5.
Table 14.5 Control transfer instructions
Mnemonics Description
Unconditional transfers
JMP addr Jump unconditionally to addr

CALL addr Call the procedure or subroutine starting at addr
RET Return from the procedure or subroutine
Conditional transfers
J A addr Jump if above to addr (jump if CF = ZF = 0)

JAE addr Jump if above or equal to addr (jump if CF = 0)
JB addr Jump if below to addr (jump if CF = 1)
JBE addr Jump if below or equal to addr (jump if CF = 1 or ZF = 1)
JC addr Jump if carry to addr (jump if CF = 1)

JCXZ addr Jump if CX = 0 to addr
JE addr Jump if equal to addr (jump if ZF = 1)

(Contd)
Table 14.5 Control transfer instructions (Contd)
JG addr Jump if greater to addr (Jump if ZF = 0 and SF = OF)

JGE addr Jump if greater or equal to addr (Jump if SF = OF)
JL addr Jump if lesser to addr (Jump if SF OF)
JLE addr Jump if lesser or equal to addr (Jump if ZF = 1 or
SF # OF)
JNA addr Jump if not above to addr (Jump if CF = 1 or ZF = 1)
JNAE addr Jump if not above or equal to addr (Jump if CF = 1)
JNB addr Jump if not below to addr (Jump if CF = 0)
JNBE addr Jump if not below or equal to addr (Jump if CF = ZF = 0)
JNC addr -, z Jjjjnp if no carry to addr (Jump if CF = 0)
JNE addr Jump if not equal to addr (jump if ZF = 0)
JNG addr Jump if not greater to addr (jump if ZF = 1 or SF OF)
JNGE addr Jump if not greater or equal to addr (jump if SF OF)
JNL addr Jump if not lesser to addr (Jump if SF = OF)
JNLE addr Jump if not lesser or equal to addr (Jump if ZF = 0 and
SF = OF)
JNO addr Jump if no overflow to addr (Jump if OF = 0)
JNP addr Jump if no parity to addr (Jump if PF = 0)
JNS addr Jump if no sign to addr (jump if SF = 0)
JNZ addr Jump if no zero to addr (jump if ZF = 0)
JO addr Jump if overflow to addr (jump if OF =1)
JP addr Jump if parity to addr (jump if PF = 1)
JPE addr Jump if parity is even to addr (jump if PF = 1)
JPO addr Jump if parity is odd to addr (jump if PF = 0)
JS addr Jump if sign to addr (jump if SF = 1)
JZ addr Jump if zero to addr (jump if ZF = 1)
In this table, ‘addr’ is the target address in the memory, to which the 8086 has
to jump, if the condition is satisfied while executing conditional jump instructions,
‘addr’ is also the target address to which the 8086 has to jump while executing
unconditional jump instructions. In the CALL instruction, ‘addr’ indicates the
address where the subroutine is located. In the case of conditional jump instructions,
the target address must be located at a relative address, which is in the range of
+127 bytes to -128 bytes from the instruction following the conditional jump
instruction.
Some of the conditional jump instructions have identical effects as follows:

JE—JZ JNE—JNZ JL—JNGE JNL—JGE
JG—JNLE JNG—JLE JB—JNAE JNB—JAE
JA—JNBE JNA—JBE JP—JPE JNP—JPO
There are a few instructions in the 8086 that are used to implement loops.
These are given in Table 14.6.
Table 14.6 Loop instructions
LOOP addr Decrement CX. Go to addr if CX # 0.
LOOPE addr Loop while equal (Decrement CX. Go to addr if CX # 0 and
ZF= 1.)
LOOPZ addr Same as LOOPE
LOOPNE addr Loop while not equal (Decrement CX. Go to addr if CX # 0 and
ZF = 0.)
LOOPNZ addr Same as LOOPNE
In this table, ‘addr’ is the target address, which must be located at a relative
address in the range of+127 bytes to -128 bytes from the instruction following the
LOOP instruction.
The use of the LOOP instruction in a program is explained here with an
example:
MOV CX, 100
AGAIN : MOV AL, BL
LOOP AGAIN ; Decrement CX and if CX * 0, go to AGAIN.

In this example, the loop starting from the address AGAIN is repeated 100
times, since CX is initialized to 100.
Finally, the software interrupt-related instructions (given in Table 14.7) can
also be used to cause the 8086 to jump to another place in the memory and execute
the interrupt service routine for a particular interrupt. The IRET instruction is used
to return the control from the interrupt service routine to the main program.
Table 14.7 Interrupt-related instructions
INT n Software interrupt instruction where n is the interrupt type, n can be

any number between OOH and FFH. This instruction causes the 8086
to execute the interrupt service routine (ISR) of interrupt type n.
INTO This instruction interrupts the 8086 if there is an overflow (i.e.,
OF = 1).
IRET This instruction returns the control from the interrupt service routine to
the main program.
The 8086 interrupts are discussed in detail in Chapter 15.

14.3.6 Shift/Rotate Instructions

The shift/rotate instructions perform logical left-shift and right-shift, and arithmetic
left-shift and right-shift operations. The arithmetic left-shift (SAL) and logical
left-shift (SHL) have the same function, but the former is used on signed data,
whereas the latter is used on unsigned data.
(i) SAL/SHL: The general format of the SAL/SHL instruction is SAL/SHL
destination, count. The destination can be a register or a memory location and a
byte or a word. This instruction shifts each bit in the destination a specified number
of bit positions to the left. As a bit is shifted out of the LSB position, a 0 is placed
in the LSB position. The MSB is shifted into the carry flag (CF) as follows:
CF <------ MSB <-------- LSB <------0
If the number of shifts to be done is 1, it can be directly specified in the
instruction, with a count value equal to 1. For shifts of more than one bit position,
the desired number of shifts is loaded into the CL register and CL is placed in the
count position of the instruction. CF, SF, and ZF are affected according to the
result. PF has meaning only when AL is used as the destination. The SAL and
SHL instructions can be used to multiply a signed number and unsigned number,
respectively, by a power of 2. Shifting a number left by one bit and two bits
multiplies the number by two and four, respectively, and so on.
Example:
(a) SAL AX, 1 ; Shift left the content of AX by one
bit.
(b)SAL BL, 1 ; Shift left the content of BL by one
bi t.
(c)SAL BYTE PTR [SI], 1 ; Shift left the byte content of the
memory at [SI] by one bit.
(d)SAL WORD PTR [BX], 1 ; Shift left the word content of the
memory at [BX] by one bit.
(e)MOV CL, 05
SAL AX, CL : Shift left the content of AX by five
bits.
(f) MOV CL, 03
SAL BYTE PTR [SI], CL ; Shift left the byte content of the
memory at [SI] by three bits.
(ii) SAR: The general format of the SAR instruction is SAR destination, count.
The destination can be a register or a memory location and a byte or a word. This
instruction shifts each bit in the destination a specified number of bit positions to
the right. As a bit is shifted out of the MSB position, a copy of the old MSB is put
in the MSB position (i.e., the sign bit is copied into the MSB). The LSB will be
shifted into the carry flag (CF) as follows:
MSB------► MSB-------- > LSB ----- > CF
The rules for the count value in the instruction are the same as those for the SAL
instruction. CF, SF, and ZF are affected according to the result. PF has meaning
only when AL is used as the destination.
(iii) SHR: The general format of the SHR instruction is SHR destination, count.
The destination can be a register or a memory location and a byte or a word. This
instruction shifts each bit in the destination a specified number of bit positions
to the right. As a bit is shifted out of the MSB position, a 0 is placed in the MSB
position. The LSB is shifted into the carry flag (CF) as follows:
0----- > MSB-------- > LSB ----- > CF
The rules for the count value in the instruction are same as those for the SHL
instruction. CF, SF, and ZF are affected according to the result. PF has meaning
only when an 8-bit destination is used.
(iv) ROR: This instruction rotates all the bits of the specified byte or word by
a specified number of bit positions to the right. The operation done when ROR is
executed is as follows:
CF MSB---------- > LSB
The general format of the ROR instruction is ROR destination, count. The data
bit moved out of the LSB is copied into CF. ROR affects only CF and OF. In the
single-bit rotate operation, if the sign bit (i.e., the MSB) changes after the execution
of ROR, OF is set. This is applicable only for the single-bit rotate operation. ROR
is used to swap nibbles in a byte and to swap bytes in a word. It can also be used
to rotate a bit in a byte/word into CF, where it can be checked and acted upon by
the JC and JNC instructions. CF contains the bit most recently rotated out of the
LSB, in the case of a multiple bit rotate operation. The rules for the count value
are same as those for the shift instruction.
Example:
(a) ROR CH, 1 ; Rotate right the byte in CH by one bit
posi ti on.
(b)ROR BX, CL ; Rotate right the word in BX by the
number of bit positions given by CL.
(c) ROR BYTE PTR [SI], 1 ; Rotate right the byte in the memory at
offset [SI] by one bit position.
(d) ROR WORD PTR [BX], CL ; Rotate right the word in the memory at
offset [BX] by the number of bit
positions given by CL.
(v) ROL: ROL rotates all the bits in a byte or word in the destination to the left, by
one or more bit positions, using CL, as follows:
CF<------MSB <--------- LSB

I t
The data bit moved out of the MSB is copied into CF. ROL affects only CF
and OF. In the single-bit rotate operation, if the sign bit (i.e., the MSB) changes
after the execution of ROL, OF is set. This is applicable only for the single-bit
rotate operation. ROL is used to swap nibbles in a byte or swap bytes in a word.
It can also be used to rotate a bit in a byte/word into CF, where it can be checked
and acted upon by the JC and JNC instructions. CF contains the bit most recently
rotated out of the LSB, in the case of the multiple bit rotate operation.
(vi) RCR: RCR rotates the byte or word in the destination right, through the carry
flag (CF), either by one bit position or by the number of bit positions given by CL,
as follows:
CF----- > MSB * LSB
The flags affected are the same as those affected during the execution of
ROR.
(vii) RCL: RCL rotates the byte or word in the destination left through the carry
flag (CF), either by one bit position or by the number of bit positions given by CL,
as follows:
CF <----- MSB <--------- LSB

I____________ f
The flags affected are the same as those affected during the execution of
ROL.
14.3.7 String Instructions

The 8086 string manipulation instructions are given in Table 14.8. The string
instructions operate on elements of strings, bytes, or words. The register SI
contains the offset address of an element (byte or word) in the source string,
which is present in the data segment. The register DI contains the offset address
of an element (byte or word) in the destination string, which is present in the extra
segment. The source string is in the data segment at the offset address given by
SI; the destination string is in the extra segment at the offset address given by
DI. After each string operation, SI and/or DI are automatically incremented or
decremented by 1 or 2 (for byte or word operation), according to the D flag in the
flag register. If D = 0, SI and/or DI are automatically incremented and if D = 1, SI
and/or DI are automatically decremented.
Table 14.8 String instructions in the 8086
Mnemonics Function
MOVSB Move the string byte from DS:[SI] to ES:[DI].

MOVSW Move the string word from DS:[SI] to ES:[DI].
CMPSB Compare string bytes (done by subtracting the byte at ES: [DI]
from the byte at DS: [SI]). Only flags are affected; the content
of the bytes compared is unaffected.
(Contd)
Table 14.8 String instructions in the 8086 (Contd)
Mnemonics Function
CMPSW Compare string words (done by subtracting the word at
ES: [DI] from the word at DS: [SI]). Only flags are affected;
the content of the words compared is unaffected.
LODSB Load the string byte at DS:[SI] into AL.
LODSW Load the string word at DS:[SI] into AX.
STOSB Store the string byte in AL at ES:[DI].
STOSW Store the string word in AX at ES:[DI],
SCASB Compare string bytes (done by subtracting the byte at ES: [DI]
from the byte at AL). Only flags are affected; the content of the
bytes compared is unaffected.
SCASW Compare string words (done by subtracting the word at ES:
[DI] from the byte at AX). Only flags are affected; the content
of the words compared is unaffected.
REP Decrement CX and repeat the following string operation if
CX # 0.
REPE or REPZ Decrement CX and repeat the following string operation if
CX # 0andZF= I.
REPNE or REPNZ Decrement CX and repeat the following string operation if
CX 0 and ZF = 0.
The REP (repeat) prefix placed before a string instruction causes the string
instruction to be executed CX times.
Example:
(a)MOV CX, 32H ; Load 32H (= decimal 50) in CX.
(b)REP MOVSW ; Execute MOVSW instruction 50 times.
Execution of these two instructions causes the moving of a string having 50
words from the data segment to the extra segment.
14.3.8 Machine or Processor Control Instructions

The machine/processor control instructions in the 8086 include HLT, LOCK,
NOP, ESC, and WAIT. Let us discuss each instruction in detail.
(i) HLT: The halt instruction stops the execution of all instructions and places
the processor in the halt state. An interrupt or a Reset signal causes the
processor to resume execution from the halt state.
(ii) LOCK: The lock instruction provides the processor an exclusive hold on
the use of the system bus. It activates an external locking signal (LOCK)
of the processor and is placed as a prefix to the instruction for which a
lock is to be asserted. The lock functions only with the XCHG, ADD, OR,
ADC, SBB, AND, SUB, XOR, NOT, NEG, INC, and DEC instructions,
when they involve a memory operand. An undefined opcode trap interrupt

is generated, if a LOCK prefix is used with any instruction not listed here.
(iii) NOP: No operation—This instruction is used to insert a delay in software
delay programs.
(iv) ESC: This instruction is used to pass instructions to a coprocessor such as
the 8087, which shares the address and data bus with an 8086. Instructions
for the coprocessor are represented by a 6-bit code embedded in the escape
instruction.
As the 8086 fetches instruction bytes from the memory, the coprocessor
catches these bytes from the data bus and puts them in a queue. However,
the coprocessor treats all the normal 8086 instructions as NOP instructions.
When the 8086 fetches an ESC instruction, the coprocessor decodes the
instruction and carries out the action specified by the 6-bit code specified in
the instruction.
(v) WAIT: When this instruction is executed, the 8086 checks the status of its
TEST input pin and if the TEST input is high, it enters an idle condition
during which it does not do any processing. The 8086 remains in this
state until the 8086’s TEST input pin is made low or an interrupt signal
is received on the INTR or NMI pins. If a valid interrupt occurs while
the 8086 is in this idle state, it returns to the idle state after the interrupt
service routine is executed. The WAIT instruction does not affect flags. It
is used to synchronize the 8086 with external hardware such as the 8087
coprocessor.
14.4 8086 ASSEMBLY LANGUAGE PROGRAMMING

A few assembly language programming examples, similar to the assembly
language programming of the 8085, are given in this section. These programs
can be converted into machine language programs and executed in an 8086-based
system, either by manually finding the opcode for each instruction or by using an
assembler. As finding the opcode of each instruction of the 8086 manually is time
consuming, the line assembler or assembler is normally used. The line assembler
converts each mnemonic of an instruction immediately into an opcode as it is
entered in the system and this type of assembler is used in microprocessor trainer
kits. The line assembler is stored in any one of the ROM type memories in the
trainer kit. The assembler needs a personal computer for generating the opcodes
of an assembly language program. The generated opcodes can be downloaded
to the microprocessor-based system such as the microprocessor trainer kit or the
microprocessor-based prototype hardware through the serial or parallel port of the
computer.
There are many assemblers such as MASM (Microsoft Macro Assembler),
TASM (Turbo Assembler), and DOS Assembler, which are used to convert the
8086 assembly language program into machine language program. While using
these assemblers, the assembly language program is written using assembler
directives. Assembler directives are commands to the assembler to indicate the
size of a variable (either byte or word), number of bytes or words to be reserved in

the memory, value of a constant, name of a segment, etc., in a program. Assembler
directives are not converted directly into opcode, but are used to generate the
proper opcode of an instruction. The use of Microsoft’s assembler is discussed in
this section.
14.4.1 Writing 8086 Programs using Line Assembler

While writing 8086 programs using the line assembler, assembler directives are
not used. The segment address and offset address of the data are directly mentioned
in the instructions. The following examples illustrate this concept.
Example 14.1:
Write a program to add a word type data located at the offset address 0800H (least
significant byte) and 0801H (most significant byte) in the segment address 3000H
to another word type data located at the offset address 0700H (least significant
byte) and 0701H (most significant byte) in the same segment. Store the result at the
offset address 0900H and 0901H in the same segment. Store the carry generated in
the addition in the same segment at the offset address 0902H.
Solution:
MOV AX, 3000H
MOV OS, AX ; Initialize DS with the value 3000H.
MOV AX, [800H] ; Move the first data word to AX.
ADD AX, T700H] ; Add AX with the second data word.
MOV E900HJ, AX ; Store AX at the offset addresses
900H and 901H.
JC CARRY ; If carry = 1, jump to CARRY.
MOV E902H] , OOH ; If there is no carry, store OOH at
the offset address 902H.
JMP END; Jump to END.
CARRY: MOV [902H], 01H ; Store 01H at the offset address 902H
END: HLT ; Stop.
Note:
(i) To initialize a segment register with a value, the value is first loaded in one of
the general-purpose registers such as AX or BX. It is then moved to the segment
register. In this example, AX is used to load 3000H into DS.
(ii) Sometimes, instead of using the HLT instruction at the end, the software
interrupt instruction (INT) may be used to return the control to the monitor program
after executing the program.
Example 14.2:
Write a program to subtract the byte content of the memory location 3000H: 4000H
from the byte content of the memory location 4000H: 5000H and store the result at
the location 2000H: 3000H. Assume that the input data and the result lie between
-128 and +127, and that the negative numbers are represented in 2’s complement
form. (Note: 3000H: 4000H represents the segment address of 3000H and the
offset address 4000H in that segment).
Solution:
MOV BX, 3000H
MOV DS, BX ; Initialize DS with the segment address
3000H.
MOV CL, [4000H] ; Get the subtrahend from the offset address
4000H.
MOV BX, 4000H
4000H.
MOV AL, L5000H] ; Get the minuend at the offset address 5000H
to AL.
SUB AL, CL : AL <- AL - CL
MOV BX, 2000H
2000H.
MOV [3000H], AL ; Store AL at the offset address 3000H.
HLT : Stop.
Note: After the execution of the program, if the result is positive, its MSB and
carry are 0. If the result is negative, it is represented in 2’s complement form; its
MSB and carry are 1.
Example 14.3:
Write a program to move a word string 200 bytes (i.e., 100 words) long from the
offset address 1000H to the offset address 3000H in the segment 5000H.
Solution:
Using the REP prefix with the MOVSW instruction, the program size can be
reduced in comparison with a program that uses the MOV instruction for the same
task.
MOV AX, 5000H
MOV DS, AX ; Initialize DS with the segment address 5000H.
MOV ES, AX ; Initialize ES with the segment address 5000H.
MOV SI, 1000H ; Initialize SI with the offset address of the
source (i.e., 1000H).
MOV DI, 3000H ; Initialize DI with the offset address of the
destination (i.e., 3000H).
MOV CX, 100 ; Initialize CX with the numberof words in the string
(decimal value of 100 or 64H).
CLD ; Clear the D flag for auto-increment mode.
REP MOVSW ; Execute MOVSW instruction CX times.
HLT : Stop.
Note:
(i) The MOVSB instruction can be used in this program instead of MOVSW, but
CX must be loaded with the value 200.
(ii) As D is 0, every time MOVSW is executed, the SI and DI registers are
incremented by 2, to point the next word in the string.
Example 14.4:
Write a program to find the smallest word in an array of 100 words stored
sequentially in the memory, starting at the offset address 1000H in the segment
address 5000H. Store the result at the offset address 2000H in the same segment.
Solution:
MOV CX, 99 ; Initialize CX with the number of
comparisons (= 100 - 1).
MOV AX, 5000H
MOV OS, AX : Initialize DS with the segment address
5000H.
MOV SI, 1000H ; Initialize SI with the offset address
1000H.
MOV AX, [SI] : Move the first word to AX.
START: INC SI
INC SI : Increment SI twice to point the next
word.
CMP AX, [SI] ; Compare the next word with the word in AX.
JC REPEAT ; If AX is smaller, jump to REPEAT.
MOV AX, [SI] ; Replace the word in AX with the smaller
word.
REPEAT: LOOP START ; Repeat the operation from START.
MOV [2000H], AX : Store the smallest number in AX at the
offset address 2000H.
HLT ; Stop.
Examples 14.5:
Write a program to find the number of positive and negative data items in an array
of 100 bytes of data stored from the memory location 3000H: 4000H. Store the
result in the offset addresses 1000H and 1001H in the same segment. Assume that
the negative numbers are represented in 2’s complement form.
(Note: The basic principle used here is that the MSB for a positive number is 0 and
that for a negative number is 1.)
Solution:
MOV AX, 3000H
MOV DS, AX ; Initialize DS with 3000H.
MOV CX, 100 ; Move the number of data items to CX.
MOV BX, 4000H ; Move the starting offset address of the
array to BX.
MOV DH, OOH ; Initialize DH with OOH to store the number of
positive data items.
MOV DL, OOH ; Initialize DL with OOH to store the number of
negative data items.
L2: MOV AL, [BX] ; Move a byte data from the array to AL.
ROL AL, 01 ; Rotate AL left by one bit. Now the MSB in AL
goes to the carry flag and also to the LSB of
AL.
JC NEG : If the carry f1 a9 is 1, the data is negative.

So jump to NEG.
INC DH ; If the carry flag is 0, the data is positive.
So increment DH.
JMP LI ; Jump to LI.
NEG: INC DL ; Increment DL.
LI: INC BX ; Increment BX to point to the next data.
LOOP L2 ; Repeat the process from L2 to check all the
data items in the array.
MOV [1000H], DH ; Store the content of DH (the number of positive
data items) at the offset address 1000H.
MOV [1001H] , DL : Store the content of DL (the number of negative
data items) at the offset address 1001H.
HLT ; Stop.
Example 14.6:
Write a program to find the seven-segment code of a digit between 0 and 9 or a
character between A and F. Assume that the seven-segment code of the characters
is stored in the memory starting at the address 2000H: 1000H. The result must be
stored at the offset address 2000H in the same segment.
Solution:
MOV AX, 2000H
MOV DS, AX ; Initialize DS with the value 2000H.
MOV BX, 1000H : Initialize BX with the starting offset address
of the table containing the seven - segment
codes.
MOV AL, 03 ; Load the number (here ‘3’) whose seven - segment
code is to be found in AL.
XLAT ; Using XLAT instruction, move the seven
segment code of 03 to AL.
MOV [2000H], AL ; Store the result at the offset address
2000H.
HLT ; Stop.
Memory Address
Seven-segment code of 0 2000H: 1OOOH
Seven-segment code of 1 2000H: 1001H
Seven-segment code of 2 2000H: 1002H
Seven-segment code of F 2000H: 100FH

Note: When the XLAT instruction is executed in this example, the content of BX
(= 1000H) is added to the content of AL (= 03H) to form an offset address (=
1003H) and the data in that offset address (seven-segment code of 03H) is moved
to AL. This technique is called look-up table technique.
Example 14.7:
Write a program to convert the 8-bit packed BCD number stored in the memory
location 3000H : 2000H into a binary number and store it in the offset address
2001H in the same segment.
Solution:
MOV AX, 3000H
MOV DS, AX ; Initialize DS with 3000H.
MOV AL, E2000HJ ; Move the 8-bit BCD number to AL.
MOV BL, AL ; Store a copy of the BCD number in BL.
AND AL, OFOH ; Mask the lower-order nibble in AL.
MOV CL, 04
ROR AL, CL ; Rotate AL right four times, to get the upper
nibble of the BCD number.
MOV BH, OAH ; Move OAH to BH.
MUL BH ; Multiply AL and BH, and store the result in
AL.
AND BL, OFH ; Mask the upper nibble in BL.
ADD AL, BL ; Add the contents of AL and BL.
MOV [2001H], AL ; Store the result in AL at the offset address
2001H.
HLT ; Stop.
Note:
(i) When the most significant digit of a hexadecimal data is any one of the digits
between A and F, it is preceded by 0, while writing in the program.
(ii) The binary number corresponding to an 8-bit packed BCD number is obtained
by multiplying the decimal value 10 (= OAH) with the upper digit of the BCD
number and adding the result with the lower digit of the BCD number. Since the
maximum 8-bit BCD number is 99 and the corresponding binary number is 63H
(= 9 x OAH + 9), the result in this program is also 8 bits. The result in AH is ignored
in the MUL BH instruction in this program, as AH = OOH after multiplication.
Example 14.8:
Write a program to convert the given 8-bit binary number into ASCII codes. The 8-
bit binary number is present in the memory location 2000H: 5000H and the result
is to be stored at the offset addresses 1000H and 1001H in the same segment.
Solution:
MOV AX, 2000H
MOV DS, AX : Initialize DS with 2000H.
MOV AL, [5000H] ; Move the binary data to AL.
MOV BL, AL ; Save a ropy of AL in BL.
ANL AL, OFOH Mask the lower nibble in AL.

MOV CL, 04
ROR AL, CL Rotate AL right four times, to get the upper
nibble.
CALL ASCII Call the subroutine ASCII.
MOV E1000H], AL Store the result in AL in the memory.
MOV AL, BL Move the binary data again to AL.
ANL AL, OFH Mask the upper nibble in AL.
CALL ASCII Call the subroutine ASCII.
MOV E1001H], AL Store the result in AL in the memory.
JMP LI Jump to LI.
ASCII: CMP AL, OAH Compare AL with the value OAH.
JC L2 If AL is lesser than OAH, go to L2.
ADD AL, 07H Add 07H witb'AL.
L2: ADD AL, 30H Add 30H with AL.
RET Return to the main program.
LI: HLT Stop.
Note: The ASCII code of the 8-bit binary number, say F8H, is obtained by first
splitting the binary number into two digits, F and 8, and then finding the ASCII
codes of F and 8 separately. The ASCII code of a digit between 0 and 9 is obtained
by adding 30H to the digit and the ASCII code of a digit between A and F is
obtained by adding 37H to the digit. The ASCII codes of F and 8 are 46H and
38H, respectively.
Example 14.9:
Write a program to add the two BCD data 29H and 98H and store the result in
BCD form in the memory locations 2000H: 3000H and 2000H: 3001H.
Solution:
MOV AL, 29H ; Move the first BCD data to AL.
ADD AL, 98H ; Add the second BCD data with AL.
DAA ; Decimal-adjust AL to get the result in
BCD form.
MOV BX, 2000H
MOV DS, BX ; Initialize DS with 2000H.
MOV E3000H], AL; Store the content of AL, which is the lower
byte of the result in the memory.
JC LI ; If the carry flag is 1, go to LI.
MOV E3001HJ, OOH ; Store OOH in the memory, since the carry is
0.
JMP L2 ; Go to L2.
LI: MOV E3001H], 01H Store 01H in memory, since the carry is 1.
L2: HLT ; Stop.
Example 14.10:
Write a program to convert the 8-bit binary number FFH into a BCD number. The
result is to be stored at memory locations 3000H: 2000H and 3000H: 2OO1H.
Solution:
MOV AX, OOFFH : Move the data FFH to AX, with the upper byte
as OOH.
MOV BL, 100 ; Store the decimal value 100 (or 64H) in BL.
DIV BL ; Divide AX by BL to find the number of hundreds
in the binary number.
MOV DL, AL ; Move the quotient in AL (number of hundreds)
to DL.
MOV AL, AH ; Move the remainder in AH to AL.
MOV AH, 00 ; Clear AH.
MOV BL, 10 ; Store the decimal value 10 (or OAH) in BL.
DIV BL ; Divide AX by BL to find the number of tens in
the binary number. AH has the remainder, which
is the number of ones in the binary number.
MOV CL, 04
ROR AL, CL ; Rotate content of AL right by 4 bits to
place number of tens in upper nibble of AL.
OR AL, AH ; Perform OR operation on AL and AH to
concatenate the number of tens and ones.
MOV BX, 3000H
MOV DS, BX : Initialize DS with 3000H.
MOV L2000H], DL ; Move the value of DL to the memory.
MOV E2001H], AL : Move the value of AL to the memory.
HLT ; Stop.
Note: The binary number FFH when converted to BCD gives the result 255, as
there are two hundreds, five tens, and five ones in it. In this program, 02H is stored
in the offset address 2000H and 55H is stored in the offset address 2001H in the
data segment.
14.4.2 8086 Assembler Directives

An assembler is a program that is used to convert an assembly language program
into an equivalent machine language program. The assembler finds the address of
each label and substitutes the value of each constant and variable in the assembly
language program during the assembly process, to generate the machine language
code. While performing these operations, the assembler may find syntax errors.
They are reported to the programmer at the end of the assembly process. The
logical and other programming errors are not found by the assembler.
For completing these tasks, an assembler needs some commands from the
programmer—the required storage class for a particular constant or a variable
such as byte, word, or double word, the logical name of the segments such as
CODE, STACK, or DATA, the type of procedures or routines such as FAR,
NEAR, PUBLIC, or EXTRN, the end of a segment, etc. These types of commands
are given to the assembler using predefined alphabetical strings called assembler
directives, which help the assembler to correctly generate the machine codes for
the assembly language program.
In addition, there are a few operators that perform the addition or subtraction
operation on constants or labels. The assembler directives commonly used in
Microsoft Macro Assembler or Turbo Assembler are as follows:
Assembler Directives for Variable and Constant Definition
The assember directives for variable and constant definition are as follows:
(i) DB, DW, DD, DQ, and DT: The directives DB (define byte), DW (define word),
DD (define double word), DQ (define quad word), and DT (define ten bytes) are
used to reserve one byte, one word (i.e., 2 bytes), one double word (i.e., 2 words),
one quad word (i.e., 4 words), and ten bytes in the memory, respectively, for
storing constants, variables, or strings.
Example:
(a) DATA1 DB 20H ; Reserve one byte for storing
DATA1 and assign the value 20H
to it.
(b) ARRAY1 DB 10H, 20H, 30H ; Reserve three bytes for storing
ARRAY1 and initialize it with
the values 10H, 20H, and 30H.
(c) CITY DB “MADURAI” ; Store the ASCII code of the
characters specified within
double quotes in the array or
list named CITY.
(d) DATA2 DW 1020H ; Reserve one word for storing
DATA2 and assign the value
1020H to it.
(e) ARRAY2 DW 1030H, 2000H,
3000H, 4000H : Reserve four words for storing
ARRAY2 and initialize them with
the specified values.
(f) DATA3 DD 1234ABCDH ; Initialize DATA3 as a double
word with 123ABCDH.
(g) DATA4 DQ 1234ABCD5678EFBBH ; Initialize DATA4 as a quad word
with 1234ABCD5678EFBBH.
(h) DATA5 DT 123456789ABCDEFl2345H; Initialize DATA5 as a series
of 10 bytes having the value
123456789ABCDE Fl2345H.
The directive DUP (duplicate) is used to reserve a series of bytes, words,
double words, or ten bytes and is used with DB, DW, DD, and DT, respectively.
The reserved area can be either filled with a specific value or left uninitialized.
Example:
(a) Array DB 20 DUP (0) ; Reserves 20 .bytes in the memory
for the array named ARRAY and
initializes all the elements
of the array to 0 (due to the
presence of 0 within the bracket
near the DUP directive).
(b) ARRAY1 DB 25 DUP (?) ; Reserves 25 bytes in the memory

for the array named ARRAY1 and
keeps all the elements of array
uninitialized (due to the
question mark present within
the bracket near the DUP
di recti ve).
(c) ARRAY2 DB 50 DUP (64H) ; Reserves 50 bytes in the memory
for the array named ARRAY2 and
initializes all the elements
of the array to 64H.
(ii) EQU: The directive EQU (equivalent) is used to assign a value to a data
name.
Example:
(a) NUMBER EQU 50H ; Assign the value 50H to NUMBER.
(b) NAME EQU “RAMESH” ; Assign the string “RAMESH” to NAME.
Assembler Directives Related to Code (program) Location

The assember directives related to code location are as follows:
(i) ORG: The ORG (origin) directive directs the assembler to start the memory
allocation for a particular segment (data, code, or stack) from the declared address
in the ORG statement. While starting the assembly process for a memory segment,
the assembler initializes a location counter (LC) to keep track of the allotted
offset addresses for the segment. When the ORG directive is not mentioned at the
beginning of the segment, LC is initialized with the offset address OOOOH. When
the ORG directive is mentioned at the beginning of the segment, LC is initialized
with the offset address specified in the ORG directive.
Example:
ORG 100H
When this directive is placed at the beginning of the code segment, the location
counter is initialized with 01 OOH and the first instruction is stored from the offset
address 01 OOH within the code segment. If it is placed in the data segment, the
next data storage starts from the offset address 01 OOH within the data segment.
(ii) EVEN: The EVEN directive updates the location counter to the next even
address, if the current location counter content is not an even number.
Example:
EVEN
ARRAY2 DW 20 DUP (0)
These statements in a segment declare an array named ARRAY2 having 20
words, starting at an even address. The advantage of storing an array of words
starting at an even address is that the 8086 takes just one memory read/write cycle
to read/write the entire word, if the word is stored starting at an even address.
Otherwise, the 8086 takes two memory read/write cycles to read/write the word.
Example:
The EVEN directive can also be used at the beginning of a procedure, so that the
instructions in it can be fetched quickly by the 8086 during execution.
EVEN
RESULT PROC NEAR
; instructions in the RESULT procedure
RESULT ENDP
Here the procedure RESULT, which is of type NEAR, is stored starting at an
even address in the code segment. The ENDP directive indicates the end of the
RESULT procedure.
(iii) LENGTH: This directive is used to determine the length of an array or string
in bytes.
Example:
MOV CX, LENGTH ARRAY
CX is loaded with the number of bytes in the ARRAY.
(iv) OFFSET: This operator is used to determine the offset of a data item in a
segment containing it.
Example:
MOV BX, OFFSET TABLE
If the data item named TABLE is present in the data segment, this statement places
the offset address of TABLE, in the BX register.
(v) LABEL: The LABEL directive is used to assign a name to the current value
in the location counter. It is used to specify the destination of the branch-related
instructions such as jump and call. When LABEL is used to specify the destination,
it is necessary to specify whether it is NEAR or FAR. When the destination is in
the same segment, the label is specified as NEAR and when the destination is in
another segment, it is specified as FAR.
Example:
REPEAT LABEL NEAR
CALCULATE LABEL FAR
LABEL can also be used to specify a data item. When it is used to specify a
data item, the type of the data item must be specified. The data may have the type
—byte or word.
Example:
A stack segment having 100 words of data is defined using the following
statements:
STACK SEGMENT
DW 100 DUP (0)
STACK_T0P LABEL WORD ; reserve 100 words for stack
STACK ENDS
The second statement reserves 100 words in the stack segment and fills them
with 0. The third statement assigns the name STACK_TOP to the location present
just after the hundredth word. The offset address of this label can then be assigned
to the stack pointer in the code segment using the following statement:
MOV SP, OFFSET STACK_TOP
Assembler Directives for Segment Declaration
The assember directives for segment declaration are as follows:
(i) SEGMENT and ENDS: The SEGMENT and ENDS directives indicate the start
and end of a segment, respectively. In some cases, the segment may be assigned a
type such as PUBLIC (i.e., it can be used by other modules of the program while
linking) or GLOBAL (i.e., it can be accessed by any other module).
Large assembly language programs are usually developed as separate assembly
modules. Each assembly module is individually assembled, tested, and debugged.
When all the assembly modules are working correctly, their object code files are
linked together to form the complete program. For the modules to link together
correctly, any segment, label, or variable name referred to in other modules must be
declared PUBLIC in the module in which it is defined. For example, the statement
DATA1 SEGMENT WORD PUBLIC makes the segment named DATA1
available to other assembly modules. Here, the term WORD is used to inform
the linker to locate the segment in the first available even address. Similarly, the
statement PUBLIC XI, X2 makes the two variables XI and X2 available to other
assembly modules. If an instruction in an assembly module refers to a variable or
label which is present in another assembly module, the assembler must be told that
it is external, using the EXTRN directive.
The GLOBAL directive can be used in place of the PUBLIC or EXTRN
directive. For a symbol or name defined in the current assembly module, the
GLOBAL directive is used to make that symbol or name available to other
assembly modules. For example, the statement GLOBAL MULTIPLIER makes
the variable MULTIPLIER public so that it can be accessed from other assembly
modules. The statement GLOBAL MULTIPLIER: WORD informs the assembler
that MULTIPLIER is a variable of type ‘word’, which is in another assembly
module.
Example:
CODEI SEGMENT
; instructions of CODE 1 segment
CODEI ENDS
This example indicates the declaration of a code segment named CODEI.
(ii) ASSUME: The ASSUME directive is used to inform the assembler, the name of
the logical segments to be assumed for different segments used in the program.
Example:
ASSUME CS: CODEI , DS: DATA1
This statement informs the assembler that the segment address where the logical
segments CODEI and DATA1 are loaded in memory during execution is to be
stored in the CS and DS registers, respectively.
(iii) GROUP: This directive is used to form a logical group of segments with a
similar purpose. The assembler passes information to the linker/loader to form
the code, such that the group declared segments or operands lie within a 64 KB
memory segment. All such segments can be addressed using the same segment
address.
Example:
PROGRAMI GROUP CODEI. DATA1, STACK1
This statement directs the loader/linker to prepare an executable (EXE) file such
that the CODEI, DATA1, and STACK 1 segments lie within a 64 KB memory
segment that is named PROGRAM 1. Now, for the ASSUME statement, we can use
the label PROGRAMI rather than CODEI, DATA1, and STACK1, as follows:
ASSUME CS: PROGRAMI, DS: PROGRAMI, SS: PROGRAMI
(iv) SEG: The segment operator is used to decide the segment address of the label,
variable, or procedure and substitute the segment address in place of the SEG
label.
Example:
MOV AX, SEG ARRAY1 ; Load the segment address in which ARRAY1 is
present, in AX.
MOV DS, AX ; Move the content of AX to DS.
Assembler Directives for Declaring Procedures
The assember directives for declaring procedures are as follows:
(i) PROC: The PROC directive indicates the start of a named procedure. The
NEAR and FAR directives specify the type of the procedure.
Example:
SQUARE_R00T PROC NEAR
This statement indicates the beginning of a procedure named SQUARE_ROOT,
which is to be called by a program located in the same segment. The FAR directive
is used for the procedures to be called by the programs present in code segments
other than the one in which this procedure is present. For example, SALARY
PROC FAR indicates the beginning of a FAR type procedure named SALARY.
(ii) ENDP: The ENDP directive is used to indicate the end of a procedure. To
mark the end of a particular procedure, the name of the procedure may appear as
a prefix with the directive ENDP.
Example:
SALARY PROC NEAR
: code of SALARY procedure
SALARY ENDP
(iii) EXTRN and PUBLIC: The directive EXTRN (external) informs the assembler
that the procedures, label/labels, and names declared after this directive has/have
already been defined in some other segments and in the segments where they
actually appear, they must be declared public, using the PUBLIC directive.
Example:
M0DULE1 SEGMENT
PUBLIC SQUARE-ROOT
SQUARE-ROOT PROC FAR
; code of SQUARE-ROOT procedure
SQUARE-ROOT ENDP
M0DULE1 ENDS
M0DULE2 SEGMENT
EXTRN SQUARE-ROOT FAR
; code of M0DULE2
CALL SQUARE-ROOT
M0DULE2 ENDS
If one wants to call the procedure named SQUARE_ROOT appearing in
MODULE 1 from MODULE2, it must be declared public using the statement
PUBLIC SQUARE-ROOT in MODULE1 and it must be declared external using
the statement EXTRN SQUARE-ROOT in MODULE2. If a jump or call address
is external, it must be represented as NEAR or FAR. If data are defined as external,
their size must be represented as BYTE, WORD, or DWORD.
Other Assembler Directives
(i) PTR: The PTR (pointer) operator is used to declare the type of a label, variable,
or memory operand. The operator PTR is prefixed by either BYTE or WORD. If
the prefix is BYTE, the particular label, variable, or memory operand is treated as
an 8-bit quantity, while if the prefix is WORD, it is treated as a 16-bit quantity.
Example:
(a) INC BYTE PTR LSI] ; Increment the byte contents of the
memory location addressed by SI.
(b) INC WORD PTR LBX] ; Increment the word contents of the
memory location addressed by BX.
The PTR directive is also used to declare a label either as FAR or NEAR type.
The FAR PTR directive indicates to the assembler that the label following FAR
PTR is not available within the same segment and the address of the label is of size
32 bits (2 bytes offset, followed by 2 bytes segment address).
Example:
(a) JMP FAR PTR DIVIDE
(b) CALL FAR PTR CONVERT

where DIVIDE and CONVERT are the names of a label and procedure,
respectively.
The NEAR PTR directive indicates that the label following NEAR PTR is in
the same segment and needs only 16 bits (2 bytes offset) to address it.
(ii) GLOBAL: The labels, variables, constants, or procedures declared GLOBAL
may be used by the other modules of the program.
Example:
The following statement declares the procedure ROOT as a GLOBAL label.
ROOT PROC GLOBAL
Example:
The following statement declares the variables DATA1, DATA2, and ARRAY1
as GLOBAL variables.
GLOBAL DATA1, DATA2, ARRAY1
(iii) LOCAL: The label, variables, constants, or procedures declared LOCAL in

a module are to be used only by that particular module. After some time, some
other module may declare a particular data type LOCAL, which was previously
declared as LOCAL by another module or modules. Thus, the same label may serve
different purposes for different modules of a program. With a single declaration
statement, a number of variables can be declared LOCAL as follows:
LOCAL DATA1, DATA2, ARRAY1, Al, A2
(iv) NAME: The NAME directive is used to assign a name to an assembly language
program module. The module may now be referred to by its declared name. The
names, if selected properly, may indicate the function of the different modules,
and hence help in good documentation.
(v) SHORT: The SHORT operator indicates to the assembler that only one byte is
required to code the displacement for a jump (i.e., the displacement is within -128
to +127 bytes from the address of the byte present next to the JMP opcode). This
method of specifying the jump address saves memory. Otherwise, the assembler
may reserve 2 bytes for the displacement in the jump instructions.
Example:
JMP SHORT MULTIPLY
where MULTIPLY is a label.
(vi) TYPE: The TYPE operator directs the assembler to decide the data type of
the specified label and replaces the TYPE label with the decided data type. For the
word type variable, the data type is 2. For the double word type, it is 4, and for the
byte type, it i® 1.
Example:
If DATA 1 is an array having word type data, the instruction MOV BX, TYPE DATA1
moves the value 0002H to BX.
(vii) MACRO and ENDM: Suppose a number of instructions occur repeatedly

in the main program, the program listing becomes lengthy. In such a situation,
a macro definition, i.e., a label, is assigned with the repeatedly appearing string
of instructions. The process of assigning a label or macro name to the repeatedly
appearing string of instructions is called macro definition. The macro name is then
used throughout the main program to refer to that string of instructions.
The difference between a macro and a subroutine is that in the macro, the
complete code of the instructions in the macro is inserted at each place where the
macro name appears. Hence, the length of the EXE file is larger and the macro
does not utilize the service of the stack. However, a subroutine is present only in
one place in a program and the control of execution is transferred to the subroutine
by calling that subroutine whenever necessary. Hence, the length of the EXE file
is smaller while using subroutines. A subroutine uses the stack for storing the
return address when it is called. The drawback with subroutines is the overhead
time needed to push the return address into the stack, while calling the subroutine,
and to retrieve the same from the stack, while returning from the subroutine to the
main program.
Defining a MACRO A MACRO can be defined anywhere in a program, using
the directives MACRO and ENDM. The label prior to the MACRO is the macro
name, which is used in the main program wherever needed. The ENDM directive
marks the end of the instructions or statements assigned to the macro name.
Example:
CALCULATE MACRO
MOV AX, [BX]
ADD AX. [BX + 2]
MOV [SI], AX
ENDM
In this example, CALCULATE is the macro name and the macro is used to add
two successive data in the memory, whose offset address is present in BX and the
result is stored in the memory at the offset address present in SL In the program,
which uses the above macro definition, wherever the instructions defined in the
above macro are repeating, we can simply use the macro name (CALCULATE)
instead of those instructions and this is called macro reference. When that program
is assembled using the assembler, the assembler replaces each macro reference by
the corresponding string of instructions defined in the macro and finds the opcode
of each instruction. This is called macro expansion.
Passing parameters to a MACRO Using parameters in a macro definition, the
programmer specifies the parameters of the macro that are likely to be changed
each time the macro is called. The macro given here (CALCULATE) can be
modified to calculate the result for different sets of data and store it in different
memory locations as follows:
CALCULATE MACRO OPERAND, RESULT
MOV BX, OFFSET OPERAND
MOV AX, [BX]
ADD AX, [BX + 2]

MOV SI, OFFSET RESULT
MOV [SIL AX
ENDM
The parameters OPERAND and RESULT can be replaced by OPERAND 1,
RESULT 1 and OPERAND2, RESULT2 while calling the macro, as follows:
CALCULATE OPERAND1, RESULT1
CALCULATE OPERAND2, RESULT2
14.4.3 Writing Assembly Language Programs using MASM

MASM (Microsoft Macro Assembler) is one of the assemblers commonly used
along with the LINK (linker) program to structure the machine codes generated by
MASM in the form of an executable (EXE) file. The MASM reads the assembly
language program, which is called source program and produces an object file as
output. The LINK program accepts the object file produced by MASM along with
library files if needed, and produces an EXE file.
While writing a program for MASM, the program listing is first typed using
a text editor in the computer, such as Norton’s Editor (NE) and Turbo C editor.
After the program editing is done, it is saved with the extension .ASM. For
example, MSI.ASM is a valid file name that can be assigned to an assembly
language program. The programmers have to ensure that all the files—the editor,
MASM.EXE (MASM assembler), and LINK.EXE (linker)—are available in the
same directory. After editing, the assembling of the program has to be done using
MASM. If all the above mentioned software is present in the root directory of the
C drive in the computer, to assemble the file MSI.ASM, the programmer has to
type the following at the DOS prompt in the computer:
C:\ > MASM MSI.ASM or C:\ > MASM MSI
After entering this command, the assembler asks for the names of the following
types of files, which it generates after the assembly process:
Object file name [.OBJ]:
List file name [NUL.LST]:
Cross reference [NUL.CRF]:
The programmer can type a name against every file name and press the enter
key after each name. If no name is entered against the file name before pressing
the enter key, all the three files will have the same name as the source file. The
.OBJ (object) file contains the machine codes of the program that is assembled.
The .LST (list) file contains the total offset map of the source file, including labels,
opcodes, offset addresses, memory allotment for different labels, and directives.
The cross reference (.CRF) file is used for debugging the source program, as it
contains information such as size of the file in bytes, list of labels, number of
labels, and routines to be called in the source program.
After the cross reference file name is entered, the assembly process starts. If the
program contains syntax errors, they are displayed using the error code number
and the corresponding line numbers at which the errors have occurred. Once
these errors are corrected by the programmer, the assembly process is completed
successfully.
The DOS linking program LINK.EXE is used to link the different object
modules of a source program and the function library routines to produce an
integrated executable code for the source program. The linker is invoked using the
following command:
C :\> LINK MSI.OBJ
After entering this command, the linker asks for the name of the following
files:
Run file [.EXE]:
List files [NUL.MAP]:
Libraries [LIB]:
If no file names are entered for these files, by default, the source file name is
considered. The optional input ‘Libraries’ expects the name of a special library (if
any) from which the functions were used by the source program. The output of the
linker program is an executable file with either the file name entered by the user or
the default file name, and .EXE extension. The executable file name can be entered
at the DOS prompt to execute the file as follows:
C :\> MSI.EXE
In the advanced version of MASM, both assembling and linking are combined
under a single menu-invocable compile function.
DEBUG.com is a DOS utility program that is used for debuggihg and
troubleshooting 8086 assembly language programs. The DEBUG utility enables
us to have control over the hardware resources and the memory in the computer
(PC) up to a certain extent, as the PC uses one of the INTEL processors (80486,
Pentium, etc.) as the CPU. DEBUG enables us to use the PC as a low-level 8086
microprocessor kit. Typing the DEBUG command at the DOS prompt and pressing
the enter key invokes the debugging facility. A (dash) appears DEBUG is
successfully invoked, as follows:
C :\> DEBUG
Now, by typing ‘R’ at the line and pressing the enter key, we can see
the content of the different registers and flags present in the CPU of the PC, as
follows:
-R
AX = 0000H BX = 0005H CX = OOODH DX = SOOOH
SP = 8500H BP = 9800H SI = 2000H DI = 7000H
DS = SOOOH ES = 3000H SS = 4000H CS = 2000H
IP = 2000H FLAGS = 0024H
7'he remaining DEBUG commands can be referred to from any book that
discusses assembly language programming in personal computers. In this section,
a few examples for writing 8086 assembly language programs while using an
assembler are given.
Example 14.11:
Write a program to add two 8-bit data (FOH and 50H) in the 8086 and to store the
result in the memory, when the assembler is used.
Solution:
ASSUME CS: CODE, DS: DATA
DATA SEGMENT ; Beginning of data segment
0PER1 DB FOH ; First operand
0PER2 DB 50H ; Second operand
RESULT DB 01 DUP (?) : A byte of memory is reserved for the
result.
CARRY DB 01 DUP (?) A byte is reserved for storing the
ca rry.
DATA ENDS End of data segment.
CODE SEGMENT Beginning of code segment

START : MOV AX, DATA Initialize AX with the segment address
of DS.
MOV DS, AX Move the content of AX to DS.
MOV BX, OFFSET 0PER1 Move the offset address of 0PER1 to BX.
MOV AL, [BX] Move the first operand to AL.
ADD AL, [BX + 1] Add the second operand to AL.
MOV SI , OFFSET RESULT Store the offset address of RESULT
in SI.
MOV LSI] , AL Store the content of AL in the location
RESULT.
INC SI Increment SI to point to the location
of the carry.
JC CAR If carry = 1, jump to CAR.
MOV [SI] , OOH Store OOH in the location CARRY.
JMP LOCI Jump to LOCI.
CAR: MOV [SI] , 01H Store 01H in the location CARRY.
LOCI: MOV AH, 4CH
INT 2IH Return to DOS prompt.
CODE ENDS End of code segment.
END START Program ends.
In this program, the instructions MOV AH, 4CH, and INT 2IH at the end of the
program are used for returning to the DOS prompt after executing the program in
the computer. Instead of these two instructions, if one writes the HLT instruction,
the computer hangs after executing the program, as the CPU goes to the halt state
and the user is unable to examine the result.
Another method to write the code segment for this program is as follows:
CODE SEGMENT ; Beginning of code segment
START: MOV AX, DATA ; Initialize AX with the segment address of DS.
MOV DS, AX : Move the content of AX to DS.

MOV AL, 0PER1 : Move the fi rst operand to A.
MOV BL, 0PER2 : Move the second operand t o B.
ADD AL, BL : Add BL to AL.
MOV RESULT, AL; Store AL in the location RESULT
JC CAR ; If carry = 1, jump to CAR.
MOV CARRY, OOH: Store OOH in the location CARRY.
JMP LOCI : Jump to LOCI.
CAR: MOV CARRY, 01H; Store 01H in the location CARRY.
LOCI: MOV AH, 4CH
INT 21H : Return to the DOS prompt.
CODE ENDS : End of code segment.
END START ; Program ends.
Note: In the second method, instead of OPER2, OPER1 + 1 can be used, and
instead of CARRY, RESULT + 1 can be used, since OPER2 is assigned the
memory location next to that of OPER1 and CARRY is assigned the memory
location next to that of RESULT, as defined in the data segment.
Example 14.12:
Write a program to find the smallest word in the given array having fifty word
type data.
Solution:
DATA SEGMENT
ARRAY DW 2500H, 1600H, 0032H... : Initialize the ARRAY with 50 words
COUNT EQU 32H : Count is assigned to the value 32H
(= 50).
SMALLEST DW DUP (?) ; Reserve one word to store the smallest
word.
DATA ENDS
CODE SEGMENT
START: MOV AX, DATA
MOV DS, AX
MOV SI, OFFSET ARRAY : Move the offset of the array to SI.
MOV CL, COUNT : Load COUNT in CL.
DEC CL : Decrement CL as the number of
comparisons is one less than the
count.
MOV AX, ESI] : Move the first word to AX.
AGAIN: ADD SI, 02 : Add 2 to SI to get the next word.
MOV BX, [SI] : Move the next word to BX.
CMP AX, BX : Compare the word in AX with BX.
JC NEXT : If AX i s sma11, go to NEXT.
MOV AX, BX : Move the small word in BX to AX.
NEXT : LOOP AGAIN ; Repeat the loop CL times.

MOV SMALLEST, AX ; Store AX In the location SMALLEST
MOV AH, 4CH
INT 21H ; Return to the DOS prompt.
CODE ENDS ; End of code segment.
END START : Program ends.
Example 14.13:
Write a program to find the number of even and odd data bytes present in the given
array having one hundred byte type data.
Solution:
DATA SEGMENT
ARRAY DB 40H, 31H, 23H, 52H... ; Enter all the data items of ARRAY
here.
COUNT EQU 64H ; Initialize COUNT with the value 100.
EVEN_NOS DB OOH ; Reserve a byte for storing the number
of even data items.
ODD_NOS DB OOH : Reserve a byte for storing the number
of odd data items.
DATA ENDS
CODE SEGMENT
START: MOV AX, DATA
MOV DS, AX
MOV BL, OOH ; Initialize BL with OOH, to store
the number of even data items.
MOV DL, OOH ; Initialize DL with OOH, to store the
number of odd data items.
MOV CL, COUNT ; Initialize CL with COUNT.
MOV SI, OFFSET ARRAY ; Move the offset address of ARRAY to
the SI register.
AGAIN: MOV AL, [SI] ; Move one byte from ARRAY to AL.
RCR AL, 1 ; Rotate AL right through the carry
by 1 bit.
JC ODD ; If carry = 1, the number is odd. So go
to ODD.
INC BL ; Otherwise, the number is even and
hence increment BL.
JMP LI ; Jump to LI.
ODD: INC DL ; Increment DL by 1 as the number is
odd.
LI: INC SI ; Increment SI to point to the next
data.
LOOP AGAIN ; Go to AGAIN, CL times.
MOV EVEN-NOS, BL ; Store the content of BL in EVEN_NOS.
MOV ODD_NOS, DL ; Store the content of DL In ODD_NOS.

MOV AH, 4CH
CODE ENDS : End of code segment.
Example 14.14:
Write a program to arrange the given array having ten word type data in ascending
order.
Solution:
DATA SEGMENT
ARRAY DW 1234H , 4050H, 0035H... ; Enter all the data items of ARRAY
here.
COUNT EQU OAH
DATA ENDS
CODE SEGMENT
START: MOV AX, DATA
MOV DS, AX
MOV CL, COUNT ; Load the number of data items in
CL.
DEC CL ; Decrement CL as the number of
passes is one less than the
number of data.
NEXT_PASS: MOV BL, CL ; Initialize BL with the number of
comparisons to be done in each
pass.
MOV SI, OFFSET ARRAY : Move the offset address of ARRAY to
the SI register.
COMPARE: MOV AX, [SI] ; Move one data item to AX.
ADD SI, 02H ; Add 02 to SI to point to the next
data.
CMP AX, [SI] ; Compare the next data with the
content of AX.
JC LI ; If the first data item is lesser
than the second, go to Ll.
XCHG AX, [SI] ; Otherwise, exchange the data in
AX and the memory.
SUB SI, 02H ; Subtract 02 from SI to point to
the previous memory location.
MOV [SI], AX ; Store the content of AX (smaller
data) in the memory.
ADD SI, 02 ; Increment SI by 2 to compare the
next data with AX.
Ll; DEC BL : Decrement the number of comparisons
in BL by 1.
JNZ COMPARE ; If BL is not 0, go to COMPARE for the

next comparison.
LOOP NEXT_PASS ; If BL is 0, go to NEXT_PASS.
MOV AH, 4CH
CODE ENDS ; End of code segment.
The algorithm used here is explained with the following simple example. Let
us consider arranging four words stored in an array in ascending order. Since there
are 4 (= N) words, 3 (= N - 1) passes have to be done. In the first pass, 3 (= N - 1)
comparisons are made and the highest number is brought to the end of the array. In
the second pass, 2 (= N - 2) comparisons are made since only the top three words
of the array need to be compared and in the third pass, only one comparison is
needed to compare the first two data in the array.
Let us assume that the data in the array is as follows:
3200H
4F35H
2350H
1FC2H
The comparisons done in each pass and the exchange of data for arranging
them in ascending order are shown here:
PASS I:
3200H <— 3200H 3200H 3200H
4F35H । 4F35H <-। 2350H 2350H
2350H 2350H <- 4F35H <-] 1FC2H
1FC2H 1FC2H 1FC2H 4F35H
PASS II:
3200H 2350H 2350H
2350H 3200H <-1 1FC2H
1FC2H 1FC2H ' 3200H
4F35H 4F35H 4F35H
PASS III:
2350H IFC2H
1FC2H 2350H
3200H 3200H
4 F35H 4F35H
Sorted array
POINTS TO REMEMBER
____________________________ V
• The addressing modes in the 8086 are classified as register, immediate, data memory,
stack memory, and program memory addressing modes.
• The data memory addressing modes are classified as direct, base, index, base plus
indexed, base-relative, index-relative, and base-relative plus index addressing modes.
• The program memory addressing modes are classified as direct, relative, and indirect
addressing modes.
■ The 8086 instructions are classified as data transfer, arithmetic, logical, shift/rotate, flag
manipulation, control transfer, string, and machine control instructions.
■ The assembly language programming of the 8086 can be done with a line assembler or
an assembler.
■ Assembler directives are used while writing an assembly language program that is to be
assembled by using an assembler.
KEY TERMS
Addressing mode This mode is the way in which the microprocessor addresses the
operands while fetching data during the execution of an instruction or the way in which
the microprocessor calculates the memory address from where the next instruction to be
executed is taken, in the case of jump or call instructions.
Assembler It is a software that is used to convert assembly language programs into
machine language programs.
Assembler directives These are commands to the assembler, which give various details
in a program such as the required storage class for a particular constant or variable (byte,
word, or double word), logical name of the segments (CODE, STACK, or DATA segment),
type of procedures or routines (FAR, NEAR, PUBLIC, or EXTRN), end of a segment
(ENDS), and macro definition (MACRO, ENDM).
Inter-segment jump This refers to the operation of jumping from one code segment to
another.
Intra-segment jump This refers to the operation of jumping within the same code
segment.
Line assembler It converts each line in an assembly language program into the
corresponding machine language program, as soon as it is entered in the system.
REVIEW QUESTIONS
1. What is the function of segment override prefix? Give two examples.

2. What is the difference between inter-segment and intra-segment jump in the 8086?
3. What is the difference between short and near jump in the 8086?
4. What is the function of the assembler directives FAR PTR, NEAR PTR, and
SHORT?
5. Write the different steps performed by the 8086 when it executes the instructions
PUSH CX and PUSH [SI],
6. What are the different uses of stack in a microprocessor?
7. Write the different steps performed by the 8086 when it executes the instructions
POP CX and POP [BX].
8. Write the operation performed by the 8086 when it executes the XLAT instruction.
What is the use of XLAT?
9. What is the difference between fixed port and variable port addressing in the 8086?
10. Which instructions of the 8086 are used to communicate with the I/O devices in the
I/O-mapped I/O scheme?
11. Write the function of the assembler directives BYTE PTR and WORD PTR.
12. What is the difference between the MUL and IMUL instructions in the 8086?
13. What is the difference between the DIV and IDIV instructions in the 8086?
14. What are the default operand and result locations for 8- and 16-bit data multiplication
instructions in the 8086?
15. What are the default operand and result locations for 8- and 16-bit data division
instructions in the 8086?
16. What is the function of the DAA instruction in the 8086?
17. Write the operations performed when the instruction AAD is executed in the 8086.
18. Which instructions of the 8086 are used to set and reset the D and I flags?
19. What is the range of the relative address that is used in the conditional jump
instructions?
20. What is the function of the INT n instruction? Which instruction of the 8086 is used to
return from the interrupt service routine to the main program?
21. What are the operations performed when the instructions LOOP and LOOPNE are
executed in the 8086?
22. What is the function of the D and I flags in the 8086?
23. Which registers are used as offset registers and segment registers for pointing to the
source and destination during the execution of the string instructions in the 8086?
24. What is the function of the REP and REPE prefixes used with string instructions in the
8086?
25. What is the function of the LOCK prefix used with an 8086 instruction?
26. What is the function of the assembler and assembler directives?
27. What is the function of the assembler directives ORG and DB?
28. What is a macro? Give an example.
29. What is the difference between a macro and a subroutine?
30. What is the need for passing parameters to a macro?
31. Describe the different data memory addressing modes in the 8086 giving an example
for each.
32. Describe the different program memory addressing modes in the 8086 giving an
example for each.
33. Explain the stack memory addressing modes in the 8086 giving examples.
34. Explain the different data transfer instructions in the 8086 giving examples for each.
35. Explain the different arithmetic instructions in the 8086 giving examples for each.
36. Describe the different logical instructions in the 8086 giving examples for each.
37. Write the assembler directives that are used to define variables and constants, with an
example for each.
38. What are the assembler directives that are related to segment declaration? Explain
with examples.
39. Write the function of assembler directives that are related to code location, with an
example for each.
40. What are the assembler directives that are related to procedure declaration? Explain
with examples.
41. Explain the function of the assembler directives PTR, TYPE, SHORT, GLOBAL, and
LOCAL with an example for each.
THINK AND ANSWER
1. Let the content of the different registers in the 8086 be as follows: DS = 1000H,
SS = 2000H, ES = 3000H, BX = 4000H, SI = 5000H, DI = 6000H, and BP = 7000H.
Find the memory address/addresses from where the 8086 accesses the data while
executing the following instructions:
(i) MOVAX, [BX]
(ii) MOVBX, [SI]
(iii) MOV CX, [BP]
(iv) MOV AL, [DI]
(v) MOV BH, SS: [SI]
(vi) MOV CX, ES: [DI]
(vii) MOV AX, [BX + DI]
(viii) MOV BX, [BP + DI + 5]
(ix) MOV AH, [BX + 10H]
(x) MOV CX, DS: [BP + 4]
(xi) MOVBX, [SI-5]
(xii) MOV AX, [BX + 10]
2. Which registers of the 8086 are modified while executing inter-segment and intra
segmentjump instructions?
3. Is it possible to exchange the content of two memory locations or the content of two
segment registers using the XCHG instruction? Why?
4. If the content of BP = 1000H and SI = 2000H, what is the value present in CX after
the 8086 executes the instructions LEA CX, [BP + SI], and LEA CX, [SI].
5. Is it possible to use two memory operands in the ADD and SUB instructions?
6. Is the carry flag affected by the execution of the INC and DEC instructions in the
8086?
7. What is the difference between SUB and CMP instructions?
8. What is the difference between TEST and AND instructions?
9. Which instructions of the 8086 are used to handle procedure or subroutine?
10. What is the difference between arithmetic and logical right-shift?
11. What are the common applications of left-shift and right-shift operations?
12. When is the CL register used with the shift and rotate instructions?
13. Consider the following pair of partial programs:
(i) MOV AX, 4000H (ii) MOV AX, 4000H
ADD AX, AX ADD AX, AX
ADC AX, AX RCL AX, 1
JZ DOWN JZ DOWN
For each case, what is the data in AX after execution of the third instruction and
from where does the processor fetch the next instruction after execution of the fourth
instruction?
14. How is the WAIT instruction used to coordinate the operation between the 8086 and
the 8087?
1. Write an 8086 assembly language program to find the sum of 100 words present in an
array stored from the address 3000H: 1000H in the data segment and store the result
from the address 3000H: 2000H.
2. Write an 8086 assembly language program to find the prime numbers among 100
bytes of data in an array stored from the address 4000H: 1000H in the data segment
and store the result from the address 4000H: 3000H.
3. Write an 8086 assembly language program to find the number of occurrences of the
character ‘A’ among 50 characters of a string type data stored from the address 5000H:
1000H in the data segment and store the result in the address 2000H: 5000H.
4. Write an 8086 assembly language program to check whether the two strings, one
stored from the address 2000H: 1000H in the data segment and the other stored from
the address 2000H: 3000H are equal or not. If they are equal, store the value OOH in
AL. Otherwise, store the value 01H in AL.
5. Write an 8086 assembly language program to find the number of bytes that have the
hexadecimal digit ‘F’ in their upper nibble among 100 bytes of data in an array stored
from the address 8000H: 1000H in the data segment. Store the result in the address
8000H: 3000H.
6. Write an 8086 assembly language program to complement the lower nibble of each
byte in 100 bytes of data in an array stored from the address 8000H: 1000H in the data
segment. Store the result from the address 8000H: 3000H.
7. Write an 8086 assembly language program to add two matrices having word type data
in each element of the matrix. Assume that each element of the result after addition
of the corresponding elements of the matrix is also word type data. The data for one
matrix is present in an array stored from the address 8000H: 1000H in the data segment
and the corresponding data for another matrix is present in an array stored from the
address 8000H: 3000H in the data segment. The result is to be stored from the address
7000H: 1000H.
8. Write an 8086 assembly language program to multiply two square matrices having
byte type data in each element of the matrix. Assume that each element of the resultant
matrix is of word type. The data for one matrix is present in an array stored from
the address 8000H: 1000H in the data segment and the corresponding data for the
other matrix is present in an array stored from the address 8000H: 3000H in the data
segment. The result is to be stored from the address 7000H: 1000H.
9. Write an 8086 assembly language program to find the factorial of the given byte of
data using a recursive algorithm. The result is to be stored in the address 7000H:
1000H.
10. Write a non-recursive assembly language subroutine for the 8086, to evaluate the
number
Fn = Fn'l + Fn 2 for giVCn D > 1
given that Fo = 0 and F, = 1. Consider the number n to be such that Fn is not more than
a 16-bit number.
11. Solve problem 1 assuming that the program is to be assembled by an assembler.
CHAPTER 15]
8086 INTERRUPTS
LEARNING OUTCOMES
• Different types of interrupts in the 8086, such as hardware and software interrupts
• Processing of an interrupt by the 8086
• Interrupt vector table and interrupt vectors in the 8086
• Functions of the different interrupts in the 8086
• Priority among the interrupts in the 8086
• Writing interrupt service routines
• A few BIOS (basic input/output system) interrupts or function calls
15.1 INTRODUCTION
The 8086 allows normal program execution to be interrupted in one of the
following ways:
(i) An external signal given through one of its interrupt pins (INTR/NMI)
(ii) A special instruction in the program, such as the software interrupt
instruction (INT N)
(iii) The occurrence of an error condition such as divide-by-0
(iv) A trap interrupt
After receiving the interrupt, the microprocessor stops the execution of the
current program and calls a procedure called interrupt service routine (ISR), which
services that interrupt. The IRET instruction executed at the end of the interrupt
service routine returns the execution to the interrupted program.
15.2 INTERRUPT TYPES IN 8086

There are 256 interrupt types in the 8086. Among these, a few interrupt types are
assigned for specific interrupts such as the divide-by-0 interrupt and the NMI interrupt.
A few interrupt types are reserved by Intel for future expansion. The programmer is
free to use the remaining interrupt types according to his/her requirement.
An 8086 interrupt can come from any one of the following three sources:
(i) An external signal applied to the non-maskable interrupt (NMI) pin or to
the interrupt (INTR) pin. An interrupt caused by a signal applied to one of
these inputs is called hardware interrupt.
(ii) The execution of the instruction INT n, where n is the interrupt type that can
take any value between OOH and FFH. This is called software interrupt.
(iii) An error condition such as divide-by-0, which is produced in the 8086 by
the execution of the DIV/IDIV instruction or the trap interrupt.
15.3 PROCESSING OF INTERRUPTS BY 8086

After executing each instruction in a program, the 8086 checks if any interrupt
has been requested. If an interrupt has been requested, the 8086 processes it by
performing the following series of steps:
(i) Pushes the content of the flag register onto the stack to preserve the status
of the interrupt (IF) and trap flags (TF), by decrementing the stack pointer
(SP) by 2
(ii) Disables the INTR interrupt by clearing IF in the flag register
(iii) Resets TF in the flag register, to disable the single step or trap interrupt
(iv) Pushes the content of the code segment (CS) register onto the stack by
decrementing SP by 2
(v) Pushes the content of the instruction pointer (IP) onto the stack by
decrementing SP by 2
(vi) Performs an indirect far jump to the start of the interrupt service routine
(ISR) corresponding to the received interrupt
Figure 15.1 shows the processing of an interrupt by the 8086.
Fig. 15.1 Processing of an interrupt by the 8086
Now, let us see in detail how the 8086 does an indirect far jump to the start
of the ISR of the received interrupt. When the 8086 responds to an interrupt, it
refers to four memory locations present in the interrupt vector table (IVT), to get
the new values of CS and IP. These memory locations are used to find the starting
address of the ISR of the received interrupt in the memory. In an 8086 system,
the first 1 KB of memory from the addresses 00000H-003FFH is set aside as a
table called interrupt vector table (IVT) for storing the interrupt vector (IV). Each
interrupt vector indicates the starting address of the ISR of a particular interrupt
in the memory. It contains four bytes, in which the lower two bytes are called
offset and the upper two bytes are called segment. The offset part of the interrupt
vector is loaded in the IP register and the segment part is loaded in the CS register.
While using interrupts in the 8086, the ISR of the different interrupts must be
initially stored in the memory at the desired locations. Then the interrupt vectors
corresponding to the various interrupts are stored in the IVT. For example, if the
ISR of interrupt type 0 is stored in the memory starting at the address 30000H,
8086 INTERRUPTS 487
the segment part of the interrupt vector is entered as 3000H and its offset part is
entered as 0000H in the IVT. When these two values are loaded in the CS and
IP registers, respectively, the 8086 calculates the address of the next instruction
to be executed using the relation CS x 10H + IP, and obtains 30000H, which is
the starting address of the ISR of interrupt type 0. Since four bytes are required
to store the CS and IP values for each ISR in the IVT, and the IVT must hold the
interrupt vector for a maximum of 256 interrupts, the maximum size of the IVT
is 1 KB. Each interrupt vector is also called interrupt pointer and the IVT is also
referred to as the interrupt pointer table.
Figure 15.2 shows the 256 interrupt vectors arranged in the IVT in the
memory. The IP value
Address
is inserted as the lower-
order word of the 003FFH Type FFH vector (available)
interrupt vector and the
Available interrupt
CS value is inserted as vectors (224) 003FCH
the higher-order word Type 21H vector (available)
of the interrupt vector. Type 20H vector (available)

Each interrupt vector is
Type 1FH vector (reserved)
identified by a number Reserved interrupt
called its type, which is vectors (27)
an 8-bit number. Hence 00014H Type 05H vector (reserved)

the different interrupt
0001 OH Type 04H vector (overflow)
types vary from 0 to 255 Dedicated
(00H-FFH). The lowest interrupt Type 03H vector
vectors (5) 0000CH (1-byte INT instruction)
five types are dedicated 0000BH
00008H Type 02H vector (NMI)
to specific interrupts
00007H Type 01H vector
such as the divide-by- (Trap or single step)
00004H
0 interrupt, the single CS I-00003H
-00002H Type OOH vector
step (trap) interrupt, the —r00001H (Divide-by-0 error)
NMI interrupt, the one- _ Loooooh
byte INT instruction 8 bits
interrupt, and the
Fig. 15.2 Interrupt vector table in the 8086
overflow interrupt.
Interrupt types 5-31 are reserved by Intel for use in advanced microprocessors
such as the 80286 and the 80386. The upper 224 interrupt types are available for
the programmer to use for hardware/software interrupts.
The interrupt vector for each interrupt type requires four memory locations.
For example, the interrupt vector for type OOH occupies the memory locations
0(X)00H-00003H, the interrupt vector for type 01H occupies the memory
locations 00004H-00007H, and so on. When the 8086 responds to a particular
type of interrupt, it automatically multiplies the type of that interrupt by 4 to find
the desired address in the vector table, from where it takes the interrupt vector
and loads it in the IP and CS registers. For example, if the interrupt type 03H is
currently received by the 8086, it goes to the memory address given by 03H x 04H
= 000CH, to get the interrupt vector for type 03H.
15.4 DEDICATED INTERRUPT TYPES IN 8086

The lowest five interrupt types in the 8086 (i.e., types 00H-04H) are dedicated to
specific interrupts such as the divide-by-0 interrupt, the single step (trap) interrupt,
the NMI interrupt, the one-byte INT instruction interrupt, and the overflow
interrupt. Let us now discuss these interrupt types in detail.
15.4.1 Type OOH or Divide-by-zero Interrupt

Whenever the quotieht from a DIV or IDIV operation is too large to fit in the result
register, which occurs while dividing a number by 0, or if the divisor is very small
compared to the dividend, the 8086 automatically generates a type 0 interrupt.
15.4.2 Type 01H, Single Step, or Trap Interrupt

The type 1 interrupt is used for single step operation, in which the 8086 executes
one instruction in the main program and then executes the ISR of the trap interrupt.
In this ISR, we write the instructions to verify the contents of certain registers and
memory locations, and display them in an output device, such as a seven-segment
display or CRT (cathode ray tube) monitor. If the expected data are present in the
registers and/or memory locations, the 8086 can be made to proceed to the next
instruction. The 8086 trap flag and type 1 interrupt response make it easier to
implement a single step feature in an 8086-based system. If the trap flag in the 8086
is set, the 8086 automatically generates a type 1 interrupt after each instruction in
the main program is executed. After executing the IRET instruction in the ISR, the
8086 again goes to execute the next instruction in the main program.
15.4.3 Type 02H or NMI Interrupt

The 8086 generates a type 2 interrupt automatically when it receives a low-to-high
transition on its NMI pin. The NMI interrupt cannot be disabled by software and
hence it is used to inform the 8086 that some condition in an external system must
be taken care of.
One of the common uses of the type 2 or NMI interrupt is to save important
data in the RAM in case of a system power failure. An external circuitry detects the
failure of the power given to the system and sends an interrupt signal to the NMI
input of the 8086. Due to the large filter capacitor present in most power supplies,
the DC power to the 8086 remains for a few ms (say 25 ms or 50 ms) after the AC
power has failed. This time is sufficient for the NMI interrupt’s ISR to copy the
important data used in the program to a RAM chip with battery-backed power
supply. When AC power is restored, the data stored in the battery-backed RAM
can be retrieved and the program resumes execution from where it stopped.
The NMI interrupt is also used to sense hazardous situations such as fire,
smoke, and unsafe pressure or temperature limits in an industrial environment,
when the 8086 is used to control the industrial processes. In these applications,
an appropriate sensor is used to detect the abnormal condition and its output is
connected to the NMI interrupt. Whenever the NMI interrupt is activated, the 8086
runs the NMI interrupt’s ISR, which is used to issue an alarm signal and shut off
the process if needed.
8086 INTERRUPTS 489
15.4.4 Type 03H or One-byte INT Interrupt

The type 3 interrupt is produced by the execution of the INT 03H instruction. It is
a single-byte instruction, which is mainly used to implement a breakpoint function
in the 8086 system, for debugging a program. When we insert a breakpoint in the
program, the 8086 system executes the instructions up to the breakpoint and then
executes the ISR corresponding to the breakpoint interrupt. Unlike the single-step
technique in which the execution is stopped after each instruction, the breakpoint
technique allows us to execute all the instructions up to the inserted breakpoint in
the main program. The processor then goes on to execute the ISR of the breakpoint
interrupt.
In an 8086 system, the breakpoint is inserted in the main program at a
particular place by temporarily replacing the instruction byte at the address with
the instruction byte CCH, which is the opcode of the INT 03H instruction. When
the 8086 executes the INT 03H instruction, the type 3 interrupt is produced. In
the type 3 interrupt’s ISR, all the register contents are saved in the stack. Then,
depending on the system requirement, the desired register and/or memory location
contents may be sent to a CRT display for debugging, while the system waits for
a command from the user to proceed further.
15.4.5 Type 04H or Overflow Interrupt

The 8086 overflow flag (OF) is set if the result of an arithmetic operation on signed
numbers is too large to be stored in the destination register or memory location.
There are two ways to detect and respond to an overflow error in a program:
(i) Place the jump on overflow (JO) instruction immediately after the arithmetic
instruction. If the overflow flag is set due to the result of the arithmetic
instruction, execution is transferred to the address specified in the JO
instruction. At this address, an error routine that responds to the overflow in
the required manner can be placed.
(ii) Place the interrupt on overflow (INTO) instruction immediately after the
arithmetic instruction in the program. If the overflow flag is not set when
the 8086 executes the INTO instruction, it is treated as a NOP (no operation)
instruction. However, if the overflow flag is set, the 8086 generates a type
4 interrupt after executing the INTO instruction. Instructions in the ISR
produce the desired response to the error condition. The advantage of using
the INTO instruction is that the type 4 interrupt’s ISR can be easily accessed
from any program in a multitasking environment.
15.5 SOFTWARE INTERRUPTS—TYPES OOH-FFH

The INT instruction of the 8086 can be used to generate any one of the 256 possible
interrupt types, which are called software interrupts. The desired interrupt type is
specified as part of the INT instruction. For example, the INT 21H instruction
causes the 8086 to generate an interrupt of the type 21H. The response of the 8086
to the software interrupt is same as that for any of the interrupt types described in
Section 15.4.
In general, when the 8086 executes the INT n instruction where n is the
interrupt type, the 8086 pushes the content of the flag register, CS, and IP values
into the stack register, and clears IF and TF. Then the 8086 goes to the memory
address (given by 4 x n) to obtain the interrupt vector for the type n from the IVT
and loads it in the IP and CS registers. This makes the 8086 execute the ISR for the
interrupt type n. The IRET instruction at the end of the ISR makes the 8086 return
to the main program to the instruction next to the INT n instruction, to continue
the execution of the main program.
Software interrupts produced by the INT instruction have the following uses:
(i) Inserting break points in a program for debugging. The INT 03H instruction
is used for this purpose.
(ii) Testing the function correctness of various ISRs. For example, the INT 02H
instruction can be used to test the ISR for the NMI interrupt, without giving
any input signal to the NMI pin of the 8086.
15.6 INTR INTERRUPTS—TYPES OOH-FFH

The 8086 INTR interrupt allows an external signal to interrupt the execution
of a program. The INTR interrupt can be masked (disabled) so as to not cause
an interrupt. If IF is set, the INTR interrupt is enabled and if IF is cleared,
INTR is disabled. IF can be set and cleared at any time, using the STI and
CLI instructions, respectively. After the 8086 is reset, IF is set using the STI
instruction, if the user needs to use the INTR interrupt. The INTR interrupt is
activated by a high level (i.e., logic 1) signal in the INTR pin. The minimum
duration for which the INTR signal must be kept high to be recognized by the
8086 is equal to the execution time of the instruction that takes longest time for
execution. This is because the 8086 tests the INTR signal during the last clock
cycle of an instruction cycle.
If the INTR input is high and IF is set, the 8086 is interrupted. As part of the
response to the interrupt, the 8086 automatically clears IF. This is done for the
following two reasons:
(i) To prevent a signal on the INTR input from interrupting a higher priority
ISR in progress. If needed, IF can be set at the beginning of the higher
priority ISR, so that 8086 can be interrupted by an INTR interrupt while
executing that ISR.
(ii) To make sure that a signal in the high state, existing for a sufficient duration
(say, a few ps), on the INTR input, does not cause the 8086 to interrupt it
again before completing the execution of its ISR.
The IRET instruction at the end of the ISR restores IF and TF to their original
value. When the 8086 processes an INTR interrupt signal, its response is slightly
different from its response to other interrupts. For an INTR interrupt, the interrupt
type is sent to the 8086 from an external hardware device such as a programmable
interrupt controller (the 8259) or a tri-state octal buffer (IC 74244) connected to
an 8-bit DIP switch having the specific interrupt type.
Figure 15.3 shows the 8086 INTR interrupt’s acknowledgement cycle.
8086 INTERRUPTS 491
Fig. 15.3 8086 INTR interrupt’s response
Figure 15.4 shows the simplified diagram for interfacing the 8259 with the 8086.
When the 8259 receives an interrupt signal on one of its IR inputs (IR0-IR7), it
sends an interrupt signal (INT) to the INTR input of the 8086. If the INTR interrupt
is enabled (in the 8086) by setting IF, the 8086 responds as shown in Fig. 15.3.
Fig. 15.4 Simplified diagram of interfacing the 8259 with the 8086
The 8086 does two interrupt acknowledge cycles when it receives the INTR
interrupt. During the first acknowledgement, the 8086 floats the data bus AD 15-
AD0 and sends out an Interrupt Acknowledgement (INTA) pulse through its INTA
pin. This pulse instructs the 8259 to perform certain internal operations to get the
interrupt type related to the interrupt received by it. The interrupt type for the IR0
interrupt in the 8259 is pre-programmed in it during its initialization process. The
interrupt type for successive interrupts in the 8259 (IR1, IR2,.. .IR7) is one greater
than the interrupt type of the previous interrupt. For example, if the interrupt type
assigned to IR0 is 50H, the interrupt type assigned to IR1 is 51H, that assigned to
IR2 is 52H, and so on. During the second acknowledge cycle, the 8086 sends out
another pulse on its INTA pin. In response to this second INTA pulse, the 8259
places the interrupt type on the lower eight lines of the data bus (AD7-AD0),
which is read by the 8086. After receiving the interrupt type, the 8086 goes on to
execute the ISR of the received interrupt type. The advantage of using the 8259
with the 8086 is the ability of the 8086 to handle multiple hardware interrupts and
not merely two (INTR and NMI).
While using the tri-state octal buffer (IC 74244) with its inputs connected to an
8-bit DIP switch and outputs connected to the data bus (AD0-AD7), the required
interrupt type is set in the 8-bit DIP switch and the INTA signal of the 8086 is
connected to the enable inputs of the octal buffer (1G and 2G). When the 8086
receives the INTR interrupt, it makes INTA low, which enables the octal buffer
IC. The interrupt type, which was set in the 8-bit DIP switch, is now placed in the
data bus (D7-D0) and the 8086 reads it.
15.7 PRIORITY AMONG 8086 INTERRUPTS

Suppose two or more interrupts occur Interrupt Priority
at the same time, how would the 8086 Divide-by-0, INT n, INTO Highest
respond? The highest priority interrupt is NMI
serviced first by the 8086, followed by the INTR
▼
next highest priority interrupt, and so on.
Single step or trap Lowest
Figure 15.5 shows the priority assigned
to the different interrupts in the 8086. Fig. 15.5 Priority among 8086 interrupts
To explain the use of the assigning of
priority among interrupts, consider the following example. Let the INTR interrupt
be enabled in the 8086. Assume that the 8086 receives an INTR interrupt while
executing the division (DIV) instruction. If divide-by-0 occurs during the division
process, the 8086 first executes the ISR of the divide-by-0 interrupt. During this
time, IF and TF are temporarily cleared. This disables the INTR interrupt from
being processed. An IRET instruction at the end of the divide-by-0 ISR again
enables the INTR interrupt by setting IF. This facilitates the 8086 to execute the
ISR of the INTR interrupt, if it is still active.
When the 8086 responds to any interrupt, IF and TF are cleared after the flag
register contents are stored (to save the initial content of the different flags) in the
stack. If needed, IF, TF, or both the flags can be set at the beginning of the ISR of
any interrupt, in case the user wants to enable them while executing the current
ISR.
15.8 INTERRUPT SERVICE ROUTINES

While using an interrupt, the programmer must set its interrupt vector with the CS
and IP addresses of the starting location of the ISR of that interrupt type, either
through the program or externally. The method of defining the ISR for software
and hardware interrupts is the same. This is explained with a few examples.
Example 15.1:
Figure 15.6 shows the interfacing of an ASCII keyboard with the 8086 through a
port in the 8255 having the address FFEOH. When a key is pressed on the keyboard,
the ASCII code of that key is available on its data lines (D7-D0) and the KBINT
pin is pulled low for some time. This causes the NMI input of the 8086 to go high,
thereby interrupting the 8086. In the NMI interrupt’s ISR, the ASCII code of the
key pressed can be read through the 8255.
8086 INTERRUPTS 493
Now, let us write an NMI

ISR such that it stores the ASCII
code of the key pressed in an
array named ASCSTRING,
and after the ASCII codes of 50
keys are received, sets a byte
named DONE to 01H, which
initially has the value OOH.
The main program is used to
initialize the array and the other
variables, and set the interrupt
vector for the NMI interrupt
in the IVT. The ISR is written
such that it can be accessed by
any program module. Fig. 15.6 Interfacing an ASCII keyboard with the 8086
Solution:
ASSUME CS: CODE, DS: DATA, SS: STACK
DATA SEGMENT WORD PUBLIC ; This segment can be accessed by
any other module.
ASC_STRING DB 50 DUP (0) : Reserve 50 bytes for storing the
ASCII codes.
ASC—POINTER DW OFFSET ASC_STRIN ; Pointer to ASCII strin g
CHR_COUNT DB 50 Assign the number of ASCII codes
to CHR_COUNT
DONE DB OOH Initialize DONE to OOH.
DATA ENDS End of the data segment.
STACK SEGMENT Set up the stack segment needed
for handling the interrupt.
DW 100 DUP (0) Reserve 100 words for the stack.
STACK_TOP LABEL WORD Assign the label STACK_TOP to the
top of the stack.
STACK ENDS End of the stack segment.
PUBLIC CHR_COUNT, DONE Make the variables available to
other modules.
EXTRN KEYBRD: FAR KEYBRD procedure (which is the NMI
ISR) is present in another module.
CODE SEGMENT WORD PUBLIC
START: MOV AX, STACK Initialize the SS register with
the segment address of the STACK.
MOV SS, AX
MOV SP, OFFSET STACK_TOP Initialize the SP register.
MOV AX, DATA Initialize the DS register with
the segment address of DATA.
MOV DS, AX ; Store the segment address and offset

address of the KEYBRD procedure in the
interrupt vector table in the addresses
0008H-000BH.
MOV AX, 0000H
MOV ES, AX ; Initialize ES with the segment address
0000H, as the IVT is stored in this
segment.
MOV WORD PTR ES: 000AH, SEG KEYBRD
; Move the segment address to KEYBRD to
the IVT.
MOV WORD PTR ES: 0008H, OFFSET KEYBRD
; Move the offset address of KEYBRD to
the IVT.
HERE: JMP HERE ; Wait until a key is pressed in the
keyboard.
CODE ENDS
END START
; The KEYBRD procedure (i.e., NMI ISR) follows.

DATA SEGMENT WORD PUBLIC : This segment can be accessed by any
other module.
EXTRN CHR_COUNT: BYTE, DONE: BYTE
; These variables are present in another
module.
DATA ENDS ; End of data segment
PUBLIC KEYBRD ; The procedure KEYBRD can be accessed
by some other module.
CODE SEGMENT WORD PUBLIC
KEYBRD PROC FAR ; Beginning of the KEYBRD procedure
PUSH AX ; Store the content of the AX, BX, and
DX registers in the stack.
PUSH BX
PUSH DX
CMP CHR_COUNT, 0 ; Check whether CHR_COUNT = 0.
JZ EXIT ; If it is 0, go to EXIT.
MOV BX, ASC.STRING ; Move the value in ASC_STRING to BX.
MOV OX, OFFEOH ; Store the address of the 8255 port
in DX.
IN AL, DX / ; Get the ASCII code of the key from the
keyboard.
MOV [BX], AL ; Store it in the ASC_STRING array.
INC ASC-POINTER : Increment the value in ASC_STRING
pointer.
8086 INTERRUPTS 495
DEC CHR_COUNT : Decrement CHR_COUNT by 1.

JNZ NOT_DONE ; If CHR_COUNT is not 0, go to N0T_D0NE
MOV DONE, 01 ; Move 1 to DONE to indicate that 50
ASCII codes have been received.
JMP EXIT ; Go to EXIT.
NOT-DONE: MOV DONE, 00 ; Move 0 to DONE.
EXIT: POP DX ; Pop the register contents from the
stack.
POP BX
POP AX
IRET : Return from ISR.
KEYBRD ENDP ; End of ISR
CODE ENDS ; End of segment
END
Example 15.2:
Write a program that displays the message ‘IRQ2 IS WORKING’, in the monitor
of the personal computer (PC), if a hardware interrupt signal appears on the IRQ2
pin present in the I/O channel of the PC, and the message ‘IRQ3 IS WORKING’ if
a hardware interrupt signal appears on the IRQ3 pin present in the I/O channel of
the PC. Make use of the DOS (disk operating system) interrupt INT 21H.
Solution:
When a hardware interrupt signal appears on the IRQ2 pin present in the I/O
channel of the PC, it activates the INTR pin of the CPU (8086). When the CPU
sends the INTA pulse, the interrupt type OAH is supplied to the CPU by the I/O
channel of the PC. Hence, the effect of this action is the same as that of executing
the software instruction INT OAH. Similarly, when a hardware interrupt signal
appears at the IRQ3 pin present in the I/O channel of the PC, it activates the INTR
pin of the CPU (i.e., processor), and when the CPU sends the INTA pulse, the
interrupt type OBH is supplied to the CPU by the I/O channel of the PC. Hence,
the effect of this action is the same as that of executing the software instruction
INT OBH.
The DOS interrupt or function call INT 21H, which comes along with the DOS
program, is used for performing various functions in the PC such as accessing
the printer, monitor, and keyboard, and creating files. Before using INT 21H for
executing a specific instruction, the register AH, DX, or DS, or a combination of
these registers has to be loaded with a specific value. Now the specified operation
is carried out and a particular value is returned in specific registers or in flags, after
the execution of the INT 21H instruction, to reflect the result of the operation.
Main program:
DATA SEGMENT
MESSAGE1 DB “IRQ2 IS WORKING”, OAH, ODH, ”$”
MESSAGE2 DB “IRQ3 IS WORKING”. OAH, ODH, ”$”
DATA ENDS
CODE SEGMENT
START:
MOV AX, CODE
MOV DS, AX ; Set DS with the segment address of
CODE, for setting the IVT.
MOV DX, OFFSET IRQ2_I SR ; Set DX with the offset of IRQ2_ISR.
MOV AX, 250AH ; Set the IVT using the function value
250AH in AX (AH = 25H, AL = OAH
(interrupt type))
INT 21H ; Call the DOS interrupt INT 21H to set
the IVT.
MOV DX, OFFSET IRQ3_ISR ; Set DX with the offset address of
IRQ3_ISR.
MOV AX, 250BH ; Set IVT using the function value 250BH
in AX (AH = 25H, AL = OBH (interrupt
type)).
INT 21H ; Call the DOS interrupt INT 21H to
set the IVT.
HERE: JMP HERE
IRQ2_ISR PROC NEAR
MOV AX, DATA
DATA.
MOV DX, OFFSET MESSAGE1 : Set DX with the offset of MESSAGE1.
MOV AH, 09H ; Display MESSAGEl in the monitor.
INT 21H
IRET ; Return from ISR.
IRQ2_ISR ENDP
IRQ3_ISR PROC NEAR
MOV AX, DATA
DATA.
MOV DX, OFFSET MESSAGE2 ; Set DX with the offset of MESSAGE2.
MOV AH, 09H ; Display MESSAGE2 in the monitor.
INT 21H
IRET ; Return from ISR.
IRQ3_ISR ENDP
CODE ENDS
END START
In this program, a data segment is first defined with the messages to be displayed
in the monitor of the PC when the interrupt signal is given in the I/O channel of
the PC. Then, storing the segment address of CODE in the DS, the offset address
of the ISR (IRQ2_LSR) in the DX, the function value 250AH in AX (i.e., AH =
25H and AL = OAH (interrupt type)), and by using the DOS interrupt INT 21H,
8086 INTERRUPTS 497
the interrupt vector for the interrupt type OAH is created in IVT. Similarly, the
interrupt vector for the interrupt type OBH is created in the IVT. In the IRQ2 ISR,
the segment address of DATA is placed in DS, the offset address of MESSAGE 1
is placed in DX, AH is loaded with the value 09H, and by calling the DOS interrupt
INT 21H, MESSAGE 1 is displayed in the monitor of the PC. A similar procedure
is used in IRQ3_ISR as well.
The OAH, ODH, and $ characters given in MESSAGEl and MESSAGE2
represent the ASCII code of line feed (LF), ASCII code of carriage return (CR),
and end of string, respectively.
Example 15.3:
Write a program to create a file named AGE in the PC and store 100 bytes of data
in it, which have to be taken from the memory block starting at 3000H: 2000H,
if the software instruction INT OAH is executed by the PC. Make use of the DOS
interrupt INT 21H.
Solution:
DATA SEGMENT
FILENAME DB “AGE”, “$”
MESSAGE DB “FILE CREATION WAS NOT SUCCESSFUL", OAH, ODH,”$”
DATA ENDS
CODE SEGMENT
START:
MOV AX, CODE
CODE, for setting the IVT.
MOV DX, OFFSET ISR ; Set DX with the offset address of
ISR.
MOV AX, 250AH ; Set the IVT using the function value
250AH in AX.
INT 21H ; Execute the DOS interrupt INT 21H to
set the IVT.
MOV DX, OFFSET FILENAME ; Set DX with the offset address of
FILENAME.
MOV AX, DATA
MOV DS, AX ; Load the segment address of DATA in
DS.
MOV CX, OOH
MOV AH , 3CH
INT 21H ; Create a file with the file name ‘AGE’,
using INT 21H.
JNC SUCCESS ; If there is no carry, the file creation
operation was successful. So go to the
location SUCCESS.
MOV DX. OFFSET MESSAGE ;; If there is a carry, display the

message using INT 21H.
MOV AH, 09H
INT 21H
JMP END1
SUCCESS: INT OAH ; Execute the software INT OAH instruction
to write the data into the file.
END1: MOV AH, 4CH ; Return to DOS prompt.
INT 21H
; ISR for interrupt type OAH is as follows:
ISR PROC NEAR
MOV BX, AX ; Take the file handle information in
AX to BX.
MOV CX, 100 ; Move the number of bytes to be
transferred, to CX.
MOV DX, 2000H ; Store the offset address of the data
to be moved into the file in DX.
MOV AX, 3000H ; Store the segment address of the data
to be moved into the file in AX.
MOV DS, AX ; Move the segment address in AX to
DS.
MOV AH, 40H ; Using INT 21H, write the data into the
file.
INT 21H
IRET
ISR ENDP
CODE ENDS
END START
In this program, a data segment is first defined with the file name to be assigned
to the file and the message to be displayed in the monitor, if the file creation is not
successful. Then, storing the segment address of CODE in DS, the offset address
of the ISR in DX, and the function value 250AH in AX (i.e., AH = 25H and AL
= OAH (interrupt type)), and by using the DOS interrupt INT 21H, the interrupt
vector for the interrupt type OAH is created in the IVT. Next, storing the offset
address of the file name in DX, the segment address of DATA in DS, OOH in CX,
and 3CH in AX, and by using the DOS interrupt INT 21H, the file named AGE is
created.
If the file creation operation is successful, the carry flag is cleared after the
execution of INT 21H and the AX register is loaded with the file handle information.
Otherwise, the carry flag is set. If the carry flag is cleared, the processor goes to the
location named SUCCESS in the program and executes the INT OAH instruction,
which causes the execution of the ISR, to store 100 bytes of data taken from the
memory block starting at 3000H: 2000H into the file. If the carry flag is set after
the execution of INT 21H, the processor executes INT 21H with DX having the
8086 INTERRUPTS 499
offset address of the message and AH having the value 09H, to display the message
‘FILE CREATION WAS NOT SUCCESSFUL’ in the monitor of the PC.
In the ISR, the file handle information in AX is first transferred to BX, followed
by the loading of CX with the number of data bytes to be stored into the file.
Then DX and DS are loaded with the offset address and the segment address,
respectively, of the memory block from where the data is to be taken. By loading
AH with the value 40H and by using INT 21H, data is moved into the file.
15.9 BIOS INTERRUPTS OR FUNCTION CALLS

The BIOS (basic input/output system) is boot firmware, which is designed to be
the first program run by a PC when powered on. The initial function of the BIOS
is to identify, test, and initialize system devices such as the video display card,
hard disk, floppy disk, and other hardware. The BIOS prepares the machine for a
known state, so that the software stored on the compatible media can be loaded,
executed, and given control of the PC. BIOS function calls, also known as BIOS
interrupts, are stored in the system ROM and in the video BIOS ROM present in
the PC. These BIOS function calls directly control the I/O devices with/without
DOS loaded in the system. Some BIOS function calls that are used to control the
monitor (video), disk, COM port, I/O devices, keyboard, and printer in the PC are
briefly discussed in this section.
15.9.1 INT10H
The INT 10H BIOS interrupt, which is also called video services interrupt, directly
controls the video display in a system. INT 10H uses register AH to select the
video service provided by this interrupt. The video BIOS ROM is located on the
video board and varies from one video card to another used in the PC.
15.9.1.1 Video Mode Selection
The mode of operation for the video display is selected by placing OOH in AH,
followed by one of the mode numbers in AL. Table 15.1 shows the mode of
operation found in VGA (video graphics array) type video display systems using
standard video modes.
Table 15.1 Video display modes
Mode Columns Rows Type Resolution Colours

OOH 40 25 Text 360 x 400 2
01H 40 25 Text 360 x 640 16
02H 80 25 Text 720 x 400 2
03H 80 25 Text 720 x 400 16
07H 80 25 Text 720 x 400 4
UH 80 30 Graphics 640 x 480 2
12H 80 30 Graphics 640 x 480 16
J3H 40 25 Graphics 320 x 200 256

The set of instructions used to place the video display in mode 2 is as follows.
After the instructions are executed in the PC, the mode of the display is changed
and the screen is cleared.
MOV AH, OOH Video mode service
MOV AL, 02H Select mode 2.
INT 10H Call BIOS interrupt.
To know the current video mode used in the display, AH is set to OFH and
INT 1OH is executed. After execution, AL has the current video mode, AH has the
number of character columns, and BH has the page number. The instructions are
as follows:
MOV AH, OFH ; Select read video mode.
INT 10H ; Call BIOS interrupt.
If an SVGA (super VGA) or an Table 15.2 Extended VGA functions

EVGA/XVGA (extended VGA)
adapter is available, the SVGA BX Extended mode
mode is set by using the INT 1OH 100H 640 x 400 with 256 colours
interrupt with AX = 4F02H and
101H 640 x 480 with 256 colours
BX = VGA mode. This conforms
to the VESA (Video Electronics 102H 800 x 600 with 16 colours
Standards Association) standard 103H 800 x 600 with 256 colours
for VGA adapters. VESA is an 104H 1024 x 768 with 16 colours
international standards body for
105H 1024 x 768 with 256 colours
computer graphics, founded in 1989
by NEC Home Electronics and 106H 1280 x 1024 with 16 colours
eight other video display adapter 107H 1280 x 1024 with 256 colours
manufacturers. Table 15.2 shows 108H 80 x 60 in text mode
the modes selected by the register
109H 132 x 25 in text mode
BX for this INT 1OH interrupt.
Most video cards are equipped with 10AH 132 x 43 in text mode
the driver called VVESA.COM or 10BH 132 x 50 in text mode
WES A.SYS, which ensures that
10CH 132 x 60 in text mode
the card conforms to the VESA
standard functions.
15.9.1.2 Cursor Control
The INT 10H interrupt is also used for cursor control in the video display (i.e.,
monitor). Table 15.3 shows the function codes placed in AH, which are used to
control the cursor on the video display. The code is shown in the Entry field and
the result obtained after execution of INT 10H is shown in the Exit field. These
cursor control functions work on a wide range of video displays—from the VGA
display to the latest SVGA display.
8086 INTERRUPTS 501
Table 15.3 Functions provided by INT 10H for cursor control
Function Entry Exit
Select cursor type AH = 01H Cursor size changed

CH = Starting line number
CL = Ending line number
Select cursor AH = 02H
position BH = Page number (usually 0)
DH = Row number (beginning with 0)
DL = Column number
(beginning with 0)
Read cursor AH = 03H CH = Starting line number
position BH = Page number (cursor size)
CL = Ending line number
(cursor size)
DH = Current row
DL = Current column
Read attribute/ AH = 08H AL = ASCII character
character at current BH = Page number code
cursor position AH = Character attribute
(Note: This function does
not advance the cursor.)
Write attribute/ AH = 09H (Note: This function does
character at current AL = ASCII character code not advance the cursor.)
cursor position BH = Page number
BL = Character attribute
CX = Number of characters to write
Write character AH = OAH (Note: This function does

at current cursor AL = ASCII character code not advance the cursor.)
position BH = Page number
CX = Number of characters to write
15.9.2 INT11H
This interrupt is used to determine the type of equipment installed in the system.
To use this interrupt, the AX register is loaded with FFFFH and then the INT
11H instruction is executed. In return, INT 11H provides information in the AX
register, as given in Fig. 15.7.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BitO
P1 PO G S2 S1 SO D2 D1
Fig. 15.7 Content of AX register after execution of INT 11H
P1 and P0 = Number of parallel ports G = 1, if game I/O is attached

S2, S1, and SO = Number of serial ports D2 and D1 = Number of disk drives
15.9.3 INT12H
The memory size present in the system is obtained by the INT 12H interrupt.
After executing the INT 12H instruction, the AX register contains the number of
1 KB blocks of memory (conventional memory in the first 1 MB of address space)
installed in the computer.
15.9.4 INT13H
This interrupt controls diskettes that are within 5.25 or 3.5 inches in size and
also hard disk drives attached to the system. Table 15.4 shows the functions
available to this interrupt via register AH. The direct control of the hard disk drive
by a programmer using INT 13H leads to problems, including the alteration or
corruption of important programs such as operating system programs, compilers,
and other software that are stored on the disk. This may result in system failure.
Only upon reinstallation of the operating system programs in the hard disk will the
PC function normally. This wastes a lot of time for the programmer. Therefore, the
functions are listed without details about their usage. Before using these functions,
the BIOS literature available from the company that produced the particular
version of the BIOS ROM in the system should be referred to.
15.9.5 INT14H
The INT 14H interrupt controls the serial COM (communication) ports attached
to the computer. There are two COM ports—COM1 and COM2—in a computer
system. In newer AT style machines, the number of COM ports is extended to
four (including COM3 and COM4). Communication ports are normally controlled
using software packages that allow programming of microcontrollers/digital signal
processors (DSPs) serially, or by transmitting and receiving data through a modem
and a telephone line. The INT 14H instruction is used to control these ports, as given in
Table 15.5.
15.9.6 INT15H
The INT 15H interrupt controls various I/O devices interfaced with the computer.
It also allows access to protected mode operation and the extended memory system
on an 80286, Pentium Pro, etc., but it is not recommended for use by the normal
user; it is commonly used by programmers to develop OS-related programs. The
functions provided by INT 15H are given in Table 15.6.
15.9.7 INT16H
The INT 16H interrupt is used to control the keyboard in a system. This interrupt is
usually accessed by the DOS interrupt INT 21H, but can also be accessed directly.
Table 15.7 indicates the functions provided by INT 16H.
15.9.8 INT17H
The INT 17H interrupt accesses the parallel printer port, called LPT 1 in most systems.
Table 15.8 shows the functions provided by INT 17H.
8086 INTERRUPTS 503
Table 15.4 Functions provided by INT 13H Table 15.6 Functions provided by INT 15H
AH Function AH Function
OOH Reset the system disk OOH Cassette motor on
01H Read disk status to AL 01H Cassette motor off
02H Read sector 02H Read cassette
03H Write sector 03H Write cassette
04H Verify sector OFH Format ESDI periodic
05H Format track interrupt
06H Format bad track 21H Keyboard intercept
07H Format drive 80H Device open
08H Get drive parameters 81H Device closed
09H Initialize fixed disk 82H Process termination
characteristics
83H Event wait
OAH Read long sector
84H Read joystick
OBH Write long sector
85H System request key
OCH Seek
86H Delay
ODH Reset fixed disk system
87H Move extended block of
OEH Read sector buffer
memory
OFH Write sector buffer
88H Get extended memory size
1OH Get drive status
89H Enter protected mode
11H Re-calibrate drive
90H Device wait
12H Controller RAM diagnostics
91H Device power on self test
13H Controller drive diagnostics (POST)
14H Controller internal diagnostics COH Get system environment
15H Get disk type C1H Get address of extended BIOS
16H Get disk changed status data area
17H Set disk type C2H Mouse pointer
18H Set media type C3H Set watchdog timer
19H Park heads C4H Programmable opinon
1AH Format ESDI drive select
Table 15.5 Functions provided by INT 14H
AH Function
OOH Initialize communications port
01H Send character
02H Receive character
03H Get COM port status
04H Extended initialize communications port
05H Extended communications port control
Table 15.7 Functions provided by INT 16H Table 15.8 Functions provided by INT 17H
AH Function AH Function
OOH Read keyboard character OOH Print character

01H Get keyboard status 01H Initialize printer
02H Get keyboard flags 02H Get printer status
03H Set repeat rate
04H Set keyboard click
05H Push character and scan code
POINTS TO REMEMBER
■ An interrupt is an external or internal event in a microprocessor that diverts it from the

execution of the main program, to another program called the interrupt service routine
(ISR).
■ The interrupt can be either a hardware interrupt or a software interrupt. The 8086 has
two hardware interrupts—NMI and INTR. The software interrupt is created in the 8086
using the INT instruction.
■ There are 256 interrupt types available in the 8086 and the interrupt vector for each
type, which is four bytes long, is stored in an interrupt vector table (IVT) from address
00000H in the memory.
■ Whenever an interrupt is received, the 8086 saves the current value of IP, CS, and the
flag register in the stack, clears TF and IF, and loads CS and IP with the interrupt vector
corresponding to the received interrupt type. This causes the 8086 to start the execution
of the ISR.
■ The IRET instruction at the end of the ISR makes the 8086 return to the main
program.
■ There exist different levels of priority among the interrupts, and if two interrupts appear
simultaneously in the 8086, the interrupt having higher priority is serviced first.
■ BIOS function calls (also called BIOS interrupts) are stored in the system ROM and the
video BIOS ROM present in the PC. These BIOS function calls directly control the I/O
devices with/without the DOS (disk operating system) loaded in the system.
KEY TERMS
Hardware interrupt It is an interrupt generated by activating the interrupt pin of the

microprocessor.
Interrupt vector It is a four-byte entry in the IVT, which contains a 16-bit offset part
and a 16-bit segment part that are loaded in the IP and CS registers, respectively, when an
interrupt is received.
Interrupt vector table (IVT) It is a table in the memory that contains the interrupt
vectors of the different interrupts.
8086 INTERRUPTS 505
INTR It is a maskable hardware interrupt in the 8086 that can be enabled/disabled using
the I flag.
Non-maskable interrupt (NMI) It is an interrupt that cannot be disabled by software.
Software interrupt It is an interrupt generated by the execution of the software interrupt
instruction in the microprocessor.
Trap interrupt It is used for performing single-step operations in the 8086 and can be
enabled/disabled using the T flag.
REVIEW QUESTIONS
1. What is the function of an interrupt in a microprocessor?

2. What is the difference between maskable and non-maskable interrupts?
3. What is the difference between hardware and software interrupts?
4. How many interrupt types are present in the 8086 and how they are classified?
5. Name the dedicated interrupts in the 8086 along with their functions.
6. What are the differences between INTR and NMI interrupts in the 8086?
7. How does the 8086 recognize an NMI interrupt?
8. What is the function of the T and I flags in the 8086 and how can they be set/reset?
9. Write the sequence of steps performed by the 8086 when it receives an interrupt other
than INTR.
10. How does the 8086 return to the main program after completing the ISR of an
interrupt?
11. What is an interrupt vector? What is the maximum number of interrupt vectors that
can be stored in the IVT of the 8086?
12. How is a software interrupt generated in the 8086?
13. What is the function of the INTO instruction?
14. What are the advantages of software interrupts?
15. Write the priority among the interrupts in the 8086.
16. Explain the interrupt structure of the 8086 in detail.
17. With the necessary timing diagram, explain the processing of the INTR interrupt by
the 8086.
18. Draw the diagram showing the supply of the interrupt type 80H through an 8-bit DIP
switch and the 74244 IC, when the 8086 receives the INTR interrupt.
19. List the BIOS interrupts used to select the video mode and cursor control in the
computer monitor.
20. What are the BIOS interrupts used to control the keyboard and the COM port?
THINK AND ANSWER
1. For what purpose is the NMI interrupt commonly used in an 8086-based system?
2. What is the minimum duration for which the INTR signal must be kept high for being
recognized by the 8086?
3. Is it possible to store the IVT starting from the address 20000H in the memory of the
8086? Why?
4. If the ISR of interrupt type 0 is stored from the memory address 2000: 3000H, what is
the segment and offset part of the interrupt vector?
5. If the ISR of interrupt type 40H is stored from the memory address 8000: 4500H, what
is the segment and offset part of the interrupt vector?
6. Is it possible to enable the INTR and the trap interrupts again when the 8086 starts
executing the ISR of an interrupt? How?
7. How does the 8086 obtain the specific interrupt type when it receives the INTR
interrupt?
8. If the interrupt type allotted for the interrupt IR0 is 70H in the 8259, what is the
interrupt type allotted for IR2 and IR4?
9. How can the breakpoint technique for debugging a program be implemented in the
8086?
10. Is it possible to access the divide-by-0 ISR by using a software interrupt in the 8086?
How?
11. If both INTR and NMI occur simultaneously in the 8086, which interrupt is processed
first? Why?
1. Write an 8086 ISR to add the byte type data stored in an array starting at the address
2000H: 5000H in the memory with the corresponding data in another array stored in the
memory starting at the address 3000H: 5000H and store the result in another array in
the memory starting at the address 4000H: 5000H, when the NMI interrupt is given to
the 8086. The number of byte type data in the array is 100. Assume that the result after
addition of all the data in the array is an 8-bit data. The ISR must be accessible by any
module.
2. Write an 8086 ISR to send the byte type data stored in the address 6000H: 5000H in the
memory, to port A in the 8255, whose address is FF00H, when the IRQ2 interrupt in the
I/O channel of the PC is activated.
3. Write an 8086 ISR to receive byte type data through port B of the 8255, whose address
is FF01H. Store the data in the address 7000H: 5000H in the memory, when the software
interrupt INT 0BH is executed by the PC.
CHAPTER 16
MEMORY AND I/O INTERFACING

LEARNING OUTCOMES
• Physical memory organization in the 8086
• Generation of separate address and data buses in the 8086
• Interfacing RAM and EPROM chips with the 8086
• Difference between l/O-mapped and memory-mapped I/O
• Interfacing I/O devices with the 8086
16.1 PHYSICAL MEMORY ORGANIZATION IN 8086

Since the 8086 has 20 address lines, it can access 1 MB (= 220 bytes) of memory.
The memory addresses in the 1 MB memory range from 00000H to FFFFFH. The
memory is constructed using RAM and ROM/EPROM chips. The 1 MB memory
in the 8086 is physically organized as an odd bank and an even bank, where each of
the 512 KB (= 1MB/2) is addressed in parallel by the 8086. Each memory location
stores one byte of data. The byte data at an even memory address is transferred
through the 8-bit data bus D7-D0, while the byte data at an odd memory address
is transferred through the 8-bit data bus D15-D8. The 8086 provides two enable
signals, BHE and A0, for the selection of odd banks and even banks, respectively.
Figure 16.1 shows the physical memory organization in the 8086. The 8086 is a
16-bit processor and hence it can transfer two bytes of data in one memory read/
write cycle (or I/O read/write cycle).
Address Address
00000H
00002H
00004H
FFFFEH
Fig. 16.1 Physical memory organization in the 8086

Two memory locations are needed to store a word in the memory in an 8086
system. While reading or writing word data (16 bits), the bus interface unit of the
8086 requires one or two memory cycles, depending upop whether the lower-
order byte of the word is located at an even or odd memory address, respectively.
It is better to store the word type data in the memory such that its lower-order byte
is stored at an even memory address, since only one read cycle is required to read
the data through the 16-bit data bus (D15-D0) of the 8086. If the lower-order byte
of the word is located at an odd memory address, the first read cycle is required
for accessing the lower-order byte of the word through the higher-order data bus
(D15-D8), and the second is required for accessing the higher-order byte of the
word through the lower-order data bus (D7-D0). Thus, two bus cycles are required
to access a word whose lower-order byte is stored in an odd memory address in the
memory. While initializing data structures such as an array of word type data or a
stuck, they should be initialized at an even address for efficient operation. This is
also applicable to the memory write operation.
The use of the BHE and AO signals to fetch data or instruction from the memory
and to write data in the memory is given in Table 16.1.
Table 16.1 Function of BHE and AO signals
BHE AO Operation
0 0 16-bit data is read from or written into the memory.
0 1 8-bit data is read from or written into the odd memory bank.
1 0 8-bit data is read from or written into the even memory bank.
1 1 Memory is not accessed.
The BHE and AO signals, along with a few higher-order address lines of the
8086, are used to generate the Chip Select (CS) or Chip Enable (CE) signal for
different memory chips.
1 6.2 FORMATION OF SYSTEM BUS

The 8086 has a multiplexed 16-bit address/data bus (AD15-AD0) and a
multiplexed 4-bit address/status bus (A19/S6-A16/S3). The multiplexed address
bus can be split into a separate address bus and data bus/status bus, using the
Address Latch Enable (ALE) signal of the 8086 and three external octal latches
(IC 74373). Figure 16.2 shows the de-multiplexing of the address bus and the data
bus using the 74373 ICs.
The data bus can be buffered using two bidirectional buffers (74245). Since
the data can flow in either direction (i.e., from and into the microprocessor) while
accessing the memory or I/O devices, the bidirectional buffers are used for deriving
the data bus. The signals DEN and DT/R indicate the presence of data on the bus
and the direction of the data (i.e., from/to the microprocessor), respectively. They
are connected to the chip enable and direction pins of the buffers, as shown in
Fig. 16.3.
MEMORY AND I/O INTERFACING 509
Fig. 16.2 De-multiplexing the address bus and data bus
Fig. 16.3 Buffering the data bus of the 8086 using IC 74245
If DEN is low, it indicates that the data is available on the multiplexed address/
data bus (ADO-AD 15). Both the bidirectional buffers (74245s) are enabled to
transfer that data since their enable inputs are activated at that time. When the DIR
pin goes high, the data available at the X pins of the 74245 are transferred to the Y
pins, i.e., data is transmitted from the 8086 to either the memory or the I/O device
(write operation). If the DIR pin goes low, the data available at the Y pins of the
74245 are transferred to the X pins, i.e., data is received by the microprocessor
from the memory or the I/O device (read operation). For generating the Memory
Read (MEMR) and Memory Write (MEMW) control signals, the RD, WR, and
M/TO signals of the 8086 are used along with the combinational circuit (as shown
in Fig. 16.4) during the minimum operation of the 8086. In the case of maximum
mode operation of the 8086, a bus controller chip (8288) derives all the memory
control signals using the status signals SO, Si, and S2.
Certain locations in the memory are reserved for specific CPU operations.
After resetting the 8086, CS and IP are initialized to FFFFH and 0000H,
Fig. 16.4 Generation of control signals for the memory in the 8086
respectively; the first instruction for execution is taken from the address FFFFOH
in the memory. Hence, the locations from FFFFOH to FFFFFH in the memory are
reserved for storing instructions, execution of which causes the 8086 to jump to
the initialization program of the system. The memory locations 00000H-003FFH
are reserved for the interrupt vector table. These memory locations are assigned to
the ROM/EPROM chips in an 8086-based system, so that the programs stored in
them are permanent. The interrupt vector table may be located in the RAM chips
in some systems. The memory chips can be interfaced with the 8086 using only
logic gates, or using both logic gates and the decoder IC 74138. This is explained
in Sections 16.3 and 16.4.
1 6.3 INTERFACING RAM AND EPROM CHIPS USING ONLY LOGIC GATES
When RAM and ROM/EPROM chips with the same or different storage capacities
have to be interfaced with the 8086, it can be easily done using logic gates. The
following example illustrates this concept.
Example 16.1:
Interface two 8K x 8 EPROMs (2764) and two 8K x 8 RAM chips (6264) with the
8086 using logic gates, such that the memory address ranges assigned to them are
FC000H-FFFFFH and 00000H-03FFFH, respectively.
Solution:
First, let us see the interfacing of the two 8K x 8 EPROM chips with the 8086,
so that they have the address range FC000H-FFFFFH. The addresses FC000H-
FFFFFH are given in binary form in Table 16.2.
Table 16.2 Memory addresses assigned to the EPROM chips
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AO Address
1 1 1 1 1 1 00000000000000 FC000H
1 1 1 1 1 1 00000000000001 FC001H
1 1 1 1 1 1 00000000000010 FC002H
1 1 1 1 1 1 00000000000011 FC003H
11111111111111111111 FFFFFH
It can be noted from Table 16.2 that even addresses such as FCOOOH, FC002H,
and FC004H are assigned to one 8K x 8 EPROM chip (say, 2764-A), which acts as
an even memory bank and odd addresses such as FC001H, FC003H, and FC005H are
assigned to another 8K x 8 EPROM chip (say, 2764-B), which acts as an odd memory
bank. Since the address line AO is 0 for all even addresses, it is used to generate the
Chip Select or Chip Enable signal for 2764-A, along with some of the higher-order
address lines of the 8086. Similarly, BHE is used along with some of the higher-order
address lines of the 8086 to select the odd memory bank formed by 2764-B.
First, the number of address lines in the 8K x 8 EPROM chip is noted, which is
13 (A12-A0) since 213= 8K. The address lines A 1-Al3 of the 8086 are connected
to the address lines A0-A12 of 2764-A and 2764-B, since the address line AO
of the 8086 is used for selecting the even memory bank. The remaining address
lines A19-A14 of the 8086 are used for address decoding. Figure 16.5 shows the
interfacing of two EPROM chips with the 8086.
Fig. 16.5 Interfacing EPROMs with the 8086 using logic gates
Since all the address lines A 14-Al9 are 1 for the addresses FC000H-FFFFFH,
these address lines are directly connected to an AND gate to produce the output
‘1’. The AND gate output and the inverted A0 signal are given to a NAND gate
and the output of this NAND gate is connected to the chip enable pin of 2764-A,
which is the even memory bank. Similarly, the same AND gate output and the
inverted BHE signal are given to another NAND gate, whose output is used to
select the 2764-B chip, which is the odd memory bank.
I
When the 8086 wants to access a byte from any odd address in the address
range FC000H-FFFFFH, the value in the address lines A 1-Al3 of the 8086 is
used to select one of the locations within 2764-B, as A 1-Al3 of the 8086 are
connected to A0-A12 of 2764-B. The address lines A 14-Al9 contain the value
1, which makes the AND gate output 1. The 8086 now activates the BHE signal
(i.e., BHE is made 0), due to which the CE pin of 2764-B goes low and is selected.
Since A0 = 1 for odd memory addresses (as it is the LSB of the address), CE of
2764-A is high and is not selected.
When the 8086 wants to access a byte from any even address in the address
range FC000H-FFFFFH, the values in the address lines A 1-Al3 and A14-Al9
are used for the purposes we have just discussed. Now, the address line A0 is 0
while the 8086 sends out an even address. BHE is made 1 by the 8086. Due to
this, CE of 2764-A is made low and is selected. Since BHE = 1, CE of 2764-B is
in high state and is not selected. While accessing a byte from either an odd or an
even memory bank, the 8086 activates MEMR after sending the memory address
to get the data.
When a word (16-bit data) whose lower-order byte is stored in an even address
is accessed by the 8086, both A0 and BHE are made 0, due to which both the chips
are selected. One byte from each memory bank is placed in the data bus (D15-D0)
when the 8086 activates the MEMR signal. The 8086 processor then reads the
entire word in the data bus. For example, if the 8086 wants to read the word whose
lower-order byte is stored in the address FFFFEH, all the address lines (Al-A 19)
of the 8086 contain 1. A0 and BHE are made 0. This makes the A0-A12 lines of
both the memory chips 1 and the CE input to both the chips 0. Due to this, the data
in the last memory location in both the chips are placed in their data buses, when
the MEMR signal is activated by the 8086.
Now, let us discuss the interfacing of the two 8K * 8 RAM chips with the 8086,
so that they have the address range 00000H-03FFFH. The addresses 00000H-
03FFFH are given in binary form in Table 16.3.
Table 16.3 Memory addresses assigned to the RAM chips
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address
00000000000000000000 00000H
00000000000000000001 00001H
00000000000000000010 00002H
00000000000000000011 00003H
000000 1 1 1 1 1111111110 03FFEH

0000001 1 1 1 1111111111 03FFFH
The even addresses such as 00000H and 00002H are assigned to one 8K x 8 RAM
chip (say, 6264-A), which acts as an even memory bank and the odd addresses
such as 00001H and 00003H are assigned to another 8K x 8 RAM chip (say, 6264-
B), which acts as an odd memory bank.
As discussed in the interfacing of the EPROM chip, the inverted AO line
and the output of the address decoder formed using the AND gate are given to a
NAND gate, and the NAND gate’s output is connected to the CE input of 6264-A.
The inverted BHE line and the same address decoder output are given to another
NAND gate, and the output of that NAND gate is connected to the CE input of
6264-B. The interfacing of the RAM chips with the 8086 is shown in Fig. 16.6.
Fig. 16.6 Interfacing RAM chips with the 8086 using logic gates
Since the address lines A 14-Al 9 contain 0 for the addresses 00000H-03FFFH,
the signals in these lines are inverted and then given to the AND gate, so that
they produce an output of 1 for the same addresses. This AND gate output and
the inverted A0 signal through the NAND gate activate the CE input of the even
memory bank. The same AND gate output and the inverted BHE signal activate
the CE input of the odd memory bank. The CE input of both the memory chips are
activated when the 8086 wants to access a word whose lower-order byte is stored
in the even memory bank.
The MEMR signal of the 8086 is connected with the OE (Output Enable) input.
The 8086 activates the MEMR signal while reading a byte or word from the RAM,
after sending the address through the address bus. The MEMW signal of the 8086
is connected with the WE (Write Enable) input. The 8086 activates the MEMW
signal while writing a byte or word in the RAM after sending the address through
the address bus and placing the data in the data bus.
514 MICROPROCESSORS AND MICROCONTROLLERS I
16.4 INTERFACING RAM/EPROM CHIPS USING DECODER IC AND LOGIC

GATES
When RAM/EPROM chips with the same storage capacity have to be interfaced
with the 8086, the interfacing can be easily done using a decoder IC and logic
gates. The following examples illustrate this concept.
Example 16.2:
Interface two 8K x 8 EPROM chips with the 8086, such that the memory address
range assigned to them is FC000H-FFFFFH, using an address decoder made up
of the 74138 IC and logic gates.
Solution:
The 13 address lines A0-A12 in the 2764 are connected to the address lines
A 1-Al3 of the 8086. For the entire address range FC000H-FFFFFH, the value
in the address lines A 19-Al4 is equal to 1. The address lines A 19-Al5 are used
to enable the 74138 decoder IC, and the address lines A14, AO, and BHE are
connected to the selection lines of the 74138 IC.
Figure 16.7 shows the interfacing of the EPROM chips with the 8086 chips
using the 74138 decoder. For simplification, only the decoder and EPROM chips
are shown in the figure. The connection of the EPROM chips with the 8086 is the
same as in Example 16.1.
Y5 Y1'^. r. _>rY3 Y1
। । Decoder"^ । ।
Fig. 16.7 Interfacing EPROM chips with the 8086 using 74138 decoder
When the address lines A19-A14 are 1, the decoder is enabled. The selection
of a particular EPROM chip under that condition is explained in Table 16.4.
When we want to interface more RAM and EPROM chips of the same capacity
with the 8086, we can use two separate decoders (74138), one for accessing the
lower bank and the other for accessing the upper bank. A0 and BHE are used to
enable the two decoders.
Table 16.4 Selection of EPROM chips
CE OF CE OF
BHE AO A14 Y5 Y3 Y1 Operation
2764-A 2764-B
0 0 1 1 1 0 0 0 A word is read from the memory.
0 1 1 1 0 1 1 0 A byte is read from the odd memory bank.
1 0 1 0 1 1 0 1 A byte is read from the even memory bank.
Example 16.3:
Interface four 8K x 8 RAM chips (6264) with the 8086, to assign the address range
80000H-87FFFH using two 74138 ICs.
Solution:
The addresses assigned to various memory chips are written in binary form as
Table 16.5 Addresses assigned to various memory chips
Address in
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AO
hex
(For
6264-IL)
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80000H
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 80002H
100000 1 1 1 1 1111111110 83FFEH

(For
6264-1H)
1 0 0 0 0 0 0 0 0 0 0000000001 80001H
1 0 0 0 0 0 0 0 0 0 0000000011 8OOO3H
100000 1 1 1 1 1111111111 83FFFH
(For
6264-2L)
1 0000 1 00000000000000 84000H
1 0000 1 00000000000010 84002H
j 0000 1 1 1 1 1 1111111110 87FFEH

(Contd)
Table 16.5 Addresses assigned to various memory chips (Contd)
Address in
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AO 1
nex
(For
6264-2H)
1 0000 1 00000000000001 84001H
1 0000 1 00000000000011 84003H
100001 1 1 1 1 11111111 1 87FFFH
Here, 6264-IL and 6264-2L are the RAM chips forming the lower banks.
6264-1H and 6264-2H are the 6264 RAM chips forming the higher banks.
For simplification, only the decoder and RAM chip connections are shown in
Fig. 16.8. The connection of the RAM chips with the 8086 is as explained in
Example 16.1.
pig. 16.8 Interfacing RAM chips using two 74138 decoders

The data for selection of the different chips is shown in Table 16.6.
Table 16.6 Data for selection of different RAM chips
A19 A18 A17 A16 A15 A14 A0 BHE RAM chips and byte/word
selected
1 0 0 0 0 0 0 0 6264-IL and 6264-1H;
a word is read/written
1 0 0 0 0 0 0 1 6264-IL; a byte is read/
written
1 0 0 0 0 0 1 0 6264-1H; a byte is
read/written
1 0 0 0 0 1 0 0 6264-2L and 6264-2H;
a word is read/written
1 0 0 0 0 1 0 1 6264-2L: a byte is read/
written
1 0 0 0 0 1 1 0 6264-2H: a byte is
read/written
16.5 I/O INTERFACING

In this section, the operation of I/O instructions (IN and OUT), the concept of I/O-
mapped I/O and memory-mapped I/O, and the interfacing of simple I/O devices
such as DIP switches and LEDs with the 8086 are discussed.
16.5.1 I/O Instructions in 8086

The IN instruction is used to read data from an input device to AL or AX in the
8086. The OUT instruction is used to send the data in AL or AX to an output
device. The I/O device’s address is stored either in the register DX as a 16-bit I/O
address or in the byte immediately following the opcode of the IN/OUT instruction
as an 8-bit I/O address. Table 16.7 lists all versions of the IN and OUT instructions
in the 8086.
Whenever data are transferred using the IN or OUT instruction, the I/O device’s
address, often called port number, appears on the address bus. The external I/O
interface decodes this address to select a particular I/O device. The 8-bit fixed port
number appears on the address lines A7-A0, with the address lines A15-A8 as
OOH. The address lines A15-A19 are undefined for an I/O instruction. The 16-bit
port number in DX appears on the address lines A15-A0.
Table 16.7 Input/output instructions in the 8086
Instruction Operation
IN AL, XXH Read a byte from the input device with address XXH and store it
in AL.
(Contd)
Table 16.7 Input/output instructions in the 8086 (Contd)
Instruction Operation
IN AL, DX Read a byte from the input device with the address specified by
DX and store it in AL.
IN AX, XXH Read a word from the input device with the address XXH and
store it in AX.
IN AX, DX Read a word from the input device with the address specified by
DX and store it in AX.
OUT XXH, AL Send a byte from AL to the output device with the address XXH.
OUT DX, AL Send a byte from AL to the output device with the address
specified by DX.
OUT XXH, AX Send a word from AX to the output device with the address XXH.
OUT DX, AX Send a word from AX to the output device with the address
specified by DX.
16.5.2 l/O-mapped and Memory-mapped I/O

Similar to the 8085, there are two methods for interfacing I/O devices with the
8086—I/O-mapped I/O and memory-mapped I/O schemes. In I/O-mapped
I/O scheme, the IN and OUT instructions are used to transfer data between the
microprocessor and the I/O devices. In memory-mapped I/O, any instruction that
references the memory can be used to transfer data.
16.5.2.1 I/O-mapped I/O
The most common I/O data transfer technique used in the Intel microprocessor
based system is I/O-mapped I/O; it is also called isolated I/O scheme. The term
isolated indicates that the I/O locations are isolated from the memory system in
a separate I/O address space. Figures 16.9 (a) and 16.9 (b) show both the isolated
I/O and memory-mapped I/O address spaces for the 8086.
Address
FFH
(a) (b)
Fig.16.9 Memory and I/O maps for the 8086 (a) l/O-mapped I/O (b) memory-mapped I/O
The address for isolated I/O devices, called ports, is separate from the memory
in the isolated I/O scheme. As a result, the user can expand the memory to its full
size (i.e., 1 MB) without using any of its address space (00000H-FFFFFH) for I/O
devices. A disadvantage of I/O-mapped I/O is that the data is transferred between
the 8086 and the I/O devices only by the IN and OUT instructions. Separate control
signals for the I/O devices are generated, which indicate an I/O read or an I/O
write operation. The generation of the IOR and IOW signals in the minimum mode
operation of the 8086 is shown in Fig. 16.10. In the maximum mode operation of
the 8086, the IOWC and IORC signals generated by the 8288 bus controller are
used to interface the I/O devices with the 8086.
Fig. 16.10 Generation of IOR and IOW signals in minimum mode operation of the 8086
16.5.2.2 Memory-mapped I/O

The memory-mapped I/O scheme does not use the IN and OUT instructions. Any
instruction that transfers data between the microprocessor and the memory can
be used for transferring data between the 8086 and the I/O devices. The main
advantage of this scheme is that there are many memory transfer instructions in
the 8086 and all of them can be used to access the VO device. The same control
signals used for accessing the memory (MEMR and MEMW in the minimum
mode and MRDC and MWTC from the 8288 in the maximum mode) are used for
accessing the I/O devices. This reduces the additional circuitry needed to generate
the control signals. The main disadvantage of the memory-mapped I/O scheme
is that a portion of the memory system is used as the I/O map. This reduces the
amount of memory available to the applications.
16.6 INTERFACING 8-BIT INPUT DEVICE WITH 8086

To interface an input device with the 8086, three-state buffers are used. A typical
example for a three-state buffer IC is the 74LS244. Let us consider the interfacing of
an 8-bit DIP switch with the 8086 using the 74LS244 IC. Depending upon whether
an 8-bit or a 16-bit address is to be assigned to the DIP switch, the construction
of the address decoder differs. The address decoder can be constructed only using
logic gates or a combination of logic gates and decoder ICs such as the 74LS138.
16.6.1 Assigning 8-bit Address to 8-bit Input Device using Address Decoder
having only Logic Gates
Let us interface an 8-bit DIP switch with the 8086 operating in the minimum
mode, such that the address assigned to it is 8FH, using an address decoder having
only logic gates. Figure 16.11 shows the required interfacing circuitry. When the
8086 has to read the data from the 8-bit DIP switch, the instruction IN AL, 8FH or
Fig. 16.11 Interfacing an 8-bit DIP switch with the 8086 (8-bit address)
IN AL, DX with DX already loaded with the value 008FH has to be executed by
it. During the execution of any one of these instructions, the address lines A7-A0
contain 8FH and the IOR signal is made low for some duration (a few ps) by the
8086. As a result, the enable inputs (1G and 2G) of the 74LS244 are activated (i.e.,
made low), and the data from the DIP switch is placed on the data bus (D15-D8).
The 8086 reads that data and places it in the AL register. The data bus D7-D0 of
the 8086 is used if the I/O device address is an even number. The reason for this
is explained in Section 16.9.
16.6.2 Assigning 8-bit Address to 8-bit Input Device using Address Decoder IC
74LS138
In Fig. 16.11, if we want to assign the address 8FH to the DIP switch using an
address decoder IC such as the 74LS138, the design of the address decoder is
done as shown in Fig. 16.12. When the 8086 places the address 8FH (10001111
in binary form) in the address lines A7-A0, the inputs C = B = A=1,G1 = 1, and
G2A = G2B = 0 in the 74LS138 IC, due to which the decoder IC is enabled, its Y7
output goes low, and other outputs remain high. This Y7 output of the decoder IC
along with the IOR signal of the 8086 is used to enable the 74LS244 IC, thereby
transferring data from the DIP switch to the AL register of the 8086 when the
instruction IN AL, 8FH is executed. The same decoder IC’s other outputs (i.e.,
Y0-Y6) can be used to assign the addresses 88H-8EH to other I/O devices.
• —— - < ,v - x -z < -; x -- v s - z. - . x Z x TV ' ~ > -7- " ' ' - ~
Fig. 16.12 Address decoder using 74LS138 IC
16.6.3 Assigning 16-bit Address to 8-bit DIP Switch using Address Decoder
having only Logic Gates
The interfacing of an 8-bit DIP switch with the 8086, such that the address assigned
to the DIP switch is FFFOH, is shown in Fig. 16.13 on page 522.
When the 8086 executes the instruction IN AL, DX with DX already loaded
with the value FFFOH (this is done using the MOV DX, FFFOH instruction), it
places the address FFFOH in the address lines A15-A0 and activates the IOR
signal for some duration (a few ps). This makes 1G and 2G of the 74LS244 low,
thereby enabling the 74LS244. Data from the DIP switch is placed in the data bus
(D7-D0) of the 8086. The 8086 reads that data and places it in the AL register.
The 16-bit address decoder can be designed using a combination of logic gates and
decoder ICs (74LS138), as explained using the 8-bit address decoder.
16.7 INTERFACING 8-BIT OUTPUT DEVICE WITH 8086

To interface an output device with the 8086, latches are used. A typical example
of an octal latch IC is 74LS373. Figure 16.14 shows the interfacing of a set of 8
LEDs with the 8086 using the 74LS373 IC. Either an 8-bit or 16-bit address can be
assigned to the set of LEDs, as explained in the interfacing of input devices with
the 8086. The address decoder can be constructed either using only logic gates or
using a combination of logic gates and decoder ICs such as the 74LS138.
Let us discuss the interfacing of an 8-bit output device having an 8-bit address
with the 8086. In Fig. 16.14, the address assigned to the LEDs is FOH. When the
Fig. 16.13 Interfacing an 8-bit DIP switch with the 8086 (16-bit address)
Fig. 16.14 Interfacing eight LEDs with the 8086 (8-bit address)
8086 has to send the data in the AL register to the LEDs, either OUT FOH, AL or
OUT DX, AL with DX already loaded with the value 00F0H has to be executed
by it. During the execution of any one of these instructions, the address lines
A7-A0 contain FOH and the data lines D7-D0 contain the data in the AL register.
The IOW signal (assuming that the 8086 is operating in minimum mode) is made
low for some duration (a few ps) by the 8086. This activates (i.e., makes high) the
clock (CLK) signal of 74LS373 IC. The data in the data bus D7-D0, which is the
content of the AL register, is latched in the 74LS373 IC and held there until the
OUT instruction with the same address is again executed by the 8086. The OC pin
in the 74LS373 IC is made low to enable the tri-state inverter connected to each
output pin.
16.8 INTERFACING PRINTER WITH 8086

There are different types of printers available today, such as the dot matrix printer,
line printer, inkjet printer, and laser printer. The dot matrix printer uses print heads
that contain pins arranged in matrix form. These pins can print characters in one
of the following matrix formats: 5 x 7, 7 x 7, or 9 x 9. Line printers differ from
dot matrix printers in that they print line by line and not character by character.
The inkjet printer reproduces digital images by propelling ink droplets of variable
size onto a page. The laser printer produces high quality text and graphics on plain
paper, at a very high speed. Like digital photocopiers, laser printers employ
a xerographic printing process. However, they differ from analog photocopiers in
that images are produced by the direct scanning of a laser beam across the printer’s
photoreceptor.
The printer can be interfaced with a microprocessor through a serial or a
parallel interface. The serial interface normally used is the RS-232C standard.
When the serial interface is used, the printer receives the data bit by bit from
the microprocessor and stores it in its internal input buffer. The input buffer can
normally hold the characters for one line to be printed. On receipt of the print
command from the microprocessor when its input buffer is full, the printer sends
the Busy signal to the microprocessor and starts printing the characters.
In the parallel interface, the printer is connected with the microprocessor
through a set of data lines (seven or eight bits) and control lines. The microprocessor
places the data to be sent to the printer in the data lines and activates a strobe
signal. The printer accepts the data, stores it in its internal buffer, and then sends
an acknowledgement signal to the microprocessor. The printer also sends status
signals such as Busy, PE (paper exhausted), and Error to the microprocessor,
which are used to identify the readiness of the printer for data transfer. Most of
the printers accept the data in ASCII (American Standard Code for Information
Interchange) form. Data transfer through a parallel interface is faster and simpler
than that through a serial interface. The Centronics interface is a popular parallel
interface that is used for interfacing the printer with the microprocessor and is
named after the manufacturer of the Centronics printer, who introduced it. Table
16.8 shows the pin number and the description of various signals in the Centronics
printer connector.
Table 16.8 Pin connections and signals in the Centronics interface
Pin Signal Direction of signal Description of signal

no. (with respect to
the printer)
1 STROBE Input When the STROBE signal goes low, the
printer reads the data in the data lines
and stores them in its internal buffer.
The minimum low state (i.e., 0) duration
of the STROBE signal must be 0.5 ps.
2-9 DATA1-DATA8 Input This represents the data (eight bits) to be
printed in the printer.
10 ACK Output When the printer has received data and

is ready for next data, it makes the ACK
signal low (i.e., 0) for a minimum period
of 5 ps.
11 Busy Output The Busy signal is high (i.e., 1) when
the printer is unable to receive data. It is
high during data entry into the printer,
during printing operation, when the
printer is in offline state, or when it is in
error state.
12 PE Output If the printer is out of paper, the PE
signal goes high.
13 SLCT Output When the printer is in selected state,

SLCT is high.
14 AUTOFEEDXT Input When this signal is low, the paper is

automatically fed one line after printing.
15 NC — Not used
16 0V — Logic ground level
17 CHASSISGND — Printer chassis ground. In the printer,

the chassis ground and logic ground are
isolated from each other.
18 NC — Not used
19- GND — This is the twisted pair return (ground)
30 signal for the STROBE, DATA, ACK,
Busy, and PE signals.
31 INIT Input When the INIT signal is made low (for
more than 50 ps), the printer controller
is reset to its initial state and the printer
buffer is cleared.
(Contd)
Table 16.8 Pin connections and signals in the Centronics interface (Contd)
Pin Signal Direction of signal Description of signal

no. (with respect to
the printer)
32 ERROR Output This signal goes low when the printer
is in ‘offline state’, ‘paper end state’, or
‘error state’.
33 GND — Ground
34 NC — Not used
35 +5V Output This signal is pulled up to +5 V through
a 4.7 kfi resistor.
36 SLCTIN Input Data entry to the printer is possible only
when this signal is low.
Figure 16.15 shows the timing diagram of the important signals involved in
interfacing of the Centronics printer with the microprocessor. When the Busy
signal is 0, which means that the printer is ready for accepting the character from
the microprocessor, the microprocessor places the ASCII code of a character or the
code of a special command in the data lines (DATA1-DATA8). After a minimum
time of 0.5 ps, it activates the STROBE signal (i.e., makes it 0) for a minimum
period of 0.5 ps. The data in the data lines is kept at the same value for a minimum
period of 0.5 ps after the STROBE signal is deactivated (i.e., made 1). When the
STROBE signal is activated, the Busy signal from the printer immediately goes
high (i.e., becomes 1). It remains high until the printer sends the ACK signal, as
shown in Fig. 16.15. This is done because the microprocessor should not send
another data to the printer before the first data is processed in the printer. During
the rising edge of the ACK signal, the Busy signal goes low (as shown in Fig.
16.15) and now, another data can be sent to the printer.
T1 = 5 ps (approx.), T2 = 0.5 ps (min.), T3 = 0.5 ps (min.), T4 = 0.5 ps (min.)
Fig. 16.15 Timing diagram of important signals in the Centronics printer interface
Table 16.9 indicates the signals that are mainly required for interfacing the
Centronics printer with the microprocessor. There are totally ten output signals
that have to be sent from the microprocessor to the printer and four input signals
that have to be received by the microprocessor from the printer. Microprocessors
such as the 8085 and the 8086 can use one 8255 IC (programmable peripheral
interface) to interface a Centronics printer.
Table 16.9 Signals needed to interface the Centronics printer with the microprocessor
Signal description Signal name Number of Input/output (with respect

signals to the microprocessor)
Data lines DATA1-DATA8 8 Output
Strobe STROBE 1 Output
Acknowledge ACK 1 Input
Busy Busy 1 Input
Error ERROR 1 Input
Paper exhausted PE 1 Input
Initialize INIT 1 Output
Figure 16.16 shows the interfacing of 8086 microprocessor with the Centronics
printer using one 8255 IC. It shows the main signals involved in the data transfer.
In Fig. 16.16, port A is used to send the data (eight bits) to the printer and hence
it should be configured as an output port. Port B is used to send the INIT and
STROBE signals to the printer and hence it should be configured as an output port.
Port C is used to receive status signals such as ACK, Busy, ERROR, and PE from
the printer and hence it should be configured as an input port.
Fig. 16.16 Interfacing the Centronics printer with the 8086 using the 8255
The complete sequence of steps to be carried out in software, for the Centronics
printer to print a message having several lines, is given in the flowchart shown in
Fig. 16.17. The ASCII code of various characters in the message to be printed
is first stored in some portion of the RAM in the microprocessor system. The
microprocessor has to send the ASCII code of characters in the RAM to the printer
Fig. 16.17 Software sequence for interfacing the Centronics printer with the microprocessor
one by one. with the line feed and carriage return characters (OAH and ODH,
respectively) as the last code. Printers are often capable of executing commands
that are sent through the data lines by the microprocessor. The difference between
the data and the command is achieved by means of escape (ESC) codes. Whenever
the microprocessor sends an ESC code, the printer interprets the following code as
a command. Such commands are needed to specify the desired font, the size of the
margin, the line spacing, etc., in the message that is printed.
16.9 INTERFACING 8-BIT AND 16-BIT I/O DEVICES OR PORTS WITH 8086
Let us see how data are transferred between the 8086 and 8- or 16-bit I/O devices.
Data transferred to an 8-bit I/O device or port exists in one of the I/O banks of
the 8086. The I/O system contains two 8-bit I/O banks, just like the memory
system of the 8086. This is shown in Fig. 16.18, which indicates the separate
I/O banks for a 16-bit system. When an 8-bit address is used for I/O devices,
the even bank contains even addresses such as OOH, 02H, and 04H and the odd
bank contains odd addresses such as 01H, 03H, and 05H. When a 16-bit address
is used for I/O devices, the even bank contains even addresses such as 0000H,
0002H, and 0004H and the odd bank contains odd addresses such as 0001H,
0003H, and 0005H.
Since two I/O banks
exist, any 8-bit I/O
write operation requires
separate write strobes to
function correctly. These
are generated as shown in
Fig. 16.19. I/O read
operations do not require
separate read strobes
because as with the
memory, the 8086 only Fig. 16.18 I/O banks in an 8086-based
reads the byte it expects system with 16-bit addresses
and ignores the other byte.
Figure 16.20 shows a system
that contains two different 8-bit
output devices located at the 8-bit
I/O addresses FOH and FlH. Since
these are 8-bit devices and appear
in different I/O banks, separate 1/
O write signals are needed. In Fig.
16.20, the connections of only the
address decoder and the 74LS373 IOWL—Write strobe for low I/O bank
ICs are shown. The remaining
connections to the 8086 are the Fig. 16-19 Generation of write strobes for I/O banks
same as in Fig. 16.14.

Fig. 16.20 I/O port decoder to select 8-bit output ports FOH and F1H
When selecting 16-bit wide I/O devices, the AO and BHE pins have no function
because both I/O banks are selected together. To interface the 16-bit ADC or DAC
ICs with the 8086, 16-bit ports are needed. Here, two successive addresses are
assigned for the same I/O device. One address is an even number such as OOH (for
8-bit address) or 0000H (for 16-bit address), where the lower-order byte of the
16-bit data is present. The other address is an odd number such as 01H (for 8-bit
address) or 0001H (for 16-bit address), where the higher-order byte of the 16-bit
data is present. In the IN or OUT instruction, only the address of the lower-order
byte of the 16-bit data is specified either directly or implicitly through DX. Figure
16.21 shows the interfacing of a 16-bit input device connected to function at the 8-
bit I/O addresses F4H and F5H. In the figure, only the connections for the address
decoder and the 74LS244 ICs are shown. The remaining connections to the 8086
are as shown in Fig. 16.11. Using the instructions IN AX, F4H or IN AX, DX with
DX already loaded with the value 00F4H, the data from the 16-bit input port can
be read and placed in AX.
16.10 INTERFACING CRT TERMINAL WITH 8086

The CRT (cathode ray tube) terminal uses the RS-232C interface for communication
with the microprocessor. Three signals in the RS-232C—TXD, RXD, and GND—
are mainly used for interfacing the CRT terminal with the microprocessor. TXD
is used for transmission of data from the CRT to the microprocessor and RXD
Fig. 16.21 16-bit input port decoded at I/O addresses F4H and F5H
is used for receiving data from the microprocessor into the CRT. The GND
(ground) signal in the CRT interface is connected to the GND (ground) signal in
the microprocessor. The RS-232C interface transmits or receives data by serial
communication, i.e., one bit of data is transmitted or received at a time. Each byte
of data transmitted or received by the RS-232C interface is enclosed by one start bit
and 1, 1.5, or 2 stop bits. Figure 16.22 shows the RS-232C format for transmission
or reception of one byte of data, 4DH (which is equal to 01001101 in binary form),
with one start bit and two stop bits. When no data is transmitted or received, the
TXD and RXD lines remain high. In the RS-232C standard, any voltage between
+3V and +12 V in the data lines (TXD and RXD) is used to represent binary 0
and any voltage between -3 V and -12 V is used to represent binary 1. Due to this
reason, the RS-232C standard is said to be using negative true logic.
Fig. 16.22 RS-232C format for transmission or reception of a byte of data (4DH)
There are three methods by which a CRT terminal can be interfaced with the
microprocessor:
(i) Direct connection of the microprocessor with the CRT terminal
A microprocessor (e.g., 8085) that has facilities for serial input/output (through
its SID/SOD pins), can be directly connected to the CRT terminal through level
translators. The SID pin of the 8085 is connected to the TXD pin of the CRT
terminal; the SOD pin of the 8085 is connected to the RXD pin of the 8085
through level translators, as shown in Fig. 16.23. The reason for using the level
translators is the mismatch in the voltage levels for representing binary 1 and 0 in
the microprocessor and the CRT terminal. We already know that the CRT terminal
uses the RS-232C interface. Microprocessors such as the 8085 and 8086 use TTL
(transistor-transistor logic) standard, in which +5 V is used to represent binary 1
and 0 V is used to represent binary 0. The level translators convert the TTL signal
to an RS-232C signal and vice versa. One example for such a level translator that
is available in an integrated circuit (IC) form is MAX-232. Each MAX-232 can
convert two TTL signals to the corresponding RS-232C signals and two RS-232C
signals to the corresponding TTL signals.
Fig. 16.23 Direct connection of the microprocessor with the CRT terminal
(ii) Connection of the microprocessor with the CRT terminal through serial-to-
parallel converter and parallel-to-serial converter
We can interface a microprocessor that does not have serial input/output
pins (e.g., 8086) with the CRT terminal using a serial-to-parallel converter, a
parallel-to-serial converter, and level translators, as shown in Fig. 16.24. Level
translators are used here because the serial-to-parallel converter and parallel-to-
serial converter operate only with TTL signals. The data (8 bits or 16 bits) that is
transmitted from the microprocessor through its data bus to the CRT terminal is
first converted to serial data using a parallel-to-serial converter and then sent to
the CRT terminal through the level translator, which converts the TTL signal into
an RS-232C signal. Similarly, the serial data that is transmitted from the CRT
terminal to the microprocessor, which is in RS-232C format, is first converted into

a TTL signal using a level translator, then converted to parallel data using a serial-
to-parallel converter, and sent to the microprocessor through its data bus.
Fig. 16.24 Connection of the microprocessor with the CRT terminal using serial-to-parallel
converter and parallel-to-serial converter
(iii) Connection of the microprocessor with the CRT terminal through USART
(universal synchronous asynchronous receiver-transmitter)
There exists a special IC chip such as USART (IC 8251), which has a built-in
parallel-to-serial converter (eight bits) and a built-in serial-to-parallel converter
(eight bits). Figure 16.25 shows the connection of the 8086 microprocessor with
the CRT terminal through USART and level translators. The level translators are
used here because the USART operates only with TTL signals.
>■
Fig. 16.25 Connection of the microprocessor with the CRT terminal using USART
The CRT terminal transmits or receives data at a fixed baud rate. Baud rate
represents the number of bits transmitted or received per second. There are some
standard values for baud rate, such as 600, 1200, 2400, 4800, and 9600. One of
these speeds can be selected in the CRT terminal by properly configuring certain
switches present in it. The microprocessor must also be programmed to the same
baud rate as the CRT terminal, for proper data transfer between them. The time
between transmitting or receiving two consecutive bits is known as bit time in
serial communication and it is the reciprocal of the baud rate. The required bit time
can be obtained using a delay program in the microprocessor. Based on the baud
rate input given to the microprocessor, the delay count used in the delay program
can be found using look-up table technique.
The microprocessor software that controls the data transfer between the
microprocessor and the CRT terminal does the following operations sequentially:
(i) During the transmission of data from the microprocessor to the CRT
terminal, the microprocessor first sends the start bit, then the data bits one
by one, and finally, the stop bit(s).
(ii) During the reception of data from the CRT terminal, the microprocessor
first checks whether start bit has occurred (i.e., whether RXD is made 0). If
start bit is received, then the microprocessor receives the data bits one by
one. Then it checks for the reception of stop bit(s).
The CRT terminal uses the parity bit along with the data, to ensure that the
transmission or reception of data does not involve any error. Some terminals use
odd parity and some use even parity. The number of Is in the data is made odd
or even using the seventh bit of the data, depending upon whether odd or even
parity, respectively, is needed. The software in the microprocessor should be able
to generate odd or even parity data during transmission and check for the same
parity of data during reception.
POINTS TO REMEMBER
• The maximum memory that can be connected with the 8086 is 1 MB, which is organized
as two separate banks—even/low memory bank and odd/high memory bank.
• The BHE signal is used to enable the odd memory bank and the data lines of the odd
memory bank are connected with the data lines D15-D8 of the 8086.
• The address line A0 is used to enable the even memory bank and the data lines of the
even memory bank are connected to the data lines D7-D0 of the 8086.
• When the lower-order byte of a word is stored in the even memory bank, the 8086 can
access both bytes of that word in a single memory read cycle. Otherwise, it takes two
memory read cycles to read the same word. Therefore, while storing an array of word
type data in the memory or while initializing the stack, the lower-order bytes of the
words are stored in the even addresses.
• There are two methods that can be used to interface I/O devices with the 8086—memory
mapped I/O and I/O-mapped I/O.
• In the memory-mapped I/O method, the I/O device is treated as if a memory location
and the instructions used for transferring data between the memory and the 8086 can be
used for data transfer between the 8086 and the I/O devices. The MEMR and MEMW
signals are used to activate the input device and output device, respectively. The I/O
devices have a 20-bit address in memory-mapped I/O and the design of the address
decoder is same as that of the memory address decoder.
• The I/O-mapped I/O scheme is commonly used to interface I/O devices with the 8086.
Here, there are two methods of addressing I/O devices—fixed port addressing (in which
the 8-bit address of an I/O device is specified in the IN or OUT instruction directly) and
variable port addressing (in which the 16-bit address of an I/O device is specified in the
IN or OUT instruction implicitly through the DX register). In I/O-mapped I/O, only the
IN and OUT instructions are used to communicate with the I/O devices. The advantage
of this method is that the user can fully utilize the 1 MB memory space, which is not
possible in memory-mapped I/O.
• The 8086 can be interfaced with either an 8-bit or a 16-bit I/O port. The I/O space in
the 8086 is also organized as two separate I/O banks—odd and even I/O bank, which
is the same as the memory organization in the 8086. The odd I/O bank contains odd
I/O addresses and the data lines of the odd I/O bank are connected to the D15-D8 lines
of the 8086. The even I/O bank contains even I/O addresses and the data lines of the
even I/O bank are connected to the D7-D0 lines of the 8086. The BHE signal is used to
enable the odd I/O bank and A0 is used to enable the even I/O bank, which is the same
as the process for enabling the memory in the 8086. The IOR and IOW signals are used
to activate the input and output devices, respectively, in the I/O-mapped I/O scheme.
KEY TERMS
16-bit input device It is an input device that sends 16-bit data to the 8086.
16-bit output device It is an output device that receives 16-bit data from the 8086.
8-bit input device It is an input device that sends 8-bit data to the 8086.
8-bit output device It is an output device that receives 8-bit data from the 8086.
BHE This is the Bus High Enable signal, which is used to enable the upper bank of the
memory in the 8086.
Even/low memory bank The even/low memory bank is a memory chip (or chips) that
contains even memory addresses; its data lines are connected to the D7-D0 lines of the
8086.
High/odd I/O bank This is the VO bank that contains odd addresses and is connected to
the data lines D15-D8 of the 8086.
I/O-mapped I/O This is a method of interfacing an VO device with the 8086, in which
an VO device is treated differently from the memory.
IN and OUT instructions These are the instructions used for transfer data between the
accumulator and the VO devices in VO-mapped VO.
IOR This is the VO read control signal that is activated during the VO read operation.
IOW This is the VO write control signal that is activated during the VO write operation.
Latch The latch is used for interfacing output device with microprocessor.
Low/even I/O bank This is the VO bank that contains even addresses and is connected
to the data lines D7-D0 of the 8086.
Memory address space or memory map The memory addresses that can be generated
by the 8086 (00000H-FFFFFH) together constitute the memory map.
Memory-mapped I/O This is a method of interfacing an I/O device with the 8086, in
which an I/O device is treated as if a memory location.
MEMR This is the Memory Read control signal that is activated during the memory read
operation.
MEMW This is the Memory Write control signal that is activated during the memory
write operation.
Odd/high memory bank The odd/high memory bank is a memory chip (or chips) that
contains odd memory addresses; its data lines are connected to the D15-D8 lines of the
8086.
Physical memory address The memory address in the physical memory such as the
RAM or EPROM chip is called physical memory address.
Tri-state buffer The tri-state buffer is used for interfacing the input device with the
microprocessor.
REVIEW QUESTIONS
1. What is the maximum memory, in terms of bytes, that can be interfaced with the
8086? Why?
2. What is the memory address space in the 8086?
3. How is the physical memory organized in the 8086?
4. How are the AO and BHE signals in the 8086 used in the selection of memory banks?
5. Why should the data structures such as array of word type data or stack be stored from
an even address in the memory?
6. How is the multiplexed address bus in the 8086 separated into address bus and data
bus? Draw the diagram for the same.
7. What are the functions of IC 74244 and IC 74245?
8. How are the Memory Read and Memory Write control signals generated in the
minimum mode of operation of the 8086?
9. What is the importance of the memory address ranges 00000H-003FFH and FFFF0H-
FFFFFH in the 8086?
10. What are the differences between memory-mapped I/O and I/O-mapped I/O?
11. Write the different forms of the IN instruction in the 8086.
12. Write the different forms of the OUT instruction in the 8086.
13. What is meant by fixed port addressing in the 8086 and how many I/O devices can be
connected to the 8086 by this method?
14. What is meant by variable port addressing in the 8086 and how many I/O devices can
be connected to the 8086 by this method?
15. Draw a diagram showing the memory and I/O map when memory-mapped I/O and
I/O-mapped I/O schemes are used.
16. Draw a circuit showing the generation of I/O read and write control signals in the
minimum mode operation of the 8086.
1. Interface two 16K x 8 EPROM chips with the 8086, such that the memory address
range assigned to the EPROM chips is F8000H-FFFFFH, using an address decoder
having only logic gates.
2. Interface two 16K x 8 RAM chips with the 8086, such that the memory address range
assigned to the RAM chips is 00000H-07FFFH, using an address decoder having only
logic gates.
3. Interface two 8K x 8 EPROM chips with the 8086, such that the memory address
range assigned to the EPROM chips is F0000H-F3FFFH, using an address decoder
that employs the 74138 IC and logic gates.
4. Interface two 8K x 8 RAM chips with the 8086, such that the memory address range
assigned to the RAM chips is 20000H-23FFFH, using an address decoder that employs
the 74138 IC and logic gates.
5. Interface four 16K x 8 EPROM chips with the 8086, such that the memory address
range assigned to the EPROM chips is 90000H-9FFFFH, using an address decoder
that employs two 74138 ICs and logic gates.
6. Interface four 16K. x 8 RAM chips with the 8086, such that the memory address
range assigned to the RAM chips is A0000H-AFFFFH, using an address decoder that
employs two 74138 ICs and logic gates.
7. Interface an 8-bit DIP switch with the 8086 operating in minimum mode, such that the
address assigned to it is FOH, using an address decoder having only logic gates. Write
the instructions needed to read the data from the DIP switch into AL, in fixed port and
variable port addressing.
8. Interface an 8-bit DIP switch with the 8086 operating in minimum mode, such that
the address assigned to it is FOH, using an address decoder that employs the 74138
decoder and logic gates.
9. Interface a seven-segment LED in common cathode connection with the 8086
operating in minimum mode, such that the address assigned to it is 7FH, using an
address decoder having only logic gates. Write the instructions needed to display the
number 5 in the LED, using fixed port and variable port addressing.
10. Interface a seven-segment LED in common cathode connection with the 8086 operating
in minimum mode, such that the address assigned to it is 3FH, using an address
decoder that employs the 74138 decoder and logic gates. Write the instructions needed
to display the number 7 in the LED, using fixed port and variable port addressing.
11. Interface an 8-bit DIP switch with the 8086 operating in minimum mode, such that
the address assigned to it is FF80H, using an address decoder having only logic gates.
Write the instructions needed to read the data from the DIP switch into AL.
12. Interface a seven-segment LED in common anode connection with the 8086 operating
in minimum mode, such that the address assigned to it is 7FFFH, using an address
decoder having only logic gates. Write the instructions needed to display the number
5 in the LED.
13. Interface a 16-bit DIP switch with the 8086 operating in minimum mode, such that the
addresses assigned to it are 80H and 81H, using an address decoder having only logic
gates. Write the instructions needed to read the data from the DIP switch into AX, in
fixed port and variable port addressing.
14. Interface two seven-segment LEDs with common cathode connection with the 8086
operating in minimum mode, such that the addresses assigned to them are 70H and
71H, using an address decoder having only logic gates. Write the instructions needed
to display the number F5 in the LEDs, using fixed port and variable port addressing.
CHAPTER 17
MULTIPROCESSOR CONFIGURATION
LEARNING OUTCOMES
• Necessity and advantages of a multiprocessor system
• Difference between closely-coupled and loosely-coupled multiprocessor systems
• Interconnection topologies between processors and memories in a multiprocessor system
• Physical interconnections between processors in a multiprocessor system
• Multiprocessor system containing 8086 and 8087 (numeric coprocessor)
• Multiprocessor system containing 8086 and 8089 (I/O processor)
17.1 INTRODUCTION
The speed of any microprocessor-based system depends upon the clock frequency
at which it is operating, amongst other factors such as the presence of a pipeline
execution unit and the microprocessor’s on-chip cache. For example, when
bulk I/O data transfer is done under the control of the microprocessor alone, the
processor has to spend most of its time idle due to the slow operating speed of
the peripherals. A single processor system has an upper limit on its processing
capability. For further enhancement of the speed of operation, an appropriate
system involving several connected processors using a certain topology may
provide the solution. Such a system is called multiprocessor system. If a system
having a single processor takes a particular duration to complete a task, a system
having more than one processor may require lesser time.
The simplest type of multiprocessor system consists of a CPU (such as the 8086)
and a numeric data processor (NDP), also called numeric coprocessor or input/
output processor (IOP). The NDP is an independent processing unit that is capable
of performing complicated numeric calculations in comparatively lesser time than
the microprocessor. The NDP works in coherence with the microprocessor. The
input/output operations in a microprocessor-based system are slow due to the low
operating speed of the I/O devices. An I/O processor (IOP) takes care of the I/O
activities of the 8086-based system and thus saves the time of the main processor
(the 8086). The NDP and IOP work in synchronism with the main processor to
complete specific tasks and are called coprocessors. Coprocessors do not work
independently, as they cannot fetch code from the memory. They work under the
control of the main processor. Additional hardware circuits such as bus arbiter
and bus controller may be needed to coordinate the activities of all the processors
working at a time in the system.
17.2 MULTIPROCESSOR SYSTEM-NEED AND ADVANTAGES

By using a DMA controller with a CPU (such as the 8086), the system throughput
can be improved by concurrently performing I/O data transfer while the CPU
continues its processing. This is possible because the CPU does not utilize all bus
cycles. Depending on the application, the 8086 typically uses only 50% to 80%
of the available bus time. A DMA controller can steal bus cycles to transfer data
between the memory and the I/O devices, while affecting the CPU processing
minimally. It releases the CPU from performing the relatively slow I/O data
transfer operations. Such a system, having more than one processor such as the
8086 and the DMA controller (8257 or 8237), with both of them operating in
parallel to improve the system performance, is an example of a multiprocessor
system.
In general, if a system includes two or more processors that can execute
instructions simultaneously, it is called a multiprocessing system. The additional
processors could be special-purpose processors, which are specifically designed
to perform certain tasks efficiently, or general-purpose processors. For example,
due to the 8086’s limited data bus width (16 bits) and its lack of floating-point
arithmetic instructions, it requires many instructions to perform a single floating
point operation. For a system requiring several floating-point computations, it is
desirable to perform such computations with a supporting numeric coprocessor
such as the 8087, which is specifically designed to quickly operate on floating
point numbers and numbers having larger size, such as 32 bits, 64 bits, and
80 bits. Sometimes, it is advantageous to include in a system, an I/O processor
such as the 8089, which has greater capabilities than a DMA controller, since
the 8089 can perform string manipulations, character searching, and bit testing as
well as the normal DMA operations. This permits the 8086 CPU to concentrate on
higher-level functions.
As the ratio of cost to performance of a single-chip microprocessor reduces
day by day, it becomes more cost effective to use multiple processors than to use a
single complex processor. In addition to improving the overall cost to performance
ratio of a system, a multiprocessor configuration offers several desirable features
that are not found in a single complex processor design. Some of these features are
listed here:
(i) Several processors may be combined to fit the needs of an application, while
avoiding the expense of the unnecessary capabilities of a single complex
processor.
(ii) The modularity of a multiprocessor system provides means for expansion
because it is easy to add more processors as the need arises.
(iii) In a multiprocessor system, tasks are divided among the processors. If a
failure occurs, it is easier and cheaper to find and replace the malfunctioning
processor than it is to find and replace the failing part in a complex
processor.
Two problems—bus contention and inter-processor communication—must

be considered while designing a multiprocessor system. Since more than one
MULTIPROCESSOR CONFIGURATION 539
processor shares the system memory and the I/O devices through a common
system bus, extra logic must be included to ensure that only one processor has
access to the system bus at a time. For one processor to send a task or return a
result to another processor, an unambiguous way must be provided for the two
processors to interact. The connections between the processors are dictated by
how the bus contention and processor communication problems are resolved.
17.3 DIFFERENT CONFIGURATIONS OF MULTIPROCESSOR SYSTEM

The maximum mode operation of the 8086 is specifically designed to implement
multiprocessor systems. Multiprocessing features are provided in the maximum
mode operation of the 8086, to accommodate three basic configurations—the
coprocessor, the closely-coupled, and the loosely-coupled configurations.
17.3.1 Coprocessor and Closely-coupled Configurations

The coprocessor and the closely-coupled configurations are similar, as both the CPU
(i.e., 8086) and the extemal/supporting processor share not only the entire memory
and the I/O subsystem, but also the same bus control logic and clock generator, as
shown in Fig. 17.1. In both these configurations, the 8086 is the master or the host,
and the supporting processor is the slave. Since the bus access control is provided
by the 8086, the bus request signal from the supporting processor is connected
to the 8086. In the closely-coupled configuration, the supporting processor may
act independent of the CPU, but in the coprocessor design, it is dependent on the
CPU and must interact directly with the CPU. Since the 8086 always acts as the
host in the coprocessor and closely-coupled designs, two 8086 processors cannot
appear in these configurations. In a coprocessor arrangement, there are more direct
connections between the processing elements.
Fig. 17.1 Closely-coupled multiprocessor configuration
17.3.2 Loosely-coupled Configuration

The loosely-coupled configuration is used for medium to large size systems.
This configuration is shown in Fig. 17.2. Each module in a loosely-coupled
system may act as the system bus master, and may consist of an 8086 or another
processor capable of being a bus master, or a coprocessor, or a closely-coupled
configuration. Several modules may share the system resources and the system
bus control logic must resolve the bus contention problem. Each potential bus
master runs independently and there are no direct connections between them.
Inter-processor communication is made possible through the shared resources. In
addition to the shared resources, each module may include its own memory and
I/O devices. The processors in the separate modules can simultaneously access
their private subsystems through their local buses and perform their local data
references and instruction fetches independently, thus improving the degree of
concurrent processing.
Fig. 17.2 Loosely-coupled multiprocessor configuration
17.4 BUS ARBITRATION IN LOOSELY-COUPLED MULTIPROCESSOR SYSTEM

In a loosely-coupled multiprocessor system, two 8086 processors cannot be tied
directly together. Each CPU has its own bus control logic, and bus arbitration is
resolved by extending this logic and adding external logic that is common to all
the master modules. Therefore, several CPUs can form a very large system and
each CPU may have independent processors and/or a coprocessor attached to it. A
loosely-coupled configuration provides the following advantages:
(i) The system can be expanded in a modular form. Each bus master module is
an independent unit and normally resides on a separate PC board and hence,
a bus master module can be added or removed without affecting the other
modules in the system.
(ii) High system throughput can be achieved by having more than one CPU.
(iii) A failure in one module does not cause a breakdown of the entire system;
the faulty module can be easily detected and replaced.
(iv) Each bus master may have a local bus to access dedicated memory or I/O
devices, so that a greater degree of parallel processing can be achieved.
In a loosely-coupled multiprocessor system, more than one bus master
module may have access to the shared system bus. Since each master is running
independently, extra bus control logic must be provided to resolve the bus arbitration
(i.e., allotment of system bus to a particular requesting master) problem. This extra
logic is called bus access logic and its responsibility is to make sure that only one
bus master at a time has control of the bus. Simultaneous bus requests are resolved
on a priority basis. There are three schemes for establishing priority—daisy
chaining, polling, and independent requesting. The three schemes are discussed in
Sections 17.4.1-17.4.3.
17.4.1 Daisy Chaining

Figure 17.3 shows the daisy chaining scheme of establishing priority. The daisy
chain method is characterized by its simplicity and low cost. All the masters use the
same line for making bus requests. To respond to a Bus Request (BR) signal, the
controller sends a Bus Grant (BG) signal if the Bus Busy (BB) signal is inactive.
The grant signal serially propagates through each master, until it encounters the
first one that is requesting access to the bus. This module blocks the propagation
of the Bus Grant signal, activates the Bus Busy line, and gains control of the
bus. Any other requesting module, which is present after the master that has now
gained the control of the bus, will not receive the grant signal. Therefore, the
priority is determined by the physical location of the modules. The requesting
module located closest to the controller has the highest priority.
Fig. 17.3 Daisy chain method of establishing priority
Compared to the other two methods, the daisy chain scheme requires the least
number of control lines and this number is independent of the number of modules
in the system. However, the arbitration time is slow due to the propagation delay
of the Bus Grant signal through the different masters. This delay is proportional
to the number of modules and therefore, a daisy-chain-based system is limited to
multiprocessor systems having only a few modules. Further, the priority of each
module is fixed by its physical location and the failure of a module in the system
causes the whole system to fail.
17.4.2 Polling
The polling scheme, which is shown in Fig. 17.4, uses a set of lines sufficient to
address each module. In response to a bus request, the controller generates and
sends out a sequence of module addresses to the requesting modules. When a

requesting module recognizes its address, it activates the Busy line and begins to
use the bus. The major advantage of polling is that the priority can be dynamically
changed by altering the polling sequence (i.e., the order in which the module
addresses are sent) stored in the controller.
Fig. 17.4 Polling method of establishing priority
17.4.3 Independent Requesting

The independent requests scheme, which is shown in Fig. 17.5, resolves the
priority in a parallel fashion. Each module has a separate pair of Bus Request (BR)
and Bus Grant (BG) lines, and each pair has a priority assigned to it. The controller
includes a priority decoder, which selects the request with the highest priority, and
returns the corresponding Bus Grant signal. Arbitration is fast and is independent
of the number of modules in the system. Compared to the other two methods, the
independent requests design is the fastest method. However, it requires more Bus
Request and Bus Grant lines (i.e., 2m lines are needed for m modules).
Master 1 Master 2 Master N

Bus access Bus access Bus access
logic logic logic
Bus Grant 1 (BG1)

Bus Request 1 (BR1)
Controller
Bus Grant2(BG2)
Bus Request 2 (BR2)
Bus Grant N : (BGN)

Bus Request N (BRN)
Bus Busy (BB)
Fig. 17.5 Independent requests method of establishing priority
A module’s host 8086 lacks the capability of requesting bus access and
recognizing bus grants. Therefore, it is necessary for each module containing a bus
master to have extra logic for sending and receiving the bus access signals. The
Intel bus arbiter (8289) is specifically designed to provide the necessary bus access
handshaking. The 8289 operates in conjunction with the bus controller (8288) and
controls the access of its associated master to the bus by using either the daisy
chain or the independent requests scheme.
17.5 INTERCONNECTION TOPOLOGIES IN A MULTIPROCESSOR SYSTEM

A microprocessor with its external bus connections needs memory to form a
minimum workable processing system. In a multiprocessor system, a number of
microprocessors are connected with each other using a single bus. The bus is also
used to address a multi-port memory or a shared single I/O port. In both the cases,
the memory serves the following purposes:
(i) It stores the local (individual) instructions and data for all the processors.
(ii) It stores the common (global) instructions and/or data for all the processors.
(iii) It acts as a temporary storage for the instructions, data, and other parameters
that are transferred between the processors.
Based on the method of communication among the microprocessors in a
multiprocessor system, we have the following interconnection topologies.
17.5. 1 Shared Bus Architecture

The shared bus architecture uses a common memory,
which may be partitioned into local memory banks for
different processors. This is shown in Fig 17.6. At a
time, only one processor performs a bus cycle to fetch
instructions or data from the memory. Once the bus
cycle is complete, the processor may internally start
the execution, allowing the other processors to use the
bus. Additional hardware is required for controlling
the access of the bus by different processors. All the
processors in Fig. 17.6 share a common memory, but
Fig. 17.6 Shared bus
they can also have a local memory individually to
architecture
store the local instructions or data.
17.5. 2 Multi-port Memory

In the multi-port memory configuration
shown in Fig. 17.7, the processors Pl and
P2 address a multi-port memory that can be
accessed at a time by both the processors.
They also have local memories, which
are used by them to store individual
instructions and data. Each processor uses
its local memory for the execution of its
individual tasks. The multi-port memory Local memory Local memory
may be used for storing the instructions,
data, and the results to be shared by more Fig. 17.7 Multi-port memory configuration
than one processor.

17.5. 3 Linked InputfOutput

The linked input/output
interconnection utilizes the
input/output capabilities
of a microprocessor-based
system to communicate
with other systems, as
shown in Fig. 17.8. Parallel
or serial I/O may be used
to establish communication
with other processors. The
Fig. 17.8 Linked input/output interconnection
direct access of common
instructions and data that are available in a local system memory is not possible
in this method.
17.5. 4 Crossbar Switching

The crossbar switching interconnection is shown in Fig. 17.9. It uses an extension
of the concept of shared memory for a number of processors. In this method,
more than one processor can have simultaneous access to the different memory
modules to be shared individually, as long as there is no conflict. The memory is
divided into modules. While one processor is accessing a memory module, the
other processor is denied access to the same module till it is relinquished by the
former processor. The crossbar switch provides the interconnection paths between
the memory modules and the processors. In the crossbar switch interconnection,
several parallel data paths are possible. Each node of the crossbar represents a
bus switch. These nodes may be controlled by one of these processors or by
a separate one.
Fig. 17.9 Crossbar switching interconnection

17.6 PHYSICAL INTERCONNECTIONS BETWEEN PROCESSORS IN A

MULTIPROCESSOR SYSTEM
The interconnections discussed in the previous sections are based on the
communication methods between the microprocessors in a multiprocessor system.
Besides those interconnections, we have star configuration, loop configuration,
complete interconnection, regular topologies, and irregular topologies. These are
based on the physical interconnections between the processors in a multiprocessor
system.
17.6.1 Star Configuration

In this configuration, all the processors are
connected to a central switching element
via dedicated paths, as shown in Fig. 17.10.
The central switching element may be
an independent processor. The switching
element controls the interconnections
between the processing elements.
Fig. 17.10 Star configuration
17.6.2 Ring or Loop Configuration
The ring or loop configuration is shown in Fig. 17.11. The processors are arranged
in a loop and each processor can communicate with the rest through intermediate
processors in the path. The number of intermediate processors depends upon the
position of the sender and the receiver in the loop. The direction of the data transfer
along the loop may be unidirectional or bidirectional.
P1 P2, P3, P4, and P5—Processors

SL S2^ S3, S4, and S5—Switches
Fig. 17.11 Ring or loop configuration

17.6.3 Completely-connected Configuration

In the complete interconnection scheme,
every processing element can directly
communicate with another processor,
one at a time, as shown in Fig. 17.12.
The main drawback of this configuration
is that the required number of dedicated
interconnection paths, which is given by
Equation 17.1, is very high when compared
to those in other configurations.
Let the required number of dedicated
interconnection paths be IP.
P1, P2, P3, and P4—Processors
N- 1
IP = 2 m (17.1) Fig. 17.12 Complete interconnection
m= 1
where N is the total number of processors.
17.6.4 Regular Topology

In this configuration, the processors are arranged in a regular fashion. The
processors can be arranged in any of the regular structures such as linear array,
square, hexagonal, or cubical configurations. Each processor (node) has a local
memory to be accessed only by that processor. Each processor can communicate
with a fixed number of neighbours in the specific regular structure. One of the
regular topologies is shown in Fig. 17.13.
17.6.5 Irregular Topology

The processors in this scheme do not follow any uniform or regular connection
pattern. The number of neighbouring processors with which a processor can
communicate is not fixed and may even be programmable.
17.7 OPERATING SYSTEM USED IN A MULTIPROCESSOR SYSTEM

All interconnection topologies are implemented using the microprocessor as a
node. The microprocessors used as nodes may also work as standalone processors
or sub-processing units under the control of other microprocessors. Once the
microprocessors are arranged in a particular topology, an appropriate operating
system and system software are required, which will be able to work in coordination
with the new system resources.
An operating system is a program that resides in the computer memory and
acts as an interface between the user or application program and the computer
resources. It provides a means of hardware and software resource management,
including memory and I/O management in a computer. It also enables the user
to communicate with the hardware using simple commands. The success of a
multiprocessor system relies on the operating system. The operating system used
for a single processor cannot be used for a multiprocessor system. The operating
system and the system software needed for the multiprocessor system should have
the flexibility and the ability to work with or run under the control of more than
one processor at a time. Distributed operating systems and the related system
software are the solution to this.
Distributed operating systems are designed to run parallel processes. Hence it is
essential that a proper environment exists for concurrent processes to communicate
and cooperate, to complete the allotted task. The features expected from a
distributed operating system used in a multiprocessor system are as follows:
(i) A distributed operating system should provide a mechanism for inter
process and inter-processor communication.
(ii) A distributed operating system must be capable of handling the structural
or architectural changes in the system, which occur due to expected or
unexpected reasons such as faults or modifications in the configuration.
(iii) A distributed operating system should also take care of unauthorized data
access and data protection, as the data sets in these systems are referred to
by more than one processor.
(iv) A distributed operating system must have a mechanism to split the given
tasks into concurrent subtasks, which can be executed in parallel on different
processors, and to collect the results of the subtasks and further process
these to obtain the final result.
17.8 TYPICAL MULTIPROCESSOR SYSTEM HAVING 8086 AND 8087

Let us see the details of a typical multiprocessor system consisting of the 8086 and
the 8087 (numeric coprocessor). The 8087 is a coprocessor that has been designed
to work under the control of the 8086 and gives additional numeric processing
capabilities to the 8086. The 8087 is a 40 pin IC and is available in 5, 8, and
10 MHz versions, compatible with different versions of the 8086.
When the 8086 is interfaced with the 8087, the instructions of the 8087 can be
included in the program to be executed by the 8086. The 8086 performs the opcode
fetch cycles and identifies the instructions for the 8087. Once the instructions
for the 8087 are identified by the 8086, they are assigned to the 8087 for further
execution. After the 8087 executes that instruction, the results may be sent to the
8086 or stored in the memory. The 8087 adds 68 new instructions to the instruction
set of the 8086.
17.8.1 Architecture of 8087

The simplified block diagram of the 8087 is shown in Fig. 17.14. The 8087 has two
internal sections—the control unit (CU) and the numeric extension unit (NEU).
The NEU executes all the numeric processor instructions, while the CU receives
and decodes the instructions, and reads or writes memory operands. The control
unit is also responsible for establishing communication between the CPU (8086)
and the memory, and also for coordinating the internal coprocessor execution. The
internal data bus in the 8087 is 84 bits wide, including the 68-bit fraction, 15-bit
exponent, and sign bit. The microcode control unit in the 8087 generates the control
signals required for the execution of the 8087 instructions. The 8087 contains a
programmable shifter, which is responsible for shifting the operands during the
execution of instructions such as FMUL and FDIV. The data bus interface in the
8087 connects its internal data bus with the system data bus of the 8086.
Fig. 17.14 Simplified block diagram of 8087
17.8.2 Pin Details of 8087

The different signals of the 8087 are discussed in detail in this section.
Figure 17.15 shows the pin diagram of the 8087.
(i) AD0-AD15: These are the multiplexed address/data lines. These lines carry
addresses during the T1 state and data during the T2, T3, TW, and T4 states,
as in the 8086. These lines act as the input lines for the 8086-driven bus
cycles and become the input/output lines for the NDP-initiated bus cycles.
(ii) A19/S6-A16/S3: These lines are time multiplexed address/status lines and
are the same as in the 8086. S3, S4, and S6 are permanently high, while S5
is permanently low.
(iii) BHE/S7: During TI, the BHE/S7 pin is used to enable the data on the
higher-order byte of the 8086 data bus. During the T2-T4 clock cycles, it
acts as the status line S7.
(iv) QS1 and QSO: The queue status input signals QS1 and QSO enable the
8087 to keep track of the instruction queue status of the 8086, to maintain
synchronism with it. Their function is same as that of the QS1 and QSO
pins in the 8086. These lines are connected to the corresponding lines of the
8086.
(v) INT: The interrupt output is used by the 8087 to indicate that unmasked
exceptions, such as invalid operation, divide-by-0, overflow, etc., have
been received during the execution of the instruction.
(vi) BUSY: This output signal indicates to the 8086 that the 8087 is busy with
the execution of an allotted instruction. This is usually connected to the
TEST input of the 8086.
(vii) READY: This input signal may be used to inform the 8087 that the addressed
device such as the memory or the I/O device will complete the data transfer
from its side. Usually this signal is synchronized by the clock generator
(8284).
(viii) RESET: This input signal is used to disc ard the internal activiti es of the
coprocessor and prepare it for further extjcution, whenever need<3d by the
8086.
(ix) CLK: The CLK input provides gnd E1 X------- X 40 —I ^cc
the basic timings for the 8087. AD14 E 2 39 □ AD15

Its frequency is the same as that AD13 *- 3 38 □ A16/S3 {
of the 8086. AD12 E: 4 37 □ A17/S4
AD11 E 5 36 □ A18/S5 |
(x) Vcc: A+5 V supply is connected AD10 6 35 □ A19/S6 |
to this pin. AD9 c 7 34 □ BHE/S7 j
(xi) GND: This is used as the return ads e8 33 □ RQ/GT1
line for the Vcc supply. ad? e 9 32 □ INT
10 8087 31
(xii) S2, SI, and SO: These pins can AD6 E □ RQ/GTO
. . ... ADR r- 11 30 □ NC
act either as output pins driven L
by the 8087 or as input pins jz 12 29 □ NC
13 28 □ S2
driven by the 8086. If these AD2 |- 14 27 □ si
are driven by the 8087, they AD1 [- 15 26 □ so
can be decoded as shown in ado e 16 25 □ QSO
Table 17.1. These are used by no E 17 24 □ QS1
the bus controllers to derive the NC E 18 23 □ BUSY
Read and Write signals. These CLK *- 19 22 □ READY

20 21 □ RESET
sianaK art as innnt shanals if
the CPU is executing a task. Fig 1715 Pin diagram of the 8087
(xiii) RQ/GTO: The request/grant pin is a bidirectional pin used by the 8087 to
gain control of the bus from the host 8086 for operand or data transfers. It
must be connected to one of the request/grant pins of the 8086. The request/
grant sequence is as follows:
An activate low pulse of one Table 17.1 Functions of S2, S1, and SO in 8087
clock duration is generated
by the 8087 for the host S2 S1 so Queue status
8086 to inform it that it 0 X X Unused

wants to gain control of the
1 0 0 Unused
local bus, either for itself
or for a coprocessor such 1 0 1 Memory read
as the 8089 (I/O processor) 1 1 0 Memory write
connected to the RQ/GT1
1 1 1 Passive
pin of the 8087. The 8087
waits for the grant pulse from the 8086, and when it is received, the 8087
either initiates a bus cycle if the request is for itself or passes the grant pulse
to RQ/GT1 if the request is for the other coprocessor. The 8087 releases the
bus by sending one more pulse on the RQ/GTO line to the host 8086, either
after completion of the last bus cycle initiated by it, or as a response to a
release pulse on the RQ/GT1 line issued by a coprocessor.
(xiv) RQ/GT1: This bidirectional pin is used by the other bus masters to convey
their need for local bus access to the 8087. At the time of request, if the
8087 does not have control of the bus, the request is passed on to the host
CPU using the RQ/GTO pin. If the 8087 has control over the bus, when it
receives a valid request on the RQ/GT1 pin, it sends a grant pulse during
the following TI or T4 clock cycle to the requesting bus master, indicating
that it has floated the bus. The requesting bus master then gains control of
the bus until there is a need. At the end, the requesting bus master issues an
active low, one clock-state-wide pulse for the 8087, to indicate that the task
is over, and the 8087 regains the control of the bus. The request/grant pins
may be used by other bus masters such as DMA controllers.
17.8.3 Interconnection of 8087 with 8086

The physical interconnection of the 8087 with the 8086 is shown in Fig. 17.16. The
8087 can be connected with the 8086 only when the 8086 is operating in maximum
mode. In the maximum mode, all control signals are derived using a separate chip
called Bus Controller (8288). The BUSY pin of the 8087 is connected with the
TEST pin of the 8086. The QS0 and QS1 lines in the 8087 are directly connected
to the corresponding pins in the 8086-based system. The RQ/GTO pin of the 8087
may be connected to the RQ/GTO pin of the 8086. The clock pin of the 8087 may
be connected to the 8086 clock input. The interrupt output of the 8087 is sent to
the 8086 through a chip called programmable interrupt controller (8259). The pins
AD15-AD0, A19/S6-A16/S3, BHE/S7, RESET, and READY of the 8087 are
connected to the corresponding pins of the 8086.
While fetching the instructions from the memory, the 8086 monitors the data
bus to check for the 8087 instructions. The control unit of the 8087 internally
8288
CLK
Control bus
S2 S1 SO
Fig. 17.16 Interconnection of 8087 with 8086
maintains a parallel queue, identical to the instruction queue of the 8086. The
8087 uses the QSO and QS1 pins to obtain and identify the instructions fetched by
the 8086. The 8086 identifies the coprocessor instructions using the escape code
bits embedded in them. The first five bits of the escape code are 11011. Once
the 8086 recognizes the escape code, it initiates the execution of the coprocessor
instructions in the 8087. Each coprocessor instruction also has the opcode of the
WAIT instruction of the 8086 as its first byte. So the 8086 waits in a loop, checking
its TEST pin, to go low. The TEST pin of the 8086 is connected to the BUSY
pin of the 8087, which remains high until the 8087 finishes the execution of the
recently received instruction from the 8086. Once the 8087 finishes the execution,
it makes its BUSY pin low and the 8086 starts its normal operation.
During the execution of a coprocessor instruction in the 8087, the escape code
identifies the coprocessor instruction that requires a memory operand and also
the one that does not require any memory operands. If the instruction requires a
memory operand to be fetched from the memory, the physical memory address
of the operand is calculated by the 8086 and a dummy read cycle is initiated.
However, the 8086 does not read the operand. The 8087 reads it and proceeds for
execution. If the coprocessor instruction does not require any memory operand,
it is directly executed by the 8087. When the 8087 is ready with the execution
results, the control unit of the 8087 gets the control of the bus from the 8086
and executes a write cycle to write the results in the memory at the pre-specified
address. The numeric extension unit of the 8087 executes all the instructions
including arithmetic, logical, transcendental, and data transfer instructions.
17.8.4 Data Types of 8087

The 8087 can operate on memory operands of seven different data types—word
integer, short integer, long integer, packed BCD, short real, long real, and
temporary real. The number of bytes, format, and approximate range for each of
these data types are as follows:
(i) Word integer data type
Number of bytes = 2
Approximate range = (-32768) - (+32767)
S—Sign bit
Bit 15 Bits 14-0
S Magnitude
(ii) Short integer data type

Number of bytes = 4
Approximate range = (-2 x 109) - (+2 x 109)
S—Sign bit
Bit 31 Bits 30-0
S Magnitude
(iii) Long integer data type

Number of bytes = 8
Approximate range = (-9 xlO18) - (+9 x 1018)
S—Sign bit
Bit 63 Bits 62-0
S Magnitude
(iv) Short real data type

Number of bytes = 4
Approximate range = (±1 x 10'38) - (±3 x IO38)
S—Sign bit __________
Bit 31 Bits 30-23 Bits 22-0
S Biased exponent Fraction
(v) Long real data type

Number of bytes = 8
Approximate range = (±1O 308) - (±1O308)
S—Sign bit
(vi) Temporary real data type

Number of bytes =10
Approximate range = (±10-4932) - (±104932)
S—Sign bit
The term biased exponent in all the real data types is obtained by adding
a bias to the exponent of the real number. The value of the bias is 127,
1023, and 16,383 for short, long, and temporary real data, respectively. The
general form of representation of the real number in the all the three cases
is
(-l)s x 2 (E~bias) x l.F
where S is the sign bit, E is the biased exponent, and F is the fraction part,
(vii) Packed BCD
Number of bytes =10
Approximate range = (-1018 + 1) - (1018- 1)
S—Sign bit
Bit 79 Bits 78-72 Bits 71-68 Bits 67-64 ... Bits 8-5 Bits 7-4 Bits 3-0
S 0 D17 D16 D2 DI DO
DO, DI, D2... DI6, and D17 represent the BCD code of each digit in
the packed BCD number. Further details of the 8087 can be obtained by
referring to the data sheet of the 8087.
17.9 TYPICAL MULTIPROCESSOR SYSTEM HAVING 8086 AND 8089

While accessing I/O devices by non-DMA data transfer using the serial and
parallel ports in the personal computer, the CPU (such as the 8086) is required to
set up the interfacing chips used to access the I/O devices and perform the actual
data transfer. For high speed devices, data are transferred using DMA, but the
CPU has to set up the device controller, initiate the DMA operation, and check
the post-transfer status after the completion of each DMA operation. The 8089 I/O
processor is designed to handle the tasks involved in I/O processing. An IOP can
fetch and execute its own instructions, unlike a DMA controller.
The instruction set of the 8089 is specifically designed for I/O operations,
but in addition to data transfer, it can perform arithmetic and logic operations,
branching, searching, and translation. The CPU communicates with the 8089
through memory-based control blocks. The CPU prepares control blocks that
describe the task to be performed, and then sends the task to the 8089 through
an interrupt-like signal. The 8089 reads the control blocks to locate a program
called a channel program, which is written using the 8089 instruction set. Then
the 8089 performs the assigned task by fetching and executing instructions from
the channel program. When the 8089 has finished the task, it informs the CPU
either through an interrupt or by updating a status location in the memory.
17.9.1 Pin Details of 8089

The pin diagram of the 8089 is shown in Fig. 17.17.
The details of various pins are as follows:
(i) A0-A15/D0-D15 (multiplexed
address/data bus): The function vss □ 1 v__ y 40 □ Vcc
39 □ A15/D15 \
of these lines is defined by A14/D14 □ 2
A13/D13 □ 3 38 □ A16/S3 I
the state of the SO, SI, and
A12/D12 □ 4 37 b A17/S4
S2 lines. The pins are floated A11/D11 □ 5 36 n A18/S5 j
after reset and when the bus A10/D10 □ 6 35 □ A19/S6
is not acquired. The signals A9/D9 □ 7 34 □ BHE
in A8-A15 remain the same A8/D8 c 8 33 □ EXT1 (
A7/D7 □ 9 32 □ EXT2
on transfer to a physical 8-
A6/D6 □ 10 8089 31 □ DRQ1
bit data bus (used with the
A5/D5 c 11 30 □ DRQ2 |
8088 processor as it has an A4/D4 □ 12 29 □ LOCK
8-bit data bus and 20-bit address A3/D3 c 13 28 □ S2
bus) and are multiplexed with A2/D2 □ 14 27 □ S1
data D8-D15 on transfers to a A1/D1 □ 15 26 □ SO
AO/DO □ 16 25 □ RQ/GT
16-bit physical bus (used with
SINTR-1 q 17 24 □ SEL
the 8086 processor). SINTR-2 □ 18 23 □ CA
A19-A16/S6-S3 (address and CLK □ 19 22 □ READY |
status bus): The address lines Vss □ 20 21 □ RESET |
are active only when addressing
memory. Otherwise, the status Fig. 17.17 Pin diagram of the 8089
lines are active and are

Table 17.2 Status bits and their significance
encoded as shown in Table
17.2. The pins are floated S6 S5 S4 S3 Significance
after reset and when the 1 1 0 0 DMA cycle on CHI
bus is not acquired.
1 1 0 1 DMA cycle on CH2
(iii) BHE (Bus High Enable):
The Bus High Enable 1 1 1 0 Non-DMA cycle on CHI
signal is used to enable 1 1 1 1 Non-DMA cycle on CH2
data operations on the most --------- ---------------------------------------------------
significant half of the data bus (D8-D15). The signal is active low when a byte
is to be transferred on the upper half of the data bus. The pin is floated after
reset and when the bus is not acquired. BHE does not have to be latched.
(iv) S2, ST, and SO (status pins): These are status pins, which define the IOP
activity during any given cycle. They are encoded as shown in Table 17.3.
The status lines Table 17.3 Status bits for defining IOP activity
are utilized by the S2 SI SO Significance
bus controller and
the bus arbiter to 0 0 0 Instruction fetch (I/O space)
generate all the 0 0 1 Data fetch (I/O space)
memory and I/O 0 1 0 Data store (I/O space)
control signals.
The signals change 0 1 1 Not used
during T4 if a 1 0 0 Instruction fetch (System memory)
new cycle is to be 1 0 1 Data fetch (System memory)
entered, while the
1 1 0 Data store (System memory)
return to passive
state in T3 or TW 1 1 1 Passive
indicates the end
of the cycle. The pins are floated after system reset and when the bus is not
acquired.
(v) READY: The Ready signal received from the addressed device indicates
that the device is ready for data transfer. The signal is active high and is
synchronized by the 8284 clock generator.
(vi) LOCK: The Lock output signal indicates to the bus controller that the bus is
needed for more than one contiguous cycle. It is set via the channel control
register and during the TSL instruction. The pin floats after reset and when
the bus is not acquired. The output is active low.
(vii) RESET: The receipt of a Reset signal causes the IOP to suspend all its
activities and enter idle state until a Channel Attention signal is received.
The signal must be active for at least four clock cycles.
(viii) CLK (clock): The clock provides all the timing needed for internal IOP
operation.
(ix) CA (Channel Attention): This signal gets the attention of the IOP. When
the falling edge of this signal is encountered, the SEL input pin is examined
to determine master/slave or CH1/CH2 information. This input is active
high.
(x) SEL (Select): The first CA received after system reset informs the IOP
via the SEL line, whether it is a master or a slave (0 and 1, respectively),
and starts the initialization sequence. During any other CA, the SEL line
signifies the selection of CHI and CH2 (0 and 1, respectively).
(xi) DRQ1 and DRQ2 (Data Request): The DMA requests inputs, which signal
to the IOP that a peripheral is ready to transfer and receive data using
CHI and CH2, respectively. The signals must be held active high until the
appropriate fetch/stroke is initiated.
(xii) RQ/GT (Request Grant): The Request Grant signal implements the
communication dialogue required to arbitrate the use of the system bus
(between IOP and CPU in local mode) or I/O bus when two lOPs share the
same bus (remote mode). The RQ/GT signal is active low. An internal pull-
up permits RQ/GT to be left floating, if not used.
(xiii) SINTR-1 and SINTR-2 (Signal Interrupt): The Signal Interrupt signal
outputs from CHI and CH2, respectively. The interrupts may be sent
directly to the CPU or through the 8295A interrupt controller. They are
used to indicate to the system the occurrence of user-defined events.
(xiv) EXT1 and EXT2 (External Terminate): The External Terminate signal inputs
from CHI and CH2, respectively. The EXT signal causes the termination
of the current DMA transfer operation, if the channel is so programmed by
the channel control register. The signal must be held active high until the
termination is complete.
Vcc: Supply voltage (+5 V) Vss: Ground
17.9.2 Local and Remote Operation of 8089

The 8089 assumes all the work involved in an I/O transfer, including device setup,
DMA operation, and programmed I/O, thereby relieving the CPU from the burden
of I/O processing. This allows the CPU to concentrate on higher-level tasks, while
the 8089 takes care of I/O processing. This greatly simplifies system software and
hardware efforts, and improves system performance and flexibility, by the distributed
processing approach. The 8089 may be operated in a local (closely-coupled)
configuration or a remote (loosely-coupled) configuration. In a local configuration,
which is shown in Fig. 17.18, the 8089 shares the bus interface with the host (8086)
by using its RQ/GT pins. All resources are accessed through the system bus.
In a remote configuration, which is shown in Fig. 17.19, the 8089 may have its
own local I/O bus and requires a bus arbiter and controller, address latches, and
Fig. 17.18 8089 IOP in local configuration

Fig. 17.19 8089 IOP in remote configuration
data transceivers for accessing the shared system bus. The RQ/GT pin on the 8089
can be used to interact with another 8089, which acts as the slave and shares the
buses with the host 8089. The 8089 accesses I/O devices dedicated to it through
the local bus, while it communicates with the CPU through the system memory.
A high speed controller may request a transfer through one of the two DRQ pins
(DRQ1 and DRQ2) in the 8089, and terminate a DMA operation through one of
two EXT pins (EXT1 and EXT2) in the 8089. To reduce the system bus loading and
enhance concurrent processing, local memory can be included to store the channel
programs or to provide storage areas. However, the local memory must respond
to I/O bus commands instead of memory read and memory write commands (i.e.,
it must act as the I/O-mapped memory). Unlike the 8086, the 8089 I/O bus need
not have the same data width as the memory bus. This allows the 8089 to transfer
data from an 8-bit source to a 16-bit destination and vice versa. Since the I/O
bus has only 16 address lines, the capacity of the local space (I/O space) is only
64 KB. On the other hand, the system space (i.e., memory space), which is
addressed by the system bus, has a capacity of 1 MB. The 8089 instructions access
I/O ports using the same addressing modes as are used for the memory operands.
Whether an address is in the I/O space or in the system space is determined by the
tag bit of the pointer register used.
17.9.3 8089 (IOP) Architecture

Figure 17.20 shows the internal structure of the 8089.
Fig. 17.20 Internal structure of the 8089
Figure 17.21 shows the registers in the 8089 IOP. Each of the two channels can
be programmed and operated independently while sharing the common control
logic and ALU. The channel control pointer (CCP) cannot be manipulated by
the user. It stores the address of the control block (CB) for channel 1 during the
initialization sequence. For channel 2, its CB starts at the address that is indicated
by adding 8 to the contents of the CCP. To
dispatch a task to either channel, the CPU
(8086) sends out a Channel Attention
(CA) signal along with the Select (SEL)
signal, which selects channel 1 (if SEL
- 0) or channel 2 (if SEL =1). Since the
channels occupy two consecutive I/O
port addresses, the AO address line of
the 8086 is connected to the SEL pin, so
that when A0 = 0, one channel is selected
and when A0 = 1, another channel is
selected.
Each channel has an identical set of
registers, each set being divided into two
(always points to system memory)
groups according to size. The pointer
19 |
group consists of those registers having
Parameter pointer (PP)
20 bits and the register group consists
of those registers having 16 bits. Each Channel control pointer (CP)
pointer, with the exception of parameter
pointer (PP), has an associated tag bit.
Fig. 17.21 Registers in 8089 IOP
When used to access a memory operand,
the tag bit indicates whether the contents of that pointer represent a 20-bit system
(i.e.. memory) space address (if tag = 0) or a 16-bit local (i.e., I/O) space address (if
tag = I). In accessing the local space, only the lower-order 16 bits of the pointer are
used as the address. Register PP always points to an address in the system space.
The registers GA, GB, GC, IX, BC, and MC can be used as general-purpose
registers for arithmetic and logical operations in a channel program. In addition,
they perform special functions when addressing memory operands and executing
DMA operations. A memory operand can only be addressed by using one of the
pointers GA, GB, GC, or PP as a base register. During a DMA operation, GA and
GB are used as the source and destination pointers. If GA points to the source. GB
points to the destination, and vice versa. When a translation operation is performed
along with the DMA transfer, the contents of GC are used as the base address of a
256-byte translation table. Register BC is used as the byte counter during a DMA
transfer, and is decremented by 1 after every byte transfer and by 2 after every
word transfer.
For a masked compare operation, register MC contains the bit pattern to be
compared against in bits 7-0 and a mask in bits 15-8. A masked compare operation
is done according to the following expression:
((OPERAND BYTE) © (MC)7J A (MC)15 8
The results of the masked compare operation can be used as a DMA termination
condition or to determine whether or not a branch is to be made by a masked
compare branch instruction. The register IX is used as an index register. In two of
the memory operand addressing modes, its contents are added to those of a base
register to form the operand address. The task pointer (TP) stores the address of
the next instruction to be executed and is equivalent to the PC in a CPU. It also
has a tag bit for indicating whether the next instruction to be executed is stored in
the system or VO space. The parameter pointer (PP) is not programmable by the
user, but is automatically filled by the 8089 while initializing a task. PP points to
the address of the parameter block.
Each channel also has an 8-bit status register (PSW), which contains the
current channel status. This status indicates status descriptors such as the source
and destination address widths, channel activity, interrupt control and servicing,
bus load limit, and priority. The PSW cannot be manipulated by the user, but can
be modified by a channel command. It is saved with TP and the four tag bits in
the first two words of the parameter block, when a channel program is suspended.
This allows the channel to resume the suspended channel program upon receipt of
a resume command.
The 8089 has the capability to perform DMA transfers using different options.
The transfer direction can be specified as I/O to VO, memory to memory, or
memory to/from VO. For each transfer, the 8089 fetches a byte or word, stores
the data in the destination and updates GA, GB, and BC accordingly. If data are
transferred from an 8-bit source to a 16-bit destination, the 8089 can fetch two
bytes and store them as one word. Conversely, if the transfer is from a 16-bit
source to an 8-bit destination, a word can be split into two bytes, betore the data
are sent to the destination. Between the fetch and the store cycles of the DMA,
the data byte can be compared or translated. Further, a DMA operation can be
terminated by an external request, a zero byte count, or a match/mismatch detected
by a masked compare. These options are specified by the contents of the channel
control register (CC) whose format is as follows:
Termination control bits 6-0 These bits specify how the DMA is to be
terminated and where to fetch the next instruction from, upon completion of the
DMA operation. A DMA transfer can be terminated after the current transfer
cycle, based on the comparison (bits 2,1, and 0) shown in Table 17.4 (a), the
byte count (bits 4 and 3) shown in Table 17.4 (b), and the external control (bits 5
and 6) shown in Table 17.4 (c), or a combination of the three. If external control
is selected, the channel terminates the DMA when the channel’s EXT (external
termination) input is activated. If the byte count is specified, a 0 in the channel’s
BC register causes the DMA to terminate. Whether or not a comparison is to result
in a termination and whether a match or mismatch is to cause the termination is
determined by bits 2 to 0.
Table 17.4 (a) Function of termination control bits 2-0
Bit 2 Bit 1 BitO Termination condition and offset

0 0 0 No termination by masked comparison
0 0 1 Terminates when comparison matches; offset is set to 0
1 0 0 No effect
1 0 1 Terminates when there is no match; offset is set to 0
Table 17. 4 (b) Function of termination control bits 4 and 3
Bit 4 Bit 3 Termination condition and offset
0 0 No termination by byte counter

0 1 Terminates when BC = 0; offset is set to 0
Table 17.4 (c) Function of termination control bits 6 and 5
Bit 6 Bit 5 Termination condition and offset
0 0 No external termination
0 1 Terminates when EXT = 1; offset is set to 0
The channel executes the instruction whose address is the contents of TP, plus
an offset upon the termination of a DMA operation. Therefore, when more than
one termination condition is specified, it is possible to use the offset in conjunction
with the branch instruction to enter different DMA completion routines, depending
on the actual cause of the DMA termination. If more than one of the selected
conditions occurs at the same time, the largest offset that corresponds to a satisfied
condition is used. To initiate a DMA transfer, the channel program should contain
instructions for setting up the source and destination pointers CC, BC and, if
necessary, GC, MC, and the I/O bus width.
Single transfer mode (bit 7) This bit is used to terminate the DMA after a single
transfer if it is set to 1 and then execute the next instruction pointed to by TP.
Chaining control (bit 8) This bit gives the other channel (i.e., channel 2, when
channel 1 is programmed and vice versa) the highest priority. This bit is not used
for DMA operation.
Lock control (bit 9) This bit activates the LOCK output of the 8089 during the
DMA transfer cycle, if it is set to 1.
Source/destination indicator (bit 10) This bit specifies whether the register
GA is used as the source pointer (i.e., the bit is 0) or the destination pointer (i.e.,
the bit is 1). In either case, GB is used as the other pointer.
Synchronization control (bits 12 and 11) These bits specify how the data
transfer is to be synchronized. An unsynchronized transfer (if the bits are 00) begins
the next transfer cycle whenever a bus cycle is available. A source-synchronized
transfer (if the bits are 01) starts the read operation of the next transfer cycle upon
receiving the DRQ signal. A destination-synchronized transfer (if the bits are 10)
starts the write operation of the next transfer cycle when the DRQ is received.
Translation mode (bit 13) This bit indicates that the data bytes are to be
translated through a 256-byte look-up table during DMA (if the bit is 1). The base
address of the translation table should be stored in register GC.
Function control (bits 15 and 14) These bits specify one of four data transfer
modes—memory to memory (if the bits are 11), I/O port to memory (if the bits are
10), memory to I/O port (if the bits are 01), and I/O port to I/O port (if the bits are
00). During a memory to memory data transfer, both the destination and source
pointers are auto-incremented, but during and after an I/O to I/O data transfer,
both pointers remain unchanged. These two modes are not supported by most
conventional DMA controllers. They are useful in moving a block of code or data
from one memory area to another and in direct device communications.
17.9.4 Communication between CPU (8086) and IOP (8089)

Inter-processor communication, including the 8089 IOP initialization and task
dispatch, is memory-based and is accomplished by means of a linked list of control
blocks. The first control block in the linked list is stored beginning at the fixed
location FFFF6H in the memory. The others may reside in user-defined areas.
each of which is pointed to by the previous control block. The IOP communication
areas are shown in Fig. 17.22. The system configuration pointer block (SCPB)
contains three words starting at location FFFF6H in the system memory. The least
significant byte (SYSBUS) specifies the width of the system bus, which is eight
bits if SYSBUS = 0 and 16 bits if SYSBUS = 1. The succeeding two words store
the offset and segment address of the location of the system configuration block
(SCB). The SCB does not need to be stored at a fixed location. However, it must
reside in the system space. The least significant byte of the SCB is the system
operation command (SOC). Bits 0 and 1 of the system operation command define
the width of the VO bus and the RQ/GT mode as follows:
Bit 1 = 0 indicates the standard RQ/GT mode.
Bit 1 = 1 indicates the modified RQ/GT mode for use with multiple 8089s.
Bit 0 = 0 indicates an 8-bit I/O bus.
Bit 0 = 1 indicates a 16-bit I/O bus.
The last two words in the SCB contain the offset and segment address of the
beginning of two consecutive channel control blocks (CBs) in the system space.
There is one control block for each channel and the first byte of each control block
is called the channel command word (CCW), which indicates the action to be taken
by the channel. The next byte (BUSY) indicates the busy status of the channel (00
for not busy and FF for busy) and the last two words contain the address of a
parameter block. A parameter block is used for providing the beginning address of
the channel program and passing information to and from this program.
Control block
(CB) for channel 1
Control block
(CB) for channel 2
System configuration
block (SCB)
System configuration
pointer block (SCPB)
Fig. 17.22 IOP communication structure

The format of a CCW is shown in Fig. 17.23. It includes a 3-bit command field,
a 2-bit interrupt control held, a bus load limit bit, and a priority bit.
Bit 7 Bit 6 Bit 5 Bits 5 and 4 Bits 2,1, and 0
P 0 B ICF CF
Fig. 17.23 Channel command word—CCW
The command held specihes one of the six possible commands shown in
Table 17.5.
Table 17.5 Function of CF field in channel command word (CCW)
CF Command field
000 Update PSW—causes PSW to be updated
001 Start channel program (VO space)—initiates the execution of a channel
program that is stored in the VO space
010 Reserved
011 Start channel program (system space)—initiates the execution of a channel
program that is stored in the system space
100 Reserved
101 Resume suspended channel operation—causes a suspended operation to be
continued from the point at which it was stopped
110 Suspend channel operation—suspends the operation currently being
performed by the channel until a resume command is given
111 Halt channel operation—aborts the current channel operation
The interrupt control held (ICF) is used for enabling (ICF =10) and disabling
(ICF = 11) interrupt requests and for removing previous interrupt requests
(ICF = 01). When an IOP sends out an interrupt request, it sets a service bit in its
PSW. While the interrupt is being serviced, this bit must be cleared by sending the
IOP a command with 01 in the interrupt control held. Otherwise, a request would
block other requests. If ICF = 00, it has no effect on interrupts.
When the bus load limit (B) bit is 0, there is no bus load limit and when it
is 1, there exists a bus load limit, during which the IOP can execute only one
instruction every 128 clock cycles. This prevents the IOP from monopolizing the
bus in situations in which there is no need for it to be the dominant processor.
The priority bit in the PSW is set or cleared according to the priority bit (P) in the
CCW. Further details about the 8089 can be obtained from the data sheet of the
8089.
.... x .... ~ A'.,

POINTS TO REMEMBER^
• In a multiprocessor system, more than one processor works cooperatively to solve a

common task.
• There are different configurations of multiprocessor systems, such as coprocessor,
closely-coupled and loosely-coupled multiprocessor system.
• There exist different interconnection topologies between processors and memories in a
multiprocessor system.
• The physical interconnections between processors in a multiprocessor system can be
different.
• A distributed operating system is commonly used in a multiprocessor system.
• The numeric coprocessor (8087) is used to perform floating-point operations
efficiently.
• The I/O processor (8089) is used to perform various I/O operations, relieving the CPU
to perform higher-level functions.
KEY TERMS
Bus arbitration This is the method by which allotment of a system bus to a particular
requesting master is done amongst the many requesting masters at a time. There are three
methods of bus arbitration—daisy chain, polling, and independent requests.
Closely-coupled system A closely-coupled multiprocessor system is one in which the
external processor or coprocessor shares not only the entire memory and I/O subsystem in
the system, but also the same bus control logic and clock generator of the main processor.
Distributed operating system This is an operating system used in a multiprocessor
system to efficiently run a task in the system and to protect the program and data of different
modules in the system from unauthorized accesses.
Interconnection topology This is the way in which communication among the
microprocessors is performed in a multiprocessor system. There are different methods of
interconnection between processors—shared bus architecture, multi-port memory, linked
input/output, and crossbar switch.
I/O processor (IOP) An I/O processor is a processor that is mainly used to perform I/O-
related operations, to relieve the microprocessor from the relatively slow I/O operations.
IOP is also a coprocessor.
Loosely-coupled system Each module in a loosely-coupled system may act as the system
bus master and may consist of an 8086 or another processor, capable of being a bus master,
a coprocessor, or a closely-coupled configuration. Several modules may share the system
resources and the system bus control logic must resolve the bus contention problem.
Multiprocessor system A multiprocessor system is one that contains more than one
processor for improving the performance of the system.
Numeric coprocessor or numeric data processor A numeric coprocessor is a processor
that works in conjunction with a microprocessor to perform floating-point operations
quickly.
REVIEW GUESTIONS
1. What is meant by a multiprocessor system?

2. What are the advantages of a multiprocessor system?
3. What are the different schemes of bus arbitration?
4. What is the advantage and disadvantage of the daisy chain method of establishing
priority among modules in a multiprocessor system?
5. What is meant by the polling method of establishing priority among the modules in a
multiprocessor system?
6. How is interconnection between processors done in multi-port memory?
7. Draw the diagram showing the linked input/output scheme of interconnection between
processors.
8. How is the interconnection between processors done in the crossbar switch scheme?
9. How are the physical interconnections between processors classified?
10. What is the drawback of the completely connected configuration method of physical
interconnection among processors?
11. What is meant by the regular topology scheme of physical interconnection among
processors?
12. What is an operating system?
13. What are the features of a distributed operating system?
14. What are the two main parts in the 8087 and their function?
15. What is the function of the BUSY and READY pins in the 8087?
16. What is the function of the QSO and QS1 pins in the 8087?
17. What is the function of the 8089?
18. Explain closely-coupled and loosely-coupled multiprocessor systems, with necessary
diagrams.
19. Describe the different bus arbitration schemes used in a loosely-coupled multiprocessor
system, with necessary diagrams.
20. With neat diagrams, explain the different interconnection topologies used for
communication among the processors in a multiprocessor system.
21. Describe the different physical interconnections between processors in a multiprocessor
system, with neat diagrams.
22. Draw and explain the block diagram of the 8087 and the main signals in the 8087.
23. Draw the diagram showing the interconnection of the 8086 with the 8087 and explain
the communication between these two processors in detail.
24. Draw and explain the block diagram of the 8089 and the main signals in the 8089.
25. Draw the diagram showing the interconnection of the 8086 with the 8089 and explain
the communication between these two processors in detail.
THINK AND ANSWER
1. How is the priority among modules in a multiprocessor system resolved in independent

requests scheme?
2. How does the 8086 identify an 8087 instruction when it fetches an instruction from the
memory?
3. How is priority among several masters established in daisy chain method?
4. Why is biased exponent used to represent floating point numbers?
5. Why is the capacity of the local I/O space 64 KB in 8089?
8086-BASED SYSTEMS
LEARNING OUTCOMES
• Minimum and maximum mode operation of an 8086-based system
• Function of the clock generator (8284A) and the bus controller (8288)
• Bus timings, interrupt acknowledgement, and bus request and grant in the 8086
18.1 INTRODUCTION
To adapt to different situations, the 8086 processors can be operated either in the
minimum or the maximum mode. The minimum mode is used for a small system
with a single processor (8086) and in any system in which the 8086 generates all
the necessary bus control signals directly, thereby minimizing the required bus
control logic. The maximum mode is for medium to large size systems, which
often include two or more processors. In the maximum mode, the 8086 encodes
the basic bus control signals into three status bits (S2, ST, and SO) and uses the
remaining control pins to provide the additional information that is needed to
support the multiprocessor configuration.
18.2 8086 IN MINIMUM MODE CONFIGURATION

The 8086 is configured in minimum mode when its MN/MX pin is connected to
+5V. A typical minimum mode configuration of the 8086 is shown in Fig. 18.1.
The figure illustrates the 8284 IC generating the clock, Ready and Reset signals for
the 8086. The decoder is used to generate the four control signals MEMR, MEMW,
IOR, and IOW using the M/IO, RD, and WR signals of the 8086. The chip select
(CS) logic is used to generate the Chip Select signals for the odd and even memory
banks of the RAM and ROM chips and the I/O devices using BHE, A0, and a few
higher-order address lines of the 8086. The CSE and the CSO signals represent the
Chip Select signal for the even bank and odd bank of the memory, respectively.
CSIO represents the Chip Select signal for the input/output (RO) devices.
The address from the 8086 and the BHE signals are latched externally using
three 74LS373 (octal latch) ICs, since they are available only during the first part
of the bus cycle. The ALE signal of the 8086 is used to indicate that the bus
contains a valid address and is connected to the G or CLK input of the 74LS373 as
shown in Fig. 18.2.
18.2.1 Formation of Separate Address Bus and Data Bus in 8086

If the 8086-based system includes several interfaces, transceivers (driver and
receiver) are required for the data lines. This may not be a requirement for small,
8086-BASED SYSTEMS 567
Fig. 18.1 Minimum mode operation of an 8086-based system
Fig. 18.2 Formation of separate address bus (A19-A0) and data bus (D15-D0) in the 8086
single-board 8086-based systems. The 74LS245 IC can be used as a transceiver

(driver/receiver) for the data lines. Since the 8086 has 16 data lines, two 74LS245
ICs are required (the 74245 being an 8-bit transceiver).
18.2.2 Formation of Buffered Address Bus and Data Bus in 8086

Figure 18.3 shows the connection of two 74LS245s with the 8086. The EN (enable)
pin determines whether or not data are allowed to pass through the 74LS245 and the
DIR (direction) pin controls the direction of the data flow. When EN = 1, data are not
transmitted through the 74245 in either direction. If EN is 0, DIR = 0 causes the data to
flow towards the 8086 and DIR = 1 results in data being outputted from the 8086. In an
8086-based system, the EN pin of the 74245 is connected to the DEN pin, since DEN
of the 8086 is made active low (i.e., logic 0) whenever the processor is performing an
I/O or memory read/write operation. The AD7-AD0 pins of the 8086 are connected
to the inputs of one 74245 and the AD8-AD15 pins are connected to the inputs of
another 74245. The DIR pin of the 74245 is tied to the processor’s DT/R pin. The
processor floats (tri-states) the DEN and the DT/R pins, in response to a bus request
on the HOLD pin. Similarly, three 74244 ICs (buffer/driver) are used to generate the
buffered address bus (BA0-BA19), as shown in Fig. 18.3. The Intel 8282 IC and the
Intel 8286 IC can be used instead of the 74LS373 and the 74245, respectively.
Fig. 18.3 Formation of buffered address bus and data bus in 8086
18.2.3 Connection of 8284A with 8086

Figure 18.4 (a) shows the clock generator IC (8284A), which supplies a train of
pulses at a constant frequency to the 8086. The connection of the 8284A with the
8086 is shown in Fig. 18.4 (b). It synchronizes the Ready (RDY) signal (which
indicates that an I/O device or memory interface is ready to complete a data transfer)
received from an I/O or memory interface, by activating the READY input of the
8086 at the right time in a bus cycle. Similarly, when the Reset (RES) signal of the
8284A is activated, it activates the RESET input of the 8086 at the right time in a
bus cycle, which initializes the 8086 system. The clock pulse source applied to the
8284A may be from a pulse generator that is connected to the EFI pin or an oscillator
that is connected across XI and X2. If the input to F/C is 1, the EFI input determines
the frequency. Otherwise, the oscillator input determines the frequency. In either
case, the 8284 clock output (CLK) is one-third of the input frequency. All the
devices, 74373, 74245, and 8284A, require only +5 V supply voltage. Their inputs
and outputs are TTL-compatible and therefore the devices are compatible with each
other and with the 8086. CSYNC is used in systems with multiple processors.
Fig. 18.4 (a) pin details of the 8284A (b) Typical 8284A connection with the 8086
In the minimum mode system, the control lines (RD, WR, and M/IO) need not
be passed through transceivers, but can be used directly. The RD, WR, and M/IO
lines indicate the type of data transfer, as shown in Table 18.1.
Since the content of CS and IP are
FFFFH and 0000H after reset, the first Table 18.1 Function of the 8086 control signals
instruction for execution is fetched in minimum mode operation
from the memory address FFFFOH M/IO RD WR Operation
(= CSX10H + IP) by the 8086. Hence,
0 0 1 I/O read
the system start-up program must be
0 1 0 I/O write
stored from the address FFFFOH in
1 0 1 Memory read
the memory. Normally, this address
1 1 0 Memory write
is assigned to a ROM type memory
chip, so that the system start-up
program is available permanently. The interrupt vector table is stored from the
address 00000H in the memory, whenever the interrupt(s) is (are) to be used in the
8086-based system. In addition, depending upon the system requirement, specific
interfacing ICs can be used along with the 8086.
(i) For interfacing the keyboard and the seven-segment display with the 8086,
the 8279 IC can be used.
(ii) To increase the number of hardware interrupts that can be handled by the
8086, the 8259 IC can be used.
(iii) To interface I/O devices such as DIP switches, ADCs, DACs, LEDs, relays,
and stepper motors with the 8086, the 8255 IC is used.
(iv) For performing serial communication, the 8251 IC is used with the 8086.
18.3 8086 IN MAXIMUM MODE CONFIGURATION

The 8086 operates in the maximum mode when its MN/MX pin is grounded.
A typical maximum mode configuration is shown in Fig. 18.5. The main difference
between the minimum and the maximum mode configuration is the need for
additional circuitry to interpret the control signals of the 8086. This additional
circuitry accepts the status signals SO, Si, and S2 from the 8086 and generates
the I/O- and memory-related control signals. It also generates the signals for
controlling the external latches (74373) and transceivers (74245).
It is normally implemented with an Intel 8288 bus controller IC. In addition, a
programmable interrupt controller (8259) is included in the system. However, its
presence is optional.
The SO, S1, and S2 status bits specify the type of transfer that is to be carried out
by the 8086 and when used with an 8288 bus controller, they are used to generate
the memory-, I/O-, and interrupt-related control signals. From the status bits SO,
S1. and S2, the 8288 is able to generate the Address Latch Enable (ALE) signal for
the 74LS373s, the enable and direction signals for the 74245 transceivers, and the
Interrupt Acknowledge signal (INTA) for the interrupt controller 8259. The QSO
and QS1 pins of the 8086 allow a system external to the 8086 processor such as the
8087 (coprocessor) to know the status of the processor instruction queue, so that it
can determine which instruction is currently executed by the 8086. The LOCK pin
indicates that an instruction with a LOCK prefix is being executed and that the bus
is not to be used by another master. These pins are needed only in multiprocessor
systems.
Fig. 18.5 Maximum mode operation of an 8086-based system
The HOLD and HLDA pins become the bus request and the bus grant (RQ/GTO
and RQ/GT1) pins in the maximum mode. Both bus requests and bus grants can be
given through these pins. Both the pins function in exactly the same way, except
that if requests are seen on both the pins at the same time, the one on RQ/GTO is
given higher priority. A request consists of an active low pulse arriving before the
start of the current bus cycle. The grant is an active low pulse that is issued at the
beginning of the current bus cycle provided that
(i) The previous bus transfer in the 8086 was not the lower-order byte of a
word to or from an odd address.
(ii) The first low pulse of an interrupt acknowledgement (INTA) did not occur
during the previous bus cycle.
(iii) An instruction with a LOCK prefix is not being executed.
If condition (i) or (ii) is not met, the grant is not given until the next bus cycle; if
condition (iii) is not met, the grant waits until the locked instruction is completed.
In response to the grant, the tri-state pins of the 8086 (i.e., address, data, and
control pins) are placed in their high impedance state and the next bus cycle is
given to the requesting master. The processor is effectively disconnected from
the system bus until the master sends a second pulse to the processor through the
RQ/GT pin.
The ALE, DT/R, DEN, and INTA pins provide the same outputs that are sent
by the 8086 processor when it is in minimum mode (except that DEN is inverted).
The CLK input permits the bus controller activity to be synchronized with that
of the 8086 processor. The remaining pins given in Fig. 18.5 have the following
functions:
(i) MRDC (memory read command)—This signal instructs the memory to
place the contents of the addressed location on the data bus.
(ii) MWTC (memory write command)—This signal instructs the memory to
accept the data on the data bus and place the data in the addressed memory
location.
(iii) IORC (I/O read command)—This signal instructs an I/O interface to place
the data contained in the addressed port on the data bus.
(iv) IOWC (I/O write command)—This signal instructs an I/O interface to
accept the data on the data bus and place the data in the addressed port.
(v) INTA (Interrupt Acknowledge)—This signal is used to send two interrupt
acknowledgement pulses to an interrupt controller such as the 8259 or an
interrupting device, when SO = SI = S2 = 0.
These five signals are active low and are outputted during the middle portion of
a bus cycle. Only one of them is issued during a bus cycle. There are two more
signals— AIOWC (advanced I/O write command) and AMWC (advanced memory
write command). They do the same function as the IOWC and MWTC pins.
However, they are activated one clock pulse earlier. This gives slow interfaces an
extra clock cycle to prepare for accepting the input data. The 8288 requires +5 V
power supply and has TTL-compatible inputs and outputs.
18.4 8086 SYSTEM BUS TIMINGS

This section discusses the timing diagram of the 8086 bus cycles—general
bus operation, memory and I/O read cycle, and memory and I/O write cycle in
minimum mode operation, and memory and I/O read cycle and memory and I/O
write cycle in maximum mode operation. It also discusses the timing diagram for
interrupt acknowledgement (INTA) and the bus request and bus grant timing in
minimum and maximum mode operation.
18.4.1 Timing Diagrams for General Bus Operation in Minimum Mode

The 8086 bus cycles are depicted with their T-states in Fig. 18.6. The length of
a bus cycle in an 8086 system is four clock cycles, denoted by T1-T4, plus any
number of wait state clock cycles, denoted by TW. If the bus is to be inactive or
idle after the completion of a bus cycle, the gap between successive bus cycles
is filled with idle state clock cycles denoted by TI. During data transfer, the wait
states are inserted between T3 and T4, when a memory or I/O interface is not able
to respond quickly.
| T1 | T2 | T3 | T4 | T1 | T2 | T3 | TW | T4 | T1 | T2 |
| T1 | T2 | T3 | Tw | Tw | T4 | T1 | T2 | T3 |
Bus cycle with two wait states
| T1 | T2 | T3 | T4 | T1 | T1 | T2 | T3 | T4 | T1 |
One idle state between bus cycles
| T1 | T2 | T3 | T4 | T1 | T1 | T1 | T2 | T3 | T4 |
Two idle states between bus cycles
Fig. 18.6 8086 bus cycles (a) normal bus cycle and bus cycle with one wait state
(b) bus cycle with two wait states (c) bus cycle with one idle state, and
(d) bus cycle with two idle states
The timing diagram for general bus operation of the 8086 in minimum mode is
shown in Fig. 18.7. If the Ready signal is still in low state at the beginning of T3,
one or more wait states (TW) will be inserted between T3 and T4, until a Ready
has been received (i.e., Ready is made 1). The bus activity during TW is the same
as the activity during T3. A signal applied to an RDY input of the 8284A causes a
Ready output to the 8086 at the falling edge of the current clock cycle.
The simplified timing diagram for the memory or I/O read cycle, which requires
one wait state in the minimum mode is shown in Fig. 18.8.
The simplified timing diagram for the memory or I/O write cycle, which
requires one wait state in the minimum mode is shown in Fig. 18.9.
When the processor is ready to initiate a bus cycle, it places the address in the
lines AD15-AD0 and A19/S6-A16/S3, and the status of BHE in the line BHE/S7,
and applies a pulse to the ALE pin during T1. Before the falling edge of the ALE
signal, the signals in the address lines DEN, DT/R, M/IO, and BHE are made
Fig. 18.7 Timing diagram for general bus operation of the 8086 in minimum mode
Fig. 18.8 Memory or I/O read cycle in minimum mode operation of the 8086
Fig. 18.9 Memory or I/O write cycle in minimum mode operation of the 8086
stable (i.e., the appropriate value, 1 or 0, is placed on the address lines), with DT/R
= 0 for the read operation, and DT/R = 1 for the write operation. At the falling
edge of the ALE signal, the 74LS373s latches the address in the lines AD 15-
ADO and A19/S6-A16/S3, and the status of BHE in the line BHE/S7. During T2,
the address in these lines is removed and the status signals S3-S7 are outputted
on the A16/S3-A19/S6 and BHE/S7 pins. DEN is made logic 0 to enable the
74LS245 transceivers. The logic value in the line M/IO (which is not shown in
Figs 18.7, 18.8, and 18.9) is 1 for memory-related operation and 0 for I/O-related
operations.
If an input operation (i.e., read operation) is to be performed, RD is active
low during T2, and the AD15-AD0 pins should enter a high impedance state in
preparation for the receiving of input data. If the memory or I/O interface is ready
to transfer data immediately, there are no wait states and the data are put on the bus
during T3. After the input data are accepted by the 8086, RD is raised to 1 at the
beginning of T4 and the memory or I/O interface removes its data upon detecting
this transition.
For an output operation (i.e., write operation), the 8086 makes the signal
WR = 0 and places the output data in the pins AD15-AD0 during T2. During T4,
WR is made logic 1 and the data are removed.
For both input and output operation, DEN is made logic 1 during T4, to disable
the transceivers. The M/IO signal is set according to the next data transfer at this
time.
The bus timing of the 8086 has been designed such that the memory or I/O
interface involved in a data transfer can control when data are to be placed on or
taken from the bus by the interface. This is done by having the interface send a
Ready signal to the 8086 (via the 8284), when it has placed data on the data bus or
has accepted data from the data bus.
18.4.2 Timing Diagrams for General Bus Operation in Maximum Mode

The timing diagram for the memory or I/O read cycle without any wait state, in a
maximum mode 8086 system, is shown in Fig. 18.10.
T1 | T2 | T3 | T4 | T1
Fig. 18.10 Memory or I/O read cycle in maximum mode operation of the 8086
The timing diagram for the memory write cycle without any wait state, in a
maximum mode 8086 system, is shown in Fig. 18.11. The status bits SO, SI, and
S2 are set just prior to the beginning of the bus cycle. Upon detecting a change
from the passive state (SO = ST = S2 = 1), the 8288 outputs a pulse on its DT/R
pin during TI. In T2, the 8288 sets DEN = 1, thus enabling the transceivers. For
memory read operation, it activates MRDC, which is maintained until the end
of the clock period T4. For a memory write operation, AMWC is activated from
T2 to T4 and MWTC is activated from T3 to T4. The status bits SO, SI, and S2
remain active until the end of T3 and become passive (all Is) during T3 and T4.
As with the minimum mode, if the Ready input of the 8086 is not activated before
the beginning of T3, the wait states are inserted between T3 and T4.
Similar to the memory read cycle, while performing the I/O read cycle, the
control signal IORC is activated instead of MRDC. Similar to the memory write
cycle, while performing the I/O write cycle, the control signals AIOWC and IOWC
are activated instead of AMWC and MWTC, respectively.
T1 | T2 | T3 | T4
Fig. 18.11 Memory or I/O write cycle in maximum mode operation of the 8086
18.4.3 Interrupt Acknowledgement (INTA) Timing

When an interrupt is received through the INTR pin of the 8086 in the minimum
and maximum modes, the 8086 generates the interrupt acknowledgement (INTA)
signal, which we shall now discuss in detail.
(i) When the 8086 is operating in minimum mode
The timing diagram for the Interrupt Acknowledgement (INTA) signals of
the INTR interrupt is shown in Fig. 18.12. If an INTR interrupt request has
been recognized during the previous bus cycle and an instruction has just been
completely executed by the 8086, a negative pulse is applied to the INTA during
the current and the next bus cycles. Each of these pulses extends from T2 to
T4. Upon receiving the second INTA pulse, the interface receiving the INTA
signal puts the interrupt type on the lines AD7-AD0, which are floated for the
rest of the time (during the two bus cycles). The interrupt type is available from
T2 to T4.
(ii)When 8086 is operating in the maximum mode

In this mode, the Interrupt Acknowledgement (INTA) signals are the same as
in the minimum mode, but, a logic 0 is applied to the LOCK pin from T2 of the
first bus cycle to T2 of the second bus cycle.
<--------- Idle states --------->

| T1 | T2 | T3 | T4 | T1 | T1 | T1 | T1 | T2 | T3 | T4 |
Fig. 18.12 Timing diagram for interrupt acknowledgement (INTA)
18.4.4 Bus Request and Bus Grant Timing

In this section, we shall discuss the timing of a bus request and grant, both in the
minimum mode and the maximum mode.
(i) When 8086 is operating in the minimum mode
The timing of a bus request and a bus grant in minimum mode system is shown
in Fig. 18.13. The HOLD pin is tested at the rising edge of each clock pulse.
If a Hold signal is received by the 8086 before T4 or during the TI state,
the 8086 activates HLDA and the succeeding bus cycles are given to the
requesting master until that master drops its request. The lowered request (i.e.,
HOLD = 0) is detected at the rising edge of the next clock cycle and the HLDA
signal is made 0 (i.e., deactivated) at the falling edge of that clock cycle.
While HLDA = 1, all the three-state outputs of the 8086 are put in their high
impedance state. The instructions already in the instruction queue continue to
be executed, until one of them requires the use of the bus to access the memory
or the I/O device.
Fig. 18.13 Bus request and bus grant timing in minimum mode operation of the 8086
(ii) When 8086 is operating in the maximum mode

The timing of a bus request and a bus grant in a maximum mode 8086 system
is shown in Fig. 18.14. A request/grant/release is accomplished by a sequence
of three pulses. The RQ/GT pins are checked at the rising edge of each clock
pulse, and if a request is detected from a master such as the coprocessor and
the necessary conditions discussed earlier are met, the 8086 applies a grant
pulse to the RQ/GT immediately following the next T4 or TI state. When the
requesting master receives this pulse, it takes over the control of the bus. This
master may control the bus for one or several bus cycles. When it is ready to
relinquish the bus, it sends the release pulse to the 8086 over the same line
through which it made the request. RQ/GTO and RQ/GT 1 are the same, except
that RQ/GTO has higher priority.
Fig. 18.14 Bus request and bus grant timing in maximum mode operation of the 8086
18.5 DESIGN OF MINIMUM MODE 8086-BASED SYSTEM

The design of a minimum mode 8086-based system requires the interfacing of
memory chips and I/O devices such as DIP switches, LEDs, 8255, etc., with the
8086. The interfacing of memory chips and I/O devices with the 8086 has already
been explained in Chapter 16. There must be a ROM/EPROM chip at the address
FFFFOH, which has the monitor program stored in it, as the 8086 fetches the first
instruction from that address for execution after power up and reset. In addition,
there must be a ROM/EPROM or RAM chip at the address 00000H, if the system
uses interrupts, as the interrupt vector table (IVT) is stored starting at that address.
For interfacing the 8255 with the 8086, the concepts used to interface 8-bit I/O
devices with the 8086, and the 8255 with the 8085, can be combined.
POINTS TO REMEMBER
• The 8086 can be configured to operate either in minimum or maximum mode.

• The 8284 IC (clock generator) is used to generate the clock and Ready signals for the
8086.
• The 8288 IC (bus controller) is used in the maximum mode of operation of the 8086 to
generate the memory and the I/O control signals using the status signals of the 8086.
• The bus cycles of the 8086 may or may not have wait states and idle states.
• There exist different timing diagrams in the 8086, such as the timing diagram for general
bus operation (i.e.. the memory or I/O read cycle and the memory or I/O write cycle) of
the 8086. interrupt acknowledgement, and bus request/grant in minimum and maximum
modes.
KEY TERMS |
Bus controller (8288) This IC is used to generate the control signals for the memory and
I/O device using the status signals SO, SI, and S2 in the maximum mode operation of the
8086.
Bus cycle Each bus cycle of the 8086 has four clock periods, T1-T4 plus any number of
wait state clock cycles denoted by Tw.
Bus request/grant cycle This cycle is needed to perform the DMA operation and also
when the bus is needed for another processor.
Clock generator (8284) This IC is used to supply a clock pulse with 33% duty cycle and
also to synchronize the Reset and Ready signals given to the 8086.
Idle state If the bus is to be inactive or idle after the completion of a bus cycle, the gap
between successive bus cycles is filled with idle state clock cycles, denoted by TI.
Interrupt acknowledgement (INTA) cycle During this cycle, the 8086 sends two INTA
pulses to an external interface after receiving the INTR interrupt, to get the interrupt type
number for the INTR interrupt.
I/O read cycle During this cycle, the 8086 reads data from the input device.
I/O write cycle During this cycle, the 8086 writes data into the output device.
Maximum mode In this mode operation, there is more than one processor, and all the
control signals for the memory and the I/O device are generated by the bus controller
(8288) chip.
Memory read cycle During this cycle, the 8086 reads data or instructions from the
memory.
Memory write cycle During this cycle, the 8086 writes data into the memory.
Minimum mode In this mode operation, there is only one 8086 processor, and all the
control signals for the memory and the I/O device are generated by the processor itself.
Wait states These states are inserted between T3 and T4, when a memory or I/O interface
is not able to respond quickly enough during a data transfer. This is achieved with the help
of the Ready input in the 8086.
REVIEW QUESTIONS
1. What is meant by minimum mode operation of the 8086?

2. What is meant by maximum mode operation of the 8086?
3. What is the function of the MN/MX pin in the 8086?
4. How are the control signals MEMR and MEMW generated using the M/IO, RD, and
WR signals in the minimum mode operation of the 8086?
5. How are the control signals IOR and IOW generated using the M/IO, RD, and WR
signals of the 8086?
6. What is the function of the chip select logic and what are the inputs given to it?
7. Write the function of the clock generator IC (8284).
8. What is the role of the bus controller IC (8288)?
9. What is meant by memory read and memory write cycles?
10. What is meant by I/O read and I/O write cycle?
11. Write the function of the signals DEN and DT/R in the 8086.
12. What is the function of the signals M/IO and BHE in the 8086?
13. What is the role of the pin F/C in the 8284A?
14. Explain the minimum mode configuration of the 8086-based system with the necessary
block diagram.
15. Describe the maximum mode configuration of the 8086 with the necessary block
diagram.
16. Explain the signals in the 8284A and the 8288 in detail.
17. Explain the bus timings for general bus operation in the 8086 under minimum mode
with necessary waveforms.
18. Explain the bus timings for general bus operation in the 8086 under maximum mode
with necessary waveforms.
19. With necessary waveforms, describe the bus timings for bus request and grant in
minimum and maximum modes.
20. How does the 8086 respond to the INTR interrupt in minimum mode operation of the
8086?
THINK AND ANSWER
1. How are wait states introduced in a bus cycle of the 8086?

2. Why and when are the idle states introduced in a bus cycle of the 8086?
3. How many clock periods are present in a bus cycle of the 8086 without wait states?
4. What is the difference between the AMWC and MWTC signals?
5. How does the 8288 generate the control signals for memory and I/O devices?
1. Design an 8086-based minimum mode system that contains the following

components:
(i) Two 8K x 8 EPROM chips having the address range FC000H-FFFFFH
(ii) Two 8K x 8 RAM chips having the address range 80000H-83FFFH
(iii) Two seven-segment LEDs with common anode connection, having the addresses
80H and81H
(iv) An 8-bit DIP switch having the address FF80H
2. Interface an 8255 chip with the 8086 operating in minimum mode so that the addresses
80H, 82H, 84H, and 86H are assigned to port A, port B, port C, and the control register
of the 8255, respectively.
Part 5
°----------------- /\/\/\^----------------- -
INTEL 8096—16-BIT
MICROCONTROLLERS
Chapter 19: Overview of Intel 8096

Microcontrollers
Chapter 20: 8096 Instruction Set and Programming
Chapter 21: Hardware Features of 8096

Chapter 19^
OVERVIEW OF INTEL 8096

MICROCONTROLLERS
LEARNING OUTCOMES
• Features of the 8096 microcontroller
• Memory organization in the 8096
• Functional blocks of the 8096
• Operation of the 8096 functional blocks
19.1 INTRODUCTION
The microprocessor or CPU contains an ALU, a program counter, a stack pointer,
some working registers, a clock timing circuit, and an interrupt circuit. To make
a complete microcomputer, one must add memory, usually ROM and RAM, a
memory decoder, an oscillator, and a number of input/output (I/O) devices such as
parallel and serial data ports. In addition, special purpose devices such as interrupt
handlers and counters may be added to relieve the CPU from time consuming
counting or timing chores.
A microcontroller, popularly called computer-on-a-chip, can act as a complete
controller, but cannot become a complete digital computer by itself. The design
incorporates all the features found in a microprocessor CPU, such as arithmetic
and logic unit (ALU), program counter (PC), stack pointer (SP), and registers. In
addition, it also has the other features such as ROM, RAM, parallel I/O, serial I/O,
counters, and clock circuit.
Like the microprocessor, the microcontroller is a programmable device, but
is meant to read data, perform limited calculations on that data, and control the
environment based on those calculations. The prime use of the microcontroller is
to control the operation of a machine using a program that is stored in its ROM and
does not change over the lifetime of the system.
Table 19.1 shows the difference between a microprocessor and a microcontroller.
It compares the pin configuration, architecture, and instruction set of a common
8-bit microprocessor, the Zilog Z80, and Intel’s 8051 and 8096 microcontroller
series.
An 8-bit microcontroller can be used in a variety of applications that involve
limited calculations and relatively simple control strategies. As the requirement
for faster response and more complex calculations grows, the 8-bit design begins
to hit a limit that is inherent with byte-wide data words. One solution is to increase
clock speed; another is to increase the size of the data word.
Table 19.1 Comparison between Intel's 8-bit and 16-bit processors
Details Z80 8051 (8-bit) 8096 (16-bit)

Pin configuration
Total pins 40 40 68
Address pins 16 (fixed) 16 16
Data pins 8(fixed) 8 16
Architecture
8-bit registers 20 34 232
16-bit registers 4 2 —
Internal ROM (bytes) 0 4K 8K
Internal RAM (bytes) 0 128 232
External memory (bytes) 64K 120K 64K
Flags 6 4 7
Timers 0 2 2
Parallel ports 0 4 5
Serial ports 0 1 2
The 16-bit microcontroller is used to solve high speed control problems of the
type that might typically be confronted in the control of servo mechanisms such
as robot arms. In the first line of development, manufacturers have produced 16-
and 32-bit processors, which in turn are used to develop more powerful personal
computers. They have become the backbone of workstations, which are becoming
the revolutionary tool for engineers. Due to their processing power and speed,
these 16- and 32-bit processors are used to design products such as electronic
instruments.
In the second mode of development, instead of focusing upon the larger word
width and address spaces, emphasis has been laid on much faster real time control.
It has focused upon the integration of the facilities needed to support fast control
in a single chip.
In the past, the highest performance real time control applications have
employed 16-bit and 32-bit microcontrollers, together with interrupt handler
chips, programmable timer chips, and ROM and RAM chips, to achieve what
we can now achieve in a single microcontroller chip. Even for those real time
control applications for which the resources of a single chip are not adequate, such
a chip still offers the optimal design approach. Its on-chip resources provide an
integrated approach to a variety of real time control tasks. The applications of the
microcontroller have no limitations and depend almost entirely on the designer’s
imaginative skills.
OVERVIEW OF INTEL 8096 MICROCONTROLLERS 587
19.2 FEATURES OF INTEL 8096 MICROCONTROLLER

Intel has a series of 16-bit microcontrollers called the 8X9X series. The Intel 8096
is the basic chip in the 8X9X series of microcontrollers. The other microcontrollers
in this series are 8094, 8396, 8394, 8097, 8095, 8397, 8395, etc. All these devices
come with the part number 8X9XBH or 8X9XJF. A comparative table of the
8X9X series microcontrollers is given in Table 19.2.
Table 19.2 Comparison between Intel’s 8X9X series microcontrollers
Details 8096 8396 8097 8397 8095 8395

Total pins 68 68 68 68 48 48
Internal ROM (bytes) 0 8K 0 8K 0 8K
Internal RAM (bytes) 256 256 256 256 256 256
Parallel port lines 40 (5 ports) 40 (5 ports) 24 24 20 20
Timers 2 2 2 2 2 2
Serial port 1 1 1 1 1 1
In general, all the 8X9X series microcontrollers have the following built-in
features:
(i) 16-bit CPU (ii) On-chip clock generator
(iii) 256 bytes RAM (iv) Special function registers
(v) Parallel ports (vi) Analog input channels and ADC
(vii) High speed inputs (viii) High speed outputs
(ix) Two timers (x) Interrupts
(xi) Serial ports (xii) Watchdog timer
19.3 FUNCTIONAL BLOCK DIAGRAM OF INTEL 8096 MICROCONTROLLER

The 8096 is a 16-bit microcontroller with dedicated I/O subsystems. The 8096
has been designed for high speed/high performance control applications, and its
architecture is different from those of the 8048 and the 8051. There are two major
sections in the 8096—the CPU section and the I/O section. Each of these sections
can be subdivided into functional blocks, as shown in Fig. 19.1.
19.3.1 CPU Section

The central processing unit (CPU) fetches instructions from the memory and
performs specified tasks. It stores results in the memory and sends them to the
output device, according to the instruction given in the program. The CPU controls
and communicates with the memory and input/output devices. The Intel 8096 is
inherently a 16-bit microcontroller in that the data path for operands is 16 bits
wide, i.e., when the data is transferred between RAM/ROM and the CPU, it is
transferred 16 bits per internal memory cycle.
The major components of the 16-bit CPU in the 8096 are the register file and the
register arithmetic and logic unit (RALU). Communication with the outside world
is done through either special function registers (SFRs) or memory controllers.

The RALU does not use an accumulator, as it operates directly on the 256-byte
register space made up of the register file and the SFRs.
The CPU of the 8096 uses a 16-bit ALU, which operates on a 256-byte register
file instead of an accumulator. The RALU performs arithmetic and logic operations
using a set of 232 register arrays. The register file or register array is in the form of
a RAM. It is used to store data temporarily during execution of the program. Any
of the locations in the register file can be used as the source or the destination in
most instructions. This is called register-to-register architecture.
The register file contains 232 bytes of RAM, which can be accessed as bytes,
words, or double words. Since each of these locations can be used by the RALU,
there are essentially 232 accumulators. The first word in the register file is reserved
for use as the stack pointer and cannot be used for data when stack manipulations
occur.
Many of the instructions can also use bytes or words from anywhere in the
64 KB address space as operands. In the lower 24 bytes of the register file are
the register-mapped I/O control locations, also called special function registers
(SFRs). These registers are used to control the on-chip I/O features. The remaining
232 bytes form the general-purpose RAM, the upper 16 bytes of which can be kept
alive using a low current power down mode.
The control unit provides the necessary timing and control signals for all
operations. It controls the flow of data between the controller, the memory, and
the peripherals. When the Reset signal is activated, all internal operations are
suspended, and the program counter is cleared. After reset, the program execution
can begin from the zero memory address.
The sequencing of the execution of instructions is carried out using the
program counter (PC). This register is a memory pointer, which always points
to the memory address from which the next instruction is to be fetched. When
an instruction is being fetched, the PC is incremented by one, to point to the next
instruction.
The microcontroller can be interrupted from its normal execution of routines and
can be asked to execute some other instructions of higher priority, called interrupt
service routine. The controller would return to its normal operations after completing
the service routine. There are many interrupt sources for a microcontroller system
and the programmer can set the priority for each interrupt.
The clock circuit unit generates the clock signal and synchronizes all operations
within the chip. It also supplies the clock necessary for communication between
the CPU and the peripheral units.
19.3.2 8096 CPU Buses

There are two buses—the A bus, which is 8 bits wide, and the D bus, which is
16 bits wide. A control unit and these two buses connect the register file and the
RALU. Figure 19.1 shows the CPU with the major bus connections.
The D bus transfers data only between the RALU and the register file or
the special function registers (SFRs). The A bus is used as the address bus for
these transfers or as a multiplexed address/data bus connecting to the memory
controller.
Instructions to the RALU are taken from the A bus and stored temporarily in
the instruction register. The control unit decodes the instructions and generates the
correct sequence of signals to have the RALU perform the desired function.
19.3.3 Register Arithmetic and Logical Unit

Most calculations performed by the 8X9X take place in the RALU. Figure 19.2
shows the block diagram of the RALU. The RALU contains a 17-bit ALU, the
program status word (PSW), the program counter (PC), a loop counter, and three
temporary registers. All the registers are 16 bits or 17 bits (16 + sign extension)
wide. Some of the registers have the ability to perform simple operations to offload
the ALU.
A separate incrementer is used for PC. However, jumps must be handled
through the ALU. A delay unit is used to convert the 16-bit bus into an 8-bit bus.
This is required as all addresses and instructions are carried on the 8-bit A bus.
19.3.4 Temporary Register

A temporary register is used to store the second operand of two-operand
instructions. This includes the multiplier and divisor during multiplication and
division, respectively. During a subtraction operation (performed using 2 s
Fig. 19.2 Block diagram of RALU
complement method), the complemented output of the data can be placed in the
temporary register.
Two of the temporary registers have their own shift logic. These registers are
used for operations that require logical shifts including normalize, multiply, and
divide. The lower word register is used only when double word (32-bit) quantities
are being shifted. The upper word register is used whenever a shift is performed.
It is also used as a temporary register for many instructions. The 5-bit loop counter
is another temporary register used to count repetitive shifts.
19.3.5 Register File

The locations 00H-0FFH contain the register file and special function registers
(SFRs). No code can be executed from this internal RAM section. If an attempt
to execute instructions from the locations 000H-0FFH is made, the instruction is
fetched from the external memory. This section of the external memory is reserved
for use by Intel development tools.
The RALU can operate on any of the 256 internal register locations. The
addresses 00H-17H are used to access the SFRs. The memory locations 18H and
19H contain the stack pointer. These locations may be used as a standard RAM, if
stack operations are not being performed. The stack pointer must be initialized by
the user program and can point anywhere in the 64K memory space.
19.3.6 Program Status Word

The program status word is a collection of Boolean flags, which contain information
concerning the state of the user’s program. The higher-order byte of the PSW
contains status flags and the lower-order byte contains an interrupt mask register.
The format of the PSW is shown in Fig. 19.3. The PSW can be saved in the system
stack with a single operation (PUSHF) and restored (POPF).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z N V VT C - I ST Interrupt mask bits
Fig. 19.3 Format of the 8096 PSW
Table 19.3 contains a description of the status flags.

Table 19.3 The 8096 status flags
Flag Name Function

ST Sticky bit Indicates whether any Is were lost due to a right-shift
operation; primarily used for floating-point routines
I Interrupt Master control for the 8096 interrupts
enable
C Carry flag Set if there is a carry (or no borrow), and cleared otherwise,
as a result of an addition or subtraction instruction
VT Overflow Set whenever the overflow flag is set; cleared only by a
trap flag CLRVT, JVT, or JNT instruction
V Overflow Set if the result is out of range for signed arithmetic
flag operation
N Negative Holds the algebraically correct sign that is obtained as a
flag result of an operation
Z Zero flag Set if the result of an operation is zero
19.3.7 Memory Controller

The RALU communicates to the memory with the help of the memory controller,
which is connected through the A bus and several control lines. Since the A bus
is eight bits wide, the memory controller uses a slave program counter to avoid
having to always get the instruction location from the RALU. In addition to holding
a slave PC, the memory controller contains a four-byte queue to help speed up the
execution.
19.3.8 Internal Timing

The 8X9X requires an input clock frequency of between 6 MHz and 12 MHz. This
frequency can be applied directly to XTAL1. Alternatively, since XTAL1 and
XTAL2 are the input and output, respectively, of the inverter, it is also possible to
use a crystal to generate the clock.
19.3.9 I/O Section

The microcontroller I/O section consists of the following on-chip peripherals:
(i) ADC interface (ii) Pulse width modulator (PWM)
(iii) Parallel I/O lines (iv) High speed I/O lines
(v) Full duplex serial port
19.3.9.1 ADC Interface
The analog-to-digital converter (ADC) has eight multiplexed inputs and 1 O-bit
resolution. It uses the successive approximation technique for conversion. The
addition of the A/D conversion capability means that a large number of transducers
for temperature, pressure, strain, position, etc., can be used directly with the
microcontroller. Any transducer that generates an output voltage proportional to
the derived physical parameters can be interfaced with the microcontroller. The
conversion of an analog voltage to a digital number is implemented in the 8096 by
the successive approximation technique.
19.3.9.2 Pulse Width Modulator
The pulse width modulation (PWM) output can be used as a digital-to-analog
converter. It can be used as a DC motor driver and for many other purposes. The
Intel 8096 includes the PWM as one of its on-chip resources. Once it has been set
up, it requires no further CPU intervention to continue generating a wave form
with a period of 64 ps and a duty cycle of any value between 0 and 255/256,
depending upon the 8-bit number written to the PWM register. Due to this, it
provides a reasonable way to carry out D/A conversion with DC components,
which is proportional to a digital quantity. This might be used directly for analog
applications, such as heating coil.
Alternatively, a low-pass filter can be used to eliminate the AC component of
the output and thereby obtain only the DC output, as shown in Fig. 19.4.
Pulse width modulation is used to obtain width-modulated pulses and thereby
generate variable average DC output, as shown in Fig. 19.5.
Fig. 19.4 PWM output driver circuit
A watchdog timer is an internal timer that can be used to reset the system if the
software fails to operate properly, i.e., it resets the 8096 if a malfunction occurs.
Duty cycle Avg. DC output

+5V--------------------------------------------------------------------------------- 100% 5V
Fig. 19.5 Output waveform
19.3.9.3 High Speed I/O Lines and Serial Port

The high speed I/O section includes a 16-bit timer, a 16-bit counter, a 4-bit
programmable edge detector, four software timers, and six output-programmable
event generators. The high speed input unit provides automatic recording of the
events. The high speed output unit provides automatic triggering of events and
real time interrupts, which are explained in Chapter 21.
The serial port has several modes and its own baud rate generator. The serial
port provides synchronous or asynchronous link.
The input/output interactions of a microcontroller sometimes require handshaking.
The 8096 includes programmable timer facilities, which can be used to cause output
events to occur at precise times without the intervention of the CPU. The 8096 has
two time bases—timer 1 and timer 2. Timer 1 is a 16-bit free running timer, which
is incremented every eight state times. A state time is three oscillator periods, or
0.25 ps with a 12 MHz crystal. Timer 2 can be clocked externally.
19.4 MEMORY STRUCTURE OF 8096

The 8096 has an internal memory with a provision for an external memory as
well. The memory in the 8096 system is divided into two types—data memory
and program memory. In general, the data memory is random access or read-write
memory. The program memory is read-only memory. With 16-bit address lines,
the 8096 can access a maximum of 64 KB of memory. RAM is the user memory
and is used to store the data. The information stored in this memory can be easily
read and altered. Figure 19.6 shows the memory map of the 8096.
The addressable memory space on an 8X9X consists of 64 KB, most of which
is available to the user for program or data memory. There are several registers
labeled ‘reserved’. These registers are reserved for future expansion and test
purposes. Operations should not be performed with these registers, as they may
produce unexpected results.
The locations 0000H-00FFH, 0100H-01FFH, and 1FFEH-2080H are
reserved. All other locations can be used either for program/data storage or for
memory-mapped peripherals. The complete memory organization of the 8X9X
microcontrollers is as shown in Fig. 19.6.
According to Intel, all the reserved locations except 2019H must be filled
with the hexadecimal value 0FFH, to ensure compatibility with future devices.
FFFFH
External memory or I/O
6000H
OFFH 255--------
Power down RAM 5FFFH
0F0H 240 External memory or I/O (6X9XBH)
Internal program storage ROM/
OEFH 239 EPROM or external memory (8X9XJF)
Internal register file (RAM) 4000H
1AH 26 Internal program storage ROM/ 3FFFH

EPROM or external memory
19H 25
Stack pointer Stack pointer
18H 24 Reserved 2080H
17H PWM-CONTROL 23
16H IOS1 IOC1 22 Signature word 2072H-207FH
15H IOSO IOCO 21 Reserved 2070H-2071H
14H 20 Security key 2030H-206FH
13H Reserved Reserved 19
12H 18 Reserved 2020H-202FH
11H SP_STAT SP-CON 17 Self jump opcode (27HFEH) 2019H
10H IO Port 2 IO Port 2 16
Chip configuration byte 2018H
OFH IO Port 1 IO Port 1 15
OEH IO PortO BAUD_RATE 14 Reserved 2012H-2017H
ODH Timer 2 (Hi) 13 Interrupt vector
OCH Timer 2 (Lo) Reserved 12 2000H
OBH Timer 1 (Hi) 11 Port 4 1FFFH
OAH Timer 1 (Lo) Watchdog 10 Port 3 1FFEH
09H INT_PENDING INT_PENDING 9 External memory or I/O 01FFH
08H INT_MASK INT_MASK 8 —
OOFFH
07H SBUF(RX) SBUF (TX) 7
External memory or I/O (8X9XBH)
06H HSLSTATUS HSO-COMMAND 6 Internal executable RAM
05H HSLTIME (Hi) HSO.TIME (Hi) 5 (XRAM) (8X9XJF)
0100H
04H HSI TIME (Lo) HSI TIME (Lo) 4
03H AD_RESULT (Hi) HSLMODE 3 Internal RAM OOFFH
AD_RESULT (Lo) AD_COMMAND 2 Register file
02H
Stack pointer
01H RO (Hi) RO (HI) 1 Special function register
OOH RO (Lo) RO (LO) 0 (When accessed as data memory) 0000H
(When read) (When written)
...... '.Z- -Z-vz,, »««««■ W- zrf'
Fig. 19.6 The 8096 memory map
Location 2019H must contain 20H. Locations 1FFEH and 1FFFH are reserved for
P3 and P4, respectively. This is to allow easy construction of these ports if external
memory is used in the system. If P3 and P4 are not going to be reconstructed, these
locations can be treated as any other external memory locations.
The nine interrupt vectors are stored in the locations 2000H-2011H. Locations
2012H-2017H are reserved for future use. Location 2018H is the chip configuration
byte, which gives configuration information. Locations 2020H-202FH hold the
security key used with the ROM lock feature.
All the unspecified addresses in locations 2000H-207FH, including those
marked reserved, should be considered reserved for use by Intel.
Special function registers All the input/output on the 8X9X are controlled
through SFRs. Many of these registers are double-buffered, i.e., reading from an
address is different from writing to the same address. There are several restrictions
on using special function registers:
(i) Neither the source nor the destination addresses of the multiply and divide
instructions can be writable special function registers.
(ii) These registers may not be used as base or index registers for indirect or
indexed instructions.
(iii) Some of the byte registers can be accessed only as bytes, while some can be
accessed only as words.
Table 19.4 gives the list of all special function registers available in the 8X9X
series.
Table 19.4 Special function registers in the 8X9X series
Register Description
RO Zero register—Always reads zero; useful as a base when indexing
and as a constant for calculations and comparisons
AD_RESULT A/D results Hi/Lo—Low and high order results of the A/D
converter (byte read only)
AD_COMMAND A/D command register—Controls the A/D
HSI_MODE HSI mode register—Sets the mode of the high speed input unit
HSI-TIME HSI time Hi/Lo—Contains the time at which the high speed input
unit was triggered (word-read only)
HSO_TIME HSO time Hi/Lo—Sets the time or count for the high speed output
to execute the command register (word-write only)
HSO_COMMAND HSO command register—Determines what happens at the time
loaded in the HSO time registers
HSI_STATUS HSI status registers—Indicates which HSI pins were detected at
the time in the HSI time registers and the current state of the pins
SBUF (TX) Transmit buffer for the serial port; holds the contents to be sent out
SBUF (RX) Receive buffer for the serial port; holds the byte just received by
the serial port
INT.MASK Interrupt mask register—Enables or disables the individual
interrupts
INT_PENDING Interrupt pending register—Indicates that an interrupt signal has
occurred on one of the sources and has not been serviced
Watchdog Watchdog timer register—Written periodically to hold off
automatic reset every 64K state times
Timer 1 Timer 1 Hi/Lo—Timer 1 higher-order and lower-order bytes
(word-read only)
Timer 2 Timer 2 Hi/Lo—Timer 2 higher-order and lower-order bytes
(word-read only)
IO Port 0 Port 0 register—Indicates the levels on the pins of port 0
BAUD_RATE Determines the baud rate. This register is loaded sequentially.
IO Port 1 Port 1 register—Used to read or write to port 1

(Contd)
Table 19.4 Special function registers in the 8X9X series (Contd)
Register Description
10 Port 2 Port 2 register—Used to read or write to port 2
SP.STAT Serial port status—Indicates the status of the serial port
SP_CON Serial port control—Sets the mode of the serial port
IOS0 VO status register 0—Contains information about the HSO status
IOS1 VO status register 1—Contains information about the status of the

timers and the HSI
IOCO VO control register 0—Controls the alternate function of HSI pins,
timer 2 reset sources, and time 2 clock sources
IOC1 VO control register 1—Controls the alternative functions of the
port 2 pins, timer interrupts, and HSI interrupts
PWM_CONTROL Pulse width modulation control register—Sets the duration of the
PWM pulse
19.5 POWER DOWN MODE OF CPU

The upper 16 RAM locations (0F0H-0FFH) receive their power from the VpD
pin. If it is desired to keep the memory in these locations alive during a power
down situation, a voltage must be applied on the VpD pin. The current required to
keep the RAM alive is approximately 1 mA. For normal operation, power must be
applied to both Vcc and VpD. If power is not applied to VpD, the power down RAM
will not function properly even though power is applied to Vcc. To place the 8096
in the power down mode, the RESET pin is pulled low.
POINTS TO REMEMBER
• The 8096 is the basic 16-bit microcontroller manufactured by Intel in the 8X9X series.
The RAM and ROM differ for each member in the 8X9X family.
• The 8096 has many parallel VO ports, serial ports, ADCs, timers, and HSI/HSO units,
in addition to the CPU unit and the memory.
• The 64K memory map registers of the 8096 consist of internal registers, special function
registers, and internal and external memory.
• The special function registers are used to control the various internal hardware resources
of the 8096.
KEY TERMS
CPU buses These are the internal buses of the microcontroller used for transfer of
address and data within it.
High speed I/O unit This unit can be used to transfer data at a predefined time and to
note the time of data input.
Memory controller It is the unit that controls the address and data buses to implement
data transfer between the CPU section and other peripherals.
Microcontroller It is also known as computer-on-a-chip, incorporates all of the features
found in a microprocessor CPU (ALU, PC, SP, and registers) and has all the other features
needed to make a complete computer (ROM, RAM, parallel I/O, serial I/O, counters, and
clock circuit).
Program counter It is a memory pointer, which always points to the memory address of
the next instruction to be fetched.
Program status word It is the register with a collection of flags, which indicate the
status of the data after any operation in the microcontroller.
Pulse width modulating unit This unit is used to generate pulses of varying width, the
width being proportional to the content of a particular internal register.
Register arithmetic and logic unit This unit is inside the CPU of the 8096, performs
arithmetic and logic operations using a set of 232 register arrays.
Special function registers These are the registers in the microcontroller that have a
specific control or function over the various peripherals of the chip.
Watchdog timer It is an internal timer that is used to reset the system if the software
fails to operate properly.
REVIEW QUESTIONS
1. What are the hardware features in the 8096?

2. What is the maximum memory addressing capacity of the 8096?
3. Write a short note on the RALU.
4. What is the difference between the 8051 and the 8096?
5. List the parts of the I/O section of the 8096.
6. What is PWM?
7. How is memory organized in the 8096?
8. Write a note on SFRs.
9. Write the importance of SFRs in the 8096.
10. What is HSI in the 8096?
CHAPTER 2(n
8096 INSTRUCTION SET AND

PROGRAMMING
LEARNING OUTCOMES
• Data types in the 8096
• Addressing modes in the 8096
• Instruction set of the 8096
• Classification of the 8096 instruction set
20.1 8096 OPERAND TYPES

The 8096 instruction set supports the following data types. The programmer must
know the appropriate instructions to handle these data types.
Bytes Bytes are unsigned 8-bit variables, which can take values between 0 and
255. Instructions for data transfer, arithmetic, and logical operations support byte
operands. The source and destination are 8-bit locations.
Words Words are unsigned 16-bit variables, which can take values between 0
and 65535. Word operands are supported by all data transfer, arithmetic, and logic
instructions. The source and destination are two-byte locations. The 16-bit operand
in the memory is accessed using an even address. The least significant byte of the
word is the even address given in the instruction and the most significant byte is
taken from the next higher-order odd address.
Short integers Short integers are 8-bit signed variables, which can take values
from -128 to +127. Arithmetic operations whose results lie outside this range set
the overflow indicators in the program status word (PSW). The actual numeric
results returned are the same as those for equivalent operations on byte variables.
Bits Bits are binary single-digit operands, which can take the Boolean values true
and false. The individual bits of words and bytes can be addressed independently.
In addition to this support for byte and word operands, the 8096 provides for the
direct testing of any bit in the internal register file.
Double words Double words are 32-bit operands, stored in four bytes or memory
locations. They are considered as unsigned and can take values between 0 and
4,294,967,295. Instructions such as rotate, multiply, and divide can use the double
word as one of their operands. The double words in the memory are accessed using
an address evenly divisible by 4. The least significant byte is stored in this address
and the higher-order bytes are stored in the subsequent higher-order addresses.
Long integers The signed form of the double word is called long integer. As the
most significant bit (MSB) is the sign bit, the magnitude of long integers varies
from -2,147,483,648 to +2,147,483,647. Long integers are used in the signed
multiply and divide instructions. The storing and addressing of long integers is
similar to the procedure followed for words. Normalization or sign extension can
be done for converting words into long words. The least significant byte must be
stored in a memory address that is evenly divisible by 4.
20.2 ADDRESSING MODES

The way the source and destination addresses are specified in the instruction
mnemonic is called addressing mode. The six basic addressing modes supported
by the 8096 are as follows:
(i) Register direct addressing (ii) Indirect addressing
(iii) Indirect addressing with auto increment (iv) Immediate addressing
(v) Short-indexed addressing (vi) Long-indexed addressing
Several other useful addressing operations can be achieved by combining these
basic addressing modes with specific registers such as the zero register and the
stack pointer. Now, we shall discuss the basic addressing modes.
20.2.1 Register Direct Addressing

Certain register names may be used as part of the opcode mnemonic as the source
or destination of data. In register direct addressing mode, one of the 256 registers
within the microcontroller is specified in the instruction itself. These registers are
addressed using an 8-bit address in the instruction.
Example:
ADDB 20H, 30H
ADD AX, BX
MULB 20H, 30H, 31H
STB AL, BL
20.2.2 Indirect Addressing

Indirect addressing is the method to address an operand in an instruction using a
pointer to that operand. The normal method is to store the operand in a memory
location and the 16-bit address of that operand in a word register, and to refer to
this register in the instruction. The register that contains the indirect address is
selected by an 8-bit field in the instruction. An instruction may have more than
one operand, but only one of them can be accessed using indirect addressing. In
assembly language instructions, indirect addressing is generally represented by
square brackets.
Example:
LD AX, [AX] ; AX = MEMWORD_CONTENT (AX)
ADDB AL, BL, [CX] ; AL = BL + MEMBYTE_CONTENT (CX)
20.2.3 Indirect Addressing with Auto Increment

The indirect addressing mode can also be used with an increment option. This
addressing mode is used to increment the contents of the register used for indirect
addressing, after the data pointed to by it has been accessed. This addressing mode
is used to access look-up tables.
Example:
LD AX, [BX] + ; AX = MEMWORD_CONTENT (BX)
: BX = BX + 2 (incremented by 2 as a word
operand is accessed)
ADDB AL, BL, [CX] + : AL = BL + MEMBYTE.CONTENT (CX)
; CX = CX + 1
20.2.4 Immediate Addressing

In immediate addressing, the operand is provided directly, as part of the instruction
itself. An immediate operand is represented by a ‘#’ prefix. Depending on the
instruction, the immediate operands can be bytes, words, or long words. An
instruction may have many operands, but only one of them can be immediate-
addressed.
Example:
LD CX, #0BA98H
SHL BX, #4H
DIV CX, #4040H
20.2.5 Short-indexed Addressing

In short-indexed addressing mode, an 8-bit number called offset is added to a
pointer, to form the effective address of the operand. The offset can be any value
between -128 and +127. The pointer can be any 16-bit register. Any instruction
must have only one index-addressed operand. In assembly language instructions,
indexed addressing is represented by the offset value followed by a pointer register
within square brackets.
Example:
LDB AL, 10ECX] ; AL = MEM_BYTE [CX + 10]
20.2.6 Long-indexed Addressing

Long-indexed addressing is similar to short-indexed addressing, except that the
offset is a 16-bit number. The pointer is a 16-bit word. An instruction can have
only one long-index-addressed operand; the others must be directly addressed.
Example:
ADD AX, BX, LOOKUPECXJ
AND AX, TABLEEBX]
20.2.7 Zero Register Addressing

The internal RAM with the address 0 is referred to as the zero register. The first
two bytes of the internal RAM are filled with 0 by the 8096 hardware. This register
can be used in the long-indexed addressing mode. This allows the direct addressing
of all memory locations.
Example:
ADD AX, 9000[0]
20.2.8 Stack Pointer Register Addressing

The stack pointer at the address 18H in the internal RAM can also be used as a
pointer to access operands in the memory. In this type of addressing, the stack
pointer can be used in indirect addressing and indexed addressing modes.
Example:
PUSH E SP] ; The top of the stack pointed to by SP is again stored
in the stack.
LD BX,-2[SP] ; Address (SP - 2) using short-indexed addressing and
move it to BX.
20.3 CLASSIFICATION OF INSTRUCTIONS

Based on their operations, the instructions of the 8096 are classified as follows:
(i) Data transfer instructions (ii) Arithmetic and logical instructions
(iii) Shift or rotate instructions (iv) Branching instructions

Data transfer instructions are used to transfer data within the microcontroller or
between the microcontroller and the memory. Here, the instructions for addressing
byte data (short integer) and word data (integer) are different. Both signed and
unsigned number formats are supported.
Instructions for byte operands
LDB Load (move a byte)
STB Store (store a byte)
LDBZE Load a byte into a word register, with zero extension on the most
significant byte
LDBSE Load a byte as a signed number into a word register, with sign
extension on the most significant byte
CLRB Clear the byte operand
Instructions for two-byte or 16-bit word

LD Load (word data)
ST Store (word data)
CLR Clear the word operand
PUSHF Push PSW onto the stack
POPF Pop PSW off the stack
PUSH Push register onto the stack
POP Pop the top of the stack to the register
20.3.2 Arithmetic and Logical Instructions

Arithmetic instructions include the add, subtract, multiply, and divide operations.
As discussed in Section 20.3.1, the instructions vary with data type. For example,
the instructions that operate on 8-bit data (byte) are different from the instructions
that operate on 16-bit data (word) and 32-bit data (double word or long word).
Arithmetic operations on signed numbers are done by a separate set of instructions.
The instructions supported by the 8096 for arithmetic and logical operations are
as follows:
(i) ADDB Add bytes
ADDCB Add bytes and carry
ADD Add words
ADDC Add words and carry
(ii) SUBB Subtract both signed and unsigned bytes
SUBCB Subtract a byte from another, along with the borrow (if any)
SUB Subtract a word from another
SUBC Subtract a word from another, along with the borrow (if any)
(iii) MULUB Multiply unsigned bytes
MULB Multiply signed bytes
MULU Multiply unsigned words
MUL Multiply signed words
(iv) DIVUB Divide bytes using unsigned arithmetic
DIVB Divide short integers using signed arithmetic
DIVU Divide words using unsigned arithmetic
DIV Divide integers (word data) using signed arithmetic
(v) AND Logical AND operation on word data
ANDB Logical AND operation on byte data
OR Logical OR operation on word data
ORB Logical OR operation on byte data
XOR Logical XOR operation on word data
XORB Logical XOR operation on byte data
NOT Logical NOT operation on word data
NOTB Logical NOT operation on byte data
(vi) DEC Decrement word data
DECB Decrement byte data
INC Increment word data
INCB Increment byte data
NEG Negate the word data (sign change)
NEGB Negate the byte data (sign change)
(vii) CMPB Compare bytes (flags set according to subtraction operation)
CMP Compare words (flags set according to subtraction operation)
(viii) EXT Sign-extend integer into long integer (16-bit data to 32-bit data)
EXTB Sign-extend short integer into integer (8-bit data to 16-bit data)
20.3.3 Shift/Rotate Instructions

Shift/rotate instructions are very important in any programming construct. These
instructions can be used to check individual bits, multiply, and divide data.
Figure 20.1 depicts the various possible shift operations of the 8096. The shift-left
operation has no options and operates on one of the following types of data—short
integer (8-bit). integer (16-bit), or long integer (32-bit)—at a time. However, the
shift-right operation has two options, based on the manipulation of the signed
number. Logical right-shift instructions (SHRB, SHR, and SHRL) are used to
shift unsigned numbers right. When signed numbers are shifted right, the sign bit
should not be lost. Therefore, arithmetic right shift instructions (SHRAB, SHRA,
and SHRAL) are used to shift signed numbers right, as they restore the sign bit.
The shift instructions of the 8096 provide another option—for initializing the
number of shifts in the instruction. The second operand in the shift instructions can
be either immediate addressed or register-direct addressed; this second operand
specifies the number of shifts to be performed on the first operand. Figure 20.1
lists the shift/rotate instructions.
SHLB Shift left 8-bit data
SHL Shift left 16-bit data
SHLL Shift left 32-bit data
SHRB (Logical) shift right 8-bit data
SHR (Logical) shift right 16-bit data
SHRL (Logical) shift right 32-bit data
SHRAB (Arithmetic) shift right 8-bit data
SHRA (Arithmetic) shift right 16-bit data
SHRAL (Arithmetic) shift right 32-bit data
Fig. 20.1 List of shift/rotate instructions

Branching instructions can be divided into two groups—conditional and
unconditional. In the 8096, conditional jumping can be done based on the flag
conditions and the contents of the bit-addressable registers in the register file. This
section describes the various branching instructions.
Unconditional branching instructions

SJMP Short jump with 11-bit offset
(Relative jump between PC - 1024 and PC + 1023)
LJMP Long jump with 16-bit offset
(Relative jump to anywhere in the memory address)
BR [indirect] Branch to any location specified by the indirect address
SCALL Short subroutine call with 11 -bit offset
(Relative call to a location between PC - 1024 and PC + 1023)
LCALL Long subroutine call with 16-bit offset

(Relative call to anywhere in the memory)
RET Return from subroutine
Conditional branching using 8-bit offset address

(i) Branch following a signed number comparison
JLT offset Jump if N = 1, PC <— PC + 8-bit offset
JGT offset Jump if N = 0 and Z = 0; PC <- PC + 8-bit offset
JGE offset Jump if N = 0, PC <- PC + 8-bit offset
JLE offset Jump if N = 1 and Z = 1; PC <— PC + 8-bit offset
JE offset Jump if Z = 1, PC <— PC + 8-bit offset
JNE offset Jump if Z = 0, PC <— PC + 8-bit offset
(ii) Branch following an unsigned number comparison
JC offset Jump if C = 1, PC <- PC + 8-bit offset
JNC offset Jump if C = 0, PC <— PC + 8-bit offset
JH offset Jump if C = 1 and Z = 0; PC <- PC + 8-bit offset
JNH offset Jump if C = 0 and Z = 1; PC <— PC + 8-bit offset
JE offset Jump if Z = 1, PC <— PC + 8-bit offset
JNE offset Jump if Z = 0, PC <— PC + 8-bit offset
(iii) Branch following a flag bit checking
JV offset Jump if V = 1, PC <- PC + 8-bit offset
JNV offset Jump if V = 0, PC <— PC + 8-bit offset
JVT offset Jump if VT = 1 and clear VT, PC <- PC + 8-bit offset
JNVT offset Jump if VT = 0, PC <- PC + 8-bit offset
JST offset Jump if ST = 1, PC <- PC + 8-bit offset
JNST offset Jump if ST = 0, PC <- PC + 8-bit offset
(iv) Branch following a bit value
JBS offset Jump if specified bit = 1, PC <— PC + 8-bit offset
JBC offset Jump if specified bit = 0, PC <- PC + 8-bit offset
(v) Branch following a comparison
DJNZ offset Decrement register and jump if the contents are not zero.
20.4 COMPLETE 8096 INSTRUCTION SET

Table 20.1 lists the instructions supported by the 8096, along with the operand
syntax and a brief description for each instruction.
Table 20.1 List of instructions supported by the 8096
Operation Mnemonics Operand syntax Description

Move byte LDB BD, BS BD <—BS
STB BS, BD BS -► BD
CLRB BD BD <—0
Move word LD WD, WS WD <- WS
LDBSE WD, BS WD <— BS, sign extend
(Contd)
Table 20.1 List of instructions supported by the 8096 (Contd)

LDBZE WD, BS WD <— BS, zero extend
ST WS, WD WS —> WD
CLR WD WD<-0
PUSH WS WS -4- Stack
PUSHF PSW -> Stack; 0 -> PSW
POP WD WD <- Stack
POPF PSW <- Stack
Increment INCB BD BD <—BD + 1
INC WD WD <- WD + 1
Decrement DECB BD BD <— BD - 1
DEC WD WD <— WD - 1
Complement NOTB BD BD <—FFH - BD
NOT WD WD <- FFFFH - WD
Sign extend EXTB WD WD <— Extend low byte
EXT LD LD <— Extend low word
Changing flag bits SETC C<- 1
CLRC C<-0
CLRVT VT <—0
Enable interrupt EI I<- 1
Disable interrupt DI I<-0
Add 8 bits ADDB BD, BS BD <-BD + BS
ADDB BD, BS1,BS2 BD<—BS1 +BS2
Add with carry ADDCB BD, BS BD <—BD + BS + C
Add 16 bits ADD WD, WS WD WD + WS
ADD WD, WS1, WS2 WD <—WS1 + WS2
Add with carry ADDC WD, WS WD <— WD + WS + C
Subtract 8 bits SUBB BD, BS BD <- BD - BS
SUBB BD, BS1,BS2 BD<—BS1 -BS2
Subtract with SUBCB BD, BS BD <—BD - BS - (1 - C)
borrow
Negate NEGB BD BD <— 0 - BD
Subtract 16 bits SUB WD, WS WD WD - WS
SUB WD, WS1, WS2 WD<—WS1 - WS2
Subtract with SUBC WD, WS WD <— WD - WS -
borrow (1-C)
Negate NEG WD WD <—0 - WD
Compare CMPB BS1, BS2 BS1 - BS2
(Contd)

CMP WS1, WS2 WS1 - WS2
Multiply unsigned MULUB WD, BS WD <-BDxBS
8x8
MULUB WD, BS1,BS2 WD«--BS1 x BS2
Multiply signed MULB WD, BS WD <--BDxBS
8x8
MULB WD, BS1,BS2 WD<--BS1 x BS2
Multiply unsigned MULU LD, WS LD <- WDx WS
16 x 16
MULU LD, WS1, WS2 LD <- WS1 x WS2
Multiply signed MUL LD, WS LD <— WDx WS
16 x 16
MUL LD, WS1, WS2 LD WS1 X WS2
Divide DIVUB WD, BS WD(L) <- WD/WS;
unsigned 16/8 WD(H) <- WD mod BS
Divide signed 16/8 DIVB WD, BS WD(L ) <- WD/BS;
WD(H) <- WD mod BS
Divide unsigned DIVU LD, WS LD(L) <- LD/WS;
32/16 LD(H) <- LD mod WS
Divide signed 32/16 DIV LD, WS LD(L) <- LD/WS;
LD(H) <- LD mod WS
AND ANDB BD, BS BD <— BD AND BS
ANDB BD, BS1,BS2 BD <— BS1 ANDBS2
AND WD, WS WD <-- WD AND WS
AND WD, WS1, WS2 WD<-- WS1 AND WS2
OR (inclusive) ORB BD, BS BD <— BD OR BS
OR WD, WS WD<-- WD OR WS
Exclusive OR XORB BD, BS BD <- BD XOR BS
XOR WD, WS WD<-- WD XOR WS
Branch SJMP Label PC<- PC ± up to 1023
unconditionally
LJMP Label PC<- PC ± up to 65535
Jump indirect BR [WS] PC<- WS
Decrement DJNZ BD, label BD <- BD - 1;
branch PC<- PC ± up to 127 if
result <> 0 BDo•0
Branch conditionally based on a particular bit of the register
Branch if bit is set JBS BS, bit, label PC <- PC ± up to 127 if
test passes
(Contd)

Branch if bit is clear JBC BS, bit, label PC PC ± up to 127 if
test passes
Branch conditionally on flag testing
IfC= 1 JC Label PC <— PC ± up to 127 if
test passes
IfC = 0 JNC Label
IfZ= 1 JE Label
IfZ = O JNE Label
IfN = 1 JLT Label
IfN = 0 JGE Label
Shift operation
Shift left SHLB BD, #shifts
SHL WD, #shifts
SHLL LD, #shifts
SHLB BD, BS
SHL WD, BS
SHLL LD, BS
Logical
shift right
SHRB BD, #shifts
SHR WD, #shifts
SHRL LD, #shifts
SHRB BD, BS
SHR WD, BS
SHRL LD, BS
Arithmetic SHRAB BD, #shifts
shift right
SHRA WD, #shifts
SHRAL LD, #shifts
SHRAB BD, BS
SHRA WD, BS
SHRAL LD, BS
Normalize long NORML LD, BS Shift LD left until
integer MSB = 1; BD <— shifts
If V= 1 JV Label
If V = O JNV Label
If VT = 1 JVT Label
If VT = 0 JNVT Label
(Contd)

If ST = 1 JST Label
If ST = 0 JNST Label
Branch following a signed number comparison
lf< JLT Label
If< JLE Label
If = JE Label
If> JGE Label
If> JGT Label
Ifo JNE Label
Branch following an unsigned number comparison
If< JC Label
If< JNH Label
If = JE Label
If> JNC Label
If> JH Label
Ifo JNE Label
Branch to subroutine SCALL Label Stack <— PC; PC <— PC
± up to 1023
LCALL Label Stack <- PC; PC <- PC
± up to 65535
Subroutine return RET PC <— Stack
and interrupt return
Software interrupt TRAP Stack <— PC;
PC <- [2011H, 2010H]
No operation NOP PC <— PC + I
SKIP XXH PC <— PC + 2
Reset system RST
Note:
BS, BS1, BS2 Byte type source operand having a page 0 address
WS, WS1, WS2 Word type source operand having a page 0 even address
BD Byte type destination operand having a page 0 address
WD Word type destination operand having a page 0 even address
LD Long word type destination operand having a page 0 address
(divisible by 4)
Label 8-bit offset address
20.5 PROGRAMMING EXAMPLES USING 8096 INSTRUCTION SET

Example 20.1:
Add the two 16-bit hexadecimal numbers stored in the registers B and C. Store the
result in the memory.

LD AX, #8500H
LD BX, #1234H
LD CX, #5678H
ADD DX, BX, CX
ST DX, [AXJ+
here: SJMP here
Example 20.2:
Subtract the two 16-bit hexadecimal numbers stored in the registers B and C. Store
the result in the memory.
LD AX, #8500H
LD BX, #9999H
LD CX, #369CH
SUB DX, BX, CX
ST DX, LAX J +
here: SJMP here
Example 20.3:
Multiply the two 16-bit hexadecimal numbers stored in the registers B and C.
Store the result in the memory.
LD AX, #8500H
LD BX, tfOFEDCH
LD CX, #0BA98H
MUL LX, BX, CX
ST LL, [AXJ+
ST LH, [AX]+
here: SJMP here
Example 20.4:
Divide a 32-bit hexadecimal number by a 16-bit hexadecimal number. Store the
quotient and remainder in the memory.
LD AX, #8500H
LD BX, tfOFFFEH
LD LL, tfOEFFFH
LD LH, tfOFFFFH
DIV LX, BX
ST LL, [AXJ+
ST LH, EAXJ+
here: SJMP here
Example 20.5:
Multiply and divide the given 16-bit hexadecimal numbers by powers of 2 using
the arithmetic shift operation.
The arithmetic shift of binary numbers means multiplication or division by
a power of 2. For instance, doubling a number involves shifting it left by one place
and halving a number involves shifting it right by one place.
Multiplication of a given number

LD AX, #8500H
LD BX, #OFFEH
SHL BX, #4H ; Multiplication by 16
ST BX, [AX]+
here: SJMP here
Division of a given number

LD AX, #8500H
LD BX, tfOFFEH
SHRBX, #4H Division by 16
ST BX, [AX]+
here: SJMP here
Example 20.6:
Store numbers from FFH to OOH in consecutive memory locations.
The program involves storing 256 numbers, from FFH to OOH, in successive
memory locations. Hence, the process has to be done 256 times. The BL register
is initialized with FFH and used for looping, i.e., continuation of the process.
In this example, the number array is assumed to start at the location 8500, as
indicated by AX. After execution, [8500] = FFH, [8501] = FEH, and so on up to
[85FF] = OOH.
LD AX, #8500H
LDB BL, 7A0FFH
Ll: STB BL, [AX] +
DJNZ Bl, Ll
STB Bl, [AX]+
here: SJMP here
Example 20.7:
Determine the greater of two given bytes, using a subroutine.
LD AX, #8500H
LDB BL, [AX] +
LDB BH, [AX] +
SCALL FINDHGH
ST B CL, [AX]+
here: SJMP here
Subroutine FINDHGH:
CMPB BL, BH
JGT fval
LDB CL, BH
RET
fval : LDB CL, BL
RET
Example 20.8:
Change the sign of a given number and store the new number in the memory.
LD REGI, #8500H
LD REG2, #9999H
NEG REG2
ST REG2, [REGI]
here: SJMP here
Example 20.9:
Normalize the given data and store it in the memory.
This example uses two registers—REGI and REG2. NORML REGI, REG2
means that REGI is shifted left until its MSB is 1. REG2 contains the number of
shifts required to perform this operation.
LDB REGI, #data
NORML REGI, REG2
STB REG2, 8500H
STB REGI, 8501H
move: SJMP move
Example 20.10:
Find the number of characters in a string. The string is terminated by a null (0)
character.
In this example, AX register is used to address the string and BH is used
to store the number of characters. Hence, each character is fetched from the
memory and compared with 0. If the zero flag is set, the end of the string has been
reached. The count is incremented after each comparison, till the end of the string
is reached.
In this example, the string is assumed to start at 8500H and the end of string has
the value 0. Let the content of the location 8540H be zero. Then the result, which
is the length of the string to be checked, is 40. This result is stored in the memory
location 8550H.
LD AX, #8500H
LDB BH, #0
LI: LDB BL, [AX] +
INCB BH
CMPB BL, #0
JNE LI
LD AX, #8550H
STB BH, [AX]
here: SJMP here
Example 20.11:
Check the status of a bit in a byte using the JBS instruction. The byte to be checked
is stored in memory location 85OOH. Check the status of bit 0. Store this status in
memory location 8501H.
LD AX, //8500H
LDB BL, [AX] +
JBS BL, 0, LI
LDB CL, #0
STB CL, EAX]

SJMP L2
Ll: LDB CL, #1
STB CL. LAX]
L2: SJMP L2
Example 20.12:
Generate switching pulses for a single-phase inverter.
The following program generates the switching pulses for a single-phase
inverter through a parallel port of the 8255. Figure 20.2 shows the switching
pulses generated for the inverter. Changing the corresponding count can change
the width of the switching pulse and hence the frequency of the output signals.
Algorithm:
(i) Initialize the 8255 programmable peripheral interface (PPI) to configure the
I/O port.
(ii) Store the port A and port B addresses in an internal register.
(iii) Output ‘FFH’ to port A and ‘OOH’ to port B.
(iv) Introduce a delay for the required half-period duration.
(v) Output ‘OOH’ to port A and ‘FFH’ to port B.
(vi) Introduce a delay for the required half-period duration.
(vii) Repeat this process for the next cycle.
Fig. 20.2 Gating signal pattern for single-phase inverter
Program:
I n i t: LD 80, //Control - port-8255
LDB 82, //Control -word
LD 84, //portA-8255-addr ; Initialize the 8255 port A
address.
LD 86, Z/portB-8255-addr ; Initialize the 8255 port B
address.
LDB 88, //Delay count : Delay count for 180 degrees
STB 82, 80 : Write control word to 8255
Start: LDB 8C, //FFH : Load data to switch on the
device in port A.
LDB 8E, //OOH : Load data to switch off the
device in port B.
STB 8C, [84] Store the data in port A

STB 8E, [86] Store the data in port B
LDB 8A, 88 Load count value
Loopl: DECB 8A Wait for T/2 secs
JNE I oopl
STB 8C, [86] Store the data in port B
STB 8E, [84] Store the data in port A
LDB 8A, 88 Load delay count val ue
Loop2: DECB 8A Wait for T/2 secs •
JNE 1 oop2
SJMP start Repeat
Example 20.13:
Generate switching pulses for a three-phase bridge inverter (for 180° conduction
mode).
The following program generates switching pulses for the three-phase inverter
in 180° switching mode. In this mode, the pulse must be on for a period of T/2 of
the switching frequency and must be spaced at an angle of 60°. The pulse for each
switch is the output on each nibble of the port. Here, the 8255 PPI IC is assumed
to be interfaced with the 8096. With three ports, six pulses are output through six
nibbles of the port pins. Figure 20.3 shows the gating signal pattern for a three-
phase bridge inverter for 180° conduction mode.
Port A
gi Lower
Port A
gz Upper
PortB
‘93 Lower
PortB
9* Upper
PortC
Lower
PortC
0 Upper
fig. 20.3 Gating signal pattern for three-phase bridge inverter

Program:
Ini t: LD 80, ^Control-port-addr
LDB 82, ^Control word
STB 82, 80 ; Write control word to 8255
LD 84, #portA-addr
LD 86, #portB-addr
LD 86, #portC-addr
LDB 8A, #00H ; Output data are stored from
8A to 8D.
LDB 8B, #F0H
LDB 8C, #0FH
LDB 8D, #FFH
LDB 8E, #delay count ; Load delay corresponding to
T/6 secs
Start: STB 8C, [84]
STB 8A, [86]
STB 8D, [88]
SCALL Del ay
STB 8D, [84]
STB 8A, [86]
STB 8B, [88]
SCALL Del ay
STB 8D, [84]
STB 8C, [86]
STB 8A, [88]
SCALL Del ay
STB 8B, [84]
STB 8D, [86]
STB 8A, [88]
SCALL Del ay
STB 8A, [84]
STB 8D, [86]
STB 8C, [88]
SCALL Del ay
STB 8A, [84]
STB 8B, [86]
STB 8D, [88]
SCALL Del ay
SJMP Start
Del ay: LDB 90, 8E
DECB 90
JNE Del ay
RET
POINTS TO REMEMBER
• The Intel 8096 instruction set supports many data types such as bytes, words, double
words, short integers, long integers, and bits.
• The addressing modes supported by the 8096 include immediate, direct, indirect, and
indexed addressing. The auto increment option is available for indirect addressing.
• The instruction set of the 8096 is more flexible in comparison with that of the 8051, with
more arithmetic and compare operations on both signed and unsigned numbers.
KEY TERMS
Bits These are operands that can take only the Boolean values true and false.
Bytes These are unsigned 8-bit variables, which can take values between 0 and 255.
Double words These are unsigned 32-bit variables, which can take values between 0 and
4,29,49,67,295.
Long integers These are 32-bit signed variables, which can take values between
-2,14,74,83,648 and +2,14,74,83,647.
Short integers These are 8-bit signed variables, which can take values from -128 to
+127.
Stack pointer It points to the top of the stack and facilitates the accessing of operands
in the stack.
Words These are unsigned 16-bit variables, which can take values between 0 and
65535.
REVIEW QUESTIONS 1
1. What is addressing?
2. Compare short-indexed and long-indexed addressing.
3. Discuss zero register addressing.
4. What is conditional and unconditional branching?
5. What is a subroutine? Explain with an example.
6. Give examples for single-operand instructions.
7. What is the difference between signed number arithmetic and unsigned number
arithmetic?
8. What is the difference between logical shift and arithmetic shift in the 8096?
PROGRAMMING EXERCISES1
1. Write a program using 8096 mnemonics to multiply two 32-bit numbers.

2. Write a program to search for a particular data byte in a block of internal RAM. Identify
and store the memory location of the data byte.
3. Write a program to arrange a block of binary numbers in ascending order.
4. Write a program to read a data from the input port and then jump to different locations
based on the setting of different bits in the data.
CHAPTER 21|
HARDWARE FEATURES OF 8096

LEARNING OUTCOMES
• Parallel ports in the 8096 and their structure
• Control and status registers in the 8096
• 8096 timers and their control registers
• Interrupts and serial port in the 8096
• ADC and DAC interface with the 8096
• 8096 high speed input and output units (HSI and HSO)
• Memory expansion and bus width in the 8096
21.1 PARALLEL PORTS IN 8096 AND THEIR STRUCTURE

The 8096 has five 8-bit I/O ports called port 0 (P0), port 1 (Pl), port 2 (P2), port 3
(P3), and port 4 (P4). These ports are discussed in Sections 21.1.1-21.1.4.
21.1.1 PortO
Port 0 is an input-only port, which is also used as the analog input port for the
analog-to-digital converter (ADC). So if the analog input features of the 8096 are
not used, port 0 can be used as the input port. The status/voltage of port 0 can be
read from its address 0EH, which lies in the on-chip memory. Figure 21.1 shows
the structure of ports 0 and 1.
Fig. 21.1 Structure of ports 0 and 1

21.1.2 Port 1
Port 1 is a quasi-bidirectional port. This means that port 1 can be used as either
the input port or the output port. It is mapped at the internal memory address OFH.
If any one of the port 1 pins is to be used as an input port, the data ‘ 1 ’ should be
written onto the corresponding bit in the address OFH, before the status of that
bit is read. For example, if bits 0 and 1 of port 1 are to be used as input ports, the
data byte 00000011 is first written onto port 1. Then the status of the bits 0 and 1
is read.
Example:
The following program inputs the status of the least significant nibble of port 1 and
outputs the complement of the input to the most significant nibble of port 1.
LDB AL, P0RT1 AL: 10010101
ANDB AL, #OFH AL: 00000101
NOTB AL:(FF-AL) AL: 11111010
SHLB AL, #4 AL: 10100000
STB AL, P0RT1
OVER: SJMP OVER
21.1.3 Port 2
Port 2 has three types of port lines—
input-only, output-only, and quasi-
bidirectional. Except for P2.6 and
P2.7 (the sixth and seventh pins of
port 2), the remaining port 6 pins have
alternative functions. The address of
port 2 is 10H. Figure 21.2 shows the
structure of port 2.
The functions of the port 2 bits are
given in Table 21.1.
Table 21.1 Bit functions of port 2
Pin Function Alternative function Controlled by

0 Output Serial port transmit IOC 1.5
1 Input Serial port receive —
2 Input External interrupt IOC1.1

3 Input Timer 2 clock input IOCO.7
4 Input Timer 2 reset IOCO.5
5 Output PWM output IOC 1.0
6 Quasi-bidirectional
7 Quasi-bidirectional
If a particular alternative function is not used, the corresponding port 2 pin can be
used as an input or an output pin. The function of P2.6 and P2.7 is similar to that
of the port 1 pins.
21.1.4 Ports 3 and 4

Ports 3 and 4 pins have two functions. They function as either bidirectional ports
with open drain outputs or as system bus pins, which the memory controller uses
when it accesses the off-chip memory. As shown in Fig. 21.3, ports 3 and 4 are
used as ADO-AD 15 lines for external memory access. Since external address and
data buses are used, port 3 and port 4 lines are not available to the user. If the EA
line is low, memory access is from the external memory and so the port pins act
as the system bus. If the EA line is high, the port pins act as parallel port bus pins.
If the pins are used as ports, the data ‘1’ must be written into them prior to bus
operation.
Pull-up resistors are only needed on

lines to be used as output port lines
Fig. 21.3 Structure of ports 3 and 4
21.2 CONTROL AND STATUS REGISTERS

The two I/O control registers are 1OC0 and IOC1. IOCO controls timer 2 and the
HSI lines. IOC1 controls some pin functions, interrupt sources, and two HSO
pins.
21.2.1 Input/Output Control Table 21.2 Bit format of IOCO
Register 0
Bit Function
IOCO is located at the memory
location 0015H. The four HSI DO HSI.O input enable/Disable
lines can be enabled or disabled DI Timer 2 reset at every write
by setting or clearing the bits in D2 HSI.l input enable/Disable
IOCO. The timer 2 functions,
D3 Timer 2 external reset enable/Disable
including clock and reset sources,
are also determined by IOCO. The D4 HSI.2 input enable/Disable
control bit definitions are shown D5 Timer 2 reset source HSI.0/T2RST
in Table 21.2. IOCO is used for
D6 HSI.3 input enable/Disable
the initialization of the timer and
HSI only. D7 Timer 2 clock source HSI.1/T2CLK
21.2.2 Input/Output Control Register 1

IOC1 is used to select some Table 21.3 Bit format of IOC1
pin functions, and enable
or disable some interrupt Bit Function y
sources. Its location is DO Select PWM/Select P2.5
0016H. The port pin 2.5 can
DI External interrupt ACH7/EXTINT
be selected to be the PWM
D2 Timer 1 overflow interrupt enable/Disable
output, instead of a standard
output, by setting the DO bit D3 Timer 2 overflow interrupt enable/Disable
of IOC1. Using the DI bit, D4 HSO.4 output enable/Disable
the external interrupt source
D5 Select TXD/Select P2.0
can be selected to be either
EXTINT (same pin as P2.2) D6 HSO.5 output enable/Disable
or analog channel 7 (ACH7, D7 HSI interrupt FIFO full/Holding register loaded
same pin as POT). The timer
1 and timer 2 overflow interrupts can be individually enabled or disabled using
the bits D2 and D3. The HSI interrupt can be activated either when there is one
FIFO entry or when there are seven, depending upon the D7 bit. The port pin P2.0
can be selected to be the TXD output by Table 21.4 Bit format of IOSO
setting the D5 bit. HSO.4 and HSO.5
can be enabled or disabled for the HSO Bit Function
unit, using the D4 and the D6 bits. The DO HSO.O current state
function of the IOC1 control bits is
DI HSO. 1 current state
D2 HSO.2 current state
21.2.3 Input/Output Status Register 0 D3 HSO.3 current state
The two I/O status registers are IOSO and
D4 HSO.4 current state
IOS 1. The address of the IOSO register is
0015H. It holds the current status of the D5 HSO.5 current state
HSO lines and the content addressable D6 CAM or holding register is full
memory (CAM). The status bits of IOSO D7 HSO holding register is full
are shown in Table 21.4.
21.2.4 Input/Output Status Register 1

IOS1 is located at 0016H. It contains status bits for the timers and for
high speed input/output (HSI/O). The function of these bits is shown in
Table 21.5. Whenever the processor
reads this register, all the timer- Table 21.5 Bit format of IOS1
related flags (bits 5-0) are cleared.
This applies not only to explicit Bit Function
read operations such as DO Software timer 0 expired

LDB AL, I0S1 DI Software timer 1 expired
but also to implicit read operations
D2 Software timer 2 expired
such as
JB I0S1.3, THERE D3 Software timer 3 expired
where the program execution jumps D4 Timer 2 overflow
to THERE if bit 3 of IOS 1 is set.
D5 Timer 1 overflow
D6 HSI FIFO is full
21.3 TIMERS
D7 HSI holding register data available
Two 16-bit timers—timer 1 and
timer 2—are available for use with
the 8096. Timer 1 is used to synchronize events to real time, while timer 2 can be
clocked externally and used to synchronize events to external occurrences.
21.3.1 Timer 1
The timer 1 of the 8096, shown in Fig. 21.4, is a 16-bit counter, which is clocked
every two microseconds (i.e., every eight internal clock cycles). It can be read
Timeri (OOOBH,000AH)
(word read)
I/O control register 1

IOC1 (0016H)
(write)
Set to enable interrupt when timer 1 overflows

(i.e., rolls over from FFFFH to 0000H); cleared
to disable timer overflow interrupts
I/O status register 1

IOS1 (0016H)
(read: clears bits 0-5)
Timer overflow 2000H
Interrupt vector 2001H
Fig. 21.4 Timer 1 operation and control

from at any time, but must never be written into. Further, while 000BH contains
the upper byte of timer 1, 000AH contains its lower byte.
The hardware accepts only reads of the entire two-byte word, as in the following
example:
ADD HSO-TIME. Timed, #15
The example reads the timer 1 value, adds 15 to that value, and stores the
result in HSO-TIME. Timer 1 is used in conjunction with the HSI/O system. This
makes up the 8096’s programmable timer capability, which times input events and
controls the timing for output events. Timer 1 can be cleared only by executing a
reset. IOC1 is used to enable the interrupts when timer 1 overflows. The overflow
can be read from the status register IOS 1.
21.3.2 Timer 2
Timer 2 of the 8096, shown in Fig. 21.5, is a 16-bit event counter. It must be clocked
by a signal coming into the chip. Timer 2 is counted on both the rising edges and the
falling edges of the input signal. The minimum time between edges is 2.0 ps. This
corresponds to a square wave input, having a maximum frequency of 250 kHz.
T2CLK
Fig. 21.5 Timer 2 clock and reset options
21.3.2.1 Clock Source for Timer 2

Either of the two input pins, T2CLK or HSI.l, can be used for the clock source
for timer 2. If it is required to keep track of the time of occurrence of the input
transitions, the HSI.l pin becomes an appropriate choice. Otherwise, T2CLK (i.e.,
bit 3 on port 2) can be selected, releasing HSI.l. The choice between these two
clock sources is made by setting or clearing bit 7 of IOCO. The operation and
control of timer 2 can be easily understood from Fig. 21.6.
Timer 2 registers (000DH, 000CH)

(word read)

IOCO (0015H) (write)
I_______ > Each write of a 1 to this bit
resets timer 2
Set to enable HSI.1 as timer 2 clock;
■> Set to enable ext. reset of timer 2
clear to enable T2CLK as timer 2 clock
7 6 5 4 3 2 1 o
Fig. 21.6 Timer 2 format, operation, and control
21.3.2.2 Reset for Timer 2

Resetting is the only other control that can be exerted over timer 2. It can be reset
in the following ways:
(i) Setting bit 1 of the IOCO register
(ii) Using a high speed output (HSO) unit
(iii) Using the rising edge on the port pin P2.4 (i.e., T2RST)
(iv) Using the rising edge on the high speed input pin HSI.O
The following points explain the four choices for resetting timer 2:
(i) Write ‘1’ to bit 1 of IOCO. This resets timer 2, but does not hold it at reset.
(ii) Set up the HSO facility to reset timer 2. This permits timer 2 to be reset
when it has reached a certain count. Thus, a modulo N counter of input
events can be produced, perhaps to generate an interrupt and an output
pulse each time that a rotating gear makes one complete revolution.
(iii) Receive a rising input edge on the high speed input pin HSI.O. This also
permits us to determine the time of resetting, since the rising edge into
HSI.O can be used to capture the value of timer 1 at that instant.
(iv) Receive a rising input edge on T2RST. This choice might be used in place
of HSI.O, if we do not actually need to know the time of resetting. Thus,
HSI.O is released to carry out a timing function.
All these options are controlled by what is written into the input 1OC0.
21.4 INTERRUPTS
There are 21 sources of interrupts in the 8096. These sources are grouped into
eight interrupt types. The I/O control registers that control some of the sources are
indicated in Fig. 21.7. Each of the eight types of interrupts has its own interrupt
vector. In addition to the eight standard interrupts, there is a TRAP instruction,
which acts as a software-generated interrupt.
Sources Interrupt types
EXTINT
TI flag Serial port
RI flag
Software timer
Software timer 0
Software timer 1
Software timer 2
Software timer 3
Reset timer 2
Start ADC
AD conversion complete AD conversion complete
Timer 1 overflow ----------- • V—> I0C1.2
------------ 1----------------------------------------------- Timer overflow

Timer 2 overflow ----------- • IOC1.3
Fig. 21.7 Interrupt sources
21.4.1 Interrupt Sources

The external interrupts can be applied to the pins EXTINT or ACH7. This forms
the first group of interrupts. The serial port interrupts TI and RI form the next
group of interrupts. The software timers 0, 1,2, and 3 and the start of the ADC
conversion form another group of interrupts. The HSI.O input can be used as an
interrupt. The HSO unit can be used for programming execution of any event at
a time specified by a timer value. Any such HSO operation, if completed, can
interrupt the processor. This is considered as a separate group of interrupts. The
HSI unit can be programmed to record the timing of any input appearing at the
HSI pins. After the recording of any event on the HSI pins, the processor can be
interrupted with the interrupt HSI data available. The ADC unit can also interrupt
the processor after completion of the conversion. The last group of interrupts is
the timer overflow interrupt. The timers are programmed to count up to the desired
count value and then interrupt the processor.
Table 21.6 gives the priority of the eight different groups of interrupts and their
interrupt vector addresses. The program at these vector locations must identify the
actual interrupt source. For example, the serial port interrupt has a single vector
address. The interrupt service routine must read the status register and identify
whether the receive interrupt or the transmit interrupt has occurred.
Table 21.6 Interrupt vector locations and their priorities
Vector location
Vector Priority
Higher-order byte Lower-order byte
Software trap 2011H 201 OH Not applicable
External interrupt 200FH 200EH 7 (highest)
Serial port 200DH 200CH 6
Software timers 200BH 200AH 5
HSI.O 2009H 2008H 4
High speed outputs 2007H 2006H 3
HSI data available 2005H 2004H 2
A to D conversion complete 2003H 2002H 1
Timer overflow 2001H 2000H 0 (lowest)
21.4.2 Polling Routine

All microcontrollers must execute a polling routine to determine the source of
the interrupt, whenever an interrupt occurs. This implies that the first part of the
interrupt service is used to poll all possible sources of the interrupt to determine
the cause of the interrupt. This is illustrated in Fig. 21.8.
21.4.3 Vectored Interrupt

In vectored interrupts, each source of interrupt leads directly to the code that needs
to be executed to service that specific source. In vectored priority interrupts, one
source of an interrupt may be receiving service, when a higher priority source
suddenly becomes ready for service. Rather than making the higher priority source
wait, the microcontroller lets the higher priority source preempt the lower one.
Thus, the lower priority service routine is put on hold until the higher priority
service routine is finished, at which point the lower one picks up again.
The sample sequence of operation for vectored priority interrupts is shown in
Fig. 21.9. On the left, interrupt service routine 5 is shown interrupting the main
line program. In the middle of its execution, the higher priority interrupt service
i-
t
Fig. 21.8 Polling routine to determine interrupt source
routine 3 comes in and gets serviced, after which 5 resumes operation. The right
side of the figure is intended to illustrate the higher priority interrupt service
routine 3 being serviced and causing the servicing of the interrupt source 5 to be
delayed until it is done.
Time
Main line
program
Higher priority
interrupt service
routine 3
Lower priority
interrupt service
routine 5
Fig. 21.9 Vectored priority interrupt

Another possibility, in which almost no interrupt service routine takes very

long, is illustrated in Fig. 21.10. The figure shows one interrupt service routine
getting serviced initially. It keeps interrupts disabled throughout its service
routine. While it is being serviced, four other sources become ready for service.
At the completion of the first interrupt service routine, the four interrupt sources
that are pending (i.e., waiting) are automatically sorted out by the CPU, which
immediately goes into the service routine for the highest priority source. The
only difference between this case and the previous is the duration of the longest
interrupt service routine, since this is the maximum amount of increased latency
(i.e., increased delay) that any source will see.
Fig. 21.10 Priority of pending interrupts handled automatically by the CPU
21.4.4 Interrupt Control

The 8096 supports the interrupt response to any of 21 different sources. Each
interrupt source filters through a sequence of enabling conditions to determine
whether it can actually interrupt the CPU operation. Figure 21.11 shows this
sequence of operations. The PSW is fundamental to interrupt operation. The most
significant byte of the PSW contains the CPU’s flag bits. One of these bits, PSW
bit 9, is the global interrupt enable bit I. This bit is cleared during reset, disabling
all interrupts initially. It is set under program control to enable any interrupt to the
CPU. The PSW also contains a global disable bit I, which is set or cleared using
the EI or DI instruction.
The three registers that control the interrupt system are as follows:
INT_PENDING register
INT.MASKING register
(iii) Program status word
Interrupts
D bus Control unit
Fig. 21.11 Block diagram of the interrupt system
21.4.5 Interrupt Pending Register

When the hardware detects one of the eight interrupts, it sets the corresponding
bit in the interrupt pending register (INT_PENDING; 09H). When the interrupt
vector is read, the pending bit is cleared automatically. The register format is
shown in Table 2E7.
This register can be read or modified as a byte register. It can be read to
determine which of the interrupts is pending at any given time, or modified, to
either clear pending interrupts or generate interrupts under software control. Any
software that modifies the INT_PENDING register should ensure that the entire
operation is indivisible. The easiest way to Table 21.7 Bit format of interrupt
do this is to use the logical instructions in the pending register
two- or three-operand format. For example,

Bit Function
to invoke the analog to digital conversion
complete interrupt service routine, we can D7 External interrupt
execute the following instruction: D6 Serial VO
ORB INT_PENDING, #0000001 OB
D5 Software timers
We can also eliminate a pending
interrupt by clearing the associated bit of D4 HSI bit 0
INT_PENDING, i.e., D3 HSO event
ANDB INT_PENDING, # 11111101B D2 HSI data available
; clears the A/D interrupt.
DI A to D conversion complete
21.4.6 Interrupt Mask Register DO Timer overflow
Individual interrupts can be enabled or
disabled by setting or clearing the bits in the interrupt mask register (INT_MASK;
08H). The format of this register is the same as that of the interrupt pending
register. A ‘1’ in any bit position enables the corresponding interrupt source and a
‘0’ disables it. The INT_MASK register can be read from or written into as a byte
register. It can also be accessed as the lower eight bits of the PSW. So the PUSHF
and POPF instructions save and restore the INT_MASK register, as well as the
global interrupt lockout (Section 21.4.7) and the arithmetic flags.
21.4.7 Global Disable

The processing of all interrupts can be disabled by clearing the bit I in the PSW.
Setting the bit I will enable interrupts that have mask register bits, which are already
set. The bit I is controlled by the EI (enable interrupt) and DI (disable interrupt)
instructions. It controls only the actual servicing of the interrupt. Interrupts that
occur during periods of lockout are held in the pending register and serviced on a
prioritized basis when the lockout period ends.
The priority encoder looks at all the interrupts that are both pending and enabled,
and selects the one with the highest priority. When the interrupt controller decides
to process an interrupt, it executes a ‘call’ to an interrupt service routine (ISR).
The address of the ISR is contained in the corresponding interrupt vector location.
The interrupt controller clears the associated pending bit, and then pushes the
return address onto the stack.
For example, consider the HSI data available interrupt. The CPU is interrupted
by the HSI data available interrupt, if the following three conditions are met:
(i) Bit 7 of IOC1 is set.
(ii) Bit 2 of the PSW, which is also bit 2 of INT_MASK, is set.
(iii) The bit I (interrupt enable) in the PSW is set.
21.4.8 Program Status Word

The program status word (PSW) is a collection of Boolean flags that contain
information concerning the state of the user’s program. The higher-order byte
of the PSW contains status flags and the lower-order byte contains an interrupt
HARDWARE FEATURES OF 8096 6 29
mask register. The format of the PSW is shown in Fig. 21.12. The PSW can be
saved in the system stack with a single operation (PUSHF) and restored to the
corresponding register (POPF).
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO
Z N V VT C - I ST INT_MASK register
Fig. 21.12 Bit format of program status word
The designers of the 8096 have provided users the flexibility of installing their
own priority scheme in place of an existing priority. For example, if the highest
priority is to be given to the analog to digital conversion complete interrupt and the
next priority is to be given to the HSO interrupt, the analog to digital conversion
complete interrupt service routine, ADCC-ISR, will take the following form:
ADCC-ISR: PUSHF ; Save the PSW, then clear it
; Service A-to-D converter (with I = 0)
POPF : Restore PSW

RET : Return from interrupt
This recasting of interrupt priorities depends upon the fact that when an interrupt
service routine is entered, its first instruction is always executed. When this is
a PUSHF instruction, its execution clears the PSW, including the bit I, disabling
further interrupts. In addition, both PUSHF and the following EI instruction
postpone any potential interrupt servicing until the instruction changing the
INT_MASK register is executed.
At the end of the interrupt service routine, the POPF instruction restores the original
value of the PSW, thereby restoring the interrupt priority scheme to the same
state it was in when the interrupt occurred. Since interrupts are not acknowledged
immediately after a POPF instruction, the RET instruction is executed (clearing
the stack) before another interrupt is serviced.
21.5 SERIAL PORTS

The serial port employs just two VO pins on the 8096 chip. They are bits 0 and 1
of port 2, renamed TXD and RXD when the pins are dedicated to serial port use.
Bit 0 of port 2 is always an output, whether used as TXD or as a general-purpose
output pin (accessed by a write to port 2). If the serial port is left unused, bit 1 of
port 2 is a general-purpose input pin (accessed by a read of port 2). When the serial
port is used as a UART, bit 1 of port 2 serves as the RXD (receive data) input pin.
On the other hand, if the serial port is used as an I/O serial port for I/O expansion,
bit 1 of port 2 serves as the data output pin (when data is transmitted) and as the
data input pin (when data is received).
21.5.1 Operating Modes of Serial Port

The serial port on the 8096 has four modes of operation—three asynchronous
modes and one synchronous mode:
(i) Synchronous mode (mode 0)
(ii) Asynchronous mode
(a) Mode 1 (b) Mode 2 (c) Mode 3
21.5.1.1 Model
Mode 1 is the standard asynchronous communication mode. The data frame used
in this mode is shown in Fig. 21.13.
Fig. 21.13 Bit format for serial transmission in mode 1
It consists of 10 bits—a start bit (0), eight data bits (LSB first), and a stop bit
(1). If parity is enabled (the PEN bit is set to ‘ 1’), an even parity bit is sent instead
of the eighth data bit, and parity is checked on reception.
21.5.1.2 Mode 2
Mode 2 is the asynchronous ninth bit recognition mode. Figure 21.14 shows the
data frame used in this mode.
Fig. 21.14 Bit format for serial transmission in mode 2
It consists of a start bit (0), 9 data bits (LSB first), and a stop bit (1). While
transmitting data, the ninth bit can be set to ‘1’, by setting the TB8 bit in the
control register, before writing to SBUF (TX). The TB8 bit is cleared on every
transmission of data. During reception, the serial port interrupt and the receive
interrupt (RI) bits are not set unless the ninth bit being received is set. This provides
an easy way to have selective reception on a data link. Parity cannot be enabled in
this mode.
21.5.1.3 Mode 3
Mode 3 is the asynchronous ninth bit mode. The data frame for this mode is
identical to that of mode 2. The transmission difference between mode 3 and mode
2 is that parity can be enabled (PEN = 1), and can cause the ninth data bit to take
the even parity value. In this mode, the TB8 bit can still be used if parity is not
enabled (PEN = 0). The reception always causes an interrupt, regardless of the
state of the ninth bit. The ninth bit is stored if PEN = 0 and can be read in the bit
RB8. If PEN = 1, RB8 becomes the receive parity error (RPE) flag.
21.5.2 Serial Port Control/Status Registers

Control of the serial port is done through the serial port control (SP-CON) and
serial port status (SP-STAT) registers as shown in Table 21.8. Writing to memory
location 11H would access the SP-CON, whereas reading the same location would
access the SP-STAT. It should be noted that reading data from SP-STAT returns
the indeterminate data in the lower five bits, and writing to the upper three bits of
SP-CON has no effect on chip functionality. Both TI and RI are cleared whenever
SP-STAT is accessed.
To transmit data through the serial port, the data is written to the serial port
buffer (location 07H). Whenever the TXD pin is used for the serial port, it must be
enabled by setting IOC.5 to ‘1’. To receive data from the serial port, REN is set to
1. After the data is received at the serial port, the data can be read from the serial
buffer.
Table 21.8 Bit format of serial port control/status register
Bit RB8/ RI TI TB8 REN PEN M2 Ml

RBE RI
Read/Write SP-STAT—read only SP-CON—write only Mode select

Explanation Ninth Receive Transmit Ninth data Enable Enable 00—mode 0
data bit interrupt interrupt bit for receive even 01—mode 1
received/ flag flag transmission function parity 10—mode 2
parity 11—mode 3
error
indicator
Bit 5 of IOC1 must be set to assign bit 0 of port 2 to the TXD serial port
function. The baud rate is selected by writing two consecutive bytes to a single
address, 000EH, designated BAUD-RATE. The 16 bits are used in two parts.
The serial port control register is used to select the serial port’s mode of
operation. Its REN bit (bit 3) is used to enable the receive function.
Data is transmitted by writing it to SBUF. When data has been received, it is
read from SBUF. Although Intel uses the name SBUF for both of these functions,
an SBUF read operation actually accesses a different register from that accessed
by an SBUF write operation.
21.5.3 Determining Baud Rate

Baud rate, in all modes, is determined by the contents of a 16-bit register at the
location 000EH. This register must be loaded sequentially with two bytes (least
significant byte first). The serial port does not function between the loading of the
first and second bytes. The MSB of this register selects one of two sources for
setting the input frequency to the baud rate generator. If it is ‘1’, the frequency on
the XTAL1 pin is selected; if not, the external frequency from the T2CLK pin is
used. It should be noted that the maximum speed of T2CLK is one transition every
two state times, with a minimum period of 16 XTAL1 cycles.
The unsigned integer represented by the lower 15 bits of the baud rate register
defines a number B, where B has a maximum value of 32,767. The baud rate for
the four serial modes, using either XTAL1 or T2CLK as the clock source, is given
as follows:
Using XT ALT.
XTAL1 freq.
Mode 0: Baud rate = 4 x (g + ;B/0
XTAL1 freq.
Other modes: Baud rate = ;B 0
64 x (B + 1)
Using T2CLK:
T2CLK freq.
Mode 0: Baud rate = ------ 5-------- ; B # 0
T2CLK freq.
Other modes: Baud rate = —iv j~d— ; B # 0
to x Jd
Table 21.9 Baud rate selection
Baud rate is determined by the contents
of a 16-bit register at the location 000EH. Baud rate Baud register content
This register must be loaded sequentially 9600 8013H
with two bytes (least significant byte first).
4800 8026H
Common baud rate values are shown in
Table 21.9. The most significant bit written 2400 804DH
in the baud rate register selects the clock 1200 809BH
source. 8270 H
300
There is an option to use T2CLK as one
of the possible clock sources for timer 2. The
remaining bits, designated B, set up a divider for the selected clock source, to
obtain the desired baud rate. Even if a crystal clock frequency other than 12 MHz
is used with the chip, this approach still permits standard baud rates to be achieved.
The registers associated with the serial port are shown in Fig. 21.15 on page 633.
21.5.4 Program for Serial Port Data Reception

The following program initializes the on-chip serial port mode 1 with a baud rate of
9600, and transmits a single byte, 41H. It receives a byte and stores it at 91 OOH.
LDB IC01, #00100000 ; Select TXD
LDB BAUD, #13H ; Baud rate = 9600
LDB BAUD, #80H
LDB SP-CON, #00011001 : Enable
LDB INT MASK, #00 : Receiver, mode 1
LDB SBUF, #41H : Transmit ‘A’
S-CHECK: LDB BL, SP-STAT
ANDB BL, #01000000
CMPB BL, #01000000
JNE S_CHECK
LDB BL, SBUF

LD AL, #9100H
STB BL, [AL]
HERE: SJMP HERE
IOC1
16H (write)
> Set to enable TXD output

Second byte written to BAUD-RATE First byte written to BAUD-RATE
Baud rate section register

BAUD-RATE (000EH) (write)
Clock source select

■> If set, XTAL1 (Internal frequency of 12MHz) is selected
If cleared, T2CLK (External clock of max. frequency 750 MHz) is selected
Receive data register
SBUF (0007H) (read)
Transmit data register

SBUF (0007H) (write)
200CH
200DH
Fig. 21.15 Registers associated with serial port
21.6 ANALOG-TO-DIGITAL CONVERTER

The 8096 has an eight-channel ADC. The special features of the on-chip ADC are
as follows:
(i) 1 O-bit successive approximation type ADC
(ii) 22 ps conversion time
(iii) 0 to 5 V unipolar input to ADC
(iv) Built-in sample and hold circuit
(v) ADC sampling through the internal timer of the 8096
The analog to digital conversion can be initiated in any one of the ADC
channels. The channel can be selected by writing into the command register or
by means of a trigger from the HSO unit. The command register is at address
02H in the on-chip memory. The format of the AD command register is shown in
Fig. 21.16.
Location 02H
7 6 5 4 3 2 1 0
X X X X Go
Fig. 21.16 Format of AD command register

CH# indicates which of the eight analog input channels is to be converted to

digital form. Go indicates when the conversion is to be initiated. Go = 1 means
that the conversion can be initiated now and Go = 0 means the conversion is to be
initiated by the HSO unit at the specified time.
The results of the ADC are read from the AD result register at memory locations
02H and 03H, as shown in Fig. 21.17. Note that the ADC status bit may not be set
until eight state times after the Go command. So it is necessary to wait eight state
times before testing it.
In the 8096, the analog inputs of channels 0-7 have voltage protection circuitry.
So even if the voltage in the analog input channels 0-7 exceeds 0-5 V range, it
does not affect the microcontroller.
AD result register
1 0
_______ I
---------- > A/D channel
number
Status
-> 0= A/D conversion over
1 = conversion in progress
Fig. 21.17 AD result register
Programming sequence To initiate a conversion in the ADC channel and to

read the converted data, the following steps are to be carried out:
(i) Send the ADC command word. In the command word, set the channel bits
(0-2) and the Go bit (bit 3). The command word selects the channel and
initiates the ADC conversion on that channel.
(ii) Wait for eight state times for the ADC status to be set.
(iii) Check the ADC result register bit 3. If bit 3 = 1, A/D conversion is in
progress. Check again until bit 3 = 0.
(iv) Input data from the ADC result register (bits 6-15).
(v) To initiate a new conversion, start from step 1.
Program'.
LD B AD-COMMAND, //OAH
NOP
NOP
CHECK: JBS AD-RESULT-L0, 3, CHECK
LD B AL, AD-RESULT-LO
LB B AH, AD-RESULT-HI
SHR AX, #6
AND AX, #3FFH
LD BX, //9000H
ST AX, [BX]
OVER: SJMP OVER
A block diagram of the complete multiplexer sample-and-hold ADC combination

is shown in Fig. 21.18. A sample-and-hold circuit takes a snapshot of the analog
input voltage and holds this value during the conversion process. The ADC
converts the analog input voltage relative to the reference voltage range defined
by the voltage inputs labelled Vref and Vgnd.
Fig. 21.18 AD converter block diagram
The output voltage of the ADC is given by the following expression:
Output = 12------ x (2" - 1)

ref Vgnd
If Vin = Vgnd OUtPUt = 00000000

If V.n = Vref output = 11111111
The resolution of a 1 O-bit ADC is calculated as follows:

Voltage range = 0-5 V
Resolution = 5/210 = 0.004883 V
21.7 DIGITAL-TO-ANALOG CONVERTER

Digital to analog conversion can be done with PWM output. A block diagram of
the PWM circuit is shown in Fig. 21.19. A PWM includes an 8-bit PWM counter,
which is continuously clocked at the internal clock rate (4 MHz, given a 12 MHz
crystal). This register is not accessible under program control. However, it is
embedded in the circuitry, which compares its output with that of the pulse width
modulation control register.
Data
bus x 8
i
Overflow
Fig. 21.19 PWM unit
The output line (Q) is set when the PWM counter equals 0. The same output
line is cleared when the PWM counter equals the pulse width modulation control
register. When the counter overflows, the output is once again switched high. A
typical PWM output waveform and the registers used are shown in Fig. 21.20 (a)
and 21.20 (b), respectively.
Fig. 21.20 (a) Output waveform of a PWM unit

Any waveform shown in Fig. 21.20 (a) can be generated, depending upon what
is written into the PWM control register. Changes in the duty cycle are made by
writing into the PWM register at the memory location 17H. The output is used to
drive a CMOS buffer, which in turn, has a DC component that is proportional to
the content of the PWM control register.
The PWM output shares a pin with pin 5 of port 2, so that the port output and
the PWM output cannot be used at the same time. The LSB in the register IOC1
has to be set to 1 for selecting the PWM function instead of the standard port
function.
Program for PWM output:
LDB AL, I0C1
ORB AL, #1
STB AL, I0C1 ; Select P2.5 for PWM output.
LDB PWM-CONTROL, #DUTY CYCLE ; Enter the required duty cycle
OVER: SJMP OVER
21.8 HIGH SPEED INPUT UNIT

High speed input (HSI) pins can be used to record the time at which an external
event occurs. The HSI unit is coupled to the timers such that it records the value
on timer 1 whenever an input transition occurs. There are four HSI lines (HSI.O,
HSI.l, HSI.2, and HSI.3), and up to eight events can be recorded using these
lines. HSI.2 and HSI.3 are bidirectional pins, which can also be used as HSO.4
and HSO.5. IOCO and IOC1 are used to determine the functions of these pins.
When a transition of voltage level occurs at a HSI pin, the timer 1 content is stored
into the HSI FIFO register automatically. The timer 1 is a 16-bit counter, which
is clocked every 2ps. So when a transition occurs at the HSI lines, a 16-bit timer
value is stored onto the FIFO. The FIFO is eight words deep and hence eight such
events can be stored in the FIFO. A block diagram of the HSI unit is shown in
Fig. 21.21.
When selected input events occur on any of the four lines, the time is
automatically read from timer 1 and stored into the FIFO along with four
Fig. 21.21 High speed input unit
identification bits. These four bits identify which one (or more) of the four inputs
caused the input capture to occur.
The FIFO has a width of 16 + 4 = 20 bits for each entry and is seven entries
deep. In addition, the oldest entry is moved out of the FIFO to the HSI holding
register. Thus the FIFO and the HSI holding register combination can record up
to eight input events before an overrun of the FIFO occurs. The HSI lines can be
individually enabled or disabled using the bits in IOCO as shown in Fig. 21.22.
7 6 5 4 3 2 1 0
X HSI.3 E/D X HSI.2 E/D X HSI.1 E/D X HSI.O E/D

■
Fig. 21.22 Input/output control register 0
In IOCO, when bit 0 is 1, HSI.O is enabled; when it is 0, HSI.O is disabled, and

so on.
There are four possible modes of operation for each of the HSI pins. The HSI
mode can be set by the HSI mode register (at the memory location 03H) as shown
in Fig. 21.23.
7 6 5 4 3 2 1 0
HSI.3 mode HSI.2 mode HSI.l mode HSI.O mode
Fig. 21.23 Format of HSI mode register

In the HSI mode control register, each 2-bit field defines one of the four possible
modes for HSI, as shown in Table 21.10.
Table 21.10 HSI modes
Bit values HSI modes

00 Sense every eighth positive transition
01 Sense each positive transition
10 Sense each negative transition
11 Sense every transition (positive or negative)
The registers associated with the HSI lines are as shown in Fig. 21.24.
7 6 5 4 3 2 1 0
IOC1 (0016H) (write)
■>■ Set to interrupt when FIFO is full
Clear to interrupt when HSI holding register data is available

(i.e., when at least one input event has been captured)
7 6 5 4 3 2 1 o
I/O status register 1
IOSI (0016H)
(read: clears bits 0-5)
7 6 5 4 3 2 1 0
HSI timer register

HSI-TIME (005H, 004H) (read)
Reads time In the HSI holding register and then
dumps this entry from the HSI holding register
Fig. 21.24 Registers associated with the HSI unit

Control of the HSI pin functions using IOCO is shown in Fig- 21.25. The
functions have been listed in Table 21.2.
Timer 2 CLK
HSI
Fig. 21.25 Control of HSI pin functions
21.8.1 HSI Interrupts

Interrupts can be generated by the HSI unit in three ways—two FIFO related
interrupts, and a 0-to-l transition on the HSI.O pin. The HSI.O pin can generate the
interrupt even if it is not enabled on the HSI FIFO. Interrupts at this pin cause the
CPU to branch to the subroutine at the vector address 2008H.
The FIFO-related interrupts are controlled by bit 7 of IOC 1 (IOC 1.7). If the bit
is 0, the interrupt is generated every time a value is loaded into the holding register.
If the bit is 1, an interrupt is generated only when the FIFO (independent of the
holding register) has six entries in it. Since all entries are rising-edge-triggered,
if IOC 1.7 = 1, the processor is not interrupted until the FIFO contains five or less
records.
21.8.2 Programming HSI

The status of the HSI FIFO can be read using the IOS1 whose address is 16H. The
format of IOS1 is shown in Fig. 21.26.
When bit 6 of IOS 1 is 1, the FIFO register is full. When bit 7 of IOS 1 is 1, the
FIFO has at least one entry to read.
7 6 5 4 3 2 1 0
Set when HSI holding register data Set when HSI FIFO X X X X X X
is available is full
...
Fig. 21.26 Input/output status register 1
Reading the HSI is done in two steps. First, the HSI status register is read. This
is done to obtain the current status of the HSI pins and to identify which pins have
changed at the recorded time. The HSI status register is at the memory location
06H. Its format is given in Fig. 21.27.
7 6 5 4 3 2 1 0
HSI.3 status HSI.2 status HSI.1 status HSI.O status
Fig. 21.27 HSI status register
For each 2-bit status field, the lower bit indicates whether or not an event has
occurred on this pin at the time stored in HSI-TIME; the upper bit indicates the
current status of the pin.
After reading the HSI status register, the HSI time register is read. The HSI-
time register is located at 04H and 05H.
Program description:
One of the most frequent uses of HSI is to measure the time between events.
This can be used for frequency determination in lab instruments or for speed/
acceleration information when connected to pulse-type encoders.
The following program can be used to determine the duration for which the
signals on HSI.O remain high/low.
LD B I0C0. #1 ; Enable HSI.O.
LD B HSI-MODE, #OFH ; Look for either positive edge or
negative edge.
WAIT: ADD PERIOD. HIGH TIME. LOW TIME
JBC I0S1, 7, WAIT ; Wait while no pulse is entered.
LD B AX. HSI-STATUS ; Load status. Note that reading
HSI-TIME clears HSI-STATUS.
LD BX. HSI-TIME ; Load the HSI time.
JBS AX, 1. HSI-HI ; Jump if HSI.O is high.
HSI-LO:ST BX. LO-EDGE
SUB HIGH TIME, LO-EDGE, HI-EDGE
SJMP WAIT
HSI-HI:ST BX, HI-EDGE
SUB LOW TIME, HI-EDGE, LO-EDGE
SJMP WAIT
END
Procedure:
Connect a square wave source to the HSI.O line. The HSI.O line is terminated at
the 50-pin frame rate converter (FRC) connector Pl. The square wave amplitude
should be in the range of 0-5 V.
Note that this program is in a continuous loop. It records the on time and off
time, and calculates the period, which is the sum of the on and off times. To see
the result, reset the kit and view the content of the period register (58H). Period is
in terms of the number of timer 1 clock pulses.
21.9 HIGH SPEED OUTPUT UNIT

The HSO unit is used to trigger the following events at specific times:
(i) Starting an analog to digital conversion
(ii) Resetting timer 2
(iii) Setting four software flags
(iv) Switching six output lines (HSO.O-HSO.5)
Up to eight events can be pending at one time and interrupts can be generated
whenever any of these events are triggered.
HSO.2 and HSO.3 are bidirectional pins, which can also be used as HSI.4 and
HSI.5, respectively. Bits 4 and 6 of IOC 1 (IOC 1.4 and IOC 1.6) enable HSO.4 and
HSO.5 as outputs. The block diagram is shown in Fig.21.28.
8 state time increment
Timer 2 input
Timer 2 reset
Port pins • Reset timer 2
Fig. 21.28 Block diagram of the HSO unit

HARDWARE FEATURES OF 8096 6 43
The heart of the HSO unit is the 23 x 8 CAM. Up to eight entries in the CAM is
looked at, once every 2ps. Each entry takes the form shown in Fig. 21.29.
Command Time
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Value to be compared, eveiy 2 ps, with the content of timer 1

or timer 2 (as selected by bit 6 of command)
Channel
0-5-HSO.0-HSO.5
6-HSO.O and HSO.1
7-HSO.2 and HSO.3
8-B—Software timers 0,1,2, and 3
E—Timer 2 reset
F—Start A/D conversion
--------------- > Set to generate interrupt when timeout occurs
Set output pin to 1 when timeout occurs

---------------------> (used with channels 0-7);
clear output pin to 0 when timeout occurs
(used with channels 0-7)
-------------------------- > Set to select timer 2 as time base;

clear to select timer 1 as time base;
> Not used
Fig. 21.29 Format of each CAM entry in the HSO unit
The 16 bits of each entry hold a value, which will be compared with the
content of either timer 1 or timer 2, every 2 ps. When a match occurs between a
CAM entry and the selected timer, the specified action is invoked and the entry is
automatically removed from the CAM.
The registers associated with the HSO unit are shown in Fig. 21.30.
While the HSO.O, HSO.l, HSO.2, and HSO.3 pins on the chip are permanently
dedicated to timer outputs, the HSO.4 and HSO.5 pins need not be wasted if the
six-timer output is not needed. Either of these two lines can serve as the timer
input. However, if we do want to use HSO.4 and/or HSO.5, we need to enable
these outputs in the IOC 1 register.
CAM is accessed through the HSO holding register shown in Fig. 21.31. Before
writing to the HSO holding register, we need to ensure that it is ready for an entry,
by checking bit 7 of IOSO as follows:
WAIT: JBS IOSO.7, WAIT
When the holding register is ready, the desired command is written to HSO-
command. Then the desired time is written to HSO time. To enter a command into
the CAM file, write the 7-bit command tag into the memory location 0006H. Then
write the time at which the action is to be carried out into the word address 0004H.
The typical code is as follows:
LDB HSO-COMMAND, #what-to-do
ADD HSO-TIME, TIMERI, #when-to-do-it
Upon writing the time value into the HSO time register, the HSO loading register
is initialized with the time and the command together. The command does not
actually enter the CAM file when an empty CAM register becomes available.
7 6 5 4 3 2 1 0
IOC1 (0016H) (write)
-> Set to enable use of HSO.4 output
■> Set to enable use of HSO.5 output
HSO command register

HSO-COMMAND (006H) (write)
HSO time register

HSO-TIME (0005H, 0004H) (write)
Writing to HSO-TIME loads the HSO holding

------------High speed outputs and software timer interrupt vectors register with this value, together with what has
previously been written to HSO-COMMAND
Fig. 21.30 Registers associated with the HSO unit

।_________________________________________ HSO-TIME_________
HSO holding register
Fig. 21.31 CAM HSO holding register
21.9.1 HSO Status

Before writing to HSO, it is desirable to ensure that the holding register is empty.
If it is not, writing to HSO overwrites the value in the holding register. IOSO
indicates the status of the HSO unit. If IOSO.6 equals 0, the holding register is
empty and at least one CAM register is also empty. If IOSO.7 equals 0, the holding
register is empty.
21.9.1.1 Clearing HSO
All eight CAM locations of the HSO are compared before any action is taken. This
allows a pending external event to be cancelled by simply writing the opposite
event to the CAM. However, once an entry is placed in the CAM, it cannot be
removed until either the specified timer matches the written value or the chip is
reset. For example, if a command has been issued to set HSO.l when timer 1 =
1234, entering a second command, which clears HSO.l when timer 1 = 1234,
results in no operation on HSO.l. Both commands remain in the CAM as long as
timer 1 = 1234.
21.10 MEMORY EXPANSION

The 8096 can be operated in either single-chip mode or multiplexed mode. In the
single chip mode, the internal memory alone is used, and the program and data
are within the chip itself. In the multiplexed mode, the external memory can be
interfaced with the chip using two of its ports as the address bus and the data bus.
21.10.1 Single-chip Mode

For the single-chip mode, the internal ROM
or EPROM must necessarily be accessed. This +5V EA 8096
choice is made by making the EA (external

access) pin of the 8096 high, as shown in
Fig. 21.32. When EA is tied high, the internal
ROM or EPROM is accessed during the Fig. 21.32 Single-chip mode
instruction and data fetches from addresses 2080H-3FFFH and the interrupt
vectors from the addresses 2000H-2011H.
21.10.2 Expanded Mode

In the expanded mode of operation of the chip, there are different choices. The first
choice is related to the use of the internal memory. The user can configure the 8096
chip in such a way that the internal ROM is used along with the external memory.
The user can also configure the chip such that the entire memory is outside the
chip and the internal memory is not used.
In the expanded mode shown in Figs 21.33 (a) and 21.33 (b), the internal ROM
or EPROM is accessed by making EA high. If the pin EA is tied high, there exists
the option of using the internal ROM or EPROM together with the external memory
and devices, using one of the bus structures. In this configuration, the internal ROM
or EPROM is accessed through addresses 2000H-2011H and 2080H-3FFFH. All
other accesses are made to the external memory. Alternatively, for ROM-less
chips, all access to off-chip memory can be made by tying the EA pin low.
Memory ready
Instruction fetch
Tie to +5V to use internal Address valid
ROM/EPROM tie to GND to +5 V/GND Read control
disable internal ROM or EPROM Write high control
Multiplexed bus
D READY __ « Memory ready

Sus Width |NST
1 —> Instruction fetch
+5 V/GND ADV o—> Address valid

EA 8096 pg o__ > Read control
AD15-AD8 o-^*- Upper byte of address (already latched)

o
AD7-AD0 < > Multiplexed bus
COB (2018H)
(b)
Fig. 21.33 (a) Expanded mode with 16-bit multiplexed bus; (b) Expanded mode with 8-bit
multiplexed bus
Another choice is for the use of the data bus width. The chip can be configured
to access the 16-bit data bus or the 8-bit data bus. The hardware connections for
these two choices are to be designed and made accordingly.
21.10.3 Choice of Bus Width

For access of the external memory, the bus width has to be selected. The external
memory can be accessed with eight or 16 data bits at a time. The data bus width is
either 8 bits or 16 bits. This width can be selected by two methods. When the 8096
comes out of reset, it reads the content of the address 2018H of the user ROM or
EPROM. This is called chip configuration byte (CCB). The data bus width can be
selected by a bit in the CCB. Another method of bus width selection is by using
a hardware signal, Buswidth. If the pin BUSWIDTH is given a voltage of logic
1, then a bus width of 16 bits is selected. If this pin is given a logic 0 voltage, an
8-bit data bus is assumed.
Chip configuration byte The chip configuration byte is an 8-bit register at the
address 2018H. The bit positions of CCB are defined in Fig. 21.34, and each bit
has its own function.
Set to 1 for compatibility with future parts

(reserved)
Bus width select
If set, then BUSWIDTH pin determines the bus
width. If cleared then external 8-bit data bus
is selected
Write strobe mode select
WR and BHE/WRL and WRH
Address valid strobe select
ALE/ADV
IRCO
Internal ready control mode
IRC 1
Program lock mode
Fig. 21.34 Chip configuration byte
Bit 1 of the CCB works with the external BUSWIDTH pin to determine the
data bus width. Note that bus width selection is necessary only when the EA pin is
tied low or when the external memory is accessed. While the BUSWIDTH pin is
tied either high or low, it can actually be changed during each bus cycle of normal
operation.
During 16-bit bus cycles, ports 3 and 4 contain the address multiplexed with
data, using address latch enable (ALE) to latch the address. In 8-bit bus cycles,
port 3 contains address multiplexed with data, while port 4 contains address
bits 8-15. The address bits on port 4 are valid throughout an 8-bit bus cycle.
Figure 21.35 shows the two options.
21.10.4 Bus Control Bus control Bus control

8096 ____ N 8096 _____ N
Using the chip configuration ____ > ____ >
V V
8-bit latched address high
register (CCR) or chip
Port 4
configuration byte (CCB), the
8096 can be made to provide bus Port 4 Port 3
control signals of several types. Port 3
16-bit multi 8-bit multiplexed address
Three control lines have dual 16-bit bus add/databus 8-bit bus low/data
functions designed to reduce the
external hardware. Bits 2 and 3 Fig. 21.35 Bus width options
of the CCR specify the functions
performed by these control lines. Table 21.11 indicates the control signals selected
for different combinations of the D2 and D3 bits of the CCR.
Table 21.11 Control signals based on the CCR
D3 D2 Control signals used
0 0 ADV, WRL, and WRH

0 1 ADV, WR, and BHE
1 0 WRL, WRH, and ALE
1 1 BHE, WR, and ALE
21.10.4.1 Standard Bus Control

If the CCR bits 2 and 3 are 1, the standard 8096 control signals WR, BHE, and
ALE are provided. As shown in Fig. 21.36, the WR signal is active for every write
operation; the BHE signal is valid throughout the bus cycle and can be combined
with WR and the address line 0, to form WRL and WRH. ALE rises when the
address is given out by the processor; it acts as a signal to externally latch the
address.
16-bit bus cycle 8-bit bus cycle

-T-M—J -4-1 • 1.1 ryjtuj r -TC - ?n ■' * ***** ' -r
Fig. 21.36 Standard bus
21.10.4.2 Wr/te Strobe Mode

The write strobe mode eliminates the necessity to externally decode odd or even
byte writes. If the CCR bit 2 is ‘0’ and the bus is in a 16-bit cycle, the WRL and
WRH signals are provided in place of WR and BHE, as shown in Fig. 21.37.
The WRL signal goes low for all byte writes to an even address and all word
writes. The WRH signal goes low for all byte writes to an odd address and all
word writes.
The write strobe mode is particularly well suited for the memory systems
latching data on the falling edge of the Write signal. The WRL signal is provided
for all 8-bit bus write cycles.
16-bit bus cycle o,u,

8-bit bus cycle
Fig. 21.37 Write strobe mode
21.10.4.3 Address Valid Strobe Mode

If the CCR bit 3 is 0, address valid strobe is provided in the place of ALE, as
shown in Fig. 21.38. When the address valid mode is selected, ADV goes low
after an external address is set up. It stays low until the end of the bus cycle, where
it goes inactive high. This can be used by ROM devices to provide a Chip Select
for a single external RAM device in a system containing a minimum number of
chips.
21.10.4.4 Address Valid with Write Strobe

If both the CCR bits 2 and 3 are 0, both the address valid and the write strobes are
provided for bus control, as shown in Fig. 21.39.
ADV ADV
WRL Valid WRL
16-bit bus cycle
Fig. 21.39 Address valid with write strobe mode
21.10.4.5 Ready control

To simplify ready control, four modes of internal ready control logic have been
provided. These modes are chosen by properly configuring bits 4 and 5 of the
CCR.
The internal ready control logic can be used to limit the number of wait states
that the devices can insert into the bus cycle. When the READY pin is pulled low,
wait states will be inserted into the bus cycle, until the READY pin goes high. The
number of wait states is limited to the number specified by the CCR bits 4 and 5.
Table 21.12 shows the number of wait states that can be selected. Internal ready
control can be disabled by loading 1 and 1 into bits 4 and 5 of the CCR.
21.10.5 ROM/EPROM Lock

Four modes of program memory Table 21.12 Internal ready control for the 8096
lock are available on the 8X9X
devices. CCR bits 6 and 7 (LOCO, IRC1 IRC0 Description
LOCI) indicate whether the internal 0 0 Limit to one wait state
program memory can be read from 0 1 Limit to two wait states
(or written to, in EPROM devices)
1 0 Limit to three wait states
by a program executing from the
external memory. The modes are 1 1 Disable internal read control
The internal ROM/EPROM addresses 2020H-3FFFH on the 8X9X are
protected from reads and writes, as set by the CCR.
It is only the code executing from internal memory that can read the protected
internal memory, whereas the write- Table 21.13 Program lock modes of the 8096
protected memory cannot be written
into, even by internal program LOC1 LOCO Protection
execution. 0 0 Read and write protected
Figure 21.40 shows the connection
0 1 Read protected
diagram for interfacing the 16K
memory with the 8096 using the 8-bit 1 0 Write protected
data bus. Port 3 acts as the multiplexed 1 1 No protection
lower-order address and data bus.
Fig. 21.40 Intel 8096 EPROM memory expansion with 8-bit external data bus
Figure 21.41 shows the hardware connections for interfacing the 16K memory
with the 8096. Ports 3 and 4 are used as the multiplexed address and data bus. To
access one 16-bit data item at a time, two memory chips are needed—one for the
lower-order eight bits and the other for the higher-order eight bits.
Figure 21.42 shows the 16-bit memory interfacing using four 16K memory
chips, of which two 8K chips are for the lower-order data and two 8K chips are for
the higher-order data.
Fig. 21.41 Intel 8096 EPROM memory expansion with 16-bit external data bus
8192 x 8 static CMOS RAM (150 ns access lime)
Fig. 21.42 Intel 8096 static RAM expansion

POINTS TO REMEMBER
• Intel 8096 has five parallel ports—port 0, 1,2, 3, and 4. The parallel port pins are
also shared with the other peripherals such as ADC, PWM, and timers. Port 1 is used
exclusively for input/output purposes.
• The special function registers control all the internal peripherals of the 8096
microcontroller.
• There are two 16-bit timers in the 8096 and they can be clocked internally or from
external sources.
• The 8096 has 21 sources of interrupts.
• The 8096 has a serial port that can be operated in one synchronous mode and three
asynchronous modes.
• The 8096 has an 8-channel ADC with 1 O-bit data output. The programmer can program
to convert one or four channels at a time.
• The PWM output of the 8096 can be used to get an analog output corresponding to the
digital data.
• The high speed input unit is used to record the time at which an input pulse appears.
• The high speed output unit can be programmed to give the desired output at a desired
time. ADC conversion can be initiated by programming the HSO unit.
• The 8096 has many bus structure options for interfacing the external memory with it.
KEYTERMS^
HSI pins These pins can be used to record the time at which an external event occurs.
HSO unit This unit is used to trigger events at specific times.
Input/output control register 1 (IOC1) This register is used to choose the functions of
select port 2 pins, and enable or disable some interrupt sources.
Input/output status register 0 (IOSO) IOSO holds the current status of the HSO lines
and CAM.
Interrupt mask register This register is used to enable or disable the individual
interrupts, by setting or clearing the bits in it.
Interrupt pending register This register holds ‘ 1 ’ for the detected interrupts.
Mode 1 This is the standard asynchronous communication mode in the serial port.
Mode 2 This is the asynchronous ninth bit recognition mode.
Mode 3 This is the asynchronous ninth bit mode.
Port 0 This is an input-only port.
Port 1 This can be used for input or output.
Port 2 This port has three types of port lines—input-only, output-only, and quasi-bi-
directional.
Program status word (PSW) This register is a collection of Boolean flags, which
contain information concerning the state of the user’s program.
Timer 1 This timer is used to synchronize events to real time.

Tinier 2 This timer can be clocked externally, and synchronizes events to external
occurrences.
Vector interrupt In this interrupt, each source of an interrupt leads directly to the code.
REVIEW QUESTIONS |
1. Write a note on port 2 and its functions.

2. Discuss timer configurations.
3. How will you reset timer 2?
4. Write about interrupt sources.
5. Tabulate the interrupt vector locations and their priority levels.
6. How will you determine the source of an interrupt?
7. Name the registers that control the interrupt system.
8. Give a brief note on PSW.
9. Explain the various modes of operation of the serial port.
10. How will you determine baud rate?
11. List the steps to be followed in analog to digital conversion.
12. What is PWM?
13. How are interrupts generated in the HSI unit?
14. Compare single-chip and expanded mode.
15. How will you make a bus selection?
16. What is ROM/EPROM lock?
Part 6
ADVANCED TRENDS
Chapter 22: Microprocessor System Developments

and Recent Trends
Chapter 23: Advanced Microprocessors and

Microcontrollers
CHAPTER 22]
MICROPROCESSOR SYSTEM
DEVELOPMENTS AND RECENT
TRENDS
LEARNING OUTCOMES
• Developments in the features and manufacturing of the microcontroller family
• Development tools used for microcontroller applications
• C cross compiler for the 8051 series microcontrollers
• Programming the 8051 microcontrollers in C language
22.1 INTRODUCTION
Different types of microprocessors and microcontrollers are commercially
available in the market. General-purpose microprocessors have been developed
and improved by manufacturers and are largely used in personal computers.
However, with the advent of very large-scale integration in IC fabrication and the
tremendous decrease in the cost of these devices, microcontrollers have almost
replaced microprocessors in most applications.
Embedded systems are electronic systems consisting of microcontrollers or
other dedicated processor chips, which perform specific tasks. Embedded systems
differ from generic PC systems, in that they are made for a specific application and
cannot be used or programmed for general applications. They are supported by a
wide array of processors and processor architectures that are usually cost-sensitive
and have real-time constraints. Microcontrollers are used in embedded systems
such as computer printers, plotters, fax machines, photocopiers, telephones, and
automotive engine control mechanisms, and in electronic instruments such as
oscilloscopes, multimeters, planimeters, and IC testers. They are also found in
domestic appliances such as washing machines, microwave ovens, iPods, and
other music systems. An advanced automobile has 25 or more microcontrollers
in different control applications. The market for microcontrollers is so large that
they occupy about 80% of all CPU market in the world. A typical home in a
developed country such as the United States is likely to have around three dozen
microcontrollers embedded in various appliances. This chapter is dedicated to the
introduction of microcontroller development tools and the latest developments in
microcontroller chips.
22.2 MICROCONTROLLER FEATURES AND DEVELOPMENTS

The number of IC manufacturers who have ventured into the microcontroller
market has increased multifold over the years. These manufacturers have produced
many versions of microcontrollers, to suit the application and requirements of
system developers.
Based on their architecture, microcontrollers may be classified into two
basic types—reduced instruction set computer (RISC) processors and complex
instruction set computer (CISC) processors. An RISC processor has fewer
instructions, with very fast execution. Almost all the instructions of RISC
processors are executed in a single clock cycle. A limited number of addressing
modes is used. RISC processors are used when there is a need for very lengthy and
intensive computations, such as speech processing and image processing. On the
other hand, CISC processors have many instructions and support many addressing
modes. They are comparatively slower in the execution of instructions.
Originally, microcontroller chips included erasable programmable read-only
memory (EPROM). These devices have a window on the top, through which
ultraviolet (UV) rays could be passed, to erase the program memory. After erasure,
the device is ready for reprogramming. The EPROM devices have the disadvantage
that they need UV light to erase their contents. This disadvantage was rectified
with the introduction of electrically erasable and programmable read-only memory
(EEPROM) devices and devices with flash memory. Both these devices provided
the advantage of electrical erasure and reuse of memory. Moreover, these devices
are cheaper to manufacture. Flash memory is a non-volatile electronic IC memory
that can be electrically erased and reprogrammed many times. It is a specific type
of EEPROM. Flash memory costs far less than byte-programmable EEPROM.
Therefore, it has become the dominant technology wherever a significant amount
of non-volatile, solid-state storage is needed.
Since embedded processors are used to control devices, they need to accept
input from the device they are controlling. These devices, in general, provide
an analog signal as output. This analog signal must be given as an input to the
processor, but the processor can handle only digital data. Hence, the conversion
of the analog data into digital form becomes inevitable and this is achieved by the
analog-to-digital converter. The analog-to-digital converter is used to convert the
incoming data into a form that the processor can recognize. Most microcontrollers
have analog-to-digital converters as an additional feature.
Microcontrollers designed specially for motor control applications have a
dedicated pulse width modulation (PWM) block. This block generates variable
frequency and variable width pulses, making it suitable to control power converters,
resistive loads, motors, etc., without using timers.
The 8031 microcontroller from Intel is the first and most basic IC in a series of
microcontrollers. The 8052 is closely related to the 8031, and has an additional 128
bytes of internal RAM, which are also indirectly addressable. The other versions
of the 8051 have increased the onboard ROM from 4K to 8K. They have an extra
timer, T2, and new associated special function registers (SFRs).
MICROPROCESSOR SYSTEM DEVELOPMENTS AND RECENT TRENDS 661
Initially, Intel was liberal in providing licenses to microcontroller manufacturers.

So, many semiconductor manufacturers started either manufacturing the 8031
devices or developing a new kind of microcontroller based on the 8031 core
architecture. Manufacturers modified the basic 8031 architecture and added many
new peripheral functions to make them attractive to the designers. To beat the
competition, manufacturers developed different microcontrollers with many
unique features. These parts are popularly known as 8031 derivatives. Philips
brought out more than 40-50 derivatives with a variety of I/O options, memory
combinations, and peripheral functions.
With the basic 8031 core, Philips manufactured microcontrollers with high
capacity program memory (up to 32K/64K) and patented FC interface bus,
8/10 bit analog-to-digital converters, CAN bus, capture and compare registers,
watch dog timer, PWM facilities, etc. More I/O ports (as many as eight ports),
an additional timer/counter, and a second serial port were also made available in
Philips devices. Dallas Semiconductor also has a range of secure microcontrollers
based on the 8031 core. This microcontroller family uses non-volatile RAM to
store both programs and data. This RAM enables the controller to provide the in-
system programming (ISP) capability. Dallas has combined the microcontroller,
the static RAM (SRAM), and the lithium cell in a single pack. This device
guarantees more than 10 years of data retention in the RAM area. Atmel applied
its expertise in flash memory technology on the basic 8031 core, and brought
out microcontrollers with a variety of flash memory options and a few devices
that carry the ISP facility. You can program/reprogram this microcontroller after
soldering the device on a target board.
22.3 MICROPROCESSOR DEVELOPMENT SYSTEMS

A microprocessor development board is a circuit board containing a
microprocessor and the minimal support logic needed to become acquainted with
the microprocessor on the board. The development board provides a system for
learning to use and program a new microprocessor. Many microprocessor training
development kits are produced by both microprocessor manufacturers and third
parties. The development boards have expansion connectors that connect to all
the necessary CPU signals, so that an engineer can build and test an experimental
interface or any other electronic device. Today some manufacturers still bring out
‘test boards’, to demonstrate their chips and also use them as a reference design.
The development system contains elements for input pin activation and output
pin monitoring. The simplest version has every port pin connected to one push
button and one LED. A high-end version of the development boards has LED
displays, LCD displays, temperature sensors, and several other elements, which
can be supplied with the target device. These peripherals can be connected to the
microcontroller via miniature jumpers. In this way, the whole program may be
tested during its development stage.
The most important feature of the microprocessor development board supplied
by the manufacturers is the integrated development environment (IDE) software
with a basic debugger and other related features. IDE is basically front-end software
that integrates an editor, debugger, emulator, and downloader, along with features
such as animation and visualization. In general, most IDE softwares have two
modes—the build mode and the run/debug mode. The build mode supports source
code creation and revision. All the project, module, and edit functions are enabled
in this mode. The run/debug mode facilitates code execution and debugging.
Project management and source code editing functions are disabled. Commands
such as run, single step, set/clear breakpoints, and watch variables are enabled
only in this mode.
22.3.1 In-system Programming

In-system programming (ISP) is the ability of the microcontroller to be programmed
when installed in a complete system or development board. This feature avoids the
need to program the chip prior to its installation in the system or board. The primary
advantage of this feature is that it allows users to program the chips themselves,
making it feasible to apply code or design changes at any time.
Typically, chips supporting ISP have internal circuitry to support programming
of the internal RAM, using communication with the IDE via a serial protocol.
Most programmable logic devices need either the JTAG (Joint Test Action Group)
protocol or the USB (universal serial bus) port for ISP.
22.3.2 Debugger
A debugger is a software supported by IDE and is used to test run and debug the
user-written programs. The application code developed by the programmers can
be examined by running or executing the code on an instruction set simulator
(ISS). The debugger allows the user to halt the program simulation when specific
conditions are encountered. For example, a program may have errors and may crash
and as a result, the program cannot be executed any further. When the program
crashes, the debugger shows the position of the bug in the program code. Typical
debuggers offer more sophisticated functions such as running a program step by
step (single-stepping) and stopping (breaking) the program at user-defined points.
These break points are useful to the programmer to examine the current state of the
variables and data at that point in the program. Some debuggers have the ability
to modify the state of the program while it is running, rather than merely examine
it. A good debugger is very important and almost all microcontroller chip vendors
offer a debugger for the program developers. The availability of a good debugger
decides the selection of a specific microcontroller chip for an application.
22.3.3 Emulator
An emulator is another tool available in IDE to duplicate the functions of a
microcontroller system. Emulation refers to the ability of a computer program or
an electronic device to imitate another program or device. It makes the software
believe that the real device is running the software. A hardware emulator is an
emulator that takes the form of a hardware device.
An in-circuit emulator (ICE) is a hardware device that is used to debug the
software of an embedded system. It is usually in the form of a processor board
that has many internal signals brought out for the purpose of debugging. These
signals provide information about the state of the processor. In-circuit emulation
can also refer to the use of hardware emulation, where the emulator is plugged into
a system in place of a yet-to-be-built chip. The ICE allows the software element to
be run and tested on the actual hardware on which it is to be run, but still allows
single-stepping and isolation of faulty code. Recent ICEs enable a programmer
to access the on-chip debug circuit that is integrated into the CPU via JTAG, to
debug the software of an embedded system. They are sometimes called in-circuit
debuggers (ICDs). The ICE emulates the CPU. From the system’s point of view,
it has a real processor fitted, but from the programmer’s point of view, the system
being tested is under full control, allowing the developer to load, debug, and test
the code directly.
22.4 CROSS COMPILER FOR 8051

Microcontrollers were originally programmed only in assembly language, but
various high-level programming languages are also in common use now. The
following problems are encountered when an assembly language is used for
project development in a microcontroller-based system.
(i) The programmer is expected to have complete knowledge of all the
mnemonics and their meanings. The mnemonics are difficult to remember.
(ii) The assembly language programs developed for one microcontroller cannot
be used for another microcontroller. The project has to be redone again
from the beginning.
(iii) The assembly language programs are usually not easily understood by those
who are not part of the programming team.
The advantages of using high-level languages for embedded programming
or microcontroller programming are better readability, portability, and ease
of rewriting and development. However, assembly language programming is
advantageous for those routines where internal port-specific and ALU-specific
operations are carried out. It is common practice to use assembly language for
such critical sections and high-level language for the other sections.
Figures 22.1 (a) and 22.1 (b) show the different steps in the compilation of a
C program, starting from program development. The programmer usually edits and
compiles the embedded system's code on the host system. The host system has special
compilers that produce executable code for the embedded system. These are called
cross compilers and cross assemblers. Compilers for general-purpose languages
typically have some restrictions; however, they also have some enhancements
to provide better support to the unique characteristics of microcontrollers. Some
microcontrollers have environments to aid the development of certain types of
applications. Microcontroller vendors often make tools available for free, to make
it easier to adopt their hardware. Many microcontrollers require their own non
standard dialects of C, such as the SDCC compiler for the 8051, which prevents
the usage of standard tools (such as code libraries or static analysis tools). Recent
microcontrollers are often integrated with an on-chip debug circuitry, which when
accessed by an ICE, allows debugging of the firmware with a debugger. The

cross compiler is used to convert the high-level language into the corresponding
assembly language. The assembler converts the assembly language program into
machine language. The linker links all the files related to the project development
and creates a single executable hex file. This file is then downloaded onto the
target microcontroller system using the serial port of the host system.
Host system
Writing a program, Target system
compiling, and Downloading with the
linking to create machine code microcontroller
machine code to the target, via
Microcontroller in
real application
Fig. 22.1 (a) Microcontroller-based system development (b) Steps in microcontroller

programming
22.5 PROGRAMMING 8051 IN C LANGUAGE

In this section, it is assumed that the reader has sufficient knowledge of
C programming. As most 8051-based microcontrollers have flash memory, these
devices support in-system programming. The software used for ISP comes with
IDE, which helps programming in a high-level language. Most C compilers for the
8051 support data types such as bit, signed char/unsigned char, signed/unsigned
short int, signed/unsigned int, signed/unsigned long int, float, sfr, and sfrl6. The
number of bytes allotted or the range of each data type can be found from the
technical specifications of the C compiler being used.
In general, embedded system programming in microcontrollers follows this
program structure:
main()
{
Initialize the variables and get ready to run the program;
while(l)
The rest of the program is here;

}
return 0;
1
The main program has a starting point, mostly does not have an end point, and
always runs in a continuous loop. So the syntax, ‘while(l) ’ is used in all programs,
resulting in an indefinite loop. The main program can call other functions and
routines, but should never end. Some programming examples are given in this
section.
Example:
Write a C program to read the status of the switches on the port 3 lines and display
them on the LEDs connected to the port 1 lines. Use the hardware interface diagram
shown in Fig. 22.2.
The C program for the example follows:

#include <8051.h>
void main(void)
unsigned int a;
P3 = OXFF;
whi1e(1)
A = P3;
Pl = A;
The program uses a header file, 805l.h. This file contains information about the
processor registers and special function registers. For example, ‘Pl’ is assigned to
point to port 1 through its port address in the SFR area. The variable ‘A’ is used to
temporarily store the data read from port 3 and then pass it on to port 1. Port 3 is
defined as an input port by writing all Is (OXFF) to it.
Example:
Write a C program to turn on alternate LEDs after a fixed time delay. Use the
hardware interface diagram shown in Fig. 22.2 and assume that the LEDs are
connected to the port 1 lines.
The C program for the example follows.
//include <8051.h>
voi d del ay ()
Uns1gned inti;
for (i = 0; i < 10000; i++);
1
void main(void)
whi led)
Pl = 01010101B; //Turn alternate LEDs on.

delay(); //Call the delay function.
Pl = 1P1; //Complement the port 1 pins.
delay(); //Call the delay function.
)
This program uses the bit data 01010101 to turn on alternate LEDs. The delay
routine is written as a separate function and is called from the main function. The
count value, 10,000, can be changed to change the delay.
Example:
Write a C program to scroll the lighting of the LEDs for the interface diagram
shown in Fig. 22.2.
The C program for the example follows:
//include <8051. h>
void main(void)
int i; // Define the integer.

int Nl; // Define the integer for assigning the hex number.
while(l)
Nl = 0X01;
while (Nl! = 0x00) // Routine for scrolling interval.
ford = 1; i < 10000; 1++); //Delay routine.

PO = Nl; //Light the LED correspond!ng
to Nl.
Nl = Nl >> 1; //Shift right by one.
Example:
Write a C program to count from 0 to 9 in the seven-segment display connected to
the port 1 pins, with a one second delay. Assume the connection diagram shown
in Fig- 22.3.
Fig. 22.3 Interfacing of seven-segment display with the 8051
Table 22.1 shows the display data for the interfacing diagram shown in Fig. 22.3.
Table 22.1 LED segments and display data for the interface diagram 22.3
D7 D6 D5 D4 D3 D2 D1 DO Data for
Decimal
number f e d c b a
display (hex)
dP g
0 0 0 1 1 1 1 1 1 3F
1 0 0 1 1 0 0 0 0 30
2 0 1 0 1 1 0 1 1 5B
3 0 1 0 0 1 1 1 1 4F
0 1 1 0 0 1 1 0 66
4
0 1 1 0 1 1 0 1 6D
5
0 1 1 1 1 1 0 1 7D
6
0 0 0 0 0 1 1 1 07
7
0 1 1 1 1 1 1 1 7F
8
0 1 1 0 1 1 1 1 6F
9
The LSB of port 1 is connected to the ‘a’ segment and the MSB is connected to the
decimal point. The program shown uses a delay routine with a delay count. The
count used here is 33,000, but this count value has to be checked and changed for
different systems, clock frequencies, and compilers. A dummy ‘for’ loop is used to
achieve this delay. The data for display is stored in the disp_data array. This data
is taken from Table 22.1. The ‘disp’ count is incremented and the corresponding
display data is taken from the array and then passed to the port 1 pins. The counter
is reset to 0 when the count exceeds 9.
The C program routine follows:

//include <8051.h>
//define count 33000
vold del ay ()
Unsigned int i ;
for (i = 0; i < count; 1++) ;
main ( )
unsigned int disp = 0; //Initialize display to 0

unsigned int disp_data(10) = {0X3F, 0X30, 0X5B, 0X4F, 0X66, 0X6D,
0X7D, 0X07, 0X7F, 0X6F} ;
whi1e(1)
Pl = disp_data(disp); //Get display code from the array and

send it to port 1.
del ay(): // Wait for a particular delay period.
d i s p++; // Increment the display count.
if (disp == 10) disp = 0; // If count is more than 9, reset to 0.
Example:
Energy efficient lighting using a microcontroller.
The lighting in a house is automated using infra red (IR) sensors and a
microcontroller. With a microcontroller-controlled switching of lights, an energy
saving of 50% can be achieved. IR sensors are placed at the entrance to each
room. Whenever a person enters the room, the light in the room is automatically
turned on. Similarly, when a person leaves the room, the light is switched off. The
hardware circuit using the IR sensors, the microcontroller, and the relays is shown
in Fig. 22.4. Write a C program for the interface diagram shown in the figure, to
achieve efficient working of the system.
The system uses many arrays of IR LED and phototransistor pairs throughout
the house. They are placed at the entrance to the rooms or in the corridors. The IR
LEDs emit IR rays continuously. The corresponding IR phototransistors are placed
Fig. 22.4 Circuit diagram for automatic switching of lights
such that they receive the IR rays after reflection. The value of the resistance
connected to the collector of the phototransistor decides its sensitivity. When the
IR link between the IR LED and the transistor breaks due to a person passing
through the door, a low to high transition takes place at the transistor collector and
this is detected by the port 0 lines. The corresponding bulbs connected to port 1
are turned on or off.
The program given assumes that the absence of an IR signal from the IR detector
indicates whether a person enters or leaves the room. This means that the relay
switching is complemented upon receipt of every signal from the IR sensor. If the
relay has turned on the light, upon receipt of the next IR sensor signal, the light is
turned off. This system can be improved by introducing one more sensor at each
entrance to detect the direction of the person passing through (i.e., whether he/she
is entering or leaving the room). Accordingly, the program has to be changed.
//include <8051.h> // Special function register declaration

// Output from the IR sensors is connected to the port pins of
port 0.
sbit sensorl = P0A0:
sbi t sensor2 = POA1;
sbit sensor3 = P0A2;

sbit sensor? = P0A6:
sbit sensorS = P0A7;
// Connecting the relays to port 1 to switch on/switch off the power
to the port.
sbit RL1 = Pl A0;
sbit RL2 = Pl A1 ;
sbit RL3 = Pl A2;
sbi t RL4 = Pl A3;
sbit RL5 = Pl A4;
sbit RL6 = PlA5 ;
sbit RL7 = Pl A6:
sbit RL8 = Pl A7 ;
void mai n (void) // Main function
P0 = 0X00;
Pl = 0X00;
while (1)
if (sensorl == 1)
ll Check the first sensor’s current
state.
RL1 = ~RL1;
// If its state is high, switch the
relay from on to off and off
to on.
else if (sensor2
!! Otherwise, check the second sensor.
RL2 = ~RL2;
el sei f ( sensor3 ===== j )
RL3 = ~RL3;
el sei f ( sensor4 =====

1
RL4 = ~RL4;
)
elseif (sensor5 =====
1
RL5 = ~RL5;
)
elseif ( sensor6 ===== )
I
RL6 = ~RL6;
elseif (sensor? == 1)
I
RL7 = ~RL7;
elseif (sensor8 == 1)
RL8 = ~RL8;
1
These programs are only indicative of the use of C language used for
programming 8051-based microcontrollers. Different C compilers have their
own syntax and the readers are requested to go through the manual of the
C compiler used by them. There are several compiling options for the programmer.
The programmer must be aware of all the options of the compiler, linker, and
optimizer.
POINTS TO REMEMBER^
• The recent developments in the microcontroller hardware include several additional

features such as flash memory, additional timers, watchdog timers, and data
converters.
• The IDE is a software that includes an editor, a compiler, a debugger, and a downloader
or programmer. It is supplied by the chip manufacturers and also available with third
party vendors.
• Embedded C programming or any high-level language programming of microcontrollers
has become very common, with the availability of many cross compilers and IDE
tools.
REVIEW QUESTIONS
1. Write a program in C for the control of a stepper motor using the 8051 microcontroller.
Assume relevant hardware interfacing.
2. Write a program in C for a real-time clock with hours and minutes display, using seven
segment displays interfaced to the 8051 microcontroller.
CHAPTER 23 1
ADVANCED MICROPROCESSORS
AND MICROCONTROLLERS
LEARNING OUTCOMES
• Architecture of the Intel 80186, 80286, 80386, 80486, and Pentium
• Protected mode operation in all microprocessors from the 80286 to the Pentium
• Paging mechanism present in all microprocessors from the 80386 to the Pentium
• Integer and floating-point pipeline operation in the Pentium
• Different versions of the Pentium microprocessor
• Hardware features of the PIC16F877 microcontroller and its family
23.1 INTRODUCTION
After the release of the 8086, Intel introduced the 80186, which is a 16-bit processor
having an architecture identical to that of the 8086. In addition, the 80186 has more
built-in hardware units, such as three timers, two DMA controllers, one interrupt
controller, and peripheral- and memory-select logic.
After the 80186, Intel released the 80286, which is also a 16-bit processor. In the
80286, Intel introduced protected mode addressing, also known as protected virtual
address mode (PVAM), which is an important milestone in the development of the
Intel X86 family. The concepts of four-level protection mechanism, descriptors,
and descriptor tables, the use of selectors, interrupt gates, and task management
were first introduced in the 80286. The 80286 processor can access 16 MB of
memory, as it has 24 address lines. The 80286 uses the numeric coprocessor 80287
for performing floating point operations.
After the 80286, Intel released the 80386, which was Intel’s first 32-bit
microprocessor. Most of the registers in the 80386 are 32 bits wide. The address
bus and data bus are also 32 bits wide. The 80386 processor can access 4 GB (1G
= 230) of memory, as it has a 32-bit address bus. The paging mechanism was first
introduced in the 80386, to efficiently handle virtual memory. The 80386 uses the
numeric coprocessor 80387 for performing floating-point operations.
After the 80386, Intel released the 80486, which is also a 32-bit microprocessor.
Most of the registers in the 80486 are 32-bits wide. The address bus and data bus
are also 32 bits wide. In addition, the 80486 has an on-chip Floating Point Unit
(FPU) and 8 KB of on-chip unified cache (both code and data are present in the
same cache). There is no need for a coprocessor in the 80486-based systems, due
to the inclusion of the FPU in the 80486 chip itself. The presence of cache memory
within the 80486 chip reduces the program execution time.
ADVANCED MICROPROCESSORS AND MICROCONTROLLERS 673
After the 80486, Intel released the Pentium, which was Intel’s first two-issue
superscalar processor (i.e., two instructions that process integer type data can be
simultaneously decoded and executed in its U and V integer pipelines, when certain
conditions are satisfied). The Pentium has 8 KB on-chip dual cache (8 KB code
cache and 8 KB data cache) and on-chip FPU, which uses an eight-stage floating
point pipeline. The Pentium has a 64-bit data bus and a 32-bit address bus. Since the
demand for embedded applications is increasing, the number of microcontrollers
with more on-chip peripherals introduced in the market is also increasing day by
day. The PIC16F877 is one such microcontroller and is a product of Microchip
Corporation. The architecture and salient features of the microprocessors from the
80186 to the Pentium, and the features of the PIC16F877 are explained in Sections
23.2-23.8.
23.2 80186 MICROPROCESSOR

As mentioned in Section 23.1, the 80186 is a 16-bit processor whose architecture
is identical to that of the 8086. The 80186 has more on-chip peripherals such as
three timers, two DMA controllers, one interrupt controller, and peripheral- and
memory-select logic. The features of the 80186 are explained in this section.
23.2.1 Architecture
The 80186 is a highly integrated 68-pin chip, which includes a CPU with
architecture identical to that of the 8086. The 80186 is available in 6, 8, 12, 16,
and 25 MHz versions. The functional block diagram of the 80186 is shown in
Fig. 23.1.
The 80186 processor includes the following subsystems:
(i) Clock generator
(ii) Programmable interrupt controller
(iii) Three 16-bit programmable timers/counters
(iv) Two programmable DMA controllers
(v) Chip select unit
(vi) Programmable control registers
(vii) Bus interface unit
(viii) Six-byte prefetch queue
The two-channel DMA unit of the 80186 performs transfers to or from any
combination of the FO space and memory space in either byte or word units. Each
DMA channel maintains independent source and destination pointers, which are
used to access the source and destination of the transferred data. The 80186 timer
unit contains three independent 16-bit timers/counters. Two of these timers can be
used to count external events, provide waveforms derived from either the CPU or
an external clock, or interrupt the CPU after a specified number of timer events.
The third timer counts only CPU clock cycles and can be used to interrupt the CPU
after a certain number of CPU clocks, give a count pulse to either or both of the
other two timers, or give a DMA request pulse to the integrated DMA unit, after a
programmable number of CPU clock cycles.
INT3/INTA1
The 80186 interrupt controller processes the interrupt requests from all the
internal and external sources. It can be directly cascaded as the master to two
external 8259As (programmable interrupt controllers). The 80186 integrated chip
select logic can be used to enable the memory or peripheral devices. Six output lines
from the integrated chip select logic are used for memory addressing and seven
output lines are used for peripheral device addressing. The integrated peripheral
and chip select circuitry is controlled by sets of 16-bit registers, accessed using
standard input, output, and memory access instructions. These peripheral control
registers are all located within a 256-byte block, which can be placed in either the
memory or the I/O space.
23.2.2 Instruction Set of 80186

The 80186 includes all the instructions of the 8086. In addition, a few new
instructions such as BOUND, ENTER, LEAVE, INS, OUTS are introduced in
the 80186. Some of the 8086 instructions have been given additional features, as
follows:
(i) PUSH n—Push an immediate value n onto the stack
(ii) PUSHA—Push all the registers onto the stack, in the order AX, CX, DX,
BX, SP, BP, SI, and DI
(iii) POPA—Pop all the registers from the stack, in the order DI, SI, BP, SP,
BX, DX, CX, and AX
(iv) IMUL n—Multiply by an immediate value zz; shift/rotate a register or

memory content by an immediate value

From the 80286 onwards, Intel introduced the concept of protected mode
addressing, also known as protected virtual address mode (PVAM). The concepts
of four-level protection mechanism, descriptors and descriptor tables, and task
management were first introduced in the 80286. The features of the 80286 are
explained in this section.
23.3.1 Architecture
The functional block diagram of the 80286 is shown in Fig. 23.2.
Address unit (AU) Address latches

Physical and drivers
Processor ->■ PEACK
Prefetcher extension
Segment adder — PEREQ
interface —READY, HOLD
bases
Segment Bus control S1,S0, INTA,
limit Segment Data > LOCK, HLDA
checker sizes transreceivers ^>015-00
6-byte
prefetch
ALU queue Bus unit (BU)
3 decoded
Registers Control instruction Instruction Instruction
Execution unit (EU) queue decoder unit(IU)
BUSY
INTR ERROR
There are four separate processing units in the 80286—bus unit (BU), instruction
unit (IU), execution unit (EU), and address unit (AU).
(i) The execution unit includes the ALU, general registers (which are the same
as in the 8086 and the 80186), and the control unit. The execution unit uses
its 16-bit ALU to execute instructions that are received from the instruction
unit.
(ii) The address unit includes the segment registers (which are the same as in
the 8086 and the 80186), an offset adder, and a physical address adder. The
address unit in the 80286 computes the physical addresses that will be sent
out to the memory or the I/O devices by the bus unit.
(iii) The bus unit includes the address latches and data transceivers, bus interface
and control circuitry, instruction prefetcher, and a six-byte instruction queue.
The bus unit performs all memory and I/O reads and writes, prefetches
instruction bytes, and controls the transfer of data to and from processor
extension devices such as the 80287.
(iv) The instruction unit includes an instruction decoder and a queue having
three decoded instructions. The instruction unit fully decodes up to three
prefetched instructions and holds them in a queue, where the execution unit
can access them.
23.3.2 Register Organization and Real or Protected Addressing in 80286

The 80286 register set is the same as that of the 8086, except for the addition of
a 16-bit machine status word (MSW) register and memory management registers
such as global descriptor table register (GDTR), local descriptor table register
(LDTR), task register (TR), and interrupt descriptor table register (IDTR). The
80286 can operate in any one of two address modes at any time—real address
mode or protected virtual address mode (PVAM).
When the 80286 is operating in the real address mode, the address unit computes
addresses using a segment base in a segment register and an offset, which is in a
register or in the instruction itself as a displacement, just as the 8086 does. The
CS, DS, SS, and ES registers are used to hold the base address for the segments
currently in use. The maximum physical address space in the real address mode is
1 MB, as in the 8086. After reset, the 80286 is configured in the real address mode.
It can be switched to the protected mode by setting the PE (protection enable) bit
in the MSW register and executing an intersegment jump instruction to the start of
the main system program.
When the 80286 is operating in the PVAM mode (simply called protected
mode), the address unit functions as a complete memory management unit
(MMU). In this mode, the 80286 uses all the 24 address lines to access up to 16
MB of physical memory. In the protected mode, the address unit also provides up
to 1 GB of virtual memory using descriptor tables. The virtual memory is managed
by the MMU in the 80286. When we write an assembly language program, we
usually refer to addresses by name. The addresses with which we work within a
program are called logical addresses or virtual addresses. Consider the instruction
JZ CHECK written in an 8086 program. The label CHECK in the JZ CHECK
instruction represents a logical address to which the execution will be transferred,
if the zero flag is set. When this 8086 program is assembled, the logical address of
CHECK is represented with a 16-bit offset and a 16-bit segment base. The 8086
bus interface unit then produces the actual physical memory address, by using
these two parts, to access the location CHECK.
When a program is assembled or compiled to run on a system with an MMU,
such as the 80286 in protected mode, each logical address or virtual address is also
represented by two components. In a segment-oriented system such as the 80286,
the upper 16-bit component of the logical address is referred to as a segment
selector, which is in a segment register, and the lower component of the logical
address is referred to as the offset, which is in a register or in the instruction itself
as a displacement, as shown in Fig. 23.3. The MMU uses the segment selector
to access a segment descriptor for the desired segment, from a table of segment
descriptors (GDT or LDT) present in the memory. A segment descriptor is an eight
byte entry that contains the physical base address for a segment (base address in
the physical memory such as RAM or ROM in the system), the privilege level of
the segment, and some control bits related to the segment. By adding the physical
1
base address of the segment present in the segment descriptor with the offset in the
logical address, the physical memory address is obtained, from where instruction
or data is transferred by the microprocessor, as shown in Fig. 23.3.
Fig. 23.3 Virtual to physical address conversion in the 80286 in protected mode
The different fields present in the 80286 segment descriptor are shown in
Fig. 23.4. The base (B23-B0) field represents the 24-bit base address of a segment
in the memory and hence, a segment can begin at any location in its 16 MB of
memory. The limit field (L15-L0) represents the last offset address found in a
segment. For example, if a segment starts at the memory location 800000H and
ends at the location 800F00H, the base field of that segment descriptor contains
800000H and the limit field contains 0F00H. The size of a segment can be between
1 byte and 64 KB in the 80286.
Byte no. <— 8 bits —> <— 8 bits —> Byte no.
7 OOH OOH 6
5 Access rights Base (B23-B16) 4
3 Base (B15-B0) 2
1 Limit (L15-L0) 0
Fig. 23.4 The 80286 segment descriptor
The access rights byte in the segment descriptor, which is shown in Table 23.1,
indicates the complete characteristics of a segment. The privilege level of the
segment is encoded in the descriptor privilege level (DPL) bits. Information about
whether the segment is currently present in the physical memory or not is encoded
in the P bit. Information about whether the segment described by the segment
descriptor is code, a data segment, or a system segment (call gate or task segment)
is encoded in the S bit. Information about whether the segment is accessed by the
CPU or not is encoded in the A bit of the segment descriptor. For code segment or
data/stack segment, some more details are encoded in the bits E, ED/C, and W/R
in the segment descriptor.
Table 23.1 Access rights byte in the segment descriptor
Bit Name Function

position
7 Present (P) P = 1 Segment is mapped into physical memory
P = 0 No mapping to physical memory exits, base
and limit are not used.
6-5 Descriptor privilege Segment privilege attribute used in privilege tests.
level (DPL)
4 Segment descriptor S = 1 Code or data (includes stack) segment descriptor
(S)
S = 0 System segment descriptor of gate descriptor.
If Data segment (S = 1, E = ( »
3 Executable (E) E = 0 Descriptor type is data segment
2 Expansion direction ED = 0 Expand up segment, offsets must be < limit.
(ED) ED = 1 Expand down segment, offsets must be > limit.
W = 0 Data segment may not be written into.
W = 1 Data segment may be written into.
If Code segment (S = 1, E = 1)
3 Executable (E) E=1 Descriptor type is code segment:
2 Conforming (C) C= 1 Code segment may only be executed when CPL
> DPL and CPL remain unchanged
1 Readable (R) R=0 Code segment may not be read.
R= 1 Code segment may be read
0 Accessed (A) A = 0 Segment has not been accessed.
A = 1 Segment selector has been loaded into segment
register or used by selector test instructions.
In the protected mode operation of the 80286, the selector, which is located in
the segment register (CS, DS, SS, and ES) selects one of the segment descriptors,
either from the global descriptor table (GDT) or the local descriptor table (LDT).
The GDT contains global descriptors, which are segment descriptors of those
segments (that belong to the compiler, assembler, etc.) that can be used by all
programs in a multi-user system. There will be only one GDT in the system. The
LDT contains segment descriptors of those segments that belong to a particular
user or task. In a multi-user or multitasking environment, there will be as many
LDTs as the number of users or the number of tasks handled by the CPU. Since
GDT and LDT can contain a maximum of 8192 descriptors each, a total of 16,384
descriptors are available for an application (i.e., a task or a user) at any time. Since
the maximum size of a segment is 64 KB in the 80286, the maximum size of the
virtual memory available for a particular user or task is equal to 1 GB (= 16,384
x 64 KB).
Figure 23.5 shows the functioning of the 80286 segment register in the
protected mode. The upper 13 bits in the segment register are known as index-, it
selects one of the descriptors from among a maximum of 8192 descriptors present
in either the GDT or the LDT. The TI bit is known as table indicator. If TI = 0,
the 80286 refers to the GDT to select a descriptor, and if TI = I, the 80286 refers
to the LDT to select a descriptor. The two least significant bits of the 80286 form
the requestor privilege level (RPL), where 00 is the highest privilege level and 11
is the lowest privilege level. The RPL bits reflect the privilege level of the task
requesting memory access.
Selector
23.3.3 Privilege Levels in Protected Mode of Operation

There are four levels of protection, called privilege levels (PL), in the 80286. They
are designed to support the needs of a multitasking operating system (OS), and to
isolate and protect user programs from each other and the OS from unauthorized
access. The privilege levels control the use of privileged instructions and I/O
instructions, and access to segments and segment descriptors. The four levels of
protection present in the 80286 are shown in Fig. 23.6.
The PLs are numbered 0, 1, 2, and 3. Level 0 is the most privileged level
and is used for the OS kernel. Level 1 is used for system services and level 2
for OS extensions. Level 3 is the least privileged level, which is used for regular
user applications. The 80286 architecture controls access to both data and code
between levels of a task, according to the following rules of privilege:
(i) Data stored in a segment with PL = m can be accessed only by code
(program) executing at a PL at least as privileged as m. For example, a data
Fig. 23.6 Four-level protection in the 80286
segment having PL = 02, can be accessed only by code executing at a PL =

00, 01, or 02.
(ii) A procedure in a code segment with PL = m can be called only by a task
(i.e., another program present in some other code segment) executing at the
same or a lower PL (more privilege) than m. For example, a procedure in a
code segment with PL = 01, can be called only by a task executing at a PL
= 01 or 00.
The privilege levels (PLs) are classified into four categories in the 80286.
(i) Descriptor privilege level (DPL) is the least PL at which a task may access a
descriptor and the segment associated with that descriptor. It is determined
by bits 6 and 5 in the access rights byte of a descriptor.
(ii) Requestor privilege level (RPL) is the PL of the original supplier of
the selector in the segment register. RPL is determined by the two least
significant bits of the segment register.
(iii) Current privilege level (CPL) is the PL at which a task is currently executing,
which equals the PL of the code segment being executed. The CPL is stored
in the two LSBs of the CS register, except for conforming code segments.
(iv) Effective privilege level (EPL) is the least privileged of RPL and CPL.
Since the largest PL number represents the least privilege level, EPL = max
(RPL, CPL).
A conforming code segment has no inherent fixed PL; it conforms to the PL of

the code segment that calls the conforming code segment or to the PL of the code
segment from where the microprocessor has made a jump to the conforming code
segment. For example, if a program with PL = 2 transfers control to a conforming
code segment, the conforming code runs with CPL = 2. A conforming code segment
can be executed and shared by programs at different PLs. The RPL bits of the CS
register are not changed when the execution of a conforming code segment starts;
they reflect the RPL bits of the previous code segment executed. The following
inequality is to be satisfied before the execution of a conforming code segment:
DPL of conforming code segment descriptor < current CPL
It means that control can be transferred only to the same level or up to a more
privileged segment. Control can never be transferred to a segment whose DPL is
greater in value (less privileged) than the privilege level of the current segment.
23.3.4 Descriptor Cache or Program-invisible Registers

Each of the segment registers contains a program-invisible register, also known
as descriptor register, used in the protected mode. Figure 23.7 shows program
invisible registers in the 80286. When a new segment number is placed in a
segment register, the microprocessor accesses either the LDT or the GDT to select
a segment descriptor and loads the segment descriptor copy into the program
invisible register corresponding to that segment register. It is held there and used
to access the memory segment, until the segment number is again changed. This
allows the microprocessor to access a memory segment quickly, without referring
back to the descriptor table for each memory access. The LDTR and TR also have
corresponding descriptor cache registers.
Segment registers Descriptor registers loaded automatically

t-
15 0 Physical base address Segment limit Other segment attributes from descriptor
Selector CS —
Selector SS — —
Selector DS — — — £
Selector ES — — —
Fig. 23.7 Segment and descriptor registers
23.3.5 Accessing Memory using GDT and LDT

The GDTR contains the base address of the GDT and its limit. The limit of the
descriptor table is 16 bits because the maximum table length is 64 KB. When
protected mode operation is desired, the base address of the GDT and its limit are
loaded into the GDTR. The location of the LDT is selected from the GDT. There
may be many LDTs in the memory at a time, depending on the number of tasks
executed by the processor, and each LDT has a corresponding descriptor called
LDT descriptor. One of the descriptors in the GDT is set up to address a particular
LDT. To access a particular LDT, the local description table register (LDTR) is
loaded with a selector. This selector accesses the GDT to select a LDT descriptor
and loads the base address, limit, and the access rights of the LDT descriptor into
the cache portion of the LDTR. The selection of an operand from the memory by
the microprocessor, using GDT, is shown in Fig. 23.8.
Handling of interrupts by the processor in the protected mode is discussed

here. The processor can handle a maximum of 256 interrupts. For each interrupt,
there is an interrupt descriptor, which is an eight-byte entry that contains a 16-
bit selector to locate the target code segment. This contains the interrupt service
routine (ISR) and a 16-bit offset, which is added to the base address of the target
code segment to get the starting address of the ISR. The interrupt descriptor for
each interrupt type, starting from the interrupt type OOH, are successively stored in
the interrupt descriptor table (IDT) present in the memory, and the base address of
the IDT is specified by the interrupt descriptor table register (IDTR). Whenever an
interrupt is received, the processor selects an interrupt descriptor corresponding to
the received interrupt from the IDT and goes to execute the ISR. Before using the
protected mode, the IDT and the IDTR must be initialized.
The selection of an operand from the memory by the microprocessor, using
LDT, is shown in Fig. 23.9.
Fig. 23.9 Accessing an operand from a data segment using LDT
23.3.6 Multitasking in 80286

The 80286 is designed for efficient handling of tasks in a multitasking environment.
A task is most often a procedure or an application program. In an 80286 system
having a multitasking and multi-user OS, the processor switches rapidly between
tasks, to give the appearance to the programmer that all tasks are executed
simultaneously. The 80286 supports the task-switching operation in hardware.
Each task has a task state segment (TSS) associated with it. The TSS is used to
save the entire state of the machine (all the registers’ contents, the address space,
and a link to the previous task) and additional information belonging to the task
such as the reason the task is inactive, the time the task spent in running, etc. The
current TSS is identified by the 16-bit register called task register (TR). The 16-
bit TR contains a selector pointing to the TSS descriptor that defines and points
to the current TSS in the GDT. The program-invisible portion of the TR is also
automatically loaded with a copy of the TSS descriptor, whenever a new value is
loaded in the TR.
Returning from a task is accomplished by the IRET instruction. When IRET

is executed, control is returned to the task that was previously interrupted. The
currently executing task’s state is saved in its TSS, a new value is loaded in the TR
to select the TSS for the old task, and the old task’s state is restored from its TSS.
Protection checks are then performed and the execution of a new task begins. Task
switching allows the 80286 to switch between tasks in a short duration of time (a
few microseconds).
23.3.7 Addressing Modes and New Instructions in 80286

The addressing modes in the 80286 are common to the real mode and the protected
mode, and they are the same as those of the 8086. The accessing of memory during
the protected mode operation by the 80286, using different addressing modes, is
Fig. 23.10 Accessing memory using different addressing modes in protected mode in the 80286
The 80286 can execute all the instructions of the 80186. In addition, the
following new instructions were introduced in the 80286:
CTS Clear task-switched flag in machine status word.
LGDT address Load GDTR from address in the memory.
SGDT address Store GDTR in address in the memory.
LIDT address Load IDTR from address in the memory.
S1DT address Store IDTR in address in the memory.

LLDT source Load LDTR from source (16-bit register or memory
location).
SLDT destination Store LDTR in destination (16-bit register or memory
location).
LTR source Load TR from source (16-bit register or memory
location).
STR destination Store TR in destination (16-bit register or memory
location).
LMSW source Load MSW (machine status word) from source (16-
bit register or memory location).
SMSW destination Store MSW in destination (16-bit register or memory
location).
LAR destination, source Load access right byte.
LSL destination, source Load segment limit.
ARPL sei, reg Adjust RPL of selector (sei, 16-bit) to not less than
RPL of reg (16-bit).
VERR dst Verify a segment for reading, selector in dst (16-bit
register or memory location), set ZF = 1 if the segment
can be read.
VERW dst Verify a segment for writing, set ZF = 1 if segment can
be written, dst is same as in VERR
All the 80286 instructions are available in the 32-bit microprocessors of the
Intel X86 family, such as the 80386, the 80486, and the Pentium.
23.3.8 Flag Register

The flag register in the 8086, 80186, and the 80286 is 16 bits; the flag register
present in all processors from the 80386 to the Pentium is 32 bits and is called
EFLAGS. Figure 23.11 shows the bits present in the flag register in all processors
from the 8086 to the Pentium. The bits that are left empty in the flag register are
reserved for future expansion.
The new bits present in the flag register in all processors from the 80286 to the
Pentium are explained here:
(i) IOPL (I/O privilege level; bits IOP0 and IOP1)—The I/O privilege level
IOPL is used to select the privilege level for the I/O devices in protected
mode operation. If the current privilege level (CPL) is higher (i.e., smaller in
number) than the IOPL, the I/O operation is performed without hindrance.
If the IOPL is lower than the CPL, an interrupt occurs, causing execution
to suspend. Note that an IOPL of OOH has the highest privilege level and an
IOPL of 11H has the least privilege level. For example, if the CPL is OOH
and the IOPL is 01H, the I/O operation is performed without hindrance.
(ii) NT (nested task)—The nested task flag indicates that the current task is
nested within another task in protected mode operation. This flag is set
when the task is nested by software.
Fig. 23.11 Flag register present in the 8086 to the Pentium microprocessors
(iii) RF (resume flag)—RF is used with debugging, to control the resumption of

execution by temporarily disabling the debug facility.
(iv) VM (virtual mode)—If VM is set, the microprocessor enters the virtual
8086 mode within the protected mode. This flag has to be set only when the
processor is in the protected mode using the IRET instruction or any task
switch operation. The VM bit selects virtual mode operation in a protected
mode system. A virtual mode system allows multiple DOS (disk operating
system) memory partitions that are 1 MB in length to coexist in the memory.
This allows the system program to execute multiple DOS programs in the
computer.
(v) AC (alignment check)—The AC flag is set if a word or double word is
accessed from a non-word or non-double-word boundary.
(vi) VIF (virtual interrupt flag)—The VIF is a copy of the interrupt flag bit
available in the Pentium.
(vii) VIP (virtual interrupt pending)—VIP provides information about the virtual
mode interrupt for the Pentium. This is used in a multitasking environment
to provide the operating system with virtual interrupt flags and interrupt
pending information.
(viii) ID (identification)—The ID flag indicates that the Pentium supports
the CPUID instruction. The CPUID instruction provides the system
with information about the Pentium, such as its version number and
manufacturer.

The 80386 is the Intel’s first 32-bit microprocessor. Most of the registers in the
80386 are 32 bits wide, and the address bus and data bus are also 32 bits wide.
The 80386 processor can access 4 GB (1 GB = 230 bytes) of memory, as it has a 32-
bit address bus. The paging mechanism in the 80386 is used to efficiently handle
virtual memory. The features of the 80386 are explained in this section.
23.4.1 Architecture of 80386

The functional block diagram of the 80386 is shown in Fig. 23.12. The 32-bit
data bus of the 80386 allows the user to read or write single-precision floating-
Segmentation unit Paging unit
ADVANCED MICROPROCESSORS AND MICROCONTROLLERS
687
Fig. 23.12 F u n ctio n a l b lo ck d ia g ra m o f the 80386

point numbers (32 bits) from or to the memory in a single memory read or write
cycle. This increases the speed of execution of any program that manipulates
real numbers in the 80386. Most high-level language programs and database
management systems use real numbers for data storage. The 80386 processor uses
the 80387 (numeric coprocessor) to perform floating point operations.
The internal architecture of the 80386 is divided to three units—bus interface
unit, memory management unit, and the central processing unit. The central
processing unit is further divided into the execution unit and the instruction unit.
The execution unit has eight general-purpose and eight special-purpose registers,
which are used either for handling data or for calculation of the offset addresses.
The instruction unit decodes the opcode bytes received from the 16-byte instruction
queue and arranges them in a three-instruction decoded instruction queue, so as to
pass it to the control section for deriving the necessary control signals. The barrel
shifter increases the speed of execution of the shift and rotate instructions. The
32-bit multiplication operation can be executed within 1 ps by the multiply/divide
logic. The memory management unit (MMU) consists of a segmentation unit
and a paging unit. The segmentation
unit allows the use of two address General-purpose registers
components—segment and offset, 31 24 23 16 15 8 7 0
for relocability and sharing of code AH AX AL EAX
and data by multiple programs. The BH BX BL EBX
maximum size of a segment is 4 GB. CH CX CL ECX
The paging unit organizes the physical DH DX DL EDX
memory in terms of pages of 4 KB SI ESI
each. The paging unit works under the DI EDI
control of the segmentation unit (i.e., BP EBP
each segment is divided into pages). SP ESP
The virtual memory is also organized

Segment registers
in terms of segments and pages by the 15 0
MMU. The 80386 requires a single CS Code segment
+5 V power supply for its operation. SS Stack segment
The clock frequency used in different DS
versions of the 80386 is 16 MHz, 20 ES Data segment
MHz, 25 MHz, and 33 MHz. FS
23.4.2 Register Organization in 80386 GS
The registers in the 80386 are shown

in Fig. 23.13. All the registers in the
80386 are 32 bits wide. The 32-bit
register, called extended register, is
represented by the register name with
the prefix E. However, 16-bit registers
such as AX, BX, CX, etc., and 8-bit
registers such as AH, AL, BH, etc., are Fig. 23.13 Registers in the 80386
also available in the 80386, as in the
8086. There are two additional segment registers, FS and GS, which provide two
additional segments that can be accessed by a program.
The 80386 includes a memory management unit (MMU) that allows memory
resources to be allocated and managed by the operating system. The segment
registers, system address registers (GDTR and IDTR), and system segment
registers (LDTR and TR), with their corresponding descriptor registers, as present
in all processors from the 80386 to the Pentium, are shown in Fig. 23.14. The
segment descriptor registers are not available for the programmer; they are
internally used to store segment descriptor information such as base address, limit,
and attributes of different segments. These registers are automatically loaded when
the corresponding segment registers are loaded with new selectors. GDTR, IDTR,
LDTR, and TR are used to access the descriptor tables GDT, IDT, LDT, and TSS
descriptor, respectively.
Segment registers Descriptor cache

Base address Limit Access
Base address Limit Access
Descriptor table addresses
GDTR Base address Limit

Program-invisible
IDTR
Fig. 23.14 Segment registers and MMU registers with corresponding descriptor registers
The 80386 has three 32-bit control registers—CRO, CR2, and CR3 (which are
shown in Fig. 23.15), to hold the global machine status independent of the executed
task. The load and store instructions are available to access these registers. The
control register CR1 is reserved for use in future Intel processors. The bits PE and
PG (bits 0 and 31) in the CRO are used to enable protected mode operation and
paging, respectively. The CR3 is used to hold the base address of the page directory
in the memory. The CR2 is used to hold the linear address for which a page fault
(required page not being present in the physical memory) has occurred, and using
this address the operating system can load the required page in the physical memory
from the secondary memory. CR4 is present only in the Pentium.
Fig. 23.15 Control registers—80386 to Pentium
Intel has provided a set of eight debug registers Debug registers

(DR0-DR7) for hardware debugging. Two of these, 31 0
Linear breakpoint address 0 DRO
DR4 and DR5, are Intel-reserved and two others,
Linear breakpoint address 1 DR1 I
the test control and test status registers, are used
Linear breakpoint address 2 DR2
for page caching. These registers are shown in Fig.
Linear breakpoint address 3 DR3
23.16. The registers DR0-DR3 are used to store Intel reserved. DR4
four program-controllable breakpoint addresses at Intel reserved. DR5
which execution of a program breaks. This is useful Breakpoint status DR6
to debug a program using breakpoint technique Breakpoint control DR7
j
easily. DR6 and DR7 hold break point status and
Test register (for page cache)
break point control information, respectively. 31 0 f
The segment registers and their default offset Test control TR6
registers in the 80386 to the Pentium processors Test status TR7
are given in Table 23.2.

Fig. 23.16 Debug and test
registers
Table 23.2 Segment registers and default offset registers
Segment Offset Function

CS EIP Instruction address
SS ESP and EBP Stack address
DS EAX, EBX, ECX, EDX, ESI, EDI, as 8-bit Data address
number, or a 32-bit number
ES EDI for string instruction String destination address
FS No default General address
GS No default General address
23.4.3 Instruction Set of 80386

The instruction set of the 80386 is upward compatible with the earlier 8086 and
80286 processors. The memory management instructions and techniques used
by the 80386 are also compatible with the 80286. These features allow 16-bit
software written for the 8086 and the 80286 to be executed in the 80386 also.
There are a few additional instructions included in the 80386, which reference the
32-bit registers and manage the memory system:
BT dest, bit Bit test—Transfer bit from ‘dest’ to carry flag (CF).
BTC dest, bit Bit test and complement—Transfer bit from ‘dest’ to CF, then
complement the bit in ‘dest’.
BTR dest, bit Bit test and reset—Transfer bit from ‘dest’ to CF, then clear the
bit in ‘dest’.
BTS dest, bit Bit test and set—Transfer bit from ‘dest’ to CF, then set the bit in
‘dest’.
BSF dest, src Bit scan forward—Scan ‘src’ from bit 0 (i.e., LSB) to the left and
store the bit number of the first bit set in ‘dest’.
BSR dest, src Bit scan reverse—Scan ‘src’ from bit 15 or 31 (i.e., MSB) to the
right and store the bit number of the first bit set in ‘dest’.
Here, ‘bit’ is one of the bits between 0 and 31 in a 32-bit register, one of the
bits between 0 and 15 in a 16-bit register, or a given 8-bit immediate value, ‘dest’
in BT, BTC, BTR, and BTS is a 16- or 32-bit register or memory location and
‘dest’ in BSF and BSR is a 16- or 32-bit register, ‘src’ is a 16- or 32-bit register
or memory location.
CDQ Convert double word in EAX into sign-extended quad
word in EDX-EAX.
CWDE Convert word in AX into sign-extended double word in
EAX.
MOVSX dest, src Move the data in the source (src) to the destination (dest)
with sign extension.
MOVZX dest, src Move the data in the source (src) to the destination (dest)
with zero extension.
LFS reg, m Load FS and register (reg) with a full pointer from memory
(m).
LGS reg, m Load GS and register (reg) with a full pointer from memory
(m).
LSS reg, m Load SS and register (reg) with a full pointer from memory
(m).
SHLD dest, reg, count Double precision shift left—Shift ‘dest’ to the left ‘count’
times and fill the bit positions with the most significant
bits of ‘reg’, ‘count’ can be the contents of CL or an
immediate 8-bit value.
SHRD dest, reg, count Double precision shift right—Shift ‘dest’ to the right
‘count’ times and fill the bit positions with the least
significant bits of ‘reg’, ‘count’ can be the contents of CL
or an immediate 8-bit value.
SET cc Set condition code flag.
23.4.4 Addressing Memory in Protected Mode

The addressing of memory when the 80386 operates in protected mode is shown
in Fig. 23.17. The selector and offset size is 16 bits each, when 16-bit addressing
is used (to run 8086 or 80286 programs) in the protected mode. The selector and
offset size is 16 bits and 32 bits, respectively, when 32-bit addressing is used (to
run 80386 to Pentium programs) in the protected mode. The base address is 32
bits (B31-B0) and the limit is 20 bits (L19-L0). If the granularity (G) bit is 1, the
limit field is multiplied by 4K to get the size of the segment in bytes, and if G is
0, the limit field itself gives the size of the segment in bytes. The available (AV)
bit indicates whether the segment is available (AV = 1), or not available (AV =
0). The D bit indicates how the processors (80386 to Pentium 4) access register
and memory data in the protected and real mode. If D is 0, the instructions are
16-bit instructions, compatible with the 8086-80286; these instructions use 16-
bit registers and 16-bit offsets by default. If D is 1, the instructions are 32-bit
instructions, compatible with the 80386-Pentium 4; these instructions use 32-bit
registers and 32-bit offsets by default.
Fig. 23.17 Addressing of the memory when the 80386-Pentium operates in the
protected mode
The format of the segment descriptor used in the 80386-Pentium is shown in

Fig- 23.18.
Byte no. 8 bits 8 bits Byte no.

7 Base (B31-B24) G D 0 AV Limit (L19—L16) 6
5 Access rights Base (B23-B16) 4
3 Base (B15-B0) 2
1 0
Limit (L15—L0)
Fig. 23.18 Format of segment descriptor in the 80386-Pentium

The accessing of memory by different addressing modes during protected

mode operation by the 80386-Pentium is shown in Fig. 23.19. From the 80386
onwards, Intel introduced a new addressing mode called scaled index addressing
mode in which the content in the index register can be multiplied by a factor of 1,
2, 4, or 8 while calculating the effective address (EA), as shown in Fig. 23.19.
Fig. 23.19 Accessing memory using different addressing modes in protected mode operation
Example:
(a)MOV EAX, [ESI x 4] ; EA is ESI x 4
(b)MOV ECX, [EBX + ESI x 2]; EA is EBX + ESI x 2
(c)MOV EDX, [EBX + EDI x 8 + 5]; EA is EBX + EDI x 8 + 5
23.4.5 Physical Memory Organization in 80386

The physical memory system of the 80386 is 4 GB. If virtual addressing is used,
using LDT and GDT, 64 TB (214 segment descriptors x 232 bytes/segment = 26 x
240 bytes) of virtual memory are mapped into the 4 GB of physical memory by
the memory management unit and descriptors. The physical memory is divided
into four 8-bit wide memory banks, each containing up to 1 GB of memory, as
shown in Fig. 23.20. This 32-bit wide memory organization allows bytes, words,
or double words of memory data to be accessed directly. The physical memory
address ranges from 00000000H to FFFFFFFFH. The physical memory location
with address 00000000H is in bank 0, 00000001H in bank 1,00000002H in bank
2, 00000003H in bank 3, etc., as shown in Fig. 23.20. The memory banks 3, 2,

1. and 0 are accessed via four bank enable signals—BE3, BE2, BE1, and BEO,
respectively. In most cases, a word is addressed in banks 0 and 1, or in banks 2
and 3.
Fig. 23.20 Physical memory system of the 80386
23.4.6 Paging Mechanism in 80386

The paging mechanism of the 80386 is shown in Fig. 23.21. The paging mechanism
provides an efficient way of handling the virtual memory. Paging can be enabled
by setting the PG bit in the control register CR0 or disabled by clearing the bit.
When paging is enabled, each segment is divided into fixed-size pages of 4 KB

each and the address generated by the segmentation mechanism is called linear
address. The linear address is then converted into a physical address by the 80386
paging mechanism, as shown in Fig. 23.22. Information about each page is stored
in a page table, in the form of a four-byte entry called page table entry (PTE). Each
page table can store a maximum of 1024 (= 210) PTEs. Hence, the size of a page table
is 4 KB. There can be a maximum of 1024 (= 2I0)page tables. Information about each
page table is stored in a page directory in the form of a four-byte entry called page
directory entry (PDE). There is only one page directory and it can store a maximum
of 1024 (= 2l0)PDEs. Hence, the size of a page directory is also 4 KB. Thus, Intel
uses a uniform size of 4 KB for each page, page table, and page directory.
Two-level paging scheme
Fig. 23.22 Conversion of linear address to physical address by paging mechanism
The linear address is divided into three fields—directory, table, and offset. The
directory field in the linear address is 10 bits wide and is used to select one of the
PDEs stored in the page directory that gives the base address of a page table in
the memory. If all the bits in the directory field are 0, the first entry in the page
directory will be selected; if all the bits are 1, the last entry in the page directory
(1,024th entry) will be selected, and so on.
The table field in the linear address is 10 bits wide and is used to select one
of the PTEs stored in a page table that gives the base address of a page in the
memory. If all the bits in the table field are 0, the first entry in the page table will
be selected; if all the bits are 1, the last entry in the page table (1,024th entry) will
be selected, and so on.
The offset field in the linear address is 12 bits wide and is used to select one
of the bytes stored in a page in the memory. If all the bits in the offset field are 0,
the first byte in a page will be selected; if all the bits are 1, the last byte in the page
will be selected, and so on. It is to be noted that the offset field, in both the linear
address and the physical address, is the same during the address translation.
The page tables and page directory are also present in the memory along with
the pages. The control register CR3 in the 80386 is loaded with the base address
of the page directory to address it.
When the required page needed by the CPU is not present in the memory,
a page fault is said to have occurred. CR2 is used to hold the linear address for
which the page fault (required page not being present in the physical memory) has
occurred and using this address, the operating system can load the required page
in the physical memory from the secondary memory.
The formats of each PTE and PDE are shown in Figs 23.23 (a) and 23.23 (b).
The PTE contains a 20-bit page frame address, which indicates the base address
of a page in the memory that is obtained by appending 12 binary Os (or three
hexadecimal Os) to the right of the page frame address. For example, if the page
frame address of a page is 2FFFFH, the base address of a page in memory is
2FFFF000H. This is done because each page is stored from a 4 KB boundary in
the memory (i.e., the base address of each page contains 12 binary Os or three
hexadecimal Os). In addition, the PTE also contains some page information that is
also common to the PDE.
The P-bit indicates whether the PTE or PDE entry can be used in address
translation, i.e., converting a linear address to a physical address (P = 1) or not (P
= 0).
The access bit (A) is set by the processor before accessing the page. If A = 0
for a page, it means that that page has not been accessed by the processor so far.
The dirty (D) bit is set before a write operation to the page is carried out. The
D bit is undefined for a PDE.
The OS reserved bits are defined by the OS software.
31 12 11 10 9 8 7 6 5 4 3 2 1 0
U R
Page Frame Address 31-12 OS Reserved 0 0 D A 0 0 P
s W
(a)
31 12 11 10 9 8 7 6 5 4 3 2 1 0
LI R
Page Table Address 31-12 OS Reserved 0 0 D A 0 0 P
S W
(b)
Fig. 23.23 (a) Format of a PTE (b) Format of a PDE
The user/supervisor (U/S) Table 23.3 Function of the U/S and R/W bits in PTE
and read/write (R/W) bits are and PDE
used to provide protection under
R/W Permitted for Permitted for
the four-level protection mode 0 U/S
level 3 levels 2,1, orO
as shown in Table 23.3. Level 0
is the highest privilege level and 0 0 None Read-write
level 3 is the least privilege level. 0 1 None Read-write
Each PDE contains a 20-bit page
1 0 Read-only Read-write
table address, which indicates
1 1 Read-write Read-write
the base address of a page table
in the memory. The address is
obtained by appending 12 binary Os (or three hexadecimal Os) to the right of the
page table address. This is done because each page table is also stored from a 4
KB boundary in the memory (i.e., the base address of each page table contains 12
binary Os or three hexadecimal Os).
The conversion of a linear address to a physical address by the paging mechanism
in the 80386 involves certain time, since the processor has to refer to a page
directory and page table to execute the conversion. To reduce the time involved in
the conversion, a small cache memory called translation lookaside buffer (TLB) is
present in the 80386, which will contain the 32 recently-used linear addresses and
their corresponding physical addresses. Whenever a linear address is to be converted
to a physical address, the 80386 first refers to the TLB to check whether the linear
address is present. If it is not present, the condition is called ‘miss’, and the processor
refers to the page directory and page table to get the physical address; it also stores
both of them in the TLB for future reference. Instead, if the TLB contains the required
linear address, the condition is called hit, and the processor gets the physical address
from the TLB itself. This is illustrated in Fig. 23.24.
Fig. 23.24 Conversion of linear address to physical address using TLB and page table

The 80486 has 1.2 million transistors and is fabricated using complementary high
speed metal-oxide-semiconductor (CHMOS) IV technology. It has 168 pins and it
is also 32-bit microprocessor. The functional block diagram of the 80486 is shown
in Fig. 23.25.
The architecture of the 80486 is similar to that of the 80386, with the additional
features being an 8 KB on-chip unified cache (storing both code and data) and a
floating point unit (FPU). The 80486 has the following subsystems:
(i) The bus interface, which is connected to the external system bus and to the
on-chip cache and prefetcher unit
(ii) The prefetcher, which includes a 32-byte queue of prefetched instructions
and is connected to the bus interface, cache, instruction decoder, and
segmentation unit
698
64-bit interunit transferbus

MICROPROCESSORS AND MICROCONTROLLERS
Fig. 23.25 F u n ctio n a l b lo ck d ia g ra m o f the 8 0 4 8 6

(iii) The cache unit, which includes an 8 KB cache, storing both code and data,
and cache management logic. It is connected through a 64-bit inter-unit
transfer (data) bus to the segmentation unit, ALU, and FPU. The cache unit
is also directly connected to the paging unit, bus interface, and prefetcher
through 128 lines, permitting the prefetching of 16 bytes of instructions
simultaneously. The cache is four-way set-associative write-through with
16 bytes/line. In the write-through policy of cache, when there is a hit during
a write operation, both the cache and main memory are updated together.
(iv) The instruction decode unit, which receives three bytes of undecoded
instructions from the prefetcher queue and transmits the decoded instructions
to the control and protection test unit
(v) The control and protection test unit, which generates micro instructions
transmitted to other units and performs protection testing
(vi) The ALU, which includes general purpose register file, a barrel shifter, and
registers for microcode use
(vii) The FPU, which includes floating point registers, an adder, a multiplier, and
a shifter
(viii) The segmentation unit, which includes segmentation management logic,
descriptor registers, and break point logic.
(ix) The paging unit, which includes paging management logic and a 32-bit
entry TLB
Here also, there are four memory banks, each storing one byte of a double
word, as in the 80386. Bytes within a 32-bit double word are selected by the four-
byte enable signals BE3-BE0, as follows:
(i) BE3 is used to enable the bank containing the bits D31-D24.
(ii) BE2 is used to enable the bank containing the bits D23-D16.
(iii) BE1 is used to enable the bank containing the bits D15-D8.
(iv) BEO is used to enable the bank containing the bits D7-D0.
The 80486 cache is unified, holding both code and data. The 80486 uses a
unified cache due to its simplicity of design and higher hit rate in comparison with
a dual cache of the same total size. The 80486 cache has a four-way set-associative
organization, to increase the hit ratio. Each line in cache is 16 bytes long. During a
‘miss’ in the cache, a line is replaced with the missing line using the pseudo least
recently used (LRU) algorithm. There are two control bits—page cache disable
(PCD) and page write-through (PWT) in the control register CR3, and in all PTEs
and PDEs in the 80486 shown in Figs 23.26 (a) and 23.26 (b), which influence the
on-chip cache operation. The value of the PCD and PWT bits is also sent out on
pins PCD and PWT, respectively, of the 80486.
When PCD = 0, the on-chip caching of a page is enabled. The bit PCD alone does
not enable caching; it depends on the activation of the cache enable (KEN) input
signal and the status of the CD (cache disable) bit in the CRO. Thus, for the caching
to be enabled, we must have PCD = 0, CD = 0, and KEN = 0. When PWT = 1, we
have a write-through policy. In the write-through policy, whenever a write operation
is to be done in the cache memory, both the cache memory and the corresponding
12 11 10 9876543200
P P U R
Page Frame Address 31-12 OS Reserved 0 0 D A C W P
D T S W
(a)
12 11 10 9876543200
P P U. R
Page Table Address 31-12 OS Reserved 0 0 D A C W P
D T s W
Fig. 23.26 (a) Format of the 80486 PTE (b) Format of the 80486 PDE
location in the main memory are updated together. This causes the main memory
to obtain the results of a program immediately after the instructions of the program
are executed by the CPU. When PWT = 0, we have a write-back policy, in which
the result is first stored in the cache memory alone when an instruction is executed.
The result is copied in the corresponding location in the main memory only when
a ‘miss’ occurs in the cache memory. Since the internal cache is inherently write-
through, PWT is intended for an external second-level cache.
23.6 PENTIUM MICROPROCESSOR

The Pentium (P5 or 80586) is the third among Intel’s 32-bit microprocessors,
released in the year 1993. It has the distinction of being the first Complex Instruction
Set Computer (CISC) type processor implementing instruction level parallelism
(ILP). It is a two-issue superscalar processor, which means that two instructions
can be simultaneously decoded and executed in it. The Pentium is manufactured
using 0.8 micron Bipolar complementary metal-oxide-semiconductor (BiCMOS)
technology and is available in a 273-pin grid array package. There are 3.1 million
transistors inside the Pentium.
23.6.1 Architecture of Pentium

The block diagram of the Pentium is shown in Fig. 23.27. The Pentium is a 32-bit
processor with a double 64-bit data bus inside and outside of the chip. The internal
and external address bus of the Pentium is 32 bits wide. Hence, it can access 4
GB of memory. There are two separate 8 KB caches—one for code and one for
data. Each cache has a separate address translation TLB associated with it. The
availability of a dual cache and a dual TLB permits the CPU to handle simultaneous
instruction and data operand access, thus providing efficient handling of the
pipeline. There are 256 lines between the code cache and the prefetch buffers,
permitting the prefetching of 32 bytes of instructions.
There are two parallel integer instruction pipelines—the U pipeline and the V
pipeline. The U pipeline has a barrel shifter in addition to the integer ALU. There
is also a separate FPU pipeline with individual floating point add, multiply, and
divide operational units. The data cache is dual-ported and accessible by the U
and V pipelines, simultaneously. There is also a Branch Target Buffer (BTB),
supplying jump target prefetch addresses to the code cache.
Fig. 23.27 Block diagram of the Pentium
The Pentium has a five-stage integer pipeline, branching out into two paths U
and V in the last three stages as shown in Fig. 23.28. The Pentium pipeline stages
are as follows:
(i) PF (Prefetch)—The CPU prefetches the code from the code cache and
aligns the code to the initial byte of the next instruction to be decoded.
(ii) DI (First decode)—The CPU decodes the instruction to generate a control
word. A single control word causes direct execution of an instruction. More
complex instructions require microcoded control sequencing.
(iii) D2 (Second decode)—The CPU decodes the control word generated in
stage DI for subsequent use in the next execution (E) stage. In addition,
addresses for data memory references are generated.
(iv) E (Execute)—The instruction is executed in the ALU. The barrel shifter

or other operational units are used, if necessary. The data cache is also
accessed at this stage, if necessary.
(v) WB (Write back)—The CPU stores the results and updates the flags at this
stage.
Fig. 23.28 Integer pipeline stages in the Pentium
There are two types of instructions—simple and complex—in the Pentium.

Simple instructions of the Pentium are entirely hardwired, and in general, execute
in one clock cycle. The exceptions are the ALU register-to-memory and memory-
to-register instructions, which take two and three clock cycles, respectively. The
instructions considered simple are move register/memory/immediate into register,
move register/immediate into memory, integer arithmetic instructions, increment,
decrement, push register/memory, pop register, load effective address, jump, call,
jump conditional near, and no operation (NOP).
The following are the conditions for simultaneous issue of two instructions in
the Pentium:
(i) Both instructions must be simple, as defined earlier.
(ii) There must be no read-after-write (RAW) or write-after-write (WAW) data
dependencies between them.
(iii) Neither instruction may contain both a displacement and an immediate
value in them.
(iv) Instruction with prefixes can only occur in the U pipeline.
RAW and WAW are two pipeline data hazards, which are explained here:
(i) RAW: Let II and 12 be two consecutive instructions in a program. Let us
assume that the result to be stored in the destination (register or memory)
by II is used as one of the sources by 12. When these two instructions
are executed without pipeline operation, the result of II is first stored in
the destination, and then 12 reads the content of that destination. The data
hazard RAW arises when 12 starts reading the content of the destination of
Il before II writes the result in it, due to the overlapping of operations that
occur in pipeline operation.
(ii) WAW: Let II and 12 be two consecutive instructions in a program. Let
us assume that the destination (register or memory) of II is also used as
destination by 12. When the two instructions are executed without pipeline
operation, the result of II is first stored in the destination, and then 12 store
its result in the same destination. The data hazard WAW arises when 12
starts writing its result in the destination of II before II writes the result in
it, due to the overlapping of operations that occur in the pipeline operation.
This may be due to II having an addressing mode that needs more clock
cycles to calculate the effective address of the destination and 12 having
a simple addressing mode that needs lesser clock cycles to calculate the
effective address of the destination. This hazard is also known as out-of-
order write.
If the first of the two decoded instructions is a jump, it is forwarded to the U
pipeline for execution and no instruction is forwarded to the V pipeline. In the
case of wrongly predicted jump, the pipeline is delayed by three or four clock
cycles. When a jump instruction is first taken, the CPU allocates an entry in the
256-entry branch target buffer (BTB), to associate the jump instruction’s address
with its target address and to initialize the history used in the branch prediction
algorithm (an algorithm used to predict whether jump will take place or not, using
the previous history of execution of the same jump instruction). As instructions
are decoded, the CPU searches the BTB to determine whether it holds an entry for
a corresponding jump instruction. When there is a hit, the CPU uses the history
to determine whether the jump should be taken. If it should, the CPU uses the
target address to begin fetching and decoding instructions from the target path.
The jump is resolved early in the WB (write back) stage, and if the prediction was
incorrect, the CPU flushes the pipeline and resumes fetching instructions along the
correct path. The CPU updates the history of the jump instruction in the WB stage.
Correctly predicted jumps execute without any delay.
The Pentium has an eight-stage floating-point pipeline, illustrated in
Fig. 23.29.
PF D1 D2 E X1 X2 WF ER
Fig. 23.29 Floating-point pipeline stages in the Pentium
(i)PF (Prefetch)—Prefetch instructions from the code cache

(ii)DI (First decode)—Same as in the integer pipeline
(iii)D2 (Second decode)—Same as in the integer pipeline
(iv) E (Operand fetch)—Fetches operands from either the floating-point register
file or the cache
(v) XI (First execute)—First step in the floating-point execution by the FPU
(vi) X2 (Second execute)—Second step in the floating-point execution by the

FPU
(vii) WF (Write float)—The FPU completes the floating point computation and
writes the result into the floating point register file.
(viii) ER (Error reporting)—The FPU reports internal special situations that
might require additional processing to complete execution and updates the
floating point status word.
The initial three stages of the floating point instruction are executed in the
U pipeline. The dual port of the data cache is used for access of 64-bit double
precision operands. The code and data caches are each 8 KB two-way set-
associative, with 32 bytes/line. The data cache is write-back and uses a modified/
exclusive/shared/invalid (MESI) cache coherency protocol. The physical memory
organization in a Pentium-based system is shown in Fig. 23.30. The eight bytes
of a 64-bit quad word are activated by the eight-byte enable signals BE7-BE0 .
Signal BEO enables the low byte D7-D0, BE1 enables the next byte D15-D0,
and so on. The two introductory versions of the Pentium operated with a clocking
frequency of 60 MHz and 66 MHz, and at a speed of 110 MIPS, and later a 100
MHz version operating at 150 MIPS appeared. Then the double-clocked Pentium
operating at 120 MHz and 133 MHz, and a higher speed version (200 MHz),
became available. The data bus transfer speed (rate at which data are transferred
D31-O24
Fig. 23.30 Physical memory (4 GB) organization in the Pentium

between the microprocessor and the main memory) was either 60 MHz or 66 MHz,
depending on the version of the Pentium.
23.6. 2 Protected Mode Operation of Pentium

The protected mode operation of the Pentium is the same as that of the 80386 and
is shown in Fig. 23.17. The segment descriptor of the Pentium is the same as that
23.6. 3 Addressing Modes in Pentium

The addressing modes in the Pentium are the same as that of the 80386, which are
23.6. 4 Paging Mechanism in Pentium

The paging mechanism of the Pentium is the same as that of the 80386 and is shown
in Figs 23.21 and 23.22. The Pentium uses the regular Intel 4 KB page. However,
it also features an optional large 4 MB page, intended for large software packages.
Each cache has its own translation lookaside buffer (TLB). The data cache TLB
is a four-way, set-associative, 64-entry for 4 KB pages. There is a separate data
cache TLB for 4 MB pages. It has eight entries and the same parameters as the
TLB for 4 KB pages. There is only one 32-entry code cache TLB for 4 KB pages.
This TLB is also four-way set-associative. Replacement in the TLBs is handled by
a pseudo-LRU algorithm, similar to the one implemented in the 80486.
23.7 OTHER VERSIONS OF PENTIUM

After the introduction of the Pentium, Intel introduced many new versions such as
Pentium Pro, Pentium II, Pentium III, and Pentium 4, subsequently. Their features
are briefly described in Sections 23.7.1-23.7.4.
23.7.1 Pentium Pro Processor

The Pentium Pro processor, formerly named P6 microprocessor, contains 21
million transistors, three integer units, as well as a floating point unit to increase
the performance of most software. The basic clock frequency was 150 MHz and
166 MHz in the initial versions of the Pentium Pro processor, made available
in late 1995. In addition to the internal 16 KB level one (LI) cache (8 KB for
code and 8 KB for data), the Pentium Pro processor also contains a 256 KB
level two (L2) cache. The Pentium Pro processor uses three execution engines.
So, it can execute up to three instructions at a time, which can conflict and still
execute in parallel. This represents a change from the Pentium, which executes
two instructions simultaneously, as long as they do not conflict. The Pentium Pro
processor has been optimized to efficiently execute 32-bit code. Hence, it is often
used with Windows NT rather than with normal versions such as Windows 95.
Intel launched the Pentium Pro processor for the server market. The Pentium Pro
processor can address either a 4 GB memory system or 64 GB memory system.
The Pentium Pro processor has a 36-bit address bus if configured for a 64 GB
memory system.
23.7.2 Pentium II Processor

The Pentium II processor was released in 1997. Instead of being an integrated
circuit, Intel placed the Pentium II on a small circuit board. The main reason for
the change is that the L2 cache found on the main circuit board of the Pentium was
not fast enough to justify a new microprocessor. On the Pentium system, the L2
cache operates at the system bus speed of 60 MHz or 66 MHz. The microprocessor
and L2 cache are on a circuit board called the Pentium II module. This on-board
L2 cache operates at a speed of 133 MHz and stores 512 KB of information. The
microprocessor on the Pentium II module is actually a Pentium Pro with MMX
(multimedia) extensions and no internal L2 cache.
Intel changed the bus speed of the Pentium II in 1998. Since the 266 MHz to
333 MHz Pentium II microprocessors used an external bus speed of 66 MHz, there
was a bottleneck in transfering data. So, the newer Pentium II microprocessors
used a bus speed of 100 MHz. The Pentium II microprocessors rated at 350 MHz,
400 MHz, and 450 MHz, all use this higher 100 MHz memory bus speed. The
higher speed memory bus requires the use of 8 ns SDRAM, in place of the 10 ns
SDRAM found with a bus speed of 66 MHz.
23.7.3 Pentium III Processor

The Pentium III is available in two versions—the slot I version (mounted on a
plastic cartridge) and a socket 370 version, called a flip-chip. The Pentium III
is available in clock frequencies of 1 GHz. The slot I version of the Pentium III
contains a 512K cache and the flip-chip version contains a 256K cache. The speeds
of both versions are comparable because the cache in the slot I version runs at
one-half the clock speed, while the cache in the flip-chip version runs at the clock
speed. Both versions use a memory bus speed of 100 MHz, while the Celeron uses
a memory bus clock speed of 66 MHz. The speed of the front-side bus, i.e., the
connection from the Pentium III to the memory controller, PCI controller, and the
AGP controller is now either 100 MHz or 133 MHz.
23.7.4 Pentium 4 Processor

The Pentium 4 was released in late 2000. It uses Intel P6 architecture. The main
difference is that the Pentium 4 is available in 1.3,1.4, and 1.5 GHz speed versions,
and the chipset that supports the Pentium 4 uses RAMBUS memory technology
in place of SDRAM technology. These higher microprocessor speeds are made
available by an improvement in the size of the internal integration. The Pentium
4 contains an 8 KB LI cache, but it may be improved to a 32 KB LI cache in
future versions of the Pentium 4. The L2 cache remains at 256 KB. The front-side
bus speed is increased from the current maximum of 133 MHz to 200 MHz or
higher.
23.8 POWERPC ARCHITECTURE

In the initial stages of development of microprocessors, limited manufacturing
techniques were available. Microprocessors of those times were manufactured
using the technology available then, in such a way that programming them in
assembly language and conserving memory were easy. Memory had to be

conserved, since it was slow to access and also expensive. From this technology
evolved the complex instruction set computer (CISC) microprocessors, which had
the following features:
(i) Very few registers, i.e., an accumulator and a few general-purpose
registers
(ii) An instruction set that had complex and variable length instructions. The
advantage of this feature was that programs could be written using very
few instructions. Simple instructions would have made the programs long.
Since program size was reduced, memory was conserved. The instructions
consisted of opcode (mostly one byte long) followed by data, address, or
pointers required for that instruction (one, two, three, or four bytes long).
(iii) Multiple styles of memory access, i.e., addressing modes. Individual memory
locations could be accessed directly, using a pointer or a combination of
pointers.
(iv) Serial execution of instructions, i.e., each instruction had to be completed
before beginning the execution of the next.
The evolution of microprocessors saw the addition of more registers and
features such as pipelining, where multiple instructions could be executed
simultaneously. However, memory conservation and ease of programming were
the main considerations during design of the microprocessor and this was usually
achieved at the cost of speed.
This basis for the processor design came to be questioned with the advent
of cheaper and faster memory and with the assembly languages being replaced
by high-level languages such as Pascal and C. The early 1980s saw the creation
of microprocessor designs that were much simpler than the earlier ones, and
optimized for speed and use with high-level languages. This introduced the
reduced instruction set computer (RISC) microprocessors whose instruction
set consisted of many simple instructions. RISC processors had the following
features:
(i) A load/store architecture where, as the name suggests, instructions had to
be loaded and stored into registers before being used.
(ii) Many general-purpose registers and a few special-purpose registers.
(iii) One or two memory addressing modes, which use a pointer in one of the
registers.
(iv) Instructions that fit into a single word and are encoded in an easily executable
format.
(v) Pipelining feature for processing multiple instructions at the same time
(vi) The presence of memory caches for faster access to instructions and data,
(vii) Restrictions on alignment of data in the memory. For example, two-byte
values had to be aligned on an even address, four-byte values on an even
multiple of four, and so on.
The PowerPC is a RISC design that has all these features, except the rules for
memory alignment.
23.8.1 Overview of PowerPC

The PowerPC (performance optimization with enhanced RISC-performance
computing) architecture is a new generation of microprocessors that provides
high performance and finds multiple applications in a wide range of fields from
personal computers to embedded systems. It is the result of a collaboration of
Apple, IBM, and Motorola and is based on IBM’s highly successful POWER
(performance optimization with enhanced RISC) architecture. This architecture,
designed for high-end scientific applications, has been optimized for both integer
and floating-point math operations and has been tweaked to suit the requirements
of desktop applications for use in the PowerPC. The POWER instruction set has
been simplified, ensuring minimal impact on performance. As a result of these
changes a low-cost, high-performance PowerPC RISC architecture has emerged
with the following features:
(i) A register-to-register (load/store) architecture, with support for both big
the-endian and little-endian data and aligned and misaligned data accesses
in the memory. The register set is large and consists of both general-purpose
and floating-point registers.
(ii) A simple instruction set with fixed length, consistently encoded instructions,
which may be modified to suit the requirement (e.g., setting the condition
codes at the end of an arithmetic operation is optional, not mandatory)
(iii) Simple and powerful addressing modes, which are consistently applied
across the instruction set
23.8.2 PowerPC Family Members

There are many RISC microprocessors in the PowerPC family—PowerPC 601
(MPC601), PowerPC 602 (MPC602), PowerPC 603 (MPC603), PowerPC 604
(MPC604), and PowerPC 620 (MPC620). PowerPC 601 has merged the power
architecture and the PowerPC architecture. It finds application in mainstream
desktop systems. The first PowerPC-only implementation of the PowerPC
architecture is the PowerPC 603, characterized by low cost and low power
consumption. It is used in portable and low cost desktop Macintosh systems.
PowerPC 604 is similar to PowerPC 601 in terms of cost and application, but
delivers higher performance. PowerPC 620 is a high performance microprocessor
that is apt for very high-end personal computers, workstations, servers, and
multiprocessor systems. It is still in the design phase. The features of PowerPC
601 (MPC601) alone are described here in detail.
23.8.3 Features of PowerPC 601 (MPC601)

PowerPC 601 is the first implementation of the PowerPC family of RISC
microprocessors. Figure 23.31 shows the block diagram of PowerPC 601.
PowerPC 601 implements the 32-bit PowerPC architecture, which provides 32-bit
logical addresses, integer data types of 8, 16, and 32 bits, and floating-point data
types of 32 and 64 bits (single- and double-precision). PowerPC 601 is capable of
issuing three instructions per clock cycle, one to each of the three execution units.
It falls under the category of superscalar processors. This ability to issue multiple
(Instruction fetch)
RTC Instruc :ion unit
RTCU Instruction
queue
RTCL
8 Words
Instruction Instruction
Issue logic
JL_
IU BPU FPU
GPR CTR FPR

FILE CR FILE
LR | FPSCR|
1 Words 2 Words
Data
Address
MMU 32-kbyte
cache
Physical address
UTLB n™~i TAGS (instruction and
BAT data)
array
Address
Data
Memory unit
4 Words
Read Write queue Data
queue Snoop 8 Words
Address
, Data
2 Words
System interface
64-bit data bus (2 words)
32-bit address bus (1 word)
Fig. 23.31 Block diagram of the PowerPC 601
instructions in parallel and the use of simple instructions with rapid execution
times yield high efficiency and throughput for this system. PowerPC 601 consists
of the following three execution units:
(i) A 32-bit integer unit (IU) having 32 general-purpose registers (GPRs)
(ii) A branch processing unit (BPU) featuring static branch prediction
(iii) A floating-point unit (FPU) having 32 floating-point registers (FPRs) for

storing single- or double-precision operands
Instructions in the PowerPC 601 can be completed out of order (i.e., the second
instruction may get executed before the first if they are independent of each other)
for increased performance. Most integer instructions execute in one clock cycle.
The FPU is pipelined and hence a single-precision multiply-add instruction can
be issued every clock cycle. PowerPC 601 includes an on-chip, 32 KB, eight-way
set-associative, physically addressed, unified instruction and data cache and an
on-chip memory management unit (MMU). The MMU contains a 256-entry, two-
way set-associative, unified translation lookaside buffer (UTLB) and provides
support for demand paged virtual memory address translation and variable-sized
block translation. Both the UTLB and the cache use least recently used (LRU)
replacement algorithms.
PowerPC 601 has a 64-bit data bus and a 32-bit address bus. The interface
protocol is such that it allows multiple masters to compete for system resources
through an external moderator. The on-chip snooping logic maintains cache
coherency in multiprocessor applications. PowerPC 601 supports single-beat
and burst data transfers for memory accesses. It also supports both memory
mapped I/O and I/O controller interface addressing. It uses an advanced, 3.6 V
CMOS process technology and maintains full interface compatibility with TTL
devices.
23.9 PIC16F877 MICROCONTROLLER

The PIC16F877 is an 8-bit CMOS flash microcontroller from Microchip
Corporation. The core architecture of the PIC 16F877 is based on a high performance
Reduced Instruction Set Computer (RISC) CPU with only 35 single word (14-bit)
instructions. Since the PIC16F877 uses RISC architecture, most of its instructions
take only one instruction cycle for execution, except for the instructions that are
used for program branchipg, which take two instruction cycles for execution.
Since each instruction cycle takes four Qperating clock cycles, the instructions
with single instruction cycle take 0.2 ps for execution when a 20 MHz oscillator
is used with the PIC16F877. The internal clock frequency of the PIC16F877
can vary from'DC to 20 MHz’ The PIC employs pipeline .technique to execute
the instructions, i.e., when the execution of one instruction is going on, the next
instruction to be executed is fetched from the program memory.
23.9.1 Features of PIC16F877

The PJC16F877 has two types of internal memory—program memory and data
memory. The program memory is made up of 8K words (or 8K x 14 bits) of flash
memory and is used to store the program or code that is executed by the CPU.
The data memory has two types of sources—368 bytes of RAM and 256 bytes of
EEPROM. The on-chip peripheral features of the PIC16F877 are as follows:
(i) Timer 0—An 8-bit timer/counter with 8-bit prescaler
(ii) Timerl—A 16-bit timer/counter with prescaler; can be incremented during

sleep mode via external crystal/clock
(iii) Timer 2—An 8-bit timer/counter with 8-bit period register, prescaler, and
postscaler
(iv) Two capture/compare/PWM modules, each having a 16-bit capture
register/16-bit compare register/1 O-bit PWM register
(v) Synchronous serial port (SSP) with SPI (master mode) and I2C (master/
slave) configuration for serial communication
(vi) Universal synchronous asynchronous receiver-transmitter (USART/SCI)
with 9-bit address detection for serial communication
(vii) 8-bit wide parallel slave port (PSP) with external RD, WR, and CS controls
(available only in 40/44-pin versions of the PIC16F877) for I/O device
interfacing
(viii) Brown-out detection circuitry for brown-out reset (BOR), to reset the
microcontroller when the supply voltage falls below the specified value
«4V)
(ix) 1 O-bit, eight-channel analog-to-digital converter (A/D) for interfacing
analog signals
(x) Analog comparator module with two analog comparators
In addition to these on-chip peripherals, the special features of the PIC16F877
are as follows:
(i) Enhanced flash program memory with 100,000 erase/write cycles (typical)
(ii) Data EEPROM memory with 1,000,000 erase/write cycles (typical)
(iii) Data EEPROM retention of more than 40 years
(iv) In-circuit serial programming (ICSP) via two pins
(v) Requires only a single power supply of 5 V
(vi) Watchdog timer (WDT) with its own on-chip RC oscillator for reliable
operation of the microcontroller. It resets the microcontroller if the device
hangs while executing the software.
(vii)' Programmable code protection
(viii) Power saving sleep mode
(ix) Selectable oscillator options
(x) In-circuit debugging (ICD) done via two pins
(xi) Uses low power., high speed flash/EEPROM technology
(xii) Wide operating voltage range (2.0 V to 5.5 V)
(xiii) Availability of commercial and industrial temperature range versions of the
PIC
(xiv) Low power consumption (< 0.6 mA typical at 3 V, 4 MHz, 20 pA typical at
3 V, 32 kHz, < 1 pA typical standby current)
23.9.2 Pin Diagram and Block Diagram of PIC16F877

The pin diagram of the PIC16F877 (DIP version) is shown in Fig. 23.32.
There are many PIC microcontrollers that come under the 16F87X family.
Table 23.4 shows the on-chip peripherals present in different PIC microcontrollers
that come under the 16F87X family.
MCLR/Vpp/THV E 1 40 RB7/PGD
RAO/ANO 2 39 RB6/PGC
RA1/AN1 3 38 RB5
RA2/AN2/VREf. E 4 37 □ RB4
RA3/AN3/Vreh 5 36 □ RB3/PGM
RA4/TOCKI E 6 35 RB2
RA5/AN4/SS E 7 34 RB1
RE0/RD/AN5 E 8 33 RB1/INT
RE1/WR/AN6 E 9 32 □
PIC 18F877
RE2/CS/AN7 E 10 31
Vdo E 11 30 □ RD7/PSP7
Vss 12 29 □ RD6/PSP6
OSC1/CLKIN 13 28 □ RD5/PSP5
OSC2/CLKOUT E 14 27 RD5/PSP4
RC0/T10S0/T1CKI E 15 26 E RC7/RX/DT
RC1/T10S1/CCP2 E 16 25 □ RC6/TX/CK
RC2/CCP1 E 17 24 □ RC5/SDO
RC3/SCK/SCL E 18 23 □ RC4/SDI/SDA
RDO/PSPO E 19 RD3/PSP3
RD1/PSP1 E 20 21 □ RD2/PSP2
Fig. 23.32 Pin diagram of PIC16F877
From the pin diagram, it is observed that except for few pins, the others have
many functions multiplexed together. By proper programming of the PIC16F877,
we can use each pin for a particular function. Figure 23.33 shows the block diagram
of the PIC16F877, in which all the internal components and on-chip peripherals
present in the IC are seen. There are five ports in the PIC16F877—ports A, B. C,
D, and E. The flash program memory is used for storing programs and the RAM
(also called register file) is used for storing data. In the RAM, some portions are
used as special function registers, which are needed to program the various on-
chip peripherals of the PIC16F877. Direct or indirect addressing mode is used
for accessing the data in the RAM. The file selection register (FSR) is used for
indirect addressing. The status register contains the flags that are affected during
the execution of arithmetic and logical instructions. The W register acts as the
accumulator. There is an eight-level stack, which is used during subroutine call
and return, and during interrupt processing.
Table 23.4 Features of PIC16F87X family
Device Program memory Data ;EEPROM I/O 10-bit CCP MSSP USART Timers Comparators
SRAM l(bytes) A/D (PWM) 8/16-bit
Bytes # Single word SPI Master
(bytes ) (ch)*
instructions PC
PIC16F873A 7.2K 4096 192 ■128 22 5 2 Yes Yes Yes 2/1 2
PIC16F874A 7.2K 4096 192 •128 33 8 2 Yes Yes Yes 2/1 2
Note: ch * denotes channels.

13. i----------------------- 1 Data bus Port A

<=7^|Program counter|<> RAO/ANO
Flash RA1/AN1
program RA2/AN2A/ /CVREF
RA3/AN3AC’
memory 8 level stack RAM file RAZ-nocug/ciouT
(13-bit) registers RA5/AN4/SS/C2OUT
Program 14 lb Port B
bus JI RAM Addr<1>
RBO/INO
[ Instruction reg [ /Addr MUX \ RB1
RB2
Direct Addr Indirect RB3/PGM
8fl addr RB4
RB5
| FSRreg RB6/PGC
RB7/PGD
Status reg
8 Port C
RC0/T10SO/T1CLK1
Power-up MUX RC1/T10SI/CCP2
timer I RC2/CCP1
RC3/SCK/SCL
Instruction Oscillator RC4/SDI/SDA
decode and start-up timer ALU RC5/SDO
control Power-on RC6/TX/CK
reset RC7/RX/DT
Timing Watchdog I Wreg 1 Port D
generation timer
OSC1/CLK1 Brown-out RDO/PSPO
OSC2/CLKO reset RD1/PSP1
R02/PSP2
In-circuit RD3/PSP3
debugger RD4/PSP4
Low-voltage RD5/PSP5
RD6/PSP6
programming RD7/PSP7
PortE
RE0/RD/AN5
MCLR V^V. RE1/WR/AN6
RE2/CS/AN7
Timer 0 Timer 1 Timer 2 10-bit A/D Parallel slave

port
Synchronous Voltage
Data EEPROM CCP1,2 serial port USART Comparator
reference
Fig. 23.33 Block diagram of the PIC16F877
23.9.3 Instruction Set of PIC16F877

The PIC16F877 instruction set comprises of three basic categories—byte-oriented
operations, bit-oriented operations, and literal and control operations. Each
PIC16F877 instruction is a 14-bit word, divided into an opcode, which specifies
the instruction type, and one or more operands, which further specify the operation
of the instruction. The format for each of the categories is presented in Fig. 23.34.
The 7-bit file register address (F) can be any one of the addresses between OOH
and 7FH. The bit address (B) can be any one of the addresses between 000 and
111 (in binary form).
Table 23.5 lists the different PIC instructions recognized by the MPASM™
assembler of Microchip Corporation.
Table 23.5 Instruction set of the PIC16F877
Mnemonics and operand Description Instruction Flags affected

cycles
Byte-oriented file register operations
AddWf F, D Add W and F. 1 C, DC, Z
ANDWF F, D AND W with F. 1 Z
CLRFF Clear F. 1 Z
CLRW Clear W. 1 Z
COMF F, D Complement F. 1 Z
DECF F, D Decrement F. 1 Z
DECFSZ F, D Decrement F, skip if 0. 1(2)
INCF F, D Increment F. 1 Z
INCFSZ F, D Increment F, skip if 0. 1(2)
IORWF F, D Inclusive OR W with F. 1 Z
MOVF F, D Move F to F or W. 1 Z
MOVWFF Move W to F. 1
NOP No operation 1
RLF F, D Rotate F left through carry. 1 C
RRFF, D Rotate F right through carry. 1 C
SUBWF F, D Subtract W from F. 1 C, DC, Z
SWAPF F, D Swap nibbles in F. 1
XORWF F, D Exclusive OR W with F. 1 Z
Bit-oriented file register operations
BCF F, B Clear bit B in F. 1
BSF F, B Set bit B in F. 1
BTFSC F, B Test bit B in F, skip if clear. 1(2)
BTFSS F, B Test bit B in F, skip if set. 1(2)
Literal and control operations
ADDLW K Add literal K with W. 1 C, DC, Z
ANDLWK AND literal K with W. 1 Z
CALLK Call subroutine at label K. 2
CLRWDT Clear watchdog timer. 1 TO*, PD*
GOTOK Go to label K. 2
IORLW K Inclusive OR literal K with W. 1
MOVLW K Move literal K to W. 1
RETFIE Return from interrupt. 2
RETLW K Return with literal K in W. 2
RETURN Return from subroutine. 2
SLEEP Go into standby mode. 1 TO*, PD*
SUBLW K Subtract W from literal K. 1 C, DC, Z
XORLW K Exclusive OR literal K with W. 1 Z
Note: '*’ denotes active low signal.
For byte-oriented instructions, ‘F’ represents a file register designator and ‘D’
represents a destination designator. The

Byte-oriented file register operations
file register designator specifies which file
8 7
13__________
register is to be used by the instruction. The
Opcode D
destination designator specifies where the
D = 0 for destination W
result of the operation is to be placed. If ‘D’ D = 1 for destination F
is 0, the result is placed in the W register. F = 7-bit file register address
If ‘D’ is 1, the result is placed in the file Bit-oriented file register operations
register specified in the instruction. For bit- 10 9
13__________ 7 6
oriented instructions, ‘B’ represents a bit Opcode B
field designator, which selects the bit (one bit B = 3-bit bit address
between 0 and 7) affected by the operation, F = 7-bit file register address
while ‘F’ represents the address of the file Literal and control operations
General
register in which the bit is located. For literal
and control operations, ‘K’ represents an 8-
2____8 7 0
Opcode K (literal)
bit or 11 -bit constant or literal value.
K = 8-bit immediate value
One instruction cycle consists of four
Call and go to instructions only
oscillator periods. For an oscillator frequency
13 11 10 0
of 4 MHz, a normal instruction takes an
Opcode K (literal)
execution time of 1 ps. All instructions
K = 11 -bit immediate value
are executed within a single instruction
cycle, unless a conditional test is true or the
Fig. 23.34 General format of PIC
program counter is changed as a result of an instructions
instruction. When this occurs, the execution
takes two instruction cycles, with the second cycle executed as a NOP.
Any instruction that specifies a file register as part of the instruction performs a
read-modify-write (R-M-W) operation. The register is read, the data is modified,
and the result is stored according to either the instruction or the destination
designator ‘D’. A read operation is performed on a register even if the instruction
writes into that register. For example, the CLRF PORTC instruction will read port
C, clear all the data bits, and then write the result back into the port.
23.9.4 Memory Organization in PIC16F877

The flash program memory and data memory of the PIC16F877 have separate buses
so that concurrent access can occur. The memory organization in the PIC16F877
is explained in detail in this section.
23.9.4.1 Program Memory Organization
The PIC16F877 has a 13-Hit program counter capable of addressing an 8K word x
14-bit program memory space. The PIC16F877 devices have 8K words x 14 bits of
flash program memory. Figure 23.35 shows the program memory map and stack in
the PIC16F877. The address of the program memory varies from 0000H to 1FFFH.
The 13-bit program counter is used to access instructions in the program memory.
After reset, PC is initialized with the value 0000H, so that the first instruction for
execution is fetched from the address 0000H. After fetching one instruction, PC
is automatically incremented by one to bring the next instruction. Whenever an
interrupt is received, the current value of PC is stored in an eight-level (i.e., eight
bytes) stacAzflfid PC is initialized with the PC <12:0>

value OO(54H. Hence, the first instruction
of the interrupt service routine (ISR) must CALL, RETURN
RETFIE, RETLW J
f 13
begin at the address 6004H. The stack is
also Accessed during'IEC.execution of-the Stack level 1
CALL, RETURN, RETFIE, and RETLW Stack level 2
instructions.
23.9.4.2 Data Memory Organization
The data memory is partitioned into four Stack level 8
ban^s (banks 0-3), which^contain the

general-purpose and special function Reset vector 0000H
registers. Bits RP1 and RPO in the status
u-----------
N------------
register (bits 6 and 5, respectively) are
the bank select bits, as shown in Table
Interrupt vector 0004H
23.6. Each bank has 128 bytes. The lower
J Page 0 0005H
locations of each bank are reserved for
the SFRs and the upper locations for the
07FFH
general-purpose registers, implemented Page 1 0800H
as static RAM. All implemented banks
contain SFRs. Some frequently used SFRs OFFFH
On-chip program
from one bank are mirrored in another bank memory Page 2 1000H
for code reduction and quicker access, as it
is not necessary to set the RP1 and RPO bits 17FFH
to a specific value using instructions, while Page 3 1800H
accessing these registers every time.

1FFFH
Table 23.6 Selection of particular bank in data
memory
Fig. 23.35 Program memory map and stack
in the PIC16F877
RP1:RP0 Selected bank
BankO
JH- Bank 1
.10 - Bank 2
n Bank 3
Figure 23.36 shows the register file map of the PIC16F877, showing the SFRs and
general-purpose registers.
General-purpose register file The register file can be accessed either directly
or indirectly through the file select register (FSR), as shown in Fig. 23.37. In the
direct addressing mode, the RP1 and RPO bits along with the seven bits in the
opcode of the instruction, select one of the register files. In indirect addressing
mode, the content of the FSR register along with the IRP bit is used for selecting
one of the registers. The bit IRP is located in the seventh bit of the status register.
File address File address File address File address
Indirect address* OOH Indirect address* 80H Indirect address* 100H Indirect address* 180H
TMRO 01H OPTIONJREG 81H TMRO 101H OPTION-REG 181H
PCL 02H PCL 82H PCL 102H PCL 182H
STATUS 03H STATUS 83H STATUS 103H STATUS 183H
FSR 04H FSR 84H FSR 104H FSR 184H
PORTA 05H TRISA 85H 105H 185H
PORTB 06H TRISB 86H PORTB 106H TRISB 186H
PORTC 07H TRISC 87H 107H 187H

.. ■. -
PORTD' 08H TRISD1 88H 108H 188H
: : ... ■ : ■
PORTE' 09H TRISE’ 89H 109H 189H
PCLATH OAH PCLATH 8AH PCLATH 10AH PCLATH 18AH

INTCON OBH INTCON 8BH INTCON 10BH INTCON 18BH
PIR1 OCH PIE1 8CH EEDATA 10CH EECON1 18CH
PIR2 ODH PIE2 8DH EEADR 10DH EECON2 18DH
TMR1L OEH PCON 8EH EEDATH 10EH RESERVED2 18EH
TMR1H OFH 8FH EEADRH 10FH RESERVED2 18FH
T1CON 10H 90H 110H 190H
TMR2 11H SSPCON2 91H 111H 191H
T2CON 12H PR2 92H 112H 192H
SSPBUF 13H SSPADD 93H 113H 193H
SSPCON 14H SSPSTAT 94H 114H 194H
CCPR1L 15H 95H 115H 195H
CCPR1H 16H 96H General-purpose General-purpose
' . ■ • • 116H 196H
register register
CCP1CON 17H 97H 16 bytes 117H 16 bytes 197H
L
RCSTA 18H TXSTA 98H 118H 198H
TXREG 19H SPBRG 99H 119H 199H
RCREG 1AH 9AH 11AH 19AH
CCPR2L 1BH 9BH 11BH 19BH
CCPR2H 1CH CMCON 9CH 11CH 19CH
CCP2CON 1DH CVRCON 9DH 11DH 19DH
ADRESH 1EH ADRESL 9EH 11EH 19EH
ADCONO 1FH ADCON1 9FH 11FH 19FH
20H AOH 120H 1A0H
General-purpose General-purpose General-purpose
register register register
General-purpose 80 bytes 80 bytes 80 bytes
EFH 16FH 1EFH
register
FOH 170H 1F0H
96 bytes
. Accesses Accesses Accesses
70H-7FH 70H-7FH 70H-7FH
7FH FFH 17FH 1FFH

BankO Bank 1 Bank 2 Bank 3
J Unimplemented data memory locations, read as 'O' Note: 1. These registers are not implemented on the PIC16F876A.
• Not a physical register 2. These registers are reserved; maintain these registers dear.
Fig. 23.36 Register file map of the PIC16F877

Direct addressing Indirect addressing

RP1 RPO 6 From opcode 0 IRP 7 FSR register 0
Bank select Location select Bank select Location select
Fig. 23.37 Direct/indirect addressing in PIC16F877
To use indirect addressing to access a particular register in the register file, the
IRP bit and the FSR register must first be loaded with the value corresponding to
the address of the particular register. For example, to access the register with the
address 120H, the IRP bit is loaded with 1 (the MSB of the address) and FSR is
loaded with the value 20H. To access the content of the register through indirect
addressing, INDF (indirect through FSR) is used in the instruction. For example,
to clear the content of the register with the address 120H using indirect addressing,
the following instructions are used:
BSF STATUS. IRP ; Set the IRP bit in the status register.
MOVLW H’20 ; Move the 1i teral 20H to W.
MOVWF FSR ; Move the content of W to FSR.
CLRF INDF : Clear th e content of the register with the
address 120H.
Special function registers The SFRs are registers used by the CPU and
peripheral modules in the PIC for controlling the desired operation of the device.
These registers are implemented as static RAM. The SFR STATUS is discussed
here in detail. The bits in the STATUS register and their meaning are shown in
Fig. 23.38. The STATUS register contains the different flags (C, Z, DC, TO*, and
PD*) that are affected during the execution of the instructions.
23.9.5 Assembly Language Programming of PIC16F877

Let us see some of the assembly language programs (ALPs) that can be executed
in the PIC16F877. While writing the ALP using the assembler, the EQU directive
is used to assign a value to a symbol and the ORG directive is used to indicate the
starting address of the program. The directive END is used to indicate the end of
the program. The symbols H’ and B’ are used to indicate hexadecimal and binary
numbers, respectively. When the file register is the destination in an instruction,
‘F* is used and when the W register is the destination in an instruction, ‘W’ is
used. The first column in the program is reserved for indicating the labels; the
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RPO TO PD Z DC C
bit 7 bitO
bit 7 IRP: Register bank select bit (used for indirect addressing)
1 = Bank 2, 3 (100H-1FFH)
0 = Bank 0,1 (00H-FFH)
bit 6-5 RP1 :RPO (Register bank select bits (used for direct addressing)
11 = Bank 3 (180H-1FFH)
10 = Bank 2 (100H-17FH)
01 = Bank 1 (80H-FFH)
00 = Bank 0 (00H-7FH)
Each bank is 128 bytes
bit 4 TO: Time out
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
(for borrow, the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding
the two's complement of the second operand. For rotate (RRF, RLF)
instructions, this bit is loaded with either the high, or low order bit of
the source register.
Legend—R/W-n
R = Readable bit W = Writable bit PoR = Power on reset
n = Value at POR ‘T = Bit is set ‘0’= Bit is cleared * = Bit is unknown
Fig. 23.38 Bits in STATUS register located at addresses 03H, 83H, 103H, and 183H
mnemonics are present from the second column onwards. The statement written
after the semicolon in each instruction is the comment.
Example 23.1:
Write a PIC16F877 ALP to add two data, 90H and 8FH, and store the result in the
internal register file in the addresses 5OH (least significant byte) and 51H (most
significant byte).
L0W_BYTE EQU H’50 : Assign the address 50H to the lower_byte.
HIGH-BYTE EQU H’51 ; Assign the address 51H to the higher byte,
STATUS EQU 3 ; The address of the status register is 03H.
C EQU 0 ; The bit address of the carry (C) is 0.
ORG 0 ; The program starts at address 0 in the
flash memory.
MOVLW H’90 : Move the value 90H to W.
ADDLW H’8F : Add 8FH to W.
MOVWF LOW_BYTE ; Store the result in W as the lower-order

byte.
BTFSC STATUS. C ; Check whether the carry is 0; if 0, skip
the next instruction.
GOTO CARRY : Go to CARRY.
MOVLW H’O ; Move 0 to W, as the carry is 0.
MOVWF HIGH-BYTE ; Store the result in W as the higher-order
byte.
GOTO END1 ; Go to END1.
CARRY: MOVLW H’l ; Move 1 to W, as the carry is 1.
MOVWF HIGH-BYTE ; Store the result in W as the higher-order
byte.
END1: GOTO END1 ; Go to END1.
Example 23.2:
Write a PIC16F877 ALP to multiply two data, 85H and 1OH, and store the result
in the internal register file in the addresses 40H (least significant byte) and 41H
(most significant byte).
The program is based on repeated addition. By adding DATA1 repeatedly, i.e.,
as many times as the value of DATA2, the result is obtained.
DATA1 EQU H’85 ; DATA1 is equal to 85H.
DATA2 EQU H’10 ; DATA2 is equal to 10H.
RE61 EQU H ’ 30 ; The address of REG1 is 30H
REG2 EQU H’31 ; The address of REG2 is 31H.
L0W_BYTE EQU H’40 : The address of L0W_BYTE is 40H.
HIGH-BYTE EQU H’41 : The address of HIGH_BYTE is 41H.
STATUS EQU 3 ; The address of the status register
is 03H.
C EQU 0 ; The bit address of the carry (C) is
0.
ORG 0 : The program starts at address 0 in
the flash memory.
MOVLW DATA1 : Move DATA1 to W.
MOVWF REG1 : Move the data in W to REG1.
MOVLW DATA2 : Move DATA2 to W.
MOVWF REG2 ; Move the data in W to REG2.
CLRF LOW_BYTE ; Clear the contents of LOW_BYTE.
CLRF HIGH-BYTE : Clear the contents of HIGH_BYTE.
MOVLW H’O : Clear W.
ADD: ADDWF REG1. W ; Add DATA1 to W and store the result
1 n W.
BTFSS STATUS.C ; If carry is 1. skip the next
i nstructi on.
GOTO NO_CARRY : Go to NO-CARRY.
INCF HIGH-BYTE, F ; Increment the contents of high_byte.

NO_CARRY: DECFSZ REG2, F ; Decrement DATA2 in REG2; if the
result is 0, skip the next
instruction.
GOTO ADD ; Go to ADD.
MOVWF LOW_BYTE : Store the lower-order byte of the
result in W in LOW_BYTE.
END1: GOTO END1 ; Go to END1.
Example 23.3:
Interface an 8-bit bipolar DAC with the PIC16F877 and write ALPs to generate
a square wave and a sine wave, and to vary the frequency and amplitude of the
signals.
Figure 23.39 shows the simplified
layout for interfacing an 8-bit bipolar DAC
with the PIC16F877. The 8-bit digital data
to the DAC is sent through port B of the
PIC16F877. If the digital data sent to the
DAC is OOH, the analog output voltage (Vo)
from the DAC will be -5 V. If the digital
data sent to the DAC is linearly increased,
the output voltage (Vo) linearly increases
from -5 V towards +5 V. When the digital
data is FFH, the analog output voltage from Fig. 23.39 Simplified layout for
the DAC will be +5 V. Let a 4 MHz crystal interfacing DAC with the 16F877
be connected to the PIC16F877. Under
this condition, the PIC instructions that need one instruction cycle for execution
get executed in 1 ps and those instructions that need two instruction cycles for
execution get executed in 2 ps.
(i) ALP to generate a square wave of 1 KHz with amplitude of 5 V
The number within brackets in the program indicates the number of instruction
cycles needed to execute the instruction. First, the value OOH is sent to the DAC
and the PIC waits for 0.5 ms. Then the value FFH is sent to the DAC and the
PIC waits for 0.5 ms. This is repeated to produce a square wave of 1 kHz with an
amplitude of 5 V.
PORTB EQU 6 ; The address of PORTB is 06.
STATUS EQU 3 : The address of STATUS is 03.
Z EQU 2 ; The address of the Z bit is 02.
COUNT EQU H’7C ; COUNT is equal to 7CH.
DATA1 EQU H’FF : DATA1 is equal to FFH.
REG1 EQU H’30 : The address of REG1 is 30H.
ORG 0 : The program starts at address 0 in
the flash memory.
START: MOVLW H’0 : Move OOH to W.
MOVWF PORTB Move the content of W to PORTB.

CALL DELAY Call the subroutine delay.
MOVLW DATA1 Move DATA1 to W.
MOVWF PORTB Move the content of W to PORTB.
CALL DELAY Call the subroutine delay.
GOTO START Go to start to produce the next
cycle; Delay subroutine
DELAY: MOVLW COUNT Move count to W. (1)
MOVWF REG1 Move the content of W to REG1. (1)
COUNTDOWN: DECF REG1, F Decrement REG1 and store the result
in REG1. (1).
BTFSS STATUS, Z ; If the Z flag is set, skip the next
instruction. (l)/(2)
GOTO COUNT-DOWN ; Go to COUNT_DOWN. (2)
RETURN : Return from subroutine. (2)
END ; Terminate program execution.
For 1 kHz frequency, the on-time is 500 ps and off-time is 500 ps.
on-time = Total number of instruction cycles executed in on-time
x Time for one instruction cycle
500 ps = (1 + 1 + (count - 1) (1 + 1 + 2) + (1 + 2) + 2) x (1 ps)
= 7 ps + (count - 1) (4) ps
Therefore, count = 123 = 7CH
Varying the amplitude and frequency of the square wave By changing the
value of COUNT in the program, using this calculation, the frequency of the
square wave can be varied. By changing the value of DATA1 in the program, the
amplitude of the square wave can be varied. For example, if the value of DATA1
is H’7F (which is half of H’FF), the amplitude of the square wave signal is
2.5 V.
(ii) ALP to generate sine wave of 1 kHz with amplitude of 5 V
To generate a sine wave using a DAC, the number of samples in one cycle
of the sine wave is first chosen, based on the accuracy needed (more number of
samples in a cycle gives higher accuracy). The samples are sent to the DAC one
by one, with a delay time between the samples. The delay time is based on the
frequency of the signal. If the frequency of the signal is low, the delay time will be
high; if the frequency is high, the delay time will be low.
Let us assume that we want to generate a sine wave of 1 kHz with an amplitude
of 5 V. Let the number of samples in a cycle be 20. This means that each sample
must be taken with an angle interval of 18°, which is obtained by dividing the total
angle for one cycle of sine wave (360°) by the total number of samples in a cycle.
The 20 analog samples in a cycle and their corresponding digital value to be sent
to the DAC are shown in Table 23.7. The analog value is obtained by substituting
the angle 0 in the expression for the sine wave, 5sin0.
Table 23.7 Analog samples and their digital values
Sample no. Angle in degree (0) Analog value of the sample Digital value to be sent to the
(V) DAC
1 0 0 7FH
2 18 1.55 A7H
3 36 2.94 CAH
4 54 4.05 E6H
5 72 4.76 F8H
6 90 5 FFH
7 108 4.76 F8H
8 126 4.05 E6H
9 144 2.94 CAH
10 162 1.55 A7H
11 180 0 7FH
12 198 -1.55 58H
13 216 -2.94 35H
14 234 -4.05 18H
15 252 -4.76 06H
16 270 -5 OOH
17 288 -4.76 06H
18 306 -4.05 18H
19 324 -2.94 35H
20 342 -1.55 58H
The digital value corresponding to the analog value of the sample during the
positive half cycle is calculated using the following formula:
Digital value in decimal form = 127 + (255/10) x analog value of the sample
(23.1)
In Equation 23.1, the value 127 represents the digital value corresponding to
the analog voltage of 0 V. The factor (255/10) represents the increment in the
digital value corresponding to a 1 V increment in the analog signal, since the
analog voltage range of 10 V (-5 V to 5 V) corresponds to the digital value range
of 255 (FFH to OOH) in the DAC.
The digital value corresponding to the analog value of the sample during the
negative half cycle is calculated using the following formula (since the analog
value is negative during the negative half cycle):
Digital value in decimal form = (5 + analog value of the sample) x (255/10)
(23.2)
Program
REG1 EQU H’50
REG2 EQU H’51
COUNT EQU H’OD
ORG 0 ; Program starts

START: MOVLW H’7F ; Store the digital value of the 20 samples
in the register file from the address H ’ 60.
MOVWF H’60
MOVLW H’A7
MOVWF H’61
MOVLW H’CA
MOVWF H’62
MOVLW H’E6
MOVWF H’63
MOVLW H’F8
MOVWF H’64
MOVLW H’FF
MOVWF H’65
MOVLW H’F8
MOVWF H’66
MOVLW H’E6
MOVWF H’67
MOVLW H’CA
MOVWF H’68
MOVLW H’A7
MOVWF H’69
MOVLW H’7F
MOVWF H’6A
MOVLW H’58
MOVWF H’6B
MOVLW H’35
MOVWF H’6C
MOVLW H’18
MOVWF H’6D
MOVLW H’06
MOVWF H’6E
MOVLW H’OO
MOVWF H’6F
MOVLW H’06
MOVWF H’70
MOVLW H’18
MOVWF H’71
MOVLW H’35
MOVWF H’72
MOVLW H’58
MOVWF H’73
; Send samples of the sine wave one after another to the DAC.
START: MOVLW H’14 : The total number of samples is stored
in REG1. (1)
MOVWF REG1 : (1)

MOVLW H’60 ; FSR is loaded with the address of the
first sample. (1)
MOVWF FSR : (1)
NEXT_SAMPLE: MOVE INDF.W ; Load the digital value of one sample
in W. (1)
MOVWF PORTB ; Send the content of W to PORTB. (1)
CALL DELAY ; Call the subroutine DELAY. (2)
INCF FSR, F ; Increment FSR to point to the next
sample in the register file. (1)
DECFSZ REG1, F ; Decrement REG1 when one sample is
sent. (1)/(2)
GOTO NEXT-SAMPLE ; If REG1 is not 0, go to NEXT-SAMPLE. (2)
GOTO START ; Go to START to produce the next
cycle of the sine wave. (2)
; DELAY subroutine
DELAY: MOVLW COUNT ; Move COUNT to W. (1)
MOVWF REG2 ; Move the content of W to REG2. (1)
COUNT_DOWN: DECFSZ REG2, F; Decrement REG2 and store the result
in REG2. (l)/(2)
GOTO COUNT DOWN ; Go to COUNT_DOWN. (2)
RETURN ; Return from subroutine. (2)
END
The count used in the delay subroutine is calculated using the following concept:
The total delay time between two samples sent to the DAC is the time spent in
the execution of the delay subroutine, plus the time spent in taking a sample value
from the register file, sending it to the DAC, calling the delay subroutine, and
checking whether all samples are sent, so as to begin the next cycle of the sine
wave. Let the first part of the total delay time be denoted by ‘m’ and the second
part by ‘n’.
Total delay time = Td = m + n (23.3)
The values of m and n are calculated as follows, with the approximation
that the DECFSZ instruction takes one instruction cycle for execution. This
approximation is valid because the condition in the DECFSZ instruction is satisfied
only once in one cycle of the sine wave in the main program, and only once in the
delay subroutine (when the count becomes zero, during which time it takes two
instruction cycles for execution). For a more accurate calculation of the count, this
factor must be considered and another 6 cycles (first 4 cycles at the label START
in the program and 2 cycles due to the GOTO START instruction at the end of the
start loop) must also be included in each cycle of the sine wave.
m = (1 + 1 + count (1 + 2) + 2) x time for one instruction cycle (23.4)
n = (l + l+ 2+ l + l + 2)x time for one instruction cycle (23.5)
Since the frequency (f) of the sine wave is 1 KHz, its time period (T) is 1 ms.
Since there are 20 samples in a cycle, the time between sending two samples (Td)
to the DAC must be 1ms divided by 20, which gives a value of 50 ps. If each
instruction cycle takes 1 ps, then the count is calculated as follows:

n = 8 x 1 ps = 8 ps using Equation (23.5)
Therefore, m = Td - n = 50 - 8 = 42 ps using Equation (23.3)
Using Equation (23.4), m = (4 + (3 x count)) x 1 ps = 42 ps
Therefore, count = 13 = ODH
Varying the amplitude and frequency of the sine wave By changing the value
of COUNT in the program using these calculations, the frequency of the sine wave
can be varied. By changing the digital value of the samples stored in the register file
in the program, the amplitude of the sine wave can be varied. For example, if the
amplitude of the sine wave is 2.5 V, the analog value of the samples is calculated
using the relation 2.5sin9 for different values of 9, and their corresponding digital
values are stored in the register file.
The delay time in these programs is created using the software delay technique.
It can also be created using the on-chip timer in the PIC. It is left to the reader to
write the programs using the on-chip timer to generate different waveforms.
POINTS TO REMEMBEtf
■ The 80186 has the same architecture as the 8086, but it also has more on-chip peripherals
such as three timers, two DMA controllers, one interrupt controller, and peripheral and
memory select logic.
■ The protected mode operation was introduced in the 80286 by Intel; it exists in all the
Intel processors that were developed after the 80286 such as the 80386, the 80486, and
the Pentium.
■ There are four privilege levels present in protected mode operation—levels 00, 01, 02,
and 03. Level 00 is considered the highest privilege level and 11 the lowest.
■ A segment is accessed using a segment descriptor, which is present either in the GDT
or the LDT in the protected mode.
■ There is only one GDT and as many LDTs as there are tasks currently being executed
by the CPU in the 80X86-based system.
■ The segment descriptor contains the complete details of a segment such as base address,
size, access rights, and other information regarding the segment.
■ With the help of the task register and the task state segment, task switching is easily
accomplished in all the microprocessors from the 80286 to the Pentium.
■ The register size is increased to 32 bits and there are two additional segments, FS and
GS, present in the range of processors from the 80386. In addition, they can access 4
GB of main memory.
■ The paging mechanism introduced in the 80386 makes the handling of virtual memory
easier.
• The 80486 microprocessor has an on-chip 8 KB unified cache and floating point unit.
• The Pentium is the first two-issue superscalar processor introduced by Intel with the
help of its two-integer U and V pipelines.
• The floating-point pipeline in the Pentium makes the operation on floating-point
numbers faster.
■ The PIC16F877 is an 8-bit microcontroller from Microchip corporation, which uses an

RISC type CPU. It has only 35 single-word instructions and more on-chip peripherals.
It can be used for embedded applications.
KEY TERMS
BOR It helps reset the microcontroller when the supply voltage falls below a specified
value.
Dual cache This refers to the presence of two cache memories, one for code and the
other for data.
EEPROM It is a non-volatile memory that can be electrically erased and programmed.
Flash memory It is a non-volatile memory and a specific type of EEPROM that can be
electrically erased programmed in large blocks.
FPU It is used to perform floating point operations quickly.
FSR It is used for indirect addressing in the PIC.
GDT It contains the segment descriptor of those segments (that belong to the operating
system, the compiler, the assembler, etc.) that can be used by all programs in a multi-user
system. There is only one GDT in the system.
GDTR It holds the base address of the GDT in the memory.
I2C It is a standard for serial communication among many I/O devices and
microcontrollers.
IDT The interrupt descriptors for the different interrupt types, starting from the interrupt
type OOH, are successively stored in the IDT present in the memory.
IDTR It holds the base address of the IDT in the memory.
LDT It contains the segment descriptor of those segments that belong to a particular
user or task. In a multi-user or a multi-tasking environment, there are as many LDTs as the
number of users or the number of tasks handled by the CPU.
LDTR It holds the base address of the LDT in the memory.
Linear address When paging is enabled, the address obtained by adding the base address
from the segment descriptor and the offset address is called linear address.
Multitasking It is the ability of a CPU to execute many user programs simultaneously.
Paging It is an efficient method to handle virtual memory, in which a segment is divided
in to equal sized pages. Intel uses a page size of 4 KB.
PD It holds the page directory entry (PDE) of different page tables in the memory. The
base address of the PD is indicated by the control register CR3.
PDE It contains the base address of a page table and control information related to that
page table in the memory.
Physical address It is the address assigned to each location in the physical memory such
as RAM or ROM.
Pipeline operation It is a type of operation that simultaneously performs different stages
of an operation on different instructions in a pipeline by overlapping the fetching, decoding,
and execution of the different instructions.
Pointer In PVAM mode, the 16-bit selector and the 16/32-bit offset are combined to
form a 32/48-bit pointer type data.
Postscaler It is a hardware used to divide the output clock frequency of the timer by
some factor.
Prescaler It is a hardware used to divide the input clock frequency of the timer by some
factor.
Protected virtual address mode (PVAM) or protected mode addressing In this
mode of addressing, the 80286 can access 16 MB of physical memory and 1 GB of virtual
memory, whereas all processors from the 80386 to the Pentium can access 4 GB of physical
memory and 64 TB of virtual memory.
PT It holds the page table entry (PTE) of different pages in the memory.
PTE It contains the base address of a page and control information related to that page
in memory.
PWM It is a type of modulation in which the duty cycle of the output square pulse is
varied.
Real mode addressing In this mode addressing, the range of microprocessors from the
80286 to the Pentium can access only 1 MB of physical memory, similar to the 8086.
Register file This is the collection of registers that is in the data RAM of the PIC.
Segment descriptor It is an eight-byte entry in the LDT or the GDT, which contains the
physical base address for a segment, the size of the segment, and the access rights allotted
to the segment.
Selector In protected mode, the 16-bit value in a segment register is called selector; it is
used to select one of the segment descriptors in the LDT or the GDT.
SPI It is a standard for serial communication and can be used for I/O expansion in a
microcontroller.
Task switching When the time slot for the execution of the current task is over, the
current state of the CPU is saved in a TSS and then the CPU state for the next task is loaded
into the CPU registers from its TSS and execution begins. This is called task switching.
TLB It is a small cache memory that contains the recently used linear addresses and their
corresponding physical addresses, used with the paging mechanism.
TR It is the register that is used to select one of the TSS descriptors from the GDT.
TSS It is the segment in which the current state of the CPU is saved during task
switching.
Two-issue superscalar execution In this type of execution, two instructions are
simultaneously decoded and executed.
Unified cache It is a cache that contains both code and data.
Watchdog timer It is a timer used for resetting the microcontroller when it hangs while
executing the software.
REVIEW QUESTIONS
1. What are the various internal components present in the 80186?

2. What is the function of the chip select logic in the 80186?
3. What are the different uses of the timers in the 80186?
4. What are the new instructions added in the 80186?

5. Explain the architecture of the 80186 with a neat block diagram.
6. How many address lines and data lines are present in the 80286?
7. How many privilege levels are present in the protected mode operation of the 80286?
For what type of service is each privilege level assigned?
8. What is a segment descriptor?
9. Write the format of the 80286 segment descriptor.
10. What is the function of the access rights byte in the segment descriptor?
11. What is the function of the base address and the limit fields in the segment
descriptor?
12. What is the maximum size of a segment in the protected mode operation of the
80286?
13. What are the different fields present in a segment register during the protected mode
operation of the 80286? Write their function.
14. With a neat block diagram, describe the architecture of the 80286.
15. Explain the protected mode operation of the 80286 in detail, indicating the concept of
the segment descriptors LDT and GDT.
16. Explain with necessary diagrams, the access of an operand from a data segment by the
80286, if its descriptor is in i) GDT ii) LDT.
18. What are the internal components present in the 80386 functional block diagram?
20. Write the format of the 80386 segment descriptor.
21. What is the maximum size of a segment in the 80386 during protected mode
operation?
22. What is the function of the Byte Enable signals BE7-BE0 in the Pentium?
23. Whatis the function of PE and PG in the control register CRO in the 80386?
24. What is the function of the control registers CR2 and CR3 in the 80386?
25. Write the format of PDE and PTE.
26. What is the function of TLB?
28. Write the different registers in the 80386 along with their function.
29. Explain the different addressing modes in the 80386 during its protected mode
operation with necessary diagrams.
30. With neat diagrams, describe the paging mechanism in the 80386 in detail.
32. Write the main internal units of the 80486.
33. What is the function of PCD and PWT bits in the PDE and PTE of the 80486?
35. What is meant by two-issue superscalar execution? From which Intel processor was
this concept introduced?
36. How many address lines and data lines are present in the 80586 and the Pentium?
37. Which instructions in the Pentium are considered as simple instructions?
38. What are the conditions to be satisfied for the simultaneous issue of two instructions
in the Pentium integer pipelines?
39. What are the different hazards in pipeline operation?
40. What is meant by the data hazards RAW and WAW?

41. Write the different stages present in the integer pipeline of the Pentium.
42. Mention the different stages present in the floating-point pipeline of the Pentium.
43. What is the function of the Byte Enable signals BE7-BE0 in the Pentium?
44. Write the salient features of the Pentium Pro processor.
45. Compare the Pentium III and Pentium 4 processors.
46. With a neat block diagram, describe the architecture of the Pentium.
47. Explain integer and floating-point pipeline operation in the Pentium in detail.
48. Describe the features of the advanced versions of the Pentium microprocessor in
detail.
49. What are the different memories present in the PIC16F877?
50. Name the different timers and their features in the PIC16F877.
51. Which features of the PIC16F877 can be used for serial communication?
52. What is meant by brown-out reset?
53. What is the function of a watchdog timer?
54. Name the different ports in the PIC16F877.
55. Write the features of different PIC microcontrollers that come under the 16F87X
family.
56. Draw the block diagram of the PIC16F877 and briefly explain its internal components.
57. Explain direct and indirect addressing of data memory in the PIC 16F877.
58. How is the flash program memory organized in the PIC16F877?
59. Write the function of different flags in the STATUS register of the PIC16F877.
THINK AND ANSWER .
1. What is the need for protected mode operation in a microprocessor?

2. What is meant by real addressing mode in the 80286?
3. How can the 80286 be made to work in the protected mode?
4. Write the differences between GDT and LDT.
5. What is the maximum size of the virtual memory in the 80286?
6. What is meant by task switching and where is it needed?
7. How is task switching done in the 80286?
8. What is the maximum number of descriptors that can be stored in the GDT or in each
LDT?
9. What is the maximum size of an LDT and a GDT in terms of bytes?
10. What is the need for paging mechanism in the 80386?
11. What is the maximum size of the virtual memory in the 80386?
12. What are the advantages of the 80486 over the 80386?
13. Why are the address lines A0 and Al not present in the 80486?
14. When can two successive instructions not be simultaneously executed in the integer
pipelines of the Pentium while executing a program?
15. What is the time taken to execute an instruction in the PIC16F877, if a 4 MHz crystal
is used?
16. If the RP1 and RPO bits have the values 0 and 1, respectively, which bank of data
memory is accessed in the PIC16F877?
17. Write an ALP to generate a triangular wave having an amplitude of 5 V and a frequency
of 1 KHz, by interfacing an 8-bit bipolar DAC with the PIC.
A |
APPENDIX A1
8085 INSTRUCTION SET

A.1 DATA TRANSFER INSTRUCTIONS
Note: No flags are affected.
Mnemonics Machine T-states Mnemonics Machine T-states
code code
Move MOV E, B 58 4
MOV A, A 7F 4 MOV E, C 59 4
MOV A, B 78 4 MOV E, D 5A 4
MOV A, C 79 4 MOV E, E 5B 4
MOV A, D 7A 4 MOV E, H 5C 4
MOV A, E 7B 4 MOV E, L 5D 4
MOV A, H 7C 4 MOV E, M 5E 7
MOV A, L 7D 4
MOV A, M 7E 7 MOV H, A 67 4
MOV H, B 60 4
MOV B, A 47 4 MOV H, C 61 4
MOV B,B 40 4 MOV H, D 62 4
MOV B, C 41 4 MOV H, E 63 4
MOV B, D 42 4 MOV H, H 64 4
MOV B, E 43 4 MOV H, L 65 4
MOV B, H 44 4 MOV H, M 66 7
MOV B, L 45 4______
MOV B, M 46 7 MOV L, A 6F 4
MOV L. B 68 4
MOV C, A 4F 4 MOV L, C 69 4
MOV C,B 48 4 MOV L, D 6A 4
MOV c,c 49 4 MOV L, E 6B 4
MOV rc,D 4A 4 MOV L, H 6C 4
MOV C,E 4B 4 MOV L, L 6D 4
MOV C, H 4C 4 MOV L,M 6E 7
MOV C,L 4D 4
MOV C, M 4E 7______ MOV M, A 77 7
MOV M, B 70 7
D, A 57 4 MOV M, C 71 7
MOV
D.B 50 4 MOV M, D 72 7
MOV
D.C 51 4 MOV M, E 73 7
MOV
D,D 52 4 MOV M, H 74 7
MOV
D,E 53 4 MOV M, L 75 7
MOV
D,H 54 4
MOV
D, L 55 4 MVI A, byte 3E 7
MOV
D, M 56 7 MVI B, byte 06 7
MOV
MVI C, byte 0E 7
E, A 5F 4 MVI D, byte 16 7
MOV
Mnemonics Machine T-states Mnemonics Machine T-states

code code
MVI E, byte IE 7 Load/store
MVI H, byte 26 7 LDAX B 0A 7
MVI L, byte 2E 7 LDAX B 1A 7
MVI M, byte 36 10 LHLD addr 2A 16
LDA addr 3A 13
Load immediate STAX B 02 7
LXI B, dble 01 10 STAX B 12 7
LXI D. dble 11 10 SHLD addr 22 16
LXI H, dble 21 10 STA addr 32 13
LXI SP, 31
10 4
dble XCHG EB
A.2 ARITHMETIC INSTRUCTIONS Mnemonics Machine T- Flags

code states affected
Mnemonics Machine T- Flags SBB B 98 4 All flags
code states affected SBB C 99 4 All flags
Add SBB D 9A 4 All flags
ADD A 87 4 All flags SBB E 9B 4 All flags
ADD B 80 4 All flags SBB H 9C 4 All flags
ADD C 81 4 All flags SBB L 9D 4 All flags
ADD D 82 4 All flags SBB M 9E 7 All flags
ADD E 83 4 All flags
ADD H 84 4 All flags Double add
ADD L 85 4 All flags DAD B 09 10 Only Carry
ADD M 86 7 All flags DAD D 19 10 Only Carry
DAD H 29 10 Only Carry
ADC A 8F 4 All flags DAD SP 39 10 Only Carry
ADC B 88 4 All flags
ADC C 89 4 All flags Increment
ADC D 8A 4 All flags INR A 3C 4 All except
ADC E 8B 4 All flags Carry
ADC H 8C 4 All flags INR B 04 4 All except
ADC L 8D 4 All flags
Carry
ADC M 8E 7 All flags
INR C OC 4 All except
Carry
Subtract
INR D 14 4 All except
SUB A 97 4 All flags
Carry
SUB B 90 4 All flags
INR E IC 4 All except
SUB C 91 4 All flags
All flags Carry
SUB D 92 4
All flags INR H 24 4 All except
SUB E 93 4
94 4 All flags Cany
SUB H
4 All flags INR L 2C 4 All except
SUB L 95
SUB M 96 7 All flags Cany
INR M 34 10 All except
SBB A 9F 4 All flags Cany
APPENDIX A—8085 INSTRUCTION SET 733
Mnemonics Machine T- Flags Mnemonics Machine T- Flags

code states affected code states affected
16-bit increment 16-bit decrement
INX B 03 6 No flags DCX B OB 6 No flags
INX D 13 6 No flags DCX D IB 6 No flags
INX H 23 6 No flags DCX H 2B 6 No flags
INX SP 33 6 No flags DCX SP 3B 6 No flags
Decrement Specia
DCR A 3D 4 All except DAA 27 4 All flags
Cany CMA 2F 4 No flags
DCR B 05 4 All except STC 37 4 Only Carry
Carry CMC 3F 4 Only Carry
DCR C 0D 4 All except
Carry Rotate
DCR D 15 4 All except RLC 07 4 Only Carry
Carry RRC OF 4 Only Carry
DCR E ID 4 All except RAL 17 4 Only Carry
Carry RAR IF 4 Only Carry
DCR H 25 4 All except
Carry Immediate
DCR L 2D 4 All except ADI Byte C6 7 All flags
Carry ACI Byte CE 7 All flags
DCR M 35 10 All except SUI Byte D6 7 All flags
Carry SBI Byte DE 7 All flags
A.3 LOGICAL INSTRUCTIONS Mnemonics Machine In Flags

code states affected
Mnemonics Machine T- Flags ORA C Bl 4 All flags
code states affected ORA D B2 4 All flags
ANA A A7 4 All flags ORA E B3 4 All flags
ANA B A0 4 All flags
ORA H B4 4 All flags
ANA C Al 4 All flags
ORA L B5 4 All flags
ANA D A2 4 All flags
ORA M B6 7 All flags
ANA E A3 4 All flags
ANA H A4 4 All flags
CMP A BF 4 All flags
ANA L A5 4 All flags
CMP B B8 4 All flags
ANA M A6 7 All flags
CMP C B9 4 All flags
CMP D BA 4 All flags
XRA A AF 4 All flags
A8 4 All flags CMP E BB 4 All flags
XRA B
XRA C A9 4 All flags CMP H BC 4 All flags
XRA D AA 4 All flags CMP L BD 4 All flags
XRA E AB 4 All flags CMP M BE 7 All flags
XRA H AC 4 All flags
XRA L AD 4 All flags Immediate
XRA M AE 7 All flags ANI Byte E6 7 All flags
XRI Byte EE 7 All flags
ORA A B7 4 All flags ORI Byte F6 7 All flags
ORA B B0 4 All flags CPI Byte FE 7 All flags
A.4 BRANCHING INSTRUCTIONS Mnemonics Machine T-states

code
Note: No flags are affected. CP adr F4 9/18
Mnemonics Machine T-states CM adr FC 9/18
code
Jump Return _____________________
JMP adr C3 10 RET C9 10
JNZ adr C2 7/10 RNZ CO 6/12
JZ adr CA 7/10 RZ C8 6/12
JNC adr D2 7/10 RNC DO 6/12
JC adr DA 7/10 RC D8 6/12
JPO adr E2 7/10 RPO E0 6/12
JPE adr EA 7/10 RPE E8 6/12
JP adr F2 7/10 RP F0 6/12
JM adr FA 7/10 RM F8 6/12
PCHL E9 6
Restart
Call RST0 C7 12
CALL adr CD 18 RST 1 CF 12
CNZ adr C4 9/18 RST 2 D7 12
CZ adr CC 9/18 RST 3 DF 12
CNC adr D4 9/18 RST 4 E7 12
CC adr DC 9/18 RST 5 EF 12
CPO adr E4 9/18 RST 6 F7 12
CPE adr EC 9/18 RST 7 FF 12
A.5 I/O AND MACHINE CONTROL Mnemonics Machine T-states

INSTRUCTIONS code
SPHL F9 12
Note: No flags are affected.
Mnemonics Machine T-states Input/output
code OUT byte D3 10
Stack-related IN byte DB 10
PUSHB C5 12
PUSHD D5 12 Control
PUSHH E5 12 DI F3 4
PUSH PSW F5 12 EI FB 4
POPB Cl 12 NOP 00 4
POPD DI 12 HLT 76 5
POPH El 12
POP PSW Fl 12 Interrupt-relatec
RIM 20 4
XTHL E3 12 SIM 30 4
■ ... BAl

B.1 8051 INSTRUCTIONS AND ADDRESSING MODES
B.1.1 Data Transfer Instructions
Addressing modes
Mnemonics Operation
MOV A, <src> A = <src> y/ a/ y/ a/
MOV <dest>, A <dest> = A yj y/
MOV <dest>, <src> <dest> = <src> y/ y/ y/ y/
DPTR = 16-bit yj
MOV DPTR, #datal6
immediate data
INC SP:
PUSH <src>
MOV ‘@SP’, <scr>
MOV <dest>, ‘@SP’: y/
POP <dest>
DEC SP
Accumulator and yj y/
XCH A, <byte>
<byte>—exchange data
Accumulator and @Ri— y/
XCHD A, @Ri
exchange low nibbles
Read 8 bits addressed
MOVX A, @Ri Only indirect addressing mode
external RAM @Ri
Write 8 bits addressed
MOVX @Ri, A Only indirect addressing mode
external RAM @Ri
Read 16 bits addressed
MOVX A, @DPTR Only indirect addressing mode
external RAM @DPTR
Write 16 bits addressed
MOVX @DPTR, A Only indirect addressing mode
external RAM @DPTR
Read program memory
MOVC A, @A+DPTR Only indexed addressing mode
at (A + DPTR)
Read program memory
MOVC A, @A+PC Only indexed addressing mode
at (A + PC)
B.1.2 Arithmetic Instructions

Addressing modes
Mnemonics Operation
ADD A, <byte> A = A + <byte> y/ y/ y/ FT
ADDC A, <byte> A = A + <byte> + C y/ T V y/
SUBB A, <byte> A = A - <byte> - C yj Al yj
INCA A = A+ 1 Accumulator only

DECA A = A- 1 Accumulator only
<byte> = <byte> + 1 yJ y/
INC <byte>
DEC <byte> <byte> = <byte> - 1 yj T
V~
MULAB B:A= B x A Accumulator only
DIV AB A = Int [A/B]; B = Mod [A/B] Accumulator only
DAA Decimal adjust accumulator Accumulator only
B.1.3 Logical Instructions

Addressing modes
Mnemonics Operation
ANL A, <byte> A = A AND <byte> yf yf V yf
ANL <byte>, A <byte> = <byte> AND A yf
ANL <byte>, #data <byte> = <byte> AND #data yf
ORL A, <byte> A = A OR <byte> yf yf yf yf
ORL <byte>. A <byte> = <byte> OR A yf
ORL <byte>, #data <byte> = <byte> OR #data yf
XRL A, <byte> A = A XOR <byte> yf yf yf yf
XRL <byte>, A <byte> = <byte> XOR A yf
XRL <byte>, #data <byte> = <byte> XOR #data yf
CLR A A = OOH Accumulator only
CLP A A = NOT A Accumulator only
RL A Rotate accumulator left 1 bit Accumulator only
Rotate accumulator left through
RLC A Accumulator only
Carry
RR A Rotate accumulator right 1 bit Accumulator only
Rotate accumulator right through
RRC A Accumulator only
Carry
B.1.4 Branching Instructions

Mnemonics Operation
SJMP rel Jump to rel addr
LJMP addr Jump to addr
AJMP 11-bit Jump to PC:addr
JMP @ A + DPTR Jump to A + DPTR
ACALLallbit Call subroutine at PC:addr
LCALL addr Call subroutine at addr
RET Return from subroutine
RETI Return from interrupt
NOP No operation
Addressing modes
Mnemonics Operation
CJNE A, <byte>, rel Jump if A <byte> yf yf
CJNE <byte>, #data, rel Jump if <byte> = #data yf yf
Decrement byte and jump if yf

DJNZ <byte>, rel yf
not zero
JZrel Jump if A = 0 Accumulator only
JNZ rel Jump if A # 0 Accumulator only
APPENDIX B—8051 INSTRUCTION SET 737
B.2 BIT MANIPULATION

INSTRUCTIONS
Mnemonics Operation
Mnemonics Operation SETB C C= 1
ANL C, bit C = C AND bit SETB bit bit = 1
ANL C, /bit C = C AND (NOT bit) CPLC C = NOT C
ORL C, bit C = C OR bit CPL bit bit = NOT bit
ORL C, /bit C = C OR (NOT bit) JC rel Jump if C = 1
MOV C, bit C = bit JNC rel Jump if C = 0
MOV bit, C bit = C JB bit, rel Jump if bit = 1
CLR C C=O JNB bit, rel Jump if bit = 0
CLR bit bit = 0 JBC bit, rel Jump if bit = 1; CLR bit
B.3 8051 INSTRUCTIONS, BYTES, AND FLAGS AFFECTED

B.3.1 Data Transfer Instructions
Instructions Opcode Bytes Flags
MOV @RO, #data 0X76 2 None
MOV @Rl,#data 0X77 2 None
MOV @RO, A 0XF6 1 None
MOV @R1, A 0XF7 1 None
MOV @RO, iram addr 0XA6 2 None
MOV @R1, iram addr 0XA7 2 None
MOV A, #data 0X74 2 None
MOV A, @RO 0XE6 1 None
MOV A, @R1 0XE7 1 None
MOV A, RO 0XE8 1 None
MOV A, RI 0XE9 1 None
MOV A, R2 0XEA 1 None
MOV A, R3 0XEB 1 None
MOV A, R4 0XEC 1 None
MOV A, R5 OXED 1 None
MOV A, R6 0XEE 1 None
MOV A, R7 OXEF 1 None
MOV A, iram addr 0XE5 2 None
MOV C, bit addr 0XA2 2 C
MOV DPTR, #datal6 0X90 3 None
MOV RO, #data 0X78 2 None
MOVRl,#data 0X79 2 None
MOV R2, #data 0X7A 2 None
MOV R3, #data 0X7B 2 None
MOV R4, #data 0X7C 2 None
MOV R5, #data 0X7D 2 None
MOV R6, #data 0X7E 2 None
MOV R7, #data 0X7F 2 None
MOV RO, A 0XF8 1 None
MOV RI, A 0XF9 1 None
MOV R2, A 0XFA 1 None
MOV R3, A 0XFB 1 None

MOV R4, A OXFC 1 None
MOV R5, A OXFD 1 None
MOV R6, A OXFE 1 None
MOV R7, A OXFF 1 None
MOV RO, iram addr 0XA8 2 None
MOV R1, iram addr 0XA9 2 None
MOV R2, iram addr OXAA 2 None
MOV R3, iram addr OXAB 2 None
MOV R4, iram addr OXAC 2 None
MOV R5, iram addr OXAD 2 None
MOV R6, iram addr OXAE 2 None
MOV R7, iram addr OXAF 2 None
MOV bit addr, C 0X92 2 None
MOV iram addr, #data 0X75 3 None
MOV iram addr, @R0 0X86 2 None
MOV iram addr, @R1 0X87 2 None
MOV iram addr, RO 0X88 2 None
MOV iram addr, RI 0X89 2 None
MOV iram addr, R2 0X8A 2 None
MOV iram addr, R3 0X8B 2 None
MOV iram addr, R4 0X8C 2 None
MOV iram addr, R5 0X8D 2 None
MOV iram addr, R6 0X8E 2 None
MOV iram addr, R7 0X8F 2 None
MOV iram addr, A 0XF5 2 None
MOV iram addr, iram addr 0X85 3 None
POP iram addr 0XD0 2 None
PUSH iram addr oxco 2 None
XCH A, @R0 0XC6 1 None
XCH A, @R1 0XC7 1 None
XCH A, RO 0XC8 1 None
XCH A, RI 0XC9 1 None
XCH A, R2 0XCA 1 None
XCH A, R3 0XCB 1 None
XCH A, R4 OXCC 1 None
XCH A, R5 0XCD 1 None
XCH A, R6 OXCE 1 None
XCH A, R7 OXCF 1 None
XCH A, iram addr 0XC5 2 None
XCHD A, @R0 0XD6 1 None
XCHD A, @R1 0XD7 1 None
MOVC A, @A + DPTR 0X93 1 None
MOVC A, @A + PC 0X83 1 None
MOVX @DPTR, A OXFO 1 None
MOVX @R0, A 0XF2 1 None
MOVX @R1, A 0XF3 1 None
MOVX A, @DPTR 0XE0 1 None
Instructions Opcode Bytes Flags __

MOVX A, @R0 0XE2 1 None
MOVX A, @R1 0XE3 1 None
B.3.2 Arithmetic Instructions

ADD A, #data 0X24 2 C, AC, OV
ADD A, iram addr 0X25 2 C, AC, OV
ADD A, @R0 0X26 1 C, AC, OV
ADD A, @R1 0X27 1 C, AC, OV
ADD A, RO 0X28 1 C, AC, OV
ADD A, RI 0X29 1 C, AC, OV
ADD A, R2 0X2A 1 C, AC, OV
ADD A, R3 0X2B 1 C, AC, OV
ADD A, R4 0X2C I C, AC, OV
ADD A, R5 0X2D 1 C, AC, OV
ADD A, R6 0X2E 1 C, AC, OV
ADD A, R7 0X2F 1 C, AC, OV
ADDC A, #data 0X34 2 C, AC, OV
ADDC A, iram addr 0X35 2 C, AC, OV
ADDC A, @R0 0X36 1 C, AC, OV
ADDC A, @R1 0X37 1 C, AC, OV
ADDC A, RO 0X38 1 C, AC, OV
ADDC A, RI 0X39 1 C, AC, OV
ADDC A, R2 0X3A 1 C, AC, OV
ADDC A, R3 0X3B 1 C, AC, OV
ADDC A, R4 0X3C 1 C, AC, OV
ADDC A, R5 0X3D 1 C, AC, OV
ADDC A, R6 0X3E 1 C, AC, OV
ADDC A, R7 0X3F 1 C, AC, OV
SUBB A, #data 0X94 2 C, AC, OV
SUBB A, iram addr 0X95 2 C, AC, OV
SUBB A, @R0 0X96 1 C, AC, OV
SUBB A, @R1 0X97 1 C, AC, OV
SUBB A, RO 0X98 1 C, AC, OV
SUBB A, RI 0X99 1 C, AC, OV
SUBB A, R2 0X9A 1 C, AC, OV
SUBB A, R3 0X9B 1 C, AC, OV
SUBB A, R4 0X9C 1 C, AC, OV
SUBB A, R5 0X9D 1 C, AC, OV
SUBB A, R6 0X9E 1 C, AC, OV
SUBB A, R7 0X9F 1 C, AC, OV
MUL AB 0XA4 1 C, OV
DIV AB 0X84 1 C, OV
DA 0XD4 1 C
DECA 0X14 1 None
DEC iram addr 0X15 2 None
dec @ro 0X16 J______ None
Instructions Opcode Bytes Flags______

0X17 1 None
DEC @R1
0X18 1 None
DEC RO
0X19 1 None
DEC Ri
0X1A 1 None
DEC R2
DEC R3 0X1B 1 None
DEC R4 0X1C 1 None
DEC R5 0X1D 1 None
DEC R6 0X1E 1 None
DEC R7 OX IF 1 None
INCA 0X04 1 None
INC iram addr 0X05 2 None
INC @R0 0X06 1 None
INC @R1 0X07 1 None
INC RO 0X08 1 None
INC RI 0X09 1 None
INC R2 0X0A 1 None
INC R3 0X0B 1 None
INC R4 oxoc 1 None
INC R5 0X0D 1 None
INC R6 0X0E 1 None_____
INC R7 0X0F 1 None
INC DPTR 0XA3 1 None
B.3.3 Logical Instructions

ANL iram addr, A 0X52 2 None
ANL iram addr, #data 0X53 3 None
ANL A, #data 0X54 2 None
ANL A, iram addr 0X55 2 None
ANL A, @R0 0X56 1 None
ANL A, @R1 0X57 1 None
ANL A, R0 0X58 1 None
ANL A, RI 0X59 1 None
ANL A, R2 0X5A 1 None
ANL A, R3 0X5B 1 None
ANL A, R4 0X5C 1 None
ANL A, R5 0X5D 1 None
ANL A, R6 0X5E 1 None
ANL A, R7 0X5F 1 None
ANL C, bit addr 0X82 2 C
ANL C, /bit addr 0XB0 2 C
ORL iram addr, A 0X42 2 None
ORL iram addr, #data 0X43 3 None
ORL A, #data 0X44 2 None
ORL A, iram addr 0X45 2 None
ORLA, @R0 0X46 1 None
ORL A, @R1 0X47 1 None

ORL A, RO 0X48 1 None
ORLA, RI 0X49 1 None
ORL A, R2 0X4A 1 None
ORL A, R3 0X4B 1 None
ORL A, R4 0X4C 1 None
ORL A, R5 0X4D 1 None
ORL A, R6 0X4E 1 None
ORL A, R7 0X4F 1 None
ORL C, bit addr 0X72 2 C
ORL C, bit addr 0XA0 2 C
XRL iram addr, A 0X62 2 None
XRL iram addr, #data 0X63 3 None
XRL A, #data 0X64 2 None
XRL A, iram addr 0X65 2 None
XRL A, @R0 0X66 1 None
XRL A, @R1 0X67 1 None
XRL A, RO 0X68 1 None
XRL A, RI 0X69 1 None
XRL A, R2 0X6A 1 None
XRL A, R3 0X6B 1 None
XRL A, R4 0X6C 1 None
XRL A, R5 0X6D 1 None
XRL A, R6 0X6E 1 None
XRL A, R7 0X6F 1 None
CLR bit addr 0XC2 2 None
CLRC 0XC3 1 C
CLR A 0XE4 1 None
CPL A 0XF4 1 None
CPLC 0XB3 1 C
CPL bit addr 0XB2 2 None
SETB C 0XD3 1 C
SETB bit addr 0XD2 2 None
RL A 0X23 1 C
RLC A 0X33 1 C
RR A 0X03 1 None
RRC A 0X13 1 C
SWAP A 0XC4 1 None
B.3.4 Program and Machine Control Instructions

ACALL pageO 0X11 2 None
ACALL pagel 0X31 2 None
ACALL page2 0X51 2 None
ACALL page5 0XB1 2 None
ACALL page6 0XD1 2 None

ACALL page7 0XF1 2 None
LCALL code addr 0X12 3 None
RET 0X22 1 None
RET1 0X32 1 None
AJMP pageO 0X01 2 None
AJMP pagel 0X21 2 None
AJMP page2 0X41 2 None
AJMP page5 0XA1 2 None
AJMP page6 0XC1 2 None
AJMP page? 0XE1 2 None_
LJMP code addr 0X02 3 None_
SJMP reladdr 0X80 2 None _
JMP @A + DPTR 0X73 1 None_
JB bit addr, reladdr 0X20 3 None _
JNB bit addr, reladdr 0X30 3 None
JBC bit addr, reladdr 0X10 3 None
JC reladdr 0X40 2 None
JNC reladdr 0X50 2 None
JZ reladdr 0X60 2 None
JNZ reladdr 0X70 2 None
CJNE A, #data, reladdr 0XB4 3 C
CJNE A, iram addr, reladdr 0XB5 3 C
CJNE @R0, #data, reladdr 0XB6 3 c
CJNE @R1, #data, reladdr 0XB7 3 c
CJNE RO, #data, reladdr 0XB8 3 c
CJNE RI, #data, reladdr 0XB9 3 c
CJNE R2, #data, reladdr 0XBA 3 c
CJNE R3, #data, reladdr 0XBB 3 c
CJNE R4, #data, reladdr 0XBC 3 c
CJNE R5, #data, reladdr 0XBD 3 c
CJNE R6, #data, reladdr 0XBE 3 c
CJNE R7, #data, reladdr 0XBF 3 c
DJNZ iram addr, reladdr 0XD5 3 None
DJNZ RO, reladdr 0XD8 2 None
DJNZ RI, reladdr 0XD9 2 None
DJNZ R2, reladdr 0XDA 2 None
DJNZ R3, reladdr 0XDB 2 None
DJNZ R4, reladdr 0XDC 2 None
DJNZ R5, reladdr 0XDD 2 None
DJNZ R6, reladdr 0XDE 2 None
DJNZ R7, reladdr 0XDF 2 None
NOP 0X00 1 None
APPENDIX Ct

C.1 DATA TRANSFER INSTRUCTIONS
Mnemonics Operands Description ____
General-purpose data transfer instructions _____
MOV Reg, Reg Move a byte or word from the specified source to
Reg, Mem the specified destination.
Mem, Reg
Reg, Imm
Mem, Imm
PUSH Reg Move the specified word to the top of the stack.
Mem
POP Reg Move a word from the top of stack to the specified
Mem location.
XCHG Reg, Reg Exchange bytes or exchange words in the specified
Reg, Mem locations.
XLAT — Translate a byte in AL using a look-up table in the
data segment accessed by BX.
Input/output instructions
IN AL, Port8 Move a byte or word from specified input port to
AX, Port8 accumulator.
AL, DX
AX, DX
OUT Port8, AL Move a byte or word from accumulator to specified
Port8, AX output port.
DX, AL
DX, AX
Address trans er instructions _____
LEA Reg, Mem Load the effective address of the operand in the
memory in the specified register.
LDS Reg, Mem Load the DS register and the specified register with
the pointer from the memory.
les Reg, Mem Load the ES register and the specified register with
the pointer from the memory._____
Flag transfer i nstructions____________________________________________________
lahf — Load AH with the low byte content of the flag
register.________________________ ________
SAHF — Store AH in the low byte content of the flag register.
PUSHF — Move the flag register content to the top of the stack.
POPF — Move the word from the top of the stack to the flag
register.________________________________________
C.2 ARITHMETIC INSTRUCTIONS
Mnemonics Operands_____ Description ________________________________

Addition instructions __ _____ __________________________________________
ADD Reg, Reg Add specified bytes or words.
Reg, Mem
Mem, Reg
Reg, Imm
Mem, Imm
ADC Reg, Reg Add specified bytes or words with Carry.
Reg, Mem
Mem, Reg
Reg, Imm
Mem, Imm
INC Reg Increment specified byte or word by 1.
Mem ____
AAA — ASCII adjust after addition.
DAA —. Decimal (BCD) adjust after addition.
Subtraction instructions______________________________________________________
SUB Reg, Reg Subtract specified bytes or words.
Reg, Mem
Mem, Reg
Reg, Imm
Mem, Imm
SBB Reg, Reg Subtract specified bytes or words with borrow.
Reg, Mem
Mem, Reg
Reg, Imm
Mem, Imm
DEC Reg Decrement specified byte or word by 1.
Mem
NEG Reg Change the sign of the specified byte or word by
Mem taking 2’s complement.
CMP Reg, Reg Compare specified bytes or words.
Reg, Mem
Mem, Reg
Reg, Imm
Mem, Imm
AAS — ASCII adjust after subtraction.
DAS — Decimal (BCD) adjust after subtraction.
Multiplication instructions-------------------------------------------------------------------------------
MUL Reg Multiply two unsigned bytes or words.
Mem ____
Reg Multiply two signed bytes or words.
IMUL
Mem
ASCII adjust after multiplication.
AAM
APPENDIX C—8086 INSTRUCTION SET 745
Mnemonics Operands Description

Division instructions ______________________________________________________
DIV Reg Divide the unsigned word in AX by the unsigned
Mem byte in the register/memory or the unsigned double
word in DX-AX by the unsigned word in the
register/memory.
IDIV Reg Divide the signed word in AX by the signed byte in
Mem the register/memory or the signed double word in
DX-AX by the signed word in the register/memory.
AAD — ASCII adjust before division.
CBW — Convert the signed byte in AL into the signed word
in AX.
CWD — Convert the signed word in AX into the signed
double word in DX-AX.
C.3 BIT MANIPULATION INSTRUCTIONS
Mnemonics Operands_____ Description

Logical instructions_______________________________________________________
NOT Reg Take the 1’s complement of the byte or word.
Mem
AND Reg, Reg AND two bytes or words.
Reg, Mem
Mem, Reg
Reg, Imm
Mem, Imm
OR Reg, Reg OR two bytes or words.
Reg, Mem
Mem, Reg
Reg, Imm
Mem, Imm
XOR Reg, Reg XOR two bytes or words.
Reg, Mem
Mem, Reg
Reg, Imm
Mem, Imm
TEST Reg, Reg AND two bytes or words to update flags; operands
Reg, Mem are not changed.
Reg, Imm
Mem, Imm
Shift instructions
SHL/SAL Reg, 1/CL Shift bits of the byte or word left either by 1 bit
Mem, 1/CL or by the number of bits specified by CL, putting
zero(s) in the LSB(s).
SHR Reg, 1/CL Shift bits of the byte or word right either by 1 bit
Mem, 1/CL or by the number of bits specified by CL, putting
zero(s) in the MSB(s).
Mnemonics Operands Description ___________

SAR Reg, 1/CL Shift the bits of the byte or word right either by 1 bit
Mem, 1/CL or by the number of bits specified by CL, putting the
old MSB into the new MSB.
Rotate instructions ________________________________________________________
ROL Reg, 1/CL Rotate the bits of the byte or word left either by 1 bit
Mem, 1/CL or by the number of bits specified by CL, the MSB
to the LSB, and to the carry flag.
ROR Reg, 1/CL Rotate the bits of the byte or word right either by
Mem, 1/CL 1 bit or by the number of bits specified by CL, the
LSB to the MSB, and to the carry flag.___________
RCL Reg, 1/CL Rotate the bits of the byte or word left either by 1 bit
Mem, 1/CL or by the number of bits specified by CL, the MSB
to the carry flag, and the carry flag to the LSB.
RCR Reg, 1/CL Rotate the bits of the byte or word right either by
Mem, 1/CL 1 bit or by the number of bits specified by CL, the
LSB to the carry flag, and the carry flag to the MSB.
C.4 STRING INSTRUCTIONS

MOVSB/MOVSW — Move the byte or word string from the data
segment to the extra segment.
COMPS/COMPW — Compare two string bytes or two string words.
SCASB/SCASW — Compare a string byte with a byte in AL or
compare a string word with a word in AX.
LODSB/LODSW — Load a string byte/word from the data segment to
AL/AX.
STOSB/STOSW — Store the string byte/word from AL/AX into the
extra segment.
REP (Prefix) — Repeat a string instruction CX times.
REPE/REPZ (Prefix) — Repeat a string instruction when the Zero flag is 1
and CX is not 0.
REPNE/REPNZ (Prefix) — Repeat a string instruction when the Zero flag is 0
and CX is not 0.
C.5 PROGRAM CONTROL TRANSFER INSTRUCTIONS

Unconditional transfer instructions
CALL Displ6 Call a subroutine or procedure present in the same
Reg segment or in another segment.
Mem
Offset 16, Segl6
RET — Return from the subroutine to the main program.
APPENDIX C—8086 INSTRUCTION SET 747

JMP Disp8 Jump to the specified address to get the next
Displ6 instruction for execution.
Reg
Mem
Offset 16, Seg!6
Conditional transfer instructions
JA/JNBE Disp8 Jump if above/Jump if not below or equal.
JAE/JNB Disp8 Jump if above or equal/Jump if not below.
jb/jnae' Disp8 Jump if below/Jump if not above or equal.
JBE/JNA Disp8 Jump if below or equal/Jump if not above.
JC Disp8 Jump if the carry flag is 1.
JE/JZ Disp8 Jump if equal/Jump if 0 (Jump if the zero flag is 1).
JG/JNLE Disp8 Jump if greater/Jump if not lesser than or equal.
JGE/JNL Disp8 Jump if greater or equal/Jump if not lesser than.
JL/JNGE Disp8 Jump if lesser than/Jump if not greater than or equal.
JLE/JNG Disp8 Jump if lesser than or equal/Jump if not greater tham
JNC Disp8 Jump if the carry flag is 0.
JNE/JNZ Disp8 Jump if not equal/Jump if not 0 (Jump if the zero
flag is 0).
JNO Disp8 Jump if the overflow flag is 0. ______
JNP/JPO Disp8 Jump if the parity flag is 0.
JNS Disp8 Jump if the sign flag is 0. ___
JO Disp8 Jump if the overflow flag is 1. _____
JP/JPE Disp8 Jump if the parity flag is 1. ___
JS Disp8 Jump if the sign flag is 1. ____
Iteration control instructions ____ _
LOOP Disp8 Execute the loop CX times. _______
LOOPE/LOOPZ Disp8 Execute the loop when CX is not 0 and the zero flag
is 1. _____
LOOPNE/ Disp8 Execute the loop when CX is not 0 and zero flag is
LOOPNZ 0. ___
JCXZ — Jump to the specified address if CX is 0. ___
Interrupt instructions ____
INT N Call the interrupt service procedure of interrupt type
N.
INTO — Call the interrupt service procedure of overflow
interrupt (type 4) if the overflow flag is 1. _
IRET — Return from the interrupt service procedure to the
main program.__________________ _______________
C.6 PROCESSOR CONTROL INSTRUCTIONS

Mnemonics Operands Description___________________________________
Flag-related ins tructions ___________________________________ —
STC — Set the carry flag to L
CLC — Clear the carry flag to 0.______________________________
CMC — Complement the content of the carry flag.
STD — Set the direction flag to 1._____________________________
CLD — Clear the direction flag to 0.
STI — Set the interrupt flag to 1.
CLI — Clear the interrupt flag to 0. __________________
External hardware synchronization instructions______ ________ __________________
HLT — Halt (do nothing) until interrupt or reset is activated.
WAIT — Wait (do nothing) until the signal on the TEST pin goes
low.
ESC — Escape to the external coprocessor such as the 8089 or the
8087.
LOCK (Prefix) An instruction prefix that prevents another processor from
taking the system bus when the instruction is executed.
No operation instruction
NOP_________ — No operation
Key: —
Reg—8-bit or 16-bit register Offset 16—16-bit offset address
Mem—8-bit or 16-bit data in memory Segl6—16-bit segment address
Imm—8-bit or 16-bit immediate data Disp8—Signed 8-bit number
Port8—8-bit port address N—8-bit number
Displ6—Signed 16-bit number
APPENDIX

Operation Mnemonics Operand syntaxDescription
Move, byte LDB BD, BS BD <—BS
STB BS, BD BS->BD
CLRB BD BD <-0
Move, word LD WD, WS WD <-WS
LDBSE WD, BS WD <— BS, Sign extend
LDBZE WD, BS WD <— BS, Zero extend
ST WS, WD WSWD
CLR WD WD<-0
PUSH WS WS -> Stack
PUSH F PSW -> Stack ; 0 -> PSW
POP WD WD <— Stack
POPF PSW«—Stack
Increment INCB BD BD <-BD + 1
INC WD WD<- WD + 1
Decrement DECB BD BD<-BD- 1
DEC WD WD <- WD - 1
Complement NOTB BD BD <— FFH-BD
NOT WD WD <- FFFFH - WD
Sign extend EXTB WD WD <— Extend low byte
EXT LD LD <— Extend low word
Changing flag bits SETC C<- 1
CLRC C<-0
CLRVT VT <—0
Enable interrupt EI I<- 1
Disable interrupt DI I<-0
Add 8-bit ADDB BD, BS BD <—BD + BS
ADDB BD, BS1,BS2 BD <—BS1 + BS2
Add with carry ADDCB BD, BS BD <—BD +BS + C
Add 16-bit ADD WD, WS WD<-WI) +WS
ADD WD, WS1, WS2 WD <— WS1 +WS2
Add with carry ADDC WD, WS WD WD + WS + C
Subtract 8-bit SUBB BD, BS BD<-BD-BS
SUBB BD, BS1,BS2 BD<-BS1-BS2
Subtract with borrow SUBCB BD, BS BD <-BD -BS-(l-C)
Negate NEGB BD BD<-0-BD
Subtract 16-bit SUB WD, WS WD <- WD - WS
SUB WD, WS1, WS2 WD<—WS1 -WS2
Subtract with borrow SUBC WD, WS WD <—WD - WS - (1 - C)
Negate NEG WD WD <- 0 - WD
Compare CMPB BS1,BS2 BS1 -BS2
CMP WS1, WS2 WS1 - WS2
Multiply unsigned MULUB WD, BS WD <— BD x BS
8x8 MULUB WD, BS1.BS2 WD<—BS1 x BS2
Signed 8x8 MULB WD, BS WD <—BD x BS
MULB WD, BS1, BS2 WD<—BS1 x BS2

Unsigned MULU LD, WS LD <- WD x WS
16 x 16 MULU LD, WS1, WS2 LD <— WS1 x WS2
Signed MUL LD, WS LD <- WD x WS
16 x 16 MUL LD, WS1, WS2 LD < WS1 x WS2
Divide DIVUB WD, BS WD(L) <- WD/WS;
Unsigned 16/8 WD(H) <-WD mod BS
Signed 16/8 DIVB WD, BS WD(L) <- WD/BS;
WD(H) <—WD mod BS
Unsigned 32/16 DIVU LD, WS LD(L) <—LD/WS;
LD(H) <—LD mod WS
Signed 32/16 DIV LD, WS LD(L) <- LD/WS;
LD(H) <—LD mod WS
AND ANDB BD, BS BD <- BD AND BS
ANDB BD, BS1,BS2 BD<-BS1 ANDBS2
AND WD, WS WD <- WD AND WS
AND WD, WS1, WS2 WD«—WS1 AND WS2
OR (inclusive) ORB BD, BS BD <- BD OR BS
OR WD, WS WD <- WD OR WS
Exclusive OR XORB BD, BS BD <- BD XOR BS
XOR WD,WS WD <- WD XOR WS
Branch SJMP Label PC<-PC ± up to 1,023
unconditionally LJMP Label PC<-PC ± up to 65,535
Jump indirect BR [WS] PC<-WS
Decrement DJNZ BD, Label BD<—BD - 1;
Branch if PC PC ± up to 127 ifBD
result <> 0 <> 0
Branch conditionally i * selected bit of BS is set (clear)
Branch if bit is set JBS BS, Bit, Label PC <— PC ± up to 127 if test
passes
Branch if bit is clear JBC BS, Bit, Label PC <— PC ± up to 127 if test
passes
Branch conditionally on flag testing
IfC = 1 JC Label PC <— PC ± up to 127 if test
passes
IfC = 0 JNC Label
IfZ = 1 JE Label
IfZ = 0 JNE Label
IfN = 1 JLT Label
lfN = 0 JGE Label •
Shift operation
Shift left SHLB BD, #shifts Shift byte left
SHL WD, #shifts Shift word left
SHLL LD, #shifts Shift double word left
SHLB BD, BS Shift byte left
SHL WD, BS Shift word left
SHLL LD, BS Shift double word left
Logical SHRB BD, #shifts Logical right shift byte
shift right SHR WD, #shifts Logical right shift word
SHRL LD, #shifts Logical right shift double word
SHRB BD, BS Logical right shift byte
SHR WD, BS Logical right shift word
SHRL LD, BS Logical right shift double word
APPENDIX D—8096 INSTRUCTION SET 751

SHRAB BD, #shifts Arithmetic right shift byte
SHRA WD, ttshifts Arithmetic right shift word
SHRAL LD, #shifts Arithmetic right shift double
Arithmetic word
shift right SHRAB BD, BS Arithmetic right shift byte
SHRA WD, BS Arithmetic right shift word
SHRAL LD, BS Arithmetic right shift double
word
Normalize long NORML LD, BS Shift LD, left until
integer MSB = 1; BD shifts
Branch conditionally on testing overflow and sticky bit
IfV= 1 JV Label PC <— PC up to 127 if test
IfV = 0 JNV Label passes
IfVT= 1 JVT Label
IfVT = 0 JNVT Label
If ST = 1 JST Label
IfST = 0 JNST Label
Branch following a signed number comparison
If< JLT Label
If< JLE Label
If = JE Label
If> JGE Label
If> JGT Label
Ifo JNE Label
Branch following an unsigned number comparison
If< JC Label
If< JNH Label
If = JE Label
If> JNC Label
If> JH Label
Ifo JNE Label
Branch to subroutine SCALL Label Stack <— PC ; PC <— PC ± up

to 1,023
LCALL Label Stack <— PC; PC <— PC ± up to
65,535
Subroutine return and RET PC <— Stack
interrupt return
Software interrupt TRAP Stack <— PC;
PC<h [201IH, 2010H]
No operation NOP PC <- PC + 1
SKIP XXH PC <- PC + 2
Reset system RST
Key:
BD—Byte operand for destination BS—Byte operand for source
WD—Word operand for destination WS—Word operand for source
LD—Long word operand
APPENDIX E
CASE STUDIES
E.1 8051-BASED WASHING MACHINE CONTROL
The washing machine is an example of an appliance that uses modem technology.
It has developed over the years—from manual and semi-automatic to fully
automatic with advanced intelligent control algorithms. The automation of a
washing machine is easily achieved using programmed microcontrollers. In
general, washing in a washing machine is achieved by alternate agitation of the
clothes in detergent soaked water.
Let us see the important parts of the washing machine (Fig. E.l), so that we can
understand how a microcontroller can be used in the automation of the washing
machine.
There are two types of tubs in the washing machine—perforated inner tub and
solid outer tub. The clothes are loaded in the inner tub along with the water and
detergent powder. The holes in the inner tub are used for draining the water. The
external tub is used to cover the inner tub and support it.
The agitator located inside the inner tub of the washing machine is used for
cleaning the clothes. The rotation of the agitator disc and the blades produces
strong currents within the detergent soaked water. The rotation of the clothes
within detergent water enables the removal of the dirt particles from the fabric of
the clothes.
The agitator is coupled to a motor to produce rotary motion. The motors used
are multi-speed motors. The speed of the motor can be changed according to the
washing cycle, load, etc.
The timer is available in the washing machine to select the wash time for
the clothes by the user. In automatic washing machines, the time is selected
automatically by a controller, depending upon parameters such as the amount of
clothes inside and the dirt wash cycle.
In addition to these basic components for washing, washing machines have a
water inlet control valve, drain control valve, and pipe and rinsing mechanism.
The water flow control is done using solenoid valves. The coils in the solenoid
valve, when energized, open the valve and allow the water through it.
Some automatic washing machines may have a water pump to pump the
water automatically, heating units to heat the water before washing, and circuits
to determine wash cycles and duration. The advanced controllers in automatic
washing machines calculate the total weight of the clothes, find the quantity of
water and detergent required, and the total time required for washing the clothes.
After these calculations, the controls are issued to various components to effectively
complete washing and rinsing.
APPENDIX E—CASE STUDIES 753
Fig. E.1 Parts of a washing machine
Now let us consider the basic operations of the washing machine and see how
they can be implemented using an 8051 microcontroller. Washing is achieved
by alternate phases of agitation and stoppage. The duration of the agitation and
stoppage phases is selected differently for different wash cycles such as normal
and heavy. For example, during normal washing, agitation may take place for four
minutes and stoppage for four minutes. Heavy washing will then take six minutes
for agitation and two minutes for stoppage. Washing is followed by the rinse and
drain phases.
It is assumed that the user has to fill the inner tub with the clothes, detergent
powder, and required amount of water before starting the washing. Washing is
started once these parameters are set by the user. The inputs connected to the
microcontroller are as follows:
(i) Inputs from the wash cycle selection switch such as normal and heavy
(ii) Water level indicators—one for full and the other for empty
(iii) Start operation button
(iv) Stop operation button
The outputs connected to the microcontroller are as follows:
(i) Drive control signal to turn on the agitator motor
(ii) Drive control signal to reverse the motor direction
(iii) Water inlet control signal
(iv) Drain valve control signal
The hardware set-up for this type of semi-automatic washing machine control
is given in Fig. E.2.
-^vcc
Indicator +5V
8051 74LS240 ' >EDs \/\/y\7
P3.0 P1.0 $■
Wash
cycle P3.1 P1.1
selector P3.2 P1.2
P3.3 P1.3 WA------+6VDC
220Q
470Q
230VAC
-GND
50 Hz
SK100 L N
N/C, L—
Agitator on +6VDC ■
From water P3.4 P1.4

Agitator reverse on 470 Q IN4007
level sensor P3.5 P1.5 Water inlet valve on^^T N/0
Start P3.6 P1.6 SK100
Drain valve on 6V100Q
Stop P3.7 P1.7 GND Relay
N/C
■WW—n
, n L1
—
J N/0 B
6V100Q Washing machine mo or
Relay
GND
Fig. E.2 Hardware for semi-automatic washing machine control

APPENDIX E—CASE STUDIES 755
The hardware uses two ports of the 8051—port 3 for inputs and port 1 for
outputs. Wash cycle selection is done through the least significant four bits of
port 3. There can be four types of wash cycles—gentle, normal, heavy, and rinse.
This selection can be done through a rotary switch. The higher-order four bits
of the port are used by the user to start and stop the washing. The water level is
detected for the full and empty levels using two level sensors. The level sensors
can be either a float with switch arrangement or of capacitance/contact type. The
contact type sensor uses two metal electrodes, one at the bottom of the tub and
connected to the ground terminal of the supply and the other placed at the point
where the water level is to be sensed. The water sensor relies upon the principle
that water is a good conductor and an open circuit or short circuit can be sensed
between the electrodes depending upon the water level. Here, three electrodes are
used—one for ground, one to sense whether the tub is full, and another to sense
whether the tub is empty.
Based on the reading sensed on the port 3 pins, the control algorithm gives
the output on the port 1 lines. The least significant bits of port 1 are used to light
indicator lamps. Here, four LEDs are used as indicator lamps—one for washing,
one for rinsing, one for draining water, and one for indicating the end of the wash
operation. The motor given in the figure is a single phase induction motor. The
supply to this motor is given through the relay, which is driven by the signal from
the microcontroller. It has two coils; the supply to them is phase-shifted using the
capacitor arrangement. The direction of motor rotation can be reversed by changing
the current direction in one of the coils. This is done by a relay arrangement, which
is again energized by the signal from the microcontroller.
The designers can change these options and also add other indicators according
to their requirements. The port 1 higher-order four bits are used for control
purposes. One bit is used for turning on the agitator motor, while the other decides
its direction. The other two in the present design are used to control the water inlet
valve and drain outlet valve.
The flowchart for the control of a washing machine is given in Fig. E.3.
The flowchart assumes that the user starts the washing process after selecting
the appropriate wash cycle—gentle, normal, heavy, and rinse. The algorithm, upon
sensing the start input, reads the wash cycle and decides the timings according to
the wash cycle set. After this the algorithm checks whether water is full in the tub
and if not, turns on the water inlet valve and fills the tub. Then the washing process
is done automatically by alternate agitate and stoppage phases of the agitator
motor for the predetermined duration. Once the wash cycle is over, the drain pipe
is opened and the tub water is emptied. The algorithm returns back to reading the
wash/rinse cycle. During this operation, the user can stop the process at any time
by giving a signal at the stop input. The algorithm scans the stop input periodically
for stopping the operation. When the stop input is available, the algorithm resets
the entire process and is reinitialized.
This algorithm is primitive; several hardware and software techniques are added
to make the washing machine a functionally complete versatile machine.
' >..... ’ <SW»I«W«« ■~-T.-rrnrw,|11||:. *
Fig. E.3 Algorithm for washing machine control

APPENDIX E-CASE STUDIES 757
E.2 8051-BASED ELEVATOR/LIFT INTERFACE

The elevator or lift is one of the common applications in which microprocessors can
be used effectively. An elevator has many electrical and electronic components,
which have to work closely in association with the user-controlled switches. An
elevator, in general, will need the following minimum user interface switches:
(i) User-controlled switches at each floor to call elevator service
(ii) Switches inside the elevator to select the destination floor
In addition to these, the following switches may also be needed:
(iii) Open and close switches for the door.
(iv) An alarm switch, which users can use to raise an alarm
This example considers the first two switches and explains the hardware and
software for controlling the elevator. The hardware for elevator control is shown
in Fig. E.4.
The elevator system basically consists of a cabin unit used to transport people
from one floor to another. The cabin unit is moved by a motor drive and the related
power control circuit. It also has a destination floor selection input, so that the
motor can be activated to move the cabin in the required direction and up to the
required distance. The control algorithm must decide the direction and the distance
of the cabin movement. This control algorithm must get its input from the switches
at each floor to decide the direction and distance.
The following elevator control algorithm assumes that there are four floors—
ground, first, second, and third. The cabin unit has four switches to select one of
the four floors through push-to-on switches. These switches are used to set an RS
flip-flop and give logic 1 input to the port pin of the 8051. This input to the ports
can be reset by another output from a port. There are switches at each floor to call
the lift service situated in the floor unit. These switches also set request flip-flops,
which can be later reset by hardware. The algorithm assumes that separate routines
are available to control the cabin movement motor in the required direction and for
the required distance.
The following sequence of operation is considered in the control algorithm
development:
Step 1: Initialize the ports and the cabin position to ground floor.
Step 2: Check for a key press from the floor units, for lift service request and cabin
unit.
Step 3: Calculate the requested floor.
Step 4: If any request is available, compare with the current floor of the cabin.
If the floor requested is higher than the current floor, give a command for the
motor control unit to move up to the next floor. If the floor requested is lesser
than the current floor, give a command for the motor control unit to move down to
the next floor. If the requested floor and current floor match, reset the lift service
request from that floor. Then open the door, wait for a predetermined time, and
close the door.
Step 5: Go to step 2.
Fig. E.4 Elevator interface with the microcontroller

appendix e-case studies 759
The algorithm is given in the flowchart shown in Fig- E.5.
Fig. E.5 Algorithm for elevator control
The requested floor calculation in this algorithm can be done by many methods.
This can be done based on pre-laid conditions such as moving the lift cabin in the
same direction until the requests in that direction are cleared. These conditions can
be changed based on the priority assigned to the floors. So the programmer can
decide the method for requested floor calculation based on the situation and the
requirements.
BIBLIOGRAPHY
Ayala, K. J., The 8051 Microcontroller Architecture, Programming and Application,

Penram International (India), Mumbai, 1996.
Brey, B. B., The Intel microprocessors 8086/8088, 80186/80188, 80286, 80386, 80486,
Pentium and Pentium Pro Processor Architecture, Programming and Interfacing, 4th
ed., Prentice Hall of India, New Delhi, 1997.
Gaonkar, R. S., Microprocessor Architecture, Programming, and Applications with
the 8085 and 8080A, Wiley Eastern, New Delhi, 1996.
Gilmore, C. M., Microprocessors: Principles and Applications, McGraw-Hill, New
York, 1995.
Hall, D. V., Microprocessors and Digital Systems, McGraw-Hill, New York, 1983.
Hall, D. V., Microprocessors and Interfacing: Programming and Hardware, 2nd ed.,
Tata McGraw-Hill, New Delhi, 1999.
Huang, Han-Way, Using the 8051 Microcontroller, Oxford University Press, New
York, 1999.
Kant, Krishna, Microprocessors and Microcontrollers: Architecture, Programming
and System Design with 8085, 8086, 8051, 8096, Prentice Hall of India, New Delhi,
2007.
Kleitz, William, Microprocessor and Microcontroller Fundamentals: The 8085 and
8051 Hardware and Software, 1st ed., Prentice Hall, New Jersey, 1997.
Liu, Yu-cheng and Gibson, G. A, Microcomputer Systems: The 8086/8088 Family
Architecture, Programming and Design, 2nd ed., Prentice Hall of India, New Delhi,
1986.
Mazidi, M. A. and Mazidi J. G., The 8051 Microcontroller and Embedded Systems,
Pearson Education, New Delhi, 2006.
Peatman, J. B., Design with Microcontrollers, McGraw-Hill, New York, 1988.
Peatman, J. B., Design with PIC Microcontrollers, Prentice Hall, New Jersey, 1998.
Predko, Myke, Programming and Customizing the 8051 Microcontroller, Tata
McGraw-Hill, New Delhi, 2000.
Ram, B., Fundamentals of Microprocessors and Microcomputers, 3rd ed., Dhanpat Rai
& Sons, New Delhi, 1988.
Ray, A. K. and Bhurchandi, K. M., Advanced Microprocessors and Peripherals. 2nd
ed., Tata McGraw-Hill, New Delhi, 2007.
Srinath, N. K., 8085 Microprocessor Programming and Interfacing, Prentice Hall of
India, New Delhi, 2007.
Tabak, Daniel, Advanced Microprocessors, 2nd ed., McGraw-Hill, New York, 1994.
INDEX
80186 microprocessor 673, 674 handshake input/output I/O mode

80286 microprocessor 675-685 201-203
80386 microprocessor 686-697 8279 keyboard and display interface IC
80486 microprocessor 697-700 display RAM 241-248
8051 addressing modes FIFO registers 241, 244
immediate addressing 314 8284A clock generator IC 569, 573
indexed addressing 315, 316 8529 programmable interrupt controller
memory direct addressing 315 IC 268-275, 491, 551, 570, 674
memory indirect addressing 315
register direct addressing 314, 315 Absolute address decoding 186, 193
8051 interrupts 347-355 Accumulator 34-47, 314-318
8051 serial port 355-362 Analog-to-digital converter (ADC)
8051 timers 339-347 analog input channel 214, 215, 371,
8086 addressing modes 634
data addressing modes 433-435 bipolar 214, 371
immediate addressing mode 433 end of conversion 215, 216, 371, 372,
program memory addressing modes 399
435-437 resolution 214, 215, 371, 592, 635
register addressing mode 432 start conversion 215, 216, 399, 635 -
stack memory addressing modes 437, unipolar 214, 371, 633
438 Arithmetic and logic unit 3, 20, 21, 34,
8086 system bus timings 572-579 305, 306, 420, 558, 588, 590, 674, 675,
8096 CPU buses 687, 698, 701,702,713
A bus 589 Arithmetic instructions 44, 45, 317, 442,
D bus 589 489, 538, 601, 702
8096 operand types Arithmetic operation 34, 45, 62, 113,
bits 598 310,317, 602, 708
bytes 598 Assembler
double words 598 cross assembler 64, 663
long integers 599 macro assembler 64, 458, 466, 474
short integers 598 one-pass assembler 64
words 598 two-pass assembler 64
8237 DMA controller IC 275-287 Assembler directives 65, 66, 322, 436,
8253 timer IC 250-261 443,459, 465,471
8255 programmable peripheral interface Assembly language 4, 33, 35, 40, 41, 50,
IC 63-150, 175, 235, 322, 405, 458, 465,
bidirectional I/O mode 203, 204 469, 474, 663,218
bit set/reset (BSR) mode 201
BIOS interrupts 499. 500 Digital-to-analog converter (DAC)

Bit manipulation instructions 123, 310, ramp wave generation 221, 222, 375,
320, 321 376
Branching instructions 48, 49. 319, 603 sine wave generation 376, 377,
Branching operation 722-726
jump instruction 48, 85, 86, 320, 436, square wave generation 219, 220,
437, 453, 703 255, 256, 374
subroutine instruction 48 staircase wave generation 220, 221,
unconditional 319, 603 374, 375
conditional 319, 604 Direct memory access (DMA)
Bus burst mode 155, 158
address bus 6, 7, 24, 28, 60, 189, 292, cycle-stealing mode 155, 158
337, 366, 509, 566, 568 Double buffering 355
control bus 6, 7, 24, 25, 276, 293, Downloader 662
400,551,698
data bus 6, 7, 24, 28, 60, 189, 251, Embedded systems 659, 662-664, 708
337, 426, 508, 566, 568, 686 Emulator
system bus 3, 158, 279, 457, 508, in-circuit emulator 662, 663
572, 706 Even/low memory bank 511-515
Bus arbitration 540, 541, 556, 557 Execution unit (EU) 419, 420, 675
Bus interface unit (BIU) 419, 420, 425 Expanded mode 646
External data memory 334, 336, 337
Central processing unit (CPU) 1, 5, 6, External program memory 334, 335, 338
29, 157, 165, 293, 305, 538, 539, 553,
587, 589, 661,673 Firmware 4, 293, 499, 664
Chip configuration byte 594, 647, 648 Flag manipulation instructions 450, 451
Clock Flag register
frequency 5, 52, 255, 344, 360 control flags 421
speed 5, 9, 357, 706 status flags 421, 591, 628
Closely-coupled configuration 539, 540, Flash memory 13, 14, 214, 401, 66C, 661
556
Compiler 4, 12, 502, 663, 664, 671 Hands, ake mode of data transfer 155,
Complex instruction set computer 200-203
(CISC) 4, 11 High speed ZO lines 593
Complex instruction set computer High speed input (HSI) unit 593,'622,
(CISC) processor 660, 700, 707 637-642
Control transfer instructions 451-453 High speed output (HSO) unit 642-645
Coprocessor 427, 458, 539, 540, 547-552 High/odd I/O bank 528, 534
Cross compiler 663, 664
I/O mapped I/O 155, 193, 517-519
Data transfer (copy) operation 34 I/O- or peripheral-mapped I/O 187-190
Data transfer instructions 41-43, 316, I/O-mapped I/O access 155
317, 439-442, 601 FC standard 400-407
DC motor 388-391 Idle mode 160, 283,311,312
De-bouncing of keys 208, 209, 235, 244, Immediate addressing 38, 50, 314, 433,
248, 378, 380 600
Debugger 662-664 Implied addressing 40
Decoder 24, 178-186, 248, 296, 514-521 Indirect addressing 39,40, 315, 599, 600
INDEX 763
Instruction cycle 51. 490, 710, 715, 721, Machine or processor control
726 instructions 49, 66, 303, 439
Instruction queue 425, 570, 675 MACRO 473
In-system programming (ISP) 661,662, MASM (Microsoft macro assembler)
664 458, 474, 475
Integrated development environment Matrix keyboard 234-238, 248, 249, 378
(IDE) 661,662, 664 Matrix keypad 234, 377-380
Interrupt Maximum mode 426-429, 519, 539,
hardware interrupt 29, 166, 168, 268, 570, 572, 576-579
351,485,495,570 MCS-51 series 304-306
non-maskable interrupt (NMI) 169, Memory
427, 488 cache memory 10-12, 672, 697, 699,
software interrupt 166, 167, 485, 489, 700
490 data memory 157, 306, 307, 336
Interrupt structure dynamic RAM (DRAM) 3, 230,
hardware 168 385-387, 706
interrupt service routine 156, 165, electrically erasable and
268, 344, 485, 492 programmable ROM (EEPROM)
interrupt vector address 165, 274, 13,401,404, 660,711
348, 624 erasable and programmable ROM
maskable 166, 168, 169, 268 (EPROM) 13, 175-183, 186, 187,
non-maskable 29, 166, 168, 268, 627 190, 423, 510, 511, 513, 579, 646,
non-vectored 165 650
software 166 flash memory 13, 401, 660, 661, 710
vectored 165 memory organization 166, 294,
Interrupt-driven data transfer 155-158, 306, 307, 507, 593, 693, 751, 716
260 primary memory 11,12
processor memory 11, 12
Liquid crystal display (LCD) 228-233, program memory 306, 317, 334, 338,
384-388,401 , 435, 593, 650,715,716
Logical instructions 46, 47, 318, 319, programmable ROM (PROM) 12, 13,
449,601,628,712 135, 175-177, 183-187, 242-250
Logical operation 35, 47, 67, 151, 314X random access memory (RAM) 3, 12,
559,602 . .j 13, 293, 294, 307-309, 409, 510,
Loosely-coupled configuration 539-541, 516, 593,594,716
556 read/write (R/W) memory 3, 228,
Low/even I/O bank 511-515 229, 384, 404, 405,696,719
r read-only memory (ROM) 3, 12, 20,
Machine control operation 35 175,294, 304, 458, 502,646
Machine cycle secondary memory 12, 689, 695
I/O read cycle 55, 572-576 static RAM (SRAM) 3,407, 661, 712
I/O write cycle 56, 572, 573, 575, 577 Memory control signals (MEMR) and
memory read machine cycle 52, 54, (MEMW) 176-180, 183, 184, 190,
59 279, 509
memory write machine cycle 54, 57 Memory direct addressing 38, 43, 315
opcode fetch machine cycle 52, 53 Memory-mapped I/O 156, 176, 190, 193
Machine language 4, 35, 40, 458, 465, Memory-mapped I/O access 155
664
Microcomputer Reduced instruction set computer

microprocessor-based system 6, 7, 30 (RISC) 4, 11,660, 707
Microcontroller Reduced instruction set computer
computer-on-a-chip 303, 585 (RISC) processor 11, 660, 707, 708
single-chip computer 3, 303, 538 Register arithmetic and logical unit
system-on-a-chip 303 (RALU) 587-591
Minimum mode 428, 519, 536, 566, Register bank select bits (RS0 and RSI)
572-579 310,411
MIPS (million instructions per second) Register direct addressing 39, 314, 315,
5,419,704 599
Multiplexed display 210, 238-240 ROM/EPROM lock 650
Multiprocessor system 537-540,
543-547 Segment register
Multitasking 489, 683, 686 code segment 422, 423, 425, 436-438,
467-470, 678-680
Odd/high memory bank 528, 534 data segment 422-424, 438-442, 495,
Overflow flag (OV) 310, 318, 422, 489, 678
591 extra segment 421-423, 427, 456,
457
Paging mechanism 694-696, 705, 726, stack segment 421-425, 427, 437,
728 438, 493, 678
Partial address decoding 186, 193 Serial communication
Pentium microprocessor 700-706 asynchronous transmission 261
Physical memory address 41, 552, 676, half-duplex 261
677, 693 RS-232C 262, 523, 529-532
PIC16F877 microcontroller 710-726 RS-422A 262
Pipeline operation 702, 703 RS-423 262
Polled mode of data transfer 155, 156, simplex 261
158 synchronous transmission 261, 263
Power down mode 312, 596 universal synchronous asynchronous
PowerPC 708-710 receiver-transmitter (USART) 263,
Processor status word (PSW) 78, 305, . 265,532,711-713
306, 308, 309, 310, 559, 589, 591, 628, Serial data transfer
629 asynchronous data transfer 155, 159
Program 4, 40, 50, 51, 63, 64-150 Data communications equipment
Program counter (PC) 23, 715 (DCE) 159-162
Programming language 4, 5, 86, 663 Data terminal equipment (DTE)
Protected virtual address mode (PVAM) 159-162
672, 675, 676 GPIB/IEEE 488 standard 159,
Pulse width modulation (PWM) 592, 163-165
594,617, 636, 637 RS-232 standard 160
Pulse width modulator 512, 672, 675, RS-485 standard 162
712 synchronous data transfer 155, 159
universal asynchronous receiver
Ready control 650 transmitter (UART) 159, 355, 356,
Real address mode 676 629
Real-time clock (RTC) 400, 404, Seven-segment display
407-409 common anode 209, 210, 239, 247,
369, 536
INDEX 765
common cathode 189, 192, 209, 210, Stopwatch 391-393

369, 536 String instructions 420-423, 456, 457
Shift/Rotate instructions 35, 46, 47, 79, Subroutine
80-83, 127, 420, 439, 454, 602, 603 parameter passing 131
Single chip mode 646 use of stack 13,1, 132
Special function register (SFR) 309, 312,
329, 339-341,343, 348, 356 Thermistor 397-400
Stack pointer (SP) 22, 23, 167, 309, 312, Timing delay 136
437, 590, 601 Timing diagram 51-60, 337-339, 401,
Stepper motor 402, 525, 572-5/74, 576-579
one-phase excitation (wave mode) Traffic light control 211-214, 393-397
224 Tri-state buffer 188, 490, 492
two-phase excitation (hi-torque T-state 40, 51, 52, 54, 56, 57, 60,
excitation) 223-225, 381, 382 137-140, 143, 572

Microprocessors: Microcontrollers

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Microprocessors: Microcontrollers

Uploaded by

Copyright:

Available Formats

OXFORD

Oxford University Press is a department of the University of Oxford.

© Oxford University Press 2010

The moral rights of the author have been asserted

First Edition published in 2010

All rights reserved. No part of this publication may be reproduced, stored in

You must not circulate this book in any other form

Typeset in Times New Roman

I dedicate this work

A microprocessor is technically a miniaturized central processing unit (CPU)

ABOUT THE BOOK

CONTENT AND ORGANIZATION

Chapter 23 offers a preview of Intel's advanced processors (80186, 80286,

PART 1: INTEL 8085 ARCHITECTURE AND PROGRAMMING

PART 2: HARDWARE INTERFACING WITH INTEL 8085

PART 3: INTEL 8051 MICROCONTROLLERS

PART 4: INTEL 8086—16-BIT MICROPROCESSORS

17. Multiprocessor Configuration 537

PART 5: INTEL 8096—16-BIT MICROCONTROLLERS

PART 6: ADVANCED TRENDS

1. MICROPROCESSORS—INTRODUCTION AND EVOLUTION 1

PART 1: INTEL 8085 ARCHITECTURE AND PROGRAMMING

2. INTEL 8085 MICROPROCESSOR ARCHITECTURE 19

2.4 Microcomputer System based on 8085 30

4. ASSEMBLY LANGUAGE PROGRAMMING OF 8085 63

PART 2: HARDWARE INTERFACING WITH INTEL 8085

5. METHODS OF DATA TRANSFER AND INTERRUPT STRUCTURE IN 8085 155

5.6.1 Introduction to RS-232 standard 160

7.7 Interfacing Stepper Motors 223

8. A COMPLETE 8085-BASED SYSTEM 292

PART 3: INTEL 8051 MICROCONTROLLERS

9. INTRODUCTION TO 8051 MICROCONTROLLERS 303

9.5.1 Special function registers 308

10. 8051 INSTRUCTION SET AND PROGRAMMING 314

11.6 8051 Serial Ports

12. 8051 INTERFACE EXAMPLES 366

PART 4: INTEL 8086—16-BIT MICROPROCESSORS

13. INTEL 8086 MICROPROCESSOR ARCHITECTURE, FEATURES,

14.1.4 Program memory addressing modes 435

16.4 Interfacing RAM/EPROM Chips using Decoder IC and Logic

17.9 Typical Multiprocessor System having 8086 and 8089 553

PART 5: INTEL 8096—16-BIT MICROCONTROLLERS

19. OVERVIEW OF INTEL 8096 MICROCONTROLLERS 585

20. 8096 INSTRUCTION SET AND PROGRAMMING 598

20.2.6 Long-indexed addressing 600

21. HARDWARE FEATURES OF 8096 616

21.9.1 HSO status 645

PART 6: ADVANCED TRENDS

22. MICROPROCESSOR SYSTEM DEVELOPMENTS AND RECENT TRENDS 659

23.6.2 Protected mode operation of Pentium '05

1.2 EXPLANATION OF BASIC TERMS

Microcontroller A microcontroller is a chip that includes microprocessor,

Firmware Software written for a microprocessor application without provision

Interpreter A computer program that reads the high-level or assembly-level

1.3 MICROPROCESSORS AND MICROCONTROLLERS

1.4 MICROPROCESSOR-BASED SYSTEM

Fig. 1.1 Microcomputer system (Von-Neumann model)

used to identify a location in the memory

1.5 ORIGIN OF MICROPROCESSORS

ol microprocessors is categorized into five generations: first, second, third, fourth,

1.5.1 First Generation (1971-1973)

1.5.2 Second Generation (1974-1978)

1.5.3 Third Generation (1978-1980)