Save trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com BCS Serials ] ine ] 156.663 Sixth Semester B.E. Degree Examination, Dec.2018/Jan.2019 Digital System Design using Verilog ‘Time: 3 hs Max, Macks: 80 Note: Answer any FIVE full questions choosing ¥ ‘ONE full question from exch module. ° i Module-t Z1a ih ilustraton, a simple design methodology followed god Maks a 8 following conseaimts imposed in real word circuits 3 HASberaUR Mitral ay ostsi 2, Develop a verilog model for 8 7-segmecetdscoder. inclug ut blank. hat # ‘overrides the BCD ip and causes all segments not 9 be Ii Marks) OR 2 a. Develop a verilog module of « debouncer for teh that uses 4 dcbownece imersal oF 1ns. Assume the system clock fi (06 Marks) Design and develop a citcut apd verilog FA counters (06 Maths) ‘© Wht is the distinction between 2 Moore: fe slate machine? {04 Mar) 8. Wee a symbol for basie memory explain its parts (We Marks) ‘Explain abou the multipor: meme 106 Marks) © Compute the 12-bit ECC Ro the 8-it data word “OLL000I". (bs Marks) oR 4 Design #64 K = 1alcom rmory using 14K » Sit component (0 Marks) bb What is the difgentSgueen asynchronous static RAM and synehronous static RAM? (06 Marks Using many check bits are required for single error comrection and souble nt data wor? (02 Marks Modute-3 sa rcoder that has 16 inputs, JO» 1S|:a d-bi encoded output. 3:0] and a ‘when any input "1 Inpat 0] bas the highest priority and 15) i the (os Marks) b ‘concept of differential signating. How does dileremial signaling impeove noise ‘immunity? (8 Marks) oR at ace the purpose of logie Macks and U0 blacks in FPGA? (06 Marks) Explain different iypes of PCB design (aa tars Explain with «neat diggram of the imma organization ofa CPLD, (07 stark Vo? BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Viuresource Go Green initiativeSave trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com 15EC663, Modute-4 1 1. What ore the purpose of fllowing in an (0 controller: i) input register i) outp ii control register i) status register. Explain neay the designing s Resting DAC © Explain about triste buses ad weak drive on a Design and develop a verilng code for an input controler that has 8-bi input fiom a sensor. Tho valuo ean be read trom an 8-bit input reas shold snded Gurmut, When input value changes, “he only ‘What ate the serial input standards? Briefly explain eae, (os marks) Modules 9 a Fplain the design flow of hardware sofware eo-sign 0 Marks riely describe techniques used in power optim (06 Mark oO 10 a. What isthe distinetion betwen logical pa eal partition? 8 Marks) 1b Explain Bul-In-Self=Test BIST) techni (08 Marky BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Viuresource Go Green initiativeSave trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com GAGS SoMENE ws [TT] | Sixth Semester B.E. Degree Examinati ly Digital System Design using Virology Time: 3 hrs, Man. Marks: 8 Note: Ansver any FIVE jull questions, choosing @ ‘ONE full question from each module, ‘Modute-t 1a Define the terms setup time, hold une and clock w output mgt a ip Ap ond w lank that ‘Ws Macks) module Mar ‘the constraints imposed hy these parameter on the eiruit 0 b, Develop verily module for 7 segment decnder nel ‘overrides the BCD input and causes all segments not 1 be ce Explain functional veriieaton and formal verification ve oR 2 a, What are the effects of capacitive load dlelay on signal teanstions between loge evels? (os Marks) Develop verilog module for 4-1 MUN. (08 Marks) Explain general view of digital systom wi ie section (4 Macks) 3a Design a 4k =8 bit four 16k» $ bit components and also explain hows ‘data outputs simplify the construction of fazer emer (0s Marks b. Explain esynchronoufiiat ining diagrams, oR 4a memories (Monks) b jorrection with one example (08 Marks &3 sa PCB desizn (0s Marks gah splaliinplementation fabri for digital system based on integrated ete, 7 Marks) é Ml and cross ak? ow on Mi cinngrwanesierog coy spn gal tay be PCB desgn and ako exh sens to vd tee ver? BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Viuresource Go Green initiativeSave trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com 15663 © Modules 17 4 Bape ser anion 6! i daa win lack donnin wa ining aga oe Explain the following serial interface standards for connecting VO devices. I) RS282 i) Fite wire 08 as on “as Marks Explain any 4 unalog sensors Explain the eonogpt of multplexed bases Module-5 Fsplain logical partitioning and physteat partitioning of cag Eyplain fault model and foul simutation. (8 Marks) (08 Mars Explain 4 bit LESR and CFSR for gen [Explain briefly area, power and timing 2082 BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Viuresource Go Green initiativeSave trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com GaCS ScHEME USN [ Sixth Semester B.E. Degree Examination, Dec.2019/Jan.202 Digital System Design Using Verilog “Time: 3 brs. Max. Ma Nate Answer FIVE fl quvions choosing neal question from eu. Modute-t 1a Explain the following constants imposed in real work! eccutlQ ff Ngo marsin (i) Stati evols (i) Propagation delay (i). Sate and ApS sump (os Marks) 1. Explain with ilsaton a simple methodology followed ig 1@adsee’ (on anh on 2 a. Developa verilog model fora 7 segment decoder. b. Develop a verilog model of a debouncer for a pust interval of 10 mS. Assume the system clock fe & Write a brief notes on finite state machine : Explain the different ROMs ug (06 ants) © Compute the 12 bit ECC word ltrespagigs tothe 8-bit data word 01100001, (24 Sark as gon Which that uses dt 7, (as Marts) (W6 Marts) Se raw. os Marks) ort, 4K = 6bit flow through SSRAML One por allows Jer por only allows data to be read. (05 Marks) a3 Marks) 4 a Explain briefly shout b. Develop a veriog data to be writen Write» nace on MM Modute-3 (oo Macks) vache) note on complex PLDs. PRRMaApErielly about the intemal organization ofan FPGA with a nest diagram Module: ain the analog inputs used in input devices Feplain any Four sri interface standards, Explain breil the eristate buses and weak keepers. BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Viuresource Go Green initiativeSave trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com 1SKC66; oR 8 a, Designand develop the verilog code for an input controle that has 8-bit binary eo {fom a sensor. The value ean be road from an S-bit input rogister, The contcllff should inerrup the embedded Gumnut core when the input value changes. The controls the only interupt source in the system. ce b. Show how G-bit data word can be transmitted serially botwoon two pons of a syst ‘Assume thatthe transmitter and the revever are both wii the signal starts set o [ona clack yee in which data Modute-5, 9 a. Explain the hardware and software co design flow. ‘Explain the design optimization tht are must to meet the sri (08 Maes) oR (08 Marts) (08 Marts) 2of2 BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Viuresource Go Green initiativeSave trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com GBCS SoHEHE sy 1SEC6 Sixth Semester B.E. Degree Examination, Aug./Sept. 2020 Digital System Design using Verilog Tine:3 hs Ma 0% a Note: Answer any FIVE full questions, choosing ONE full question from 1a Develop a that expresses the logical stucture@#t Rye git for vat buzzer. Assume that the sensor sighals and the switch signl apts 1 Wedel, nd that the buzzer signal is the output from the model. (orntaris) Develop a verilog model for a 7-segment decoder. Inctud® input, blac that ‘overides the BCD inpat and causes all segments not ta be lit, (@6niaris) 6. Develop a data path to perform = complex multiplied of two @WMplex numbers. Whose real and imaginary pars are represented as signe bers with 4-pre binary points and 12 post ~ binary points real and i fhe product ae represemed ‘with 8 pre-binary points and 24 post-binay p the main constraint. (@6Murhs) 2 a. Explain design methodology followed GC tagugry Wh nea: sketch. (Womans) 'b, Develop a test bench model for the roller, Verity the conditions that, when the enable input is 1, the output is te WM es. light iopur and when dhe enable input is “0° all ight outputs ate inactive (4 ais) ‘e. Write evetilog code for nite ‘of complex multiple control sequence. (aa Mtasts) fule-2 3 a Design IM 8 bite: -mory using $12 kx Sbit memory component. 4 Marko) b in the ECC word 000111000100 and if so correct it (6 darks) . al-port, 4K * 16 bit Low through SSRAM, One port allows ile the other port only allows data to be read. (Marks) o1 4a, Design a Wy = 1OvARomposite memory using 16K x 8 bit component saris) b. Co 2 bit ECC word corresponding tothe §-bit data word 01100001. (ot Marks) © Dé store upto 256 data itoms of 16 bits each, using a 256 x 16 bit dual-port, SSRAM fOrPW cata storage. The FIFO should provide sets outputs, to indicate, when the IFO is empty aad tall, Assume thatthe FIFO will wot be read when itis empty, nor be ten apn itis il, and ha the wete and read ports share « common clock. (6 Mask) Module-3 Outline witha neat sketch, the intemal organization of a CPLD. Marks) Jesign 4-igit cecimal counter with seven segment LED display with neat sketch using '4L$390 dual decade counter, four 74LS47 BCD Wo seven. seyment decoder, four 7-segment Aisplay, plus any additional gates required, cu yas) 10rd BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Vturesource Go Green initiativeSave trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Vturesource Go Green initiative