Journal of Integrated Circuits and Systems, vol. XX, n.
XX, 2018
Zero Temperature Coefficient behavior for Ellipsoidal MOSFET
M. P. Braga de Lima1, L. M. Camillo2, M. A. P. Peixoto2, M. M. Correia3 and S. P. Gimenez3
1
Electric Engineering Program, Federal University of Rio de Janeiro, Rio de Janeiro, Brazil
2
Electronics Technical Academic Coordination, CEFET/RJ Maracanã, Rio de Janeiro, Rio de Janeiro, Brazil
3
Electrical Engineering Department, FEI University Center, São Bernardo do Campo, São Paulo, Brazil,
e-mail: marcospblima007@gmail.com
Abstract—The zero temperature coefficient (ZTC) is investi-
gated by three-dimensional numerical simulations in the Metal-
Oxide-Semiconductor (MOS) Field Effect Transistor
(MOSFET) with the ellipsoidal (EM) and conventional rectan-
gular gate geometries (CM), considering the same channel
widths (W), gate areas (AG) and bias condition (BC). In this
work an improved simple model which predicts the ZTC point
taking into account only the mobility degradation factor (c) and
threshold voltage (Vth) parameters as function of temperature
is proposed in the linear and saturation operation regions. The
analysis takes into account the temperature variations of the
threshold voltage and the mobility degradation factor. Alt-
hough simple, the model predictions present a good agreement
with the numerical simulations results
Index Terms— Zero temperature coefficient, Ellipsoidal lay-
out style, Simple model, Mobility degradation.
I. INTRODUCTION
MOSFETs are widely used in the field of military, satel-
lite communications, medical equipment, automobile, nu-
clear sectors, wireless and mobile communications, etc., as
amplifier design, analog integrated circuits (ICs), digital
CMOS design, mixed-signal ICs, power electronics and
switching devices. As for demand in variety of applications
and the use the nanoscale transistors, it is important to ana-
lyze the performances at a wide range of temperatures [1].
It is desirable that the changes in temperature do not mod-
ify significantly the circuit performance. One of the solutions
for that is to bias the circuits at a point where the current
voltage characteristics show no or very little variation with
temperature, i.e., a bias point where the drain current is prac-
tically temperature independent. Such a point is known as the
zero-temperature coefficient (ZTC) bias point. Circuit de-
signers just start to consider biasing analog circuits at the
ZTC bias point in order to have low thermal drift variation
[2- 3].
Key to the design of high-temperature analog CMOS ICs
is biasing all circuits stages at ZTC drain currents, which re-
quires that appropriate gate voltages VGS at ZTC (VZTC) be
available on chip. For a given CMOS process, the magnitude
of VZTC is fixed for all n and p MOSFETs, and the desired
value of the corresponding IDS at ZTC (IZTC) is obtained by
adjusting the W/L ratio [4]. Some researchers have studied
the ZTC point in bulk MOSFETs [4,5] and partially depleted
(PD) SOI devices [6], taking into consideration the tempera-
ture dependence of the threshold voltage (Vth) and the mo-
bility (n) [4], including the body factor (n) [5] and also the
mobility degradation due to the transverse electric field ()
Digital Object Identifier 10.29292/jics.vXXiX.X
1
[6]. Recently, experimental studies have described the ad-
vantage of using the ellipsoidal layout style for MOSFETs in
relation to the typical rectangular one [7, 8]. The goal of this
work is to study the ZTC bias point for the ellipsoidal layout
style for MOSFETs and the typical rectangular one devices
based on three-dimensional (3D) numerical simulations data.
A simple ZTC analytical model is also used and updated for
the ellipsoidal devices, in order to validate if this model can
still be useful for these new devices, and consequently for
analog circuits designers.
II. THE ELLIPSOIDAL LAYOUT STYLE FOR PLANAR
MOSFETS
The shape of the ellipsoidal gate is a way to improve the
electrical performance of the MOSFET, since the resulting
Longitudinal Electric Field (LEF) is composed of three LEF
components along the central channel region (Longitudinal
Corner Effect, LCE) [9,10]. The parallel association of
MOSFETs with different channel lengths effect (PAMDLE)
[10,11,12] is an effect presented in the Ellipsoidal MOSFET
(EM) structure. In addition to improving tolerance to ioniz-
ing radiation, considering the effects of the Total Ionization
Dose (TID) and the Single Event Effects (SEE) due to the
parasitic Deactivation Parasitic MOSFETs in the Bird’s
Beak Region Effect (DEPAMBBRE) [13].
The new LCE and PAMDLE effects occur simultane-
ously and both contribute to improving the drain current of
MOSFET ellipsoidal as compared to the conventional one
counterpart.
These three effects (LCE, PAMDLE and DEPAMBBRE)
are able to improve the electrical performance of EM. We
also observed that EM not presents corners in its active struc-
ture, so this geometry is able to increase the tolerance of the
rupture voltage (BVDS) and the Electrostatic Discharge
(ESD) [14, 15].
The Figure 1 illustrations of the three-dimensional struc-
tures of the rectangular transistor type MOSFET (CM) in-
vestigated can be seen. Its shows a three-dimensional image
of the CM, whose main characteristic is the shape of the rec-
tangular gate. In the Figure, the dimensions of the channel
length (L), the channel width (W), the drain contact and the
source of the device are also observed.
The Figure 2 illustrations of the three-dimensional struc-
tures of the ellipsoidal type MOSFETs investigated can be
seen. Its shows the three-dimensional image of the Ellipsoi-
dal transistor type MOSFET (EM), whose main characteris-
tic is the structure of the gate region in an ellipse shape. In
2 M. P. Braga de Lima et al.: Zero Temperature Coefficient behavior for Ellipsoidal MOSFET

Fig. 1 - Rectangular transistor type MOSFET (CM) its three-dimen- Fig. 2 - Ellipsoidal layout style for planar mosfets its three-dimen-
sional (3D) structure. sional (3D) structure

the Fig. 1, the dimensions of B and b are also observed, current gain (IDS) of the EM in relation to the CM counter-
which are, respectively, the largest and the shortest channel part, due to the PAMDLE effect [10,11].
lengths of the EM device, the channel width (W), the drain Looking at the Table I, the reductions in EM Leff com-
contact and the source of the device. pared to those found in the CMs counterparts are 12.3%,
In order to make the necessary comparisons for this study, 14.4% and 15.2%, respectively, due to the PAMDLE effect.
dimensions W and b were kept constant in all EMs and their Thus, the LCE effect and the PAMDLE effect, displayed in
equivalent CMs. In addition, comparisons were made for de- the EM, are able to increase the performance in relation to
vices with ellipsoidal gate geometry EM and CM counterpart the CM counterparts (the same AG).
considering the same electrical polarization conditions (BC), The gate oxide thickness has the same value for both de-
with the same gate areas (AG) and aspect ratio (W/L). vices, EM and CM, tox equal to 14.2nm, the concentration of
Due to the ellipsoidal shape of the channel region, the re- dopant (NA) type P in the channel region assumes the value
sulting longitudinal electric field (LEF) vector is the sum of of 1.7x1017cm-3, the concentration of dopants from the drain
the LEF vector components due to the polarization between and source (ND) is equal to 1x1020 cm-3.
drain and source (VDS), so when considering the same AG
and the same polarization condition, the EM device has a III. ZTC ANALYTICAL MODEL
higher value for the LEF result than that found in the respec-
tive conventional CM homologous (only one LEF). The ZTC condition was analyzed using the Camillo-
[16,9,10]. Matino ZTC (Zero Temperature Coefficient) analytical
This important property is called the Longitudinal Corner model [17], a simple model that was proposed to study the
Effect (LCE). Thus, for the EM device, the vector resulting behavior of the gate voltage at ZTC (VZTC) in the linear and
from the LEF forces the drain current to flow further to the the saturation region for conventional rectangular gate geom-
center of the transistor's channel region, due to the greater etries devices. In this work is also used and updated for the
interaction of the LEF components along the channel. ellipsoidal devices.
In addition, EM can be represented electrically by a par-
A. Linear Region VZTC model
allel connection of MOSFETs with different channel lengths
[9,10]. Therefore, the EM aspect ratio (W/Leff) can be ob- The drain current (ID) of a MOSFET transistor operating
tained by the equation below. [10]. in the linear region at a temperature T1, can be described by
𝐿𝑒𝑓𝑓 =
𝑏
(1) equation (2)[18].
2 𝑏 𝑊 𝑛 𝑉2
𝑎𝑟𝑐𝑠𝑖𝑛(√1−
𝐵2
) 𝐼𝐷𝑆1 = 𝜇𝑛1 𝐶𝑜𝑥𝑓 [(𝑉𝐺𝐹 − 𝑉𝑡ℎ1 )𝑉𝐷𝑆 − 1 𝐷𝑆]
𝐿 2
(2)
Table I shows the dimensions of the three-dimensional
structures of the EMs and Its equivalent CMs, which were where Coxf = ox/tox, tox is the gate oxide thickness, ox is
simulated. In addition, the Table shows the percentage of L the permittivity of SiO2, W and L are the channel width and
reduction in EM devices (Leff) in relation to Its respective length respectively, VGF and VDS are the front gate and drain
equivalent CMs, considering the equation [10]. The Table voltage, respectively. The effective electron mobility n1, the
presents the dimensions of the EMs and CMs counterparts, threshold voltage Vth1 and the body factor n1 are at a temper-
AG, Leff and the Leff reductions of the EMs in relation to the ature T1. By definition, the ZTC point represents the gate
L of the CMs counterparts, which correspond to the drain voltage (VZTC), which insures that the drain current remains
constant with temperature variations.
Table I. Geometric characteristics of the structures of The parameter n1 depends on: low field mobility (µn0(T1)),
the EMs and the simulated CMs. mobility degradation due to the transverse electric field (),
W/L Gate CM EM Leff reduc-
Area [μm] [μm] tions in re- gate voltage (VGF) and the threshold voltage (Vth1). These pa-
lation to rameters are related according to (3).
the L 𝜇𝑛0[𝑇1]
W/L AG W L W LGeo b B Leff [%] 𝜇𝑛1 = 𝜃1 (3)
[μm2] 1+ (𝑉𝐺𝐹 −𝑉𝑡ℎ1 )
𝑛1
0,85 41,65 5,95 7,000 5,95 7,000 1,05 8,913 6,14 +12,3
0,5965 59,35 5,95 9,975 5,95 9,975 1,05 12,701 8,53 +14,4
0,4971 71,22 5,95 11,97 5,95 11,97 1,05 15,241 10,15 +15,2
For simplification purposes one can consider that n1 ≈ n2
≈ n, θ1 ≈ θ2 ≈ θ and can be approximated using by the equa-
tions (4), (5) e (6):
Journal of Integrated Circuits and Systems, vol. XX, n. XX, 2018 3

𝜃1 𝜃2
≈ (4)
𝑛1 𝑛2 Analyzing ellipsoidal MOSFETs with 0° < β < 90° in (12)
𝜃1 𝜃2
1+ (𝑉𝐺𝐹 − 𝑉𝑡ℎ1 ) = 1 + (𝑉𝐺𝐹 − 𝑉𝑡ℎ2 ) (5) at two different temperatures: T1 and T2, one obtains IDS EM
𝑛1 𝑛2
𝑇 𝑐 [T1] and IDS EM [T2], respectively.
𝜇𝑛2 = 𝜇𝑛1 ( 1) (6)
𝑇 2
𝑊 𝐿
where µn1 and µn2 represent, respectively, the effective elec- 𝐼𝐷𝑆𝐸𝑀[𝑇1] = √2 [1 + 𝑐𝑜𝑠 (2𝑡𝑎𝑛−1 (𝛽𝜋 ))] 𝐿 𝐶𝑀 𝐼𝐷𝑆𝐶𝑀[𝑇1] (16)
−2𝑏 𝑒𝑓𝑓
2
trons mobilities, temperature mobility degradation factor (c)
and the threshold voltages Vth1 and Vth2 at temperatures T1 𝐼𝐷𝑆𝐸𝑀[𝑇2] = √2 [1 + 𝑐𝑜𝑠 (2𝑡𝑎𝑛−1 (𝛽𝜋
𝑊 𝐿
))] 𝐿 𝐶𝑀 𝐼𝐷𝑆𝐶𝑀[𝑇2] (17)
and T2. By definition, the ZTC point represents the gate volt- 2
−2𝑏 𝑒𝑓𝑓

age (VZTC), which insures that the drain current remains con-
stant with temperature variations. We could observe that the parameters W, B, b, LCM and Leff
Using (3) at a temperature T2 (T2>T1), the cross point be- show no variation with temperature, because are the physical
tween both curves (IDSxVGF) presents the coordinates, and geometry parameters, therefore the influence of the tem-
VZTC(T1,T2) and IZTC(T1,T2), the VZTC LIN can be isolated as perature variation will be verified in the term of the conven-
𝑇1 𝑐
tional MOSFET current drain (IDSCM). Thus, we can apply the
(𝑉𝑡ℎ1 −𝑉𝑡ℎ2 )( )
𝑉𝑍𝑇𝐶 𝐿𝐼𝑁 = 𝑉𝑡ℎ1 +
𝑇2
+𝑛
𝑉𝐷𝑆
(7) simple ZTC analytical model, for the linear and the satura-
𝑇1 𝑐 2
1−(
𝑇2
) tion operating regions. The same methodology can be ap-
plied to (13) for transistors with 90° < β <180° using the FCV
B. Saturation region VZTC model correction factor.
The drain current (ID) of a MOSFET transistor operating Analyzing the FCH correction factor, we can see limit val-
in the saturation region and temperature T1 can be described ues that lead an allowed range of due to the geometry and
by equation (8)[18]. structure limitations of the device technology. It is assumed
𝑊 (𝑉𝐺𝐹 −𝑉𝑡ℎ1)2 that B >> W means that the ratio in tangent arc term tends to
𝐼𝐷𝑆1 = 𝜇𝑛1 𝐶𝑜𝑥𝑓 [ ] (8) zero:
𝐿 2𝑛1
𝑊
The same methodology can be applied to the linear re- 𝛽𝜋 →0 (18)
−2𝑏
2
gion, but considering (8) in the saturation region at a temper-
ature T2 (T2>T1). The cross point between both curves Replacing (16) in (12):
(IDSxVGF) corresponds with the coordinates VZTC(T1,T2) and 𝐿𝐶𝑀
IZTC(T1,T2). So that by using the approximation that (4), (5) and 𝐹𝐶𝐻 = √2[1 + 𝑐𝑜𝑠(2𝑡𝑎𝑛−1 0)]
𝐿𝑒𝑓𝑓
(6), and the VZTC SAT can be determined as shown in: 𝐿𝐶𝑀
𝐹𝐶𝐻 = 2 (19)
𝐿𝑒𝑓𝑓
𝑉𝑍𝑇𝐶 𝑆𝐴𝑇 = 𝐴 + √𝐴2 + 𝐵 (9)
For the case of B = W, we can see that this is the smallest
𝑇 𝑐
(𝑉𝑡ℎ1 −𝑉𝑡ℎ2 )( 1 )
𝑇2
possible value of B, because the ellipse becomes a circle. Us-
𝐴 = 𝑉𝑡ℎ1 + 𝑇 𝑐 (10) ing value maximum b = B/2 and replacing these values in
1−( 1 )
𝑇2 (14):
2 2 𝑇 𝑐
𝑉𝑡ℎ1 −𝑉𝑡ℎ2 (𝑇1 )
2
𝐵= 𝑇 𝑐 (11) 𝑊 𝐿𝐶𝑀
1−( 1 ) 𝐹𝐶𝐻 = √2 [1 + 𝑐𝑜𝑠 (2𝑡𝑎𝑛−1 ( ))]
𝑇2
𝑊𝜋 𝑊 𝐿𝑒𝑓𝑓
−2
2 2
C. The Analysis ZTC Model to ellipsoidal transistors 𝐿𝐶𝑀
𝐹𝐶𝐻 = 1 ∙ (20)
Analyzing the model drain current equations IDSEM (12) 𝐿𝑒𝑓𝑓
and (13)[19], for ellipsoidal MOSFETs[7] with 0° < β < 90°
and 90° < β <180° respectively, we can see that there is a Results (19) and (20) show that the drain current in the ZTC
correction factor applied to the drain current of the conven- point (IZTC) to ellipsoidal transistors for W ≤ B, is within the
tional MOSFETs IDSCM, due to longitudinal corner effect range:
𝐿 𝐿
(LCE) and The Parallel connection of MOSFETs with Dif- 2 𝐶𝑀 𝐼𝐷𝑆 𝐶𝑀(𝑍𝑇𝐶) < 𝐼𝐷𝑆 𝐸𝑀(𝑍𝑇𝐶) < 1 𝐶𝑀 𝐼𝐷𝑆 𝐶𝑀(𝑍𝑇𝐶)
𝐿 𝐿
(21)
𝑒𝑓𝑓 𝑒𝑓𝑓
ferent channel Lengths Effect (PAMDLE).
Performing the same analysis to FCV correction factor,
(12) described by (15), initially assuming that W >> B, this takes
the ratio in tangent arc term tends a high value; consequently
leading its result to tend to π/2. Substituting this value in
(15):
(13)
This factor will be called "Correction Factor" and repre- 𝑊 𝐿𝐶𝑀
𝐹𝐶𝑉 = √2 + 𝑐𝑜𝑠 [2𝑡𝑎𝑛−1 ( )]
sented by: FCH for transistors with 0° < β < 90° and FCV for 𝑊𝜋 𝑊 𝐿𝑒𝑓𝑓
−2
2 2
transistors with 90° < β <180°, according to (14) and (15). 𝐿𝐶𝑀
𝐹𝐶𝑉 = 1 ∙ (22)
𝑊 𝐿𝐶𝑀
𝐿𝑒𝑓𝑓
𝐹𝐶𝐻 = √2 [1 + 𝑐𝑜𝑠 (2𝑡𝑎𝑛−1 (𝛽𝜋
−2𝑏
))] 𝐿 (14) Defining now, for the same FCV correction factor, as W = B,
𝑒𝑓𝑓
2
that this is the smallest possible value of W, because the el-
𝑊 𝐿
𝐹𝐶𝑉 = √2 + 𝑐𝑜𝑠 [2𝑡𝑎𝑛−1 (𝛽𝜋 )] 𝐿 𝐶𝑀 (15) lipse becomes a circle. Using maximum b = B/2 and replac-
−2𝑏 𝑒𝑓𝑓
2
ing these values in equation (15):
4 M. P. Braga de Lima et al.: Zero Temperature Coefficient behavior for Ellipsoidal MOSFET

𝑊 𝐿𝐶𝑀
𝐹𝐶𝑉 = √2 + 𝑐𝑜𝑠 [2𝑡𝑎𝑛−1 ( )]
𝑊𝜋 𝑊 𝐿𝑒𝑓𝑓
−2
2 2
𝐿𝐶𝑀
𝐹𝐶𝑉 = 1.22 (23)
𝐿𝑒𝑓𝑓
The results (22) and (23), shows that the drain current at
the ZTC point (IZTC) for ellipsoidal transistors, where W > B
is in the range in (24):
𝐿 𝐿
1,22 𝐶𝑀 𝐼𝐷𝑆 𝐶𝑀(𝑍𝑇𝐶) < 𝐼𝐷𝑆 𝐸𝑀(𝑍𝑇𝐶) < 𝐶𝑀 𝐼𝐷𝑆 𝐶𝑀(𝑍𝑇𝐶)
𝐿 𝐿
(24)
𝑒𝑓𝑓 𝑒𝑓𝑓

IV. SIMULATION RESULTS AND DISCUSSION

Simulations of the rectangular transistor type MOSFET

(CM) and the Ellipsoidal transistor type MOSFET (EM)
were performed by using the SILVACO TCAD tools.
SILVACO TCAD tool called DevEdit3D was used to gener-
ate the device structure and ATLAS was used to simulate the
current–voltage characteristics [20].
The devices with ellipsoidal gate geometry EM and CM
counterpart considering the same electrical polarization con-
ditions (BC), with the same gate areas (AG) and aspect ratio
(W/L). The gate oxide thickness has the same value for both
devices, EM and CM, tox equal to 14.2nm, the concentration
of dopant (NA) type P in the channel region assumes the
value of 1.7x1017cm-3, the concentration of dopants from the Fig. 3. IDS x VGS curves simulated obtained of the rectangular transistor
drain and source (ND) is equal to 1x1020 cm-3. type MOSFET (CM) and the Ellipsoidal transistor type MOSFET (EM)
Figure 3 shows the drain current (IDS) as a function of devices for a temperature range from 300 up to 450 K in linear (VDS =
gate-source voltage (VGS) with the temperature ranging from 50mV) and saturation region (VDS = 1.5V).
300 to 450 K in the linear and saturation regions of the CMs
obtained by simulations for each temperature, using the dou-
and EMs structures with its respective ZTC point. ble derivative method[22].
By definition, the ZTC point represents the gate bias To determine the best c values to fit the simulated data a
which ensures that the drain current remains constant with simple arithmetic mean of the values obtained in each inter-
temperature variations [5]. This point is reached when the
action between the different simulated temperatures, for both
temperature mobility reduction compensates the threshold
operating regime linear and saturation.
voltage shift with T. The decrease of mobility and threshold
Figs. 4, 5 e 6 show the VZTC values, obtained by simula-
voltage are the main contributing factors to the position of
the ZTC point [21]. tions and the simple model, in function of temperature for
The table II shows the values of the ZTC voltage extracted EM structures operating in linear and saturation regime.
for ellipsoidal and conventional devices with the same gate
areas (AG) and aspect ratio (W/L). A reasonable close agreement with simulated results is
observed even though some simplifications were adopted.
TABLE II - Results of the VZTC obtained from simulations of to the EM and
CM transistor operating in the linear and saturation region. The maximum errors obtained from comparison between
Linear region simulation and theoretical data are reported in Table III
Gate
Devices Ellipsoidal Conventional
Area
AG [μm2] VZTC (V) IZTC (A) VZTC (V) IZTC (A)
41,65 4165 0,98 1,14 0,99 0.58
59,35 5935 0,99 1,34 0,99 0.43
71,22 7122 0,98 1,28 1,00 0.36
Saturation region
41,65 4165 1,20 11.1 1,20 4,29
59,35 5935 1,20 10.5 1,20 2,97
71,22 7122 1,20 11.3 1,20 2,43

Based on Table II we notice that the same value of the

ZTC voltage was obtained in all regimes (linear and satura-
tion) for ellipsoidal and conventional devices, and the EM
IZTC values are always higher than those extracted in the CM
equivalent. In both operating regions, by Eq. (8) and Eq. (10)
shows that when the temperature increases, (Vth1-Vth2) in- Fig. 4. VZTC obtained by simulations and the simple model for
creases and [T1/T2]c decreases. The competition of these two EM4165 device (AG = 41,65 [μm2]) operating in the linear and the
terms depends on the value of the c coefficient, which is re- saturation region.
sponsible for the VZTC changes as a function of temperature.
The Vth1 and Vth2 used in Eqs. (8) and (10) are the values
Journal of Integrated Circuits and Systems, vol. XX, n. XX, 2018 5

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