Memristor Devices Fabrication Characterization Simulation and Circuit Design

MEMRISTOR DEVICES: FABRICATION, CHARACTERIZATION, SIMULATION,
AND CIRCUIT DESIGN
Thesis
Submitted to
The School of Engineering of the
UNIVERSITY OF DAYTON
In Partial Fulfillment of the Requirements for
The Degree of
Master of Science in Electrical Engineering
By
Chris Yakopcic
Dayton, Ohio
August, 2011
AND CIRCUIT DESIGN
Name: Yakopcic, Chris
APPROVED BY:
_________________________________ _________________________________
Tarek M. Taha, Ph.D. Guru Subramanyam, Ph.D.
Advisory Committee Chairman Committee Member
Associate Professor Chair and Professor
Electrical and Computer Engineering Electrical and Computer Engineering
_________________________________
Andrew Sarangan, Ph.D.
Committee Member
Associate Professor
Electro-Optics
_________________________________ _________________________________
John G. Weber, Ph.D. Tony E. Saliba, Ph.D.
Associate Dean Dean, School of Engineering
School of Engineering & Wilke Distinguished Professor
ii
©Copyright by
Chris Yakopcic
All Rights Reserved
2011
iii
ABSTRACT
AND CIRCUIT DESIGN
Name: Yakopcic, Chris

University of Dayton
Advisor: Dr. Tarek M. Taha
Significant interest has been placed on developing systems based on memristors
since the initial fabrication by HP Labs in 2008 [1]. The memristor is a nanoscale device
with dynamic resistance that is able to retain the last programmed resistance value after
power is removed from the device. This property shows that the memristor can be used as
a non-volatile memory component, and has potential to enhance many types of systems,
such as high density memory, and neuromorphic computing architectures.
This thesis presents the fabrication and characterization results obtained based
memristor devices developed at the University of Dayton. In addition, a comparison
between the existing memristor device models was completed to show how the memristor
can be used in a multistate operation. Lastly, circuit designs were completed that
demonstrate the writing and reading of information to and from memristor devices. These
represent the initial steps required in developing electronic systems based on memristors.
A large portion of the work completed in this thesis has been published in [2-4].
iv
ACKNOWLEDGMENTS
My special thanks are in order to Dr. Tarek M. Taha, my advisor, for providing
the time and equipment necessary for the work contained herein, and for directing this
thesis and bringing it to its conclusion with patience and expertise.
I would also like to express my appreciation to everyone who has helped me with
this work. This includes Dr. Andrew Sarangan and Dr. Eunsung Shin, who were
responsible for fabricating the devices characterized in these experiments; Dr. Guru
Subramanyam and Dr. Douglas Hansen, who provided the necessary equipment for
characterizing the devices; and Mark Patterson, who offered his help and expertise when
designing the mask set used for the second device fabrication experiment.
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TABLE OF CONTENTS
ABSTRACT ....................................................................................................................... iv
ACKNOWLEDGMENTS ...................................................................................................v
LIST OF FIGURES ........................................................................................................... ix
I. INTRODUCTION ............................................................................................................1
II. BACKGROUND .............................................................................................................5
2.1 Memristor Origin ....................................................................................................... 5
2.2 Physical Memristor Discovery .................................................................................. 6
2.2.1 HP Labs Titanium Dioxide Memristor................................................................ 7
2.2.2 Alternative Thin-Film Memristor Designs .......................................................... 9
2.2.3 Spintronic Memristor Devices .......................................................................... 10
2.3 RRAM ..................................................................................................................... 11
2.4 Device Modeling ..................................................................................................... 11
2.5 Circuit Design .......................................................................................................... 12
2.6 Applications ............................................................................................................. 14
III. PHYSICAL DEVICE EXPERIMENT 1 .....................................................................15
3.1 Device Fabrication ................................................................................................... 15
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3.2 Experimental Test Setup .......................................................................................... 17
3.3 Experimental Test Results ....................................................................................... 18
3.3.1 Characterization by User Controlled Test Setup ............................................... 18
3.3.2 Characterization by Computer Controlled Test Setup ...................................... 22
3.3.3 Characterization Using Pulse Waveform .......................................................... 25
IV. PHYSICAL DEVICE EXPERIMENT 2 .....................................................................27
4.1 Mask Design for Future Devices ............................................................................. 27
4.1.1 Overall Mask Set ............................................................................................... 28
4.1.2 Device Patterns in Mask Design ....................................................................... 29
4.2 Second Generation Device Fabrication ................................................................... 31
4.3 Second Generation Device Characterization ........................................................... 34
V. COMPARISON OF DEVICE MODELING METHODS ............................................37
5.1 Modeling Equations ................................................................................................. 37
5.2 Equation Based Device Simulation ......................................................................... 40
5.2.1 Device Simulation Based on Linear Model ...................................................... 40
5.2.2 Device Simulation Based on Non-Linear Model 1 ........................................... 42
5.2.3 Device Simulation Based on Non-Linear Model 2 ........................................... 43
5.3 Resistance State Analysis Based on Device Models ............................................... 44
5.3.1 Resistance States in the Linear Device Model .................................................. 44
5.3.2 Resistance States in the Non-Linear Device Models ........................................ 45
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5.3.3 Resistance State Comparison ............................................................................ 47
5.4 Device Modeling Based on Fabrication Data .......................................................... 50
VI. CIRCUIT DESIGN BASED ON NON-LINEAR DRIFT MODEL ...........................53
6.1 Circuit for Writing to Memristor ............................................................................. 53
6.1.1 Write Circuit Schematic .................................................................................... 53
6.1.2 Simulation Results for Memristor Write Circuit ............................................... 54
6.2 Circuit for Reading Resistance of a Memristor Device ........................................... 56
6.2.1 Read Circuit Schematic ..................................................................................... 56
6.2.2 Simulation Results for Memristor Read Circuit ................................................ 57
VII. CONCLUSION ..........................................................................................................59
BIBLIOGRAPHY ..............................................................................................................62
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LIST OF FIGURES
3.1. Device layout for UDMEM1. .................................................................................... 16
3.4. Memristors on wafer: (a) alignment of multiple memristors on a wafer, and (b) probe
applied to test a single device. .......................................................................................... 17
3.5. Test results for UDMEM1 with a voltage loop ranging from -4V to 4V. ................. 19
3.6. Test results for UDMEM2 with a voltage loop ranging from -4V to 4V. ................. 19
3.7. I-V curve results for UDMEM2 with voltage ranging from -8V to 5V.................... 20
3.8. Multiple voltage loop test, first pass. ......................................................................... 21
3.9. Multiple voltage loop test, second pass. .................................................................... 21
3.10. Multiple voltage loop test, third pass. ...................................................................... 21
3.11. Test results for UDMEM2 with a voltage from -5 to 5V on the first pass. ............. 23
3.12. Test results for UDMEM2 with a voltage from -5 to 5V on the second pass.......... 23
3.13. Test results for UDMEM2 with a voltage from -5 to 5V on the fifth pass. ............. 23
3.15. Test results for UDMEM8 with a voltage from -4 to 4V on the second pass.......... 25
3.17. Test results showing the resistance drop across the memristor as a function of the
number of voltage pulses applied to the device. ............................................................... 26
ix
4.1. Layout of entire mask. ............................................................................................... 28
4.2. Layout for (a) top metal mask, (b) etch mask, and (c) bottom metal mask. .............. 28
4.3. Layout of 4 different areas in the mask set including (a) the larger individual devices,
(b) the crossbar with 100 µm2 overlap, (c) the smaller individual devices, and (d) the
crossbar with 25 µm2 overlap. .......................................................................................... 30
4.4. Span of devices that are included in the larger device set (25 µm2 to 400 µm2). ...... 31
4.5. Span of devices in the smaller devices set (0 µm2 to 35 µm2). .................................. 31
4.6. Device layout for second generation memristor device (contact pads not shown).... 32
4.7. Images of the SiO2 wafer after Pt deposition displaying (a) the contact pad and wire
leading to an isolated device, and (b) the wire passing through the circular definition of a
crossbar device. ................................................................................................................. 32
4.8. Image displaying memristor wafer after deposition of TiO2 and TiO2-x layers. ........ 33
4.9. Images displaying the lithography pattern for the top metal for (a) an isolated device,
and (b) a device in a crossbar. ........................................................................................... 33
4.10. Images of fabricated wafer displaying (a) portion of a memristor crossbar, and (b)
an array of single devices in a wire bonded packaging. ................................................... 33
4.11. Test results for the 200µm2 memristor device. ........................................................ 36
4.12. Test results for the 100µm2 crossbar memristor device. .......................................... 36
5.1. Simulation results for testing liner drift velocity model. The top left plot shows the
current and voltage waveforms with respect to time, and the top right plot shows the I-V
characteristic. The bottom left plot shows position of the barrier between the titanium
oxide layers and the bottom right plot shows resistance as a function of time. Simulation
x
parameters are, RON=100Ω, ROFF=1000Ω, D=46nm, µD=10-14m2V-1s-1, w0/D=.2, with a
triangle voltage input where f=2Hz and A=.25V. ............................................................. 41
5.2. Simulation results for testing the Joglekar non-linear drift velocity model with p=1.
The top left plot shows the current and voltage waveforms w. r. t. time, and the top right
plot shows the I-V characteristic. The bottom left plot shows position of the barrier
between the titanium oxide layers and the bottom right plot shows resistance as a function
of time. Simulation parameters are, RON=100Ω, ROFF=1000Ω, D=37nm, µD=10-14m2V-1s-

1
, w0/D=.2, with a triangle voltage input where f=2Hz and A=.25V. ................................ 42
5.3. Simulation results for testing the Biolek non-linear drift velocity model with p=1.
of time. Simulation parameters are, RON=100Ω, ROFF=1000Ω, D=32nm, µD=10-14m2V-1s-

1
,w0/D=.2, with a triangle voltage input where f=2Hz and A=.25V. ................................. 43
5.4. Plot on the left shows number of resistance levels achieved using the linear drift
model for D=90-115nm where RON/ROFF=10 for current pulse differentials given as 5, 10,
and 15%. Plot on the right shows same data for RON/ROFF=50 and D=42-55nm. Other
simulation parameters are, RON=100Ω, µD=10-14m2V-1s-1, w0/D=.2, with a triangle voltage
input where f=4Hz and A=2V. .......................................................................................... 45
5.5. Plot on the left shows number of resistance levels achieved using the Joglekar non-
linear drift model for D=60-120nm where RON/ROFF=10 for current pulse differentials
given as 5, 10, and 15%. Plot on the right shows same data for RON/ROFF=50 and D=30-
xi
50nm. Other simulation parameters are, RON=100Ω, µD=10-14m2V-1s-1, w0/D=.2, with a
triangle voltage input where f=4Hz and A=2V. ................................................................ 46
5.6. Simulation results for testing the Joglekar non-linear drift velocity model with p=1.
of time. Due to the strong memristive effect, device operates as a linear resistor after 1.5s.
Simulation parameters are, RON=100Ω, ROFF=1000Ω, D=50nm, µD=10-14m2V-1s-

1
,w0/D=.2, with a triangle voltage input where f=4Hz and A=2V. .................................... 47
5.7. Plot on the left shows number of resistance levels achieved using the Biolek non-
linear drift model for D=50-110nm where RON/ROFF=10 for current pulse differentials
given as 5, 10, and 15%. Plot on the right shows same data for RON/ROFF=50 and D=30-
50nm. Other simulation parameters are, RON=100Ω, µD=10-14m2V-1s-1, w0/D=.2, with a
triangle voltage input where f=4Hz and A=2V. ................................................................ 47
5.8. Comparison of results for resistance level data presented in previous section using a
minimum pulse differential of 5%. ................................................................................... 49
5.9. Device conductance as a function of doped layer thickness when using simulations
based on equation (1). ....................................................................................................... 49
5.10. Simulation results for numerically based model that incorporates programming
threshold displaying (a) the voltage input, (b) the memristor state, and (c) the dynamic
resistance value. ................................................................................................................ 52
6.1 MOSFET based memristor write circuit. .................................................................... 54
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6.2. Memristor response to write circuit simulation with voltage applied from V1. Top
left plot shows the voltage across the memristor, when the 5V pulses are applied, the top
right plot shows the current in the memristor and the voltage pulse are applied, and the
bottom plot shows the shift if the state variable w(t) relative to the thickness of the
device. ............................................................................................................................... 55
6.3. Memristor response to write circuit simulation with voltage applied from V2. Top
left plot shows the voltage across the memristor, when the 5V pulses are applied, the top
right plot shows the current in the memristor and the voltage pulse are applied, and the
bottom plot shows the shift if the state variable w(t) relative to the thickness of the
device. ............................................................................................................................... 55
6.4 Comparator based read circuit for memristor. ............................................................ 57
6.5. Read circuit simulation. The top plot shows the input voltage, the middle plot shows
the voltage generated between the memristor and the 75k resistor, and the bottom plot
shows the output of each of the comparators. ................................................................... 58
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CHAPTER I
INTRODUCTION
For nearly 180 years, it has been accepted that there are three fundamental
passive circuit elements, the resistor (1827), the capacitor (1745), and the inductor
(1831). In 1971 Dr. Leon Chua theorized that mathematically there should be a fourth
fundamental circuit element based on the symmetry of the equations that govern passive
circuit theory [5]. Dr. Chua called this device the memristor (short for memory-resistor),
and in 2008 Hewlett Packard Labs published results of the device in physical form [1].
The physical memristor is nanoscale device that has unique properties that can be
used to greatly improve existing electronic systems and computing architectures. The
memristor can be thought of as a time varying resistor where the resistance changes due
to the summation of current that has passed through the device [5]. When the current
flowing through the device is zero, the summation of current becomes constant, and thus
the resistance remains unchanged. This shows that the memristor can be used as a non-
volatile memory component.
Furthermore, the dynamics of a memristor closely resemble those of a synapse in
brain tissue. Just as the values of synaptic weights change with the application of neural
spikes, the resistance value of a memristor can be changed with the application of a
voltage pulse. This could provide significant advancements in the field of neuromorphic
1
computing as electronic systems using memristors could be fabricated with a device
density similar to that of the human brain [6].
Since the memristor‘s physical discovery, several institutions have published
memristor device fabrications using a variety of different materials and device structures
[2, 7-13]. Different device structures are still being developed to determine which
memristor device would be the best option for commercial use. This is based on many
factors such as size, switching speed, power consumption, switching longevity, and
CMOS compatibility.
Several device models have also been proposed that can be used simulate
memristor based circuits [1, 14, and 15]. The circuits published thus far involve methods
of writing to and reading from memristors [16-19], and using a memristor based circuit as
a component in a neuromorphic system [20, 21]. The memristor devices, memristor
models, and basic circuit designs will serve as the first steps in developing electronic
systems and computing architectures based on memristors.
The work presented in this thesis involves memristor device fabrication and
characterization, memristor model comparisons, and read and write circuit designs. Two
different memristor fabrication experiments are described. The first was based on a set of
wafers containing an array of isolated devices with a large cross-sectional area (375 by
375µm) where each wafer was fabricated with different oxide thicknesses. The results of
this experiment showed that the wafer with a total oxide thickness of 100 nm provided
the most reliable devices. A large hysteresis pattern could be seen when the device was
positively biased. The work based on this experiment was published in [3, 4]. The second
memristor fabrication experiment was based on a much more complex wafer. A mask set
2
was designed to produce isolated memristor devices with variable cross-sectional area
(2.5µm2 to 400µm2) in addition to small crossbar arrays containing 36 devices at a cross-
sectional area of ether 25µm2 or 100µm2. The results of the wafer based on this design
provided a stronger hysteresis pattern in both the positive and negative voltage regimes.
A comparison of three existing memristor device models was performed to show
how the memristor could be used as a multistate memory device for use in a high density
memory system or a synaptic weight in a neural system. The three models compared
were published in [1, 14, and 15] and were developed on the basis that a memristor acts
as two variable resistors in series where the dynamic resistance component is determined
by a state variable. The state variable assigns a numerical value to the physical changes in
the device that relate to a change in resistance. The motion of the state variable differs in
each of these models. The simulations completed in this experiment examine how many
distinguishable resistance values can be observed after a series of voltage pulses are
applied to the device model. The results showed that the model in [15] provided the
maximum amount of observable resistance levels, although the models have a large
amount of discrepancy when comparing to actual characterization data. The work
completed based on the model comparisons was published in [2]. An alternative
modeling approach was developed based on characterization data provided in [10], and
was developed using a lookup table approach.
Circuits were then developed to write information and to read information from
memristors. Simulations of the circuit designs were performed in SPICE using the
memristor model published in [15]. The simulation results for the write circuit show that
the state (conductivity) of a memristor can be increased or decreased when a positive
3
voltage pulse is applied to one of two inputs. The read circuit shows how a system of
comparators can be used to quantize the resistance value of a memristor into a discrete
number of states for digital processing.
Chapter 2 provides a background section that describes the work completed based
on memristors since it was first theorized by Dr. Chua [5]. Chapter 3 presents the
fabrication techniques and results for the first memristor fabrication experiment carried
out at the University of Dayton. Chapter 4 describes the mask design for the more
complex set of memristors along with fabrication information and test results. Chapter 5
shows how existing memristor models and characterization data may be used to predict
the behavior of a memristor when used as a multi-state device. Chapter 6 presents circuit
designs and simulation results for reading and writing to memristor devices. Lastly,
Chapter 7 provides a conclusion of the results.
4
CHAPTER II
BACKGROUND
2.1 Memristor Origin
The memristor was first theorized by Dr. Leon Chua in 1971 [5] as the fourth
passive fundamental circuit element. Based on the symmetry of the equations that govern
the resistor, capacitor and inductor, Dr. Chua hypothesized that fourth device should exist
that holds a relationship between magnetic flux and charge. This would complete the
circle where the resistor holds the relation between current and voltage, the inductor
holds the relationship between current and flux, and the capacitor holds the relationship
between voltage and charge. Dr. Chua proved that the abilities of the memristor could not
be duplicated by any of the other three passive elements, and that an active circuit that
mimics the functionality of the theorized device would require approximately 25
transistors. The memristor was predicted to be a device with a dynamic resistance that is
determined by the integral of current flowing through it. Since this is an integral
relationship, applying zero current would result in a constant charge, thus leaving the
resistance constant. This shows that the theorized memristor possesses the ability to
retain a resistance value even after the power source is removed from the device. Unlike
the capacitor and inductor, this is not an energy storage device, so the voltage must equal
zero whenever the current goes to zero. This causes the I-V curve of the device to
5
produce a pinched hysteresis loop, revealing that the device has a memory effect
associated with it.
A few years later, Dr. Chua and Dr. Sung Mo Kang, produced further research on
the theoretical memristor device, claiming the memristor to be a subset of a broader class
defined as memristive systems [22]. Like memristors, all memristive systems must have a
zero output whenever the input is zero, and this is what distinguishes them from arbitrary
dynamical systems. Chua and Kang found publications dating back to the early 1900s
that described systems that could be classified as memristive, but this connection had
never been realized. The memristor was considered nothing more than a mathematical
curiosity until the first successful fabrication of a memristor device was published in
2008 [1].
2.2 Physical Memristor Discovery
The first fabrication of a memristor device was developed by a research team at
HP Labs lead Dr. Stanley Williams [1]. The research team at HP Labs was formed in
1995, and they initially started working on ways to further increase computing power
once transistors reach their minimum size constraint. They decided the solution should be
a nanoscale crossbar series of switches, which would be designed so the system could
still function even if some of the components were defective [23].
The initial device structure for the switches at each crossbar junction was a layer
of platinum dioxide, followed by a monolayer film of switching molecules, and finally a
layer of titanium. When considering the platinum crossbars as electrodes, the resulting
device was defined within this 5 layer structure. As the internal mechanism in the device
6
was studied, it became apparent that the oxygen atoms in the device migrated through the
monolayer, and formed titanium dioxide on the other side. They also found that the
titanium dioxide was formed in two different patterns, a stoichiometric layer, and a
slightly oxygen deficient layer. The monolayer was then removed and a fabrication
method was determined that would yield reliable devices that contained both the
stoichiometric and oxygen deficient layers of titanium oxide [23]. Testing of these
devices showed that the resistance of the device did not change when the voltage source
was removed, and although it wasn‘t circular, the device provided an I-V characteristic in
the form of a pinched hysteresis loop [1]. Following this discovery, HP Labs has
produced extensive research based on the fabrication, modeling, and dynamics of
titanium dioxide memristor devices [24-32].
2.2.1 HP Labs Titanium Dioxide Memristor
The structure of the thin-film titanium dioxide memristor was decided to be a
stoichiometric layer of titanium dioxide (TiO2) and an oxygen deficient layer (TiO2-x)
sandwiched between two platinum electrodes [1]. The device was determined to be
functioning by the migration of the charged vacancies in the oxygen deficient layer.
When a positive voltage was applied to the device, the oxygen vacancies expanded. This
created a thicker oxygen deficient layer, thus reducing the resistance of the device.
Conversely, when a negative voltage was applied to the device, the oxygen vacancies
contracted and the resistance of the device increased. HP Labs created a simple
mathematical model that described this phenomenon based on two dynamic resistors and
a differential equation that modeled the migration of oxygen vacancies [1].
7
HP Labs has since published many more papers based on the characterization of
the TiO2 memristors that they developed [24-32]. One of these papers describes a more
complex test setup for characterizing memristor devices [26]. A series of pulses was
applied to the device with a constant voltage, but a variable pulse width. This was done to
characterize the state variable that determined the resistance of the device. The state
variable was then fit to the Simmon‘s tunneling equation for a metal-insulator-metal
(MIM) junction with image forces [33]. The mechanism for resistance change was then
described as a tunnel barrier with variable thickness.
Further work was done on this device to see if Joule heating had an impact on the
resistive switching process of a memristor device [27]. These results also concluded that
the resistance change is determined by the modulation of the width of a tunnel barrier.
Furthermore, as temperature significantly changed the resistance value, temperature can
potentially be seen as a hidden state variable within the device.
Dr. Paul Strachan et al. published a paper that describes the electroforming
process in the memristive devices [30]. These devices were fabricated using TiO2
sandwiched between two platinum electrodes. The application of a high voltage changed
the makeup of the device, leaving a bubble of oxygen deficient material in the thin-film.
The TiO2-x channel formed only in a small portion of the device, and a small layer of
TiO2 was left between the oxygen deficient channel and the platinum conductor which
supports the possibility of a tunnel gap. Dr. Strachan et al. described the oxygen deficient
layer as possibly having a crystal structure of Ti4O7, [32]. These results were supported
by a group led by Dr. Deok-Hwang Kwon at Seoul National University as they found the
same crystal structure present in their devices [34].
8
2.2.2 Alternative Thin-Film Memristor Designs
Since HP labs discovered the memristor, several academic institutions, including
the University of Dayton, have published results of memristor devices. These devices
show that the memristor can be developed using a wide variety of materials and device
structures. The reasons for the memristive effect include, but are not limited to, the
motion of oxygen vacancies [1], the motion of silver dopants [7], and the state change in
chalcogenide materials [9]. A complete study of which materials contain the required
properties to be considered memristive has not yet been published. Until then, the
reasoning for choosing each material in the devices appears to be on a case by case basis.
Sung Hyun Jo and Wei Lu at the University of Michigan fabricated memristors
published in [7] that are based on an amorphous silicon and silver. As voltage is applied,
Ag ions are pulled into the a-Si layer to lower the resistance of the device. The thickness
of the a-Si was 120nm and the cross-sectional area of the devices was 100 by 100nm.
Sung Hyun Jo et al. also fabricated devices using a slightly different method in
[8]. In this paper, a-Si is co-sputtered with Ag at a ratio that changes as the layer is
formed on the wafer. This produces a film that has a low concentration of Ag at one end
and a higher concentration of Ag at the other. These devices have an area of 100 by
100nm. The devices had significantly lower switching times of about 5-10ns when
compared to the device previously described in [7].
Antonio S. Oblea et al. has fabricated chalcogenide based devices where Ag2Se
and Ag were placed between tungsten electrodes, [10]. Ge2Se3 was placed between each
layer to help the tungsten adhere, and to make it possible to deposit the Ag layer. The
devices had a diameter of 180nm and were fabricated by first depositing a substrate, then
9
etching vias where the devices would be deposited. The electrodes were formed with a
much larger area of 80 by 80µm.
Nadine Gergel-Hackett et al. developed a flexible memristor that was deposited
on a laserjet transparency [11]. The device is formed by letting a titanium isopropoxide
solution hydrolyze to form a 60nm layer of amorphous TiO2 placed between Al
electrodes. The device is large with cross-sectional area of 4mm2. The device shows
on/off rations greater that 10,000:1 and has data retention capabilities of about 14 days.
This suggests that the memristive effect can be seen in devices with sizes that exceed the
nanometer scale.
A group led by T. Prodromakis conducted a study that tested memristance on
devices that range from 1 by 1µm2 to 200 by 200µm2 to further show that the memristive
effect is not only present in the nanoscale. The results show that hysteresis size and the
ratio between the maximum and minimum resistance increase as the device area
decreases [12].
Titanium dioxide memristors have also been fabricated using a slightly different
approach; using a TiO2+x layer in addition to the stoichiometric one. In this case, the
abundance of oxygen atoms is negatively charged which theoretically creates a memristor
with charges that move opposite to the TiO2-x structure. T. Prodromakis et al. developed
TiO2/TiO2+x devices that exhibit memristive behavior with an active area of 1 to 25µm2
[13].
2.2.3 Spintronic Memristor Devices
In addition to the development of thin-film memristors, attempts have been made
to develop spintronic memristors [35-37]. The resistance is variable dependent on the
10
magnetoresistance and the spin torque induced magnetized motion. The device was
designed using two ferromagnetic layers, one reference layer and one free. The free layer
is split into two sections magnetized in opposite directions. The position of the barrier
dividing the layers of opposite magnetization directions is what determines the resistance
of the device. The advantage of this system is that it can be integrated into CMOS just as
magnetic RAM that is currently commercialized.
2.3 RRAM
RRAM is a device that works similarly to memristor devices, as it is a form of
non-volatile memory that works by changing the resistance of a dielectric material. They
are primarily made using an oxide layer between two electrodes. A common dielectric
used in these devices is hafnium oxide where one example shows a device containing a
5nm HfO2 layer [12]. The RRAM devices that have been fabricated generally have high
and low resistance states that represent logic 0 or 1, as opposed to memristors that could
potentially hold many resistance states.
2.4 Device Modeling
In addition to physical device development and characterization, memristor
devices have also been modeled based on the equations first proposed by HP Labs [1, 14,
and 15]. The memristor device was first modeled by two variable resistors in series. The
resistance of each was determined by the instantaneous thickness of the two thin-film
layers made up of high resistivity TiO2 and low resistivity TiO2-x. The thickness of the
TiO2-x layer is modeled using a state variable that changes based on the net charge
11
applied to the device. Some additional analysis was done in [14, 15] that expands on the
equations presented by HP Labs in [1].
HP Labs released a memristor model in [1] that describes the charges in the doped
layer to move with linear dopant drift. Since then, Joglekar and Wolf expanded on the
model in [14] by defining a non-linear drift velocity. Furthermore, Zdenek Biolek et al.
describe an alternative non-linear drift model for the memristor [15]. These models do
not take into account the non-linear tunneling and heating effects described in [26, 27].
Further modeling has been completed based on the chalcogenide device
developed at Boise State University [9, 39]. These models were developed so that the I-V
characteristics of both the fabricated device and the model match very closely. The
drawback of this type of model is that it conforms to the device data for a limited number
of voltage inputs.
2.5 Circuit Design
Circuit designs have been published that show how the memristor could be added
to passive circuit theory using RLCM designs [14, 40]. This is an addition to RLC
passive circuit theory that involves a non-linear, time-varying element. First and second
order systems were developed as a memristor based approach to design chaotic
oscillators.
Circuits have also been published that use the memristor as a programmable
resistor in an analog circuit [41]. Since high frequency signals with zero net flux do not
disrupt the state of a memristor, a DC signal is applied to set the resistance value, and
then the AC signal propagates with stable memristor operation. This technique has been
12
applied to programmable gain amplifiers, where the memristor is in place of the feedback
resistor.
Dr. Eshraghian et al. proposed a circuit design for a content addressable memory
(CAM) cell that utilizes memristors [42]. For this design, the memristor is combined with
CMOS transistors to provide a CAM cell with a 45% reduction in area when compared
with an SRAM equivalent. This new MCAM cell also provides a 74% reduction in power
consumption, although the write operation time is substantially longer due to the slow
switching time of the memristor.
Circuits have also been proposed that use memristors in cellular neural network
(CNN) structures [20, 21]. The memristors act as synaptic weights, where the resistance
represents signal strength. These circuits are based on a memristor/CMOS hybrid design
that would replace a transistor based design.
A large number of read and write circuits were developed to control the information
processing aspect of memristor devices. Some of these circuits involve using op amps as
analog comparators that determine the state of a memristor [16-18]. To change the state
of the memristor, a voltage pulse is applied where a transistor switching mechanism is
used to control whether to read or write to the device. The read and write circuits
proposed in [19] are complex designs that have the ability to modify the memristor
resistance to a pre-defined set of 8 different values.
13
2.6 Applications
The three most promising applications of the memristor are non-volatile memory
[8, 16-19, 43], neuromorphic architectures [6, 7, 20, 21, 44, 45], and implication logic
used for digital circuit design [46].
Non-volatile memory can be designed based on the dynamic resistance of the
memristor device. For a simple one bit storage application, a high resistance could
represent logic 0, and a low resistance could represent logic 1. Memristor based non-
volatile memory could potentially provide much more data storage per footprint area
when compared the current technology [23]. Higher density can be achieved using the
memristor as a multistate memory device [19].
Memristor based neuromorphic systems could be developed where the memristor
holds a value representing the synaptic weight in a neural network [6]. Several papers
have shown memristor fabrications where the memristor is capable of storing several
different resistance values based on the application of a string of voltage pulses [6, 7, and
10].
Due to the dynamics of the memristor, logic design based on these devices is best
done using material implication. A set containing the implication operator and the not
operator, is computationally complete, as is the set {and, not}. The change in the logic
operators is required as this would create a mathematical system that more closely
resembles how memristors work [32].
14
CHAPTER III
PHYSICAL DEVICE EXPERIMENT 1
The following chapter discusses the fabrication and characterization of TiO2
memristor devices. Of the all of the fabricated devices, the three most successful
fabrications are known as UDMEM1, UDMEM2, and UDMEM8. The fabrication
method of these devices is discussed, as well as the experimental setup and results
obtained when testing the devices.
3.1 Device Fabrication
UDMEM1, UDMEM2 and UDMEM8, differ in the thickness of the dielectric
layers. UDMEM1 includes a 900 nm titanium oxide layer and a 440 nm oxygen deficient
titanium oxide layer sandwiched between top and bottom electrodes (see Figures 3.1, 3.2,
and 3.3). UDMEM2 has the same device structure except that the titanium dioxide layer
was reduced to 450 nm and the TiO2-x layer was reduced to 220 nm. UDMEM8 is a
similar device with thinner titanium oxide layers (50 nm for titanium oxide and 50 nm for
oxygen deficient layers). In each case, the bottom layer on the device is a 400 nm layer of
Si with resistivity of 1 to 10 Ωcm.
The titanium oxide layers were formed by magnetron sputtering at an oxygen
pressure of 14 mTorr. The UDMEM1, UDMEM2, and UDMEM3 devices were formed
at a temperature of 200°C, 350°C, and 400°C respectively.
15
For each of the devices, the bottom electrode was a typical metal stack used for
Ohmic contact on low resistivity Si – about 500 nm thick (Ti/Al/Ni/Au) capped with a
100 nm Pt layer. The top layer was a Ti/Au layer with a thickness of about 800 nm. The
bottom metal layer was rapid thermal annealed at 850°C for 30 seconds to create the
Ohmic contact to the Si substrate. Three wafers, one for each of the devices (UDMEM1,
UDMEM2 and UDMEM8), were fabricated with several devices on each wafer.
Metal 2 800 nm
TiO2-x 440 nm
900 nm
TiO2
Metal 1 500 nm
Low Resistivity Si 400 nm
Figure 3.1. Device layout for UDMEM1.
Metal 2 800 nm
TiO2-x 220 nm
450 nm
TiO2
Metal 1 500 nm
Metal 2 800 nm
TiO2-x 50 nm
TiO2 50 nm
Metal 1 500 nm
Figure 3.4 (a) shows how multiple devices are aligned on the UDMEM2 wafer.
Figure 3.4 (b) shows a single device being examined using a probe under a microscope.
To test each device, a probe was applied to the top electrode, the 800 nm Ti/Au (see Figs.
16
1 and 2). The device was grounded through the low resistivity Si, which was connected to
the bottom layer of the device.
(a) (b)
Figure 3.4. Memristors on wafer: (a) alignment of multiple memristors on a wafer, and (b) probe applied to
test a single device.
3.2 Experimental Test Setup
Two different methods were used to obtain the I-V curves for the devices.
UDMEM1 and UDMEM2 were tested using a Keithley 2400 SourceMeter, so that a
voltage could be applied and the current read to generate device I-V curves. Each voltage
was entered in step intervals by hand, first increasing to the maximum voltage, then
decreasing past zero to the minimum voltage, and back to zero. This provides the ability
to use a DC voltage source to apply voltage in a cyclic fashion.
The UDMEM2 device was again tested along with UDMEM8 using a Princeton
Applied Research computer controlled parameter analyzer in a cyclic voltammetry setup.
UDMEM1 was not subject to further testing as it had inferior performance when
compared to UDMEM2 in the initial testing. This method allowed many more points to
be collected in a more accurate and efficient manner. The current for a number of voltage
steps was recorded to obtain the resulting I-V plots.
17
3.3 Experimental Test Results
The tests conducted on the fabricated memristors were done to first determine that
the devices are acting as memristors, then to determine the extent to which these devices
can successfully act as electrical synapses. First, tests were conducted to produce an I-V
curve, both by hand and using a parameter analyzer. Then, repetitive pulses were applied
to determine if this can effectively change the resistance of the device.
3.3.1 Characterization by User Controlled Test Setup
The current-voltage results for UDMEM1 and UDMEM2 done using the Keithley
SourceMeter are now examined to determine if the memristor device functions properly.
First, a single device on each of the wafers was selected and a voltage loop was applied.
In this test, a voltage loop is considered to be from 0V to 4V, then 4V to -4V, and back to
0V. Figure 3.5 shows the I-V curve for the UDMEM1 sample. A slight hysteresis loop
can be seen where positive voltage was applied to the device. The current flowing
through the device was slightly higher on the voltage decrease as opposed to the initial
increase. Figure 3.6 shows the I-V results for the UDMEM2 sample. This sample had a
thinner titanium dioxide layer, and had a larger hysteresis loop when comparing to the
UDMEM1 sample. A small hysteresis can also be seen where the voltage is negative. The
conductivity of UDMEM2 was slightly higher due to a thinner oxide layer.
18
Test 1: I-V UDMEM1 - .2V step -4:4V, SubTH=400um, A = .0014cm 2
30
Voltage Increase
25 Voltage Decrease
20
Current (  A)
15
10
-5
-4 -2 0 2 4
Voltage (V)
Figure 3.5. Test results for UDMEM1 with a voltage loop ranging from -4V to 4V.
Test 2: I-V UDMEM2 - .2V step -4:4V, SubTH=200um, A = .0014cm2

70
Voltage Increase
60 Voltage Decrease
50
40
Current (  A)
30
20
10
-10
-4 -2 0 2 4
Voltage (V)
Figure 3.6. Test results for UDMEM2 with a voltage loop ranging from -4V to 4V.
The UDMEM2 sample was then tested with an increased voltage range to see the
changes in the hysteresis loop. The voltage loop was set from 0V to 5V, 5V to -8V, then -
8V to 0V. The upper limit on the voltage in this test was 5V because the meter used to
determine current can only measure up to 105µA. At 5V, the current measurement was at
a maximum so the voltage was then decreased. When the voltage was decreased, the
current through the device peaked at -10.51µA. These results are plotted in Figure 3.7. It
can be seen that the size of the hysteresis loop increased as voltage range tested became
greater.
19
Test 3: I-V UDMEM2 - .5V step -8:5V, SubTH=200um, A = .0014cm2
120
Voltage Increase
100 Voltage Decrease
80
Current (  A)
60
40
20
-20
-8 -6 -4 -2 0 2 4 6
Voltage (V)
Figure 3.7. I-V curve results for UDMEM2 with voltage ranging from -8V to 5V.
The next test was designed to see how the hysteresis loop changed as multiple
voltage loops were applied in succession. The UDMEM2 sample was selected for this
test, as it provided the superior results when comparing the data in the previous plots. The
voltage applied was increased from 0V to 5V, from 5V to -12V, then -12V to 0V. Since
these tests were done on a different device on the UDMEM2 wafer, the results look
different when comparing to the UDMEM2 test in Figure 3.7, especially when the
voltage was negative. This device had a much higher current flow in the negative region
as well as a larger hysteresis loop. This suggests that the wafer is not uniform, and
different devices behave differently in different locations throughout the wafer. The
following three plots show the I-V results when three consecutive voltage loops were
applied to the device. Figure 3.8 shows the I-V curve for the first voltage loop, Figure 3.9
shows the second, and Figure 3.10 shows the third.
20
Test 4: I-V UDMEM2 - .5V step -12:5.5V, A = .0014cm2 First Pass
120
Voltage Increase
100
Voltage Decrease
80
60
Current (  A)
40
20
0
-20
-40
-60
-80
-10 -5 0 5
Voltage (V)
Figure 3.8. Multiple voltage loop test, first pass.
Test 4: I-V UDMEM2 - .5V step -12:5.5V, A = .0014cm2 Second Pass

120
Voltage Increase
100
Voltage Decrease
80
60
Current (  A)
40
20
0
-20
-40
-60
-80
-10 -5 0 5
Voltage (V)
Figure 3.9. Multiple voltage loop test, second pass.
Test 4: I-V UDMEM2 - .5V step -12:5.5V, A = .0014cm2 Third Pass

120
Voltage Increase
100
Voltage Decrease
80
60
Current (  A)
40
20
0
-20
-40
-60
-80
-10 -5 0 5
Voltage (V)
Figure 3.10. Multiple voltage loop test, third pass.
21
When comparing Figures 3.8, 3.9, and 3.10, it can be seen that the hysteresis loop
became less uniform as the second and third voltage loops were applied. The three I-V
curves appeared to be most predictable when the voltage was positive. When the voltage
was negative, the hysteresis changed much more between each pass and degraded more
severely. This test clearly shows the hysteresis loop with an intersection when the current
and voltage are both 0. This shows that the necessary conditions are met for this device to
be considered memristive.
3.3.2 Characterization by Computer Controlled Test Setup
After testing the devices using the Keithley setup, the computer controlled
parameter analyzer was used to obtain further I-V results. First, a single device on the
UDMEM2 wafer was selected and a voltage loop was applied similar to when using the
Keithley SourceMeter. In this test, a voltage loop was considered to be from 0V to 5V,
then 5V to -5V, and back to 0V. This loop was applied to the device five times and each
pass was observed to see how the I-V curves changed. Figure 3.11 shows the I-V curve
for the first pass on the UDMEM2 sample. A slight hysteresis loop can be seen when a
positive voltage is applied to the device. Figure 3.12 shows the I-V curve for the second
pass when testing the UDMEM2 sample. These results show that the size of the
hysteresis loop increased when compared to the first pass. Then, the hysteresis started to
degrade after the second pass, and the resulting I-V curve after the fifth pass can be seen
in Figure 3.13. In all three cases, the device was only conductive when positively biased.
22
I-V Curve for UDMEM2 Pass 1
10
Current (  A)
4
-2
-5 -4 -3 -2 -1 0 1 2 3 4 5
Voltage (V)
Figure 3.11. Test results for UDMEM2 with a voltage from -5 to 5V on the first pass.

18
16
14
12
10
Current (  A)
-2
-5 -4 -3 -2 -1 0 1 2 3 4 5
Voltage (V)
Figure 3.12. Test results for UDMEM2 with a voltage from -5 to 5V on the second pass.

10
6
Current (  A)
-2
-5 -4 -3 -2 -1 0 1 2 3 4 5
Voltage (V)
Figure 3.13. Test results for UDMEM2 with a voltage from -5 to 5V on the fifth pass.
23
The test results for the UDMEM8 sample were similar to UDMEM2, except the
hysteresis loop was slightly larger. Also, the device was more conductive since the
titanium dioxide layers in this device were thinner than in the UDMEM2 sample. The
initial increase in conductivity happened much faster in this sample when looking at the
data for the first voltage loop pass in Figure 3.14. Figure 3.15 shows how the size of the
hysteresis loop increased during the second voltage pass. The fifth pass in Figure 3.16
shows degradation in the hysteresis much like in the UDMEM2 device. The UDMEM8
sample also shows that conductivity was only present when the device was positively
biased. These tests both show the hysteresis loop with zero current at a zero voltage bias.

100
80
60
Current (  A)
40
20
-20
-2 -1 0 1 2 3 4
Voltage (V)
24
120
100
80
Current (  A)
60
40
20
-20
-2 -1 0 1 2 3 4
Voltage (V)
Figure 3.15. Test results for UDMEM8 with a voltage from -4 to 4V on the second pass.
120
100
80
Current (  A)
60
40
20
-20
-2 -1 0 1 2 3 4
Voltage (V)
3.3.3 Characterization Using Pulse Waveform
The next test shows the UDMEM2 device‘s reaction to voltage pulses as opposed
to a DC bias. Figure 3.17 shows the results when applying pulses to the device. This test
was done by applying a 2% duty cycle pulse oscillating between 0 and 4V to the
memristor, with a frequency in the range of 3-50Hz. The number of pulses was
determined by multiplying the frequency of the pulse waveform by the amount of time it
was applied to the device. The source was applied for a set amount of time and then an
Ohmmeter was used to measure the resistance across the device as the signal was turned
25
off. This resistance was then compared to the resistance of the device before the source
was applied to obtain the total resistance drop. This data supports the ultimate goal of
having a memristor device model brain function, as the resistance was reduced with the
application of pulse waveforms.
Resistance Drop as a Function of the Number of Voltage Pulses Applied

0
-10
Change in Resistance (k  )
-20
-30
-40
-50
-60
0 200 400 600 800 1000
Number of Pulses Applied (t*f)
Figure 3.17. Test results showing the resistance drop across the memristor as a function of the number of
voltage pulses applied to the device.
26
CHAPTER IV
PHYSICAL DEVICE EXPERIMENT 2
A mask set has been developed to fabricate a more complex set of memristor
devices. This mask set makes it possible to fabricate much smaller devices in terms of
footprint area, as well as memristor crossbar arrays. The fabrication method for the
second generation of devices is discussed, as well as the experimental test results for the
first wafer fabrication using this new method.
4.1 Mask Design for Future Devices
The second generation of memristor devices is based on a new mask set that
makes it possible to fabricate devices that are isolated, as well as devices arranged in a
crossbar pattern. The layout of the entire mask can be seen in Figure 4.1. The device area
when using this mask is determined by the overlap between the top and bottom metal
layers, and the overlap area ranges from 0µm2 to 400 µm2 for different the device
patterns.
27
Figure 4.1. Layout of entire mask.
4.1.1 Overall Mask Set
The mask set contains three different masks, the top metal, the bottom metal, and
an etch mask. Figure 4.2 shows each mask it the mask set. It can be seen that all of the
probing pads are present on the top metal mask, and only the pads connecting to the
bottom electrode on the device are present on the bottom metal mask. The etch mask is
used to provide access to the bottom metal, as vias will be etched wherever the pads
connected to the bottom electrode need to be accessed from the top of the device.
(a) (b) (c)

Figure 4.2. Layout for (a) top metal mask, (b) etch mask, and (c) bottom metal mask.
28
4.1.2 Device Patterns in Mask Design
Each mask is divided in to 4 different sections with an area of 1 cm2, and 8 of
each section are spread out over the entire mask. The four different sections of the mask
are displayed in Figure 4.3. There are two different crossbar designs and two different
sections of individual devices. Figure 4.3 (a) contains 9 different individual devices that
range from 25µm2 (rightmost device) to 400 µm2 (leftmost device). Each of these device
patterns resides between two larger patterns that will act as pads for the device to be
probed. It can be seen that there are four rows of device patterns where each column
represents a different device size. The pad above the device acts as the top electrode, and
the pad below the device provides access to the bottom electrode. The actual memristor
device is defined as a circular overlap between the top and bottom electrodes. This layout
can be seen in more detail in Figure 4.4. The layout in Figure 4.3 (c) is a similar pattern,
except that the devices are smaller in size and are defined by the overlap of two wires
with a width of 5 µm as opposed to a circular overlap. The device size ranges from 2.5
µm2 to 35 µm2 with an additional device with zero overlap area. This was done to
possibly examine the amount of fringe effects that are present in the devices fabricated
using this mask design. The device level layout for the smaller devices can be seen in
Figure 4.5.
Figure 4.3 (b) shows one of the crossbar designs, the horizontal lines reside in the
top metal mask, and the vertical lines represent the bottom metal. All of the larger pads
are on the top metal mask so all the devices can be accessed using probes. The horizontal
row of pads along the bottom are connected to the lower electrode as the etch mask is
used to provide access. This will allow a voltage to be applied between one top wire and
29
one bottom wire to access any of the devices in the array. Each of the 36 devices at each
of the cross-points is defined by a circle with an area of 100 µm2. The layout in Figure
4.3 (d) is almost identical to the one in Figure 4.3 (c), except that there is no circle added
and the devices are defined only by the crossing of the vertical and horizontal 5 µm wires
for a device area of 25 µm2.
(a) (b)
(c) (d)
Figure 4.3. Layout of 4 different areas in the mask set including (a) the larger individual devices, (b) the
crossbar with 100 µm2 overlap, (c) the smaller individual devices, and (d) the crossbar with 25 µm2
overlap.
30
. . .
Figure 4.4. Span of devices that are included in the larger device set (25 µm2 to 400 µm2).
. . .
Figure 4.5. Span of devices in the smaller devices set (0 µm2 to 35 µm2).
4.2 Second Generation Device Fabrication
After the mask set was designed, it was used to fabricate a wafer for experimental
testing. The device layout can be seen in Figure 4.6. A high resistivity SiO2 film was
deposited on a Si wafer so that the bottom electrode on each device would not short
together. The Pt bottom metal was deposited using electron beam evaporation. Due to the
high melting temperature of platinum, the process had to be completed in steps to prevent
the heat radiated from the Pt target from destroying the wafer. Images of the wafer after
Pt deposition can be seen in Figure 4.7. The TiO2 and TiO2-x layer were then deposited by
sputter deposition using a Ti target with 6% O2 in a 4mTorr Ar environment. The amount
of DC power was varied to determine the composition of each oxide layer (230W for
31
TiO2-x and 50W for TiO2). The stoichiometric oxide layer was set to be much thinner than
the oxygen deficient layer to create a device similar to the one described in [26]. An
image of the wafer with the deposited oxide layers can be seen in Figure 4.8. The Pt top
metal was applied to the wafer again using electron beam evaporation. The photoresist
patterned for the top metal can be seen in Figure 4.9, and the completed wafer can be
seen in Figure 4.10.
Au 500Å
Pt 500Å
Ti 50Å
TiO2 40Å
TiO2-X 1100Å
Pt 500Å
Ti 50Å
SiO2 1mm
Figure 4.6. Device layout for second generation memristor device (contact pads not shown).
(a) (b)
Figure 4.7. Images of the SiO2 wafer after Pt deposition displaying (a) the contact pad and wire leading to
an isolated device, and (b) the wire passing through the circular definition of a crossbar device.
32
Figure 4.8. Image displaying memristor wafer after deposition of TiO2 and TiO2-x layers.
(a) (b)
Figure 4.9. Images displaying the lithography pattern for the top metal for (a) an isolated device, and (b) a
device in a crossbar.
(a) (b)
Figure 4.10. Images of fabricated wafer displaying (a) portion of a memristor crossbar, and (b) an array of
single devices in a wire bonded packaging.
33
4.3 Second Generation Device Characterization
The six plots in Figure 4.11 show the test results for an isolated memristor device
with a cross-sectional area of 200µm2. Tests 1 through 6 were performed in order to
observe how the switching effects of the device change when different voltages were
applied.
In all tests, the voltage sweep went from 0V to the max voltage, from the max
voltage to the minimum voltage, and then from the minimum back to zero. Test 1 was the
initial test on the device, and it appears that the memristor was already in the ‗on‘ state as
the first non-zero data point hit the current limit (about 550µA). The current was limited
until the voltage increase towards 0V. At about -1V, the memristor can be seen switching
to the ‗off‘ state as the conductivity dropped to a non-zero voltage.
Tests 2 and 3 were performed in a similar manner with a lower maximum voltage.
In these tests, the device was not able to switch completely to the on state but a small
hysteresis can be seen. In test 4, the maximum voltage was increased to 4V and the size
of the hysteresis was slightly larger. In these three tests, a negative voltage caused the
device to be conductive but very little hysteresis was displayed.
In test 5, the maximum voltage was pushed to 5V, and this caused a large
switching effect in both the positive and negative regimes. The device went into a very
conductive state after a positive voltage threshold was reached (about 3V), and returned
to the high resistance state as the voltage approached 0 from the negative region (at about
-1V). This result is similar to a device characterization that was published by the
University of Michigan for an a-Si based device [8]. The main difference is that the
conductive state resistance can be calculated when looking at the University of Michigan
34
device, as there are data points present at low voltages (this test also shows a much higher
current limit). Also, the ‗off‘ switching in the device in [8] appears to occur when the
negative voltage is increasing in magnitude. The ‗off‘ switching effect in the device
described in Figure 4.11 appears to occur when the negative voltage is decreasing in
magnitude. Since the switching of a memristor is said to be related to the summation of
the current through the device, a switching that occurs on the voltage increase could still
be valid. Enough current may not have accumulated in the voltage decrease due to the
current limit of the analyzing system.
Test 6 shows a final I-V test when reducing the voltage to see if the result in test 5
had a forming effect on the device. The result is similar to tests 2 – 4 except the
hysteresis is much smaller, and almost negligible relative to the conductivity.
A 100 µm2 device in a crossbar was also tested and the result can be seen in
Figure 4.12. This device has a much lower conductivity, and this could be caused by the
alternate current paths in the crossbar structure. The first test was performed with a max
voltage of 3V and the second had a max voltage of 5V. The size of the hysteresis
increased as the voltage was increased.
35
Test 1 Test 2
500 500
Current (A)
Current (A)
0 0
-500 -500
-5 -4 -3 -2 -1 0 1 2 3 4 5 -5 -4 -3 -2 -1 0 1 2 3 4 5
Voltage (V) Voltage (V)
Test 3 Test 4
500 500
Current (A)
Current (A)
0 0
-500 -500
-5 -4 -3 -2 -1 0 1 2 3 4 5 -5 -4 -3 -2 -1 0 1 2 3 4 5
Test 5 Test 6
500 500
Current (A)
Current (A)
0 0
-500 -500
-5 -4 -3 -2 -1 0 1 2 3 4 5 -5 -4 -3 -2 -1 0 1 2 3 4 5
Figure 4.11. Test results for the 200µm2 memristor device.

Test 1 Test 1
0.1 2
0
0
-2
-0.1
Current (A)
Current (A)
-4
-0.2
-6
-0.3
-8
-0.4
-10
-0.5 -12
-5 -4 -3 -2 -1 0 1 2 3 4 5 -5 -4 -3 -2 -1 0 1 2 3 4 5
Figure 4.12. Test results for the 100µm2 crossbar memristor device.
36
CHAPTER V
COMPARISON OF DEVICE MODELING METHODS
To develop simulations of more complex memristor based systems, the device
models must be studied. If the memristor is to be used to simulate a synapse in
neuromorphic architecture, then it must be capable of holding many different independent
resistance states. Three existing models for the memristor device were studied to
determine the number of resistance levels that can be discerned dependent on device
thickness and the resistance of the device materials.
5.1 Modeling Equations
The equations used to develop the memristor model were introduced in [1], with a
more comprehensive analysis completed in [14]. HP labs described the I-V relationship
for the TiO2 memristor using equation (5.1). This equation states that the memristor can
be modeled using two resistors in series where the resistance of each is dependent
on ( ), the dynamic thickness of the oxygen deficient (low resistivity) layer. For
analysis purposes, ( ) can be seen as the position of a mobile barrier between the doped
and undoped layers. is the resistance of the device when ( ) is equal to 1 and
is the resistance of the device when ( ) is equal to 0; is the total thickness of
both of the oxide layers.
37
( ) ( )
( ) ( ( )) ( ) (5.1)
According to [1], the drift velocity, of the charges in the oxygen deficient layer can be
described using equation (5.2).
( ) (5.2)
The term is equal to ±1 depending on the orientation of the memristor. If
then the width of the oxygen deficient layer will expand under positive bias, otherwise it
will contract. The term represents the mobility of the charges in the low resistivity
layer. Equation (5.2) describes a linear drift velocity for the memristor where the charges
migrate at the same rate regardless of the position of the barrier between the layers. A
more accurate model is described in [14] where a non-linear drift velocity is introduced,
velocity now changes based on position of the barrier between the high and low
resistivity layers. The drift velocity should be at a maximum when the barrier between
the layers is in the middle of the device, and zero when the position of the barrier is at
either end [4]. Joglekar proposed equation (5.3), a window function that is used to
achieve the desired velocity based on barrier position. The term is a positive integer
that controls the intensity at which the function drives velocity to zero at either end of the
device.
( ) ( )
( ) ( ( ) ) (5.3)
Similarly, Biolek et al. proposed another window function in [15] to produce the
same effect with a slightly different shape using equations (5.4) and (5.5).
38
( ) ( )
( ) (( ) ( )) (5.4)
( ) { (5.5)
The value is the current through the memristor. Equation (5.6) shows the drift velocity
definition with the addition of a window function [4-6].
( )
( ) ( ) (5.6)
Recall that equation (1) is a function of ( ) that relates voltage to current. So the
complex relationship shown in equation (5.6) must be solved in terms of ( ) to provide
a current-voltage relationship. A numerical time step solution was developed in [45] to
generate a solution for the current in the memristor based on input voltage. This can be
seen in equations (5.7) to (5.10).
( ) ( )
( ( )) ( ) (5.7)
( )
( ) (5.8)
( ( ))
( )
( ) ( ) ( ) (5.9)
( ) ( )[ ] ( ) (5.10)
In this system of equations, ( ( )) can be calculated assuming ( )
is a known value, which represents the initial thickness of the doped layer. It will also be
assumed that ( ) since no charges in the device are moving when there is no
voltage applied. The next section discusses the implementation of the memristor models
in MATLAB.
39
5.2 Equation Based Device Simulation
Existing studies of these models have utilized sinusoidal inputs to examine if the
output has the characteristic hysteresis seen in memristors. Such inputs cannot be used to
examine the number of resistance levels. Therefore, this study focuses on the application
of successive positive voltage sweeps to determine the number of different resistive states
that can be achieved in the devices. The applied voltage is in the form of a triangular
wave that oscillates between zero and a peak voltage in the range of .25V to 2V. The
initial thickness of the oxygen deficient layer is set to be for all of the simulations.
This is done to provide more room for ( ) to increase while remaining conscious of the
fact that a value any lower may produce results for an unrealistic fabrication. Lastly, is
set equal to 1 for all of the following simulations.
The simulation results discussed first show characterization information based on
the triangular voltage input signal for each of the three models. The three models are
considered to be the linear drift model, Joglekar‘s non-linear drift model, and Biolek‘s
non-linear drift model. Then, as a way to provide theoretical information about the
number of resistance states obtainable, simulations were carried out that display a
relationship between device thicknesses, the ratio , and the number of
achievable resistance states. In the tests conducted, MATLAB was used to test the linear
drift model as well as each of the models using window function to produce non-linear
drift. The next section discusses the results obtained when comparing the models.
5.2.1 Device Simulation Based on Linear Model
The results for the characterization plots of the linear model are shown in Figure
5.1. The plot on the top left shows the voltage and current waveforms for the simulation.
40
The current increases with every triangle pulse that is applied to the device. This is the
intuitive result, as the plot on the bottom right shows that the resistance drops with each
pulse applied. The top right plot shows the I-V characteristic for this simulation. There is
a separate hysteresis loop for each pulse since the variable ( ) is at a different position
at the beginning of each period of the voltage input. When considering the response of
the device when a sine wave is applied, the net charge through the device is zero at the
end of each period. This causes the variable ( ) to be periodic with an overlapping
hysteresis for multiple periods, so no state information is obtained. It can be seen in
Figure 5.1 that the size of the hysteresis increases with each period of the voltage
waveform. This is correlates to the voltage and current waveforms where each current
pulse grows at an exponential rate. The plot on the bottom left shows the thickness of the
doped layer over time as a ratio to the total thickness of the device. It is seen that the
doped layer expanded due to the voltage applied.
Voltage and Current Waveforms I-V Curve

0.3 1.5 1
0.8
Current (mA)
Current (mA)
Voltage (V)
0.2 1
0.6
0.4
0.1 0.5
0.2
0 0 0
0 2 4 6 0 0.05 0.1 0.15 0.2 0.25
time (s) Voltage (V)
w(t) - Width of Doped Region Resistance Change
1
1000
0.8
Resistance ()
800
w(t)/D
0.6 600
0.4 400
0.2 200
0 0
0 2 4 6 0 2 4 6
time (s) time (s)
Figure 5.1. Simulation results for testing liner drift velocity model. The top left plot shows the current and
voltage waveforms with respect to time, and the top right plot shows the I-V characteristic. The bottom left
plot shows position of the barrier between the titanium oxide layers and the bottom right plot shows
resistance as a function of time. Simulation parameters are, RON=100Ω, ROFF=1000Ω, D=46nm, µD=10-
14 2 -1 -1
m V s , w0/D=.2, with a triangle voltage input where f=2Hz and A=.25V.
41
5.2.2 Device Simulation Based on Non-Linear Model 1
Figure 5.2 provides the simulation results when the non-linear drift velocity is
defined by Joglekar‘s window function with . A low value for was chosen
because this limits the last hysteresis loop from increasing dramatically. The current and
voltage waveforms can be seen in the upper left; they look similar to the linear device,
except that the exponential increase in current reduces between the last two pulses. The
hysteresis in the I-V curve on the right shows that the widest loop is now in the middle
where the window function is a maximum. The plots for ( ) and the resistance also
look similar to Figure 5.1, but they have a smoother decay as the window function is
affecting the drift velocity near the edges of the device.

0.25 2.5 2.5
0.2 2 2
Current (mA)
Current (mA)
Voltage (V)
0.15 1.5 1.5
0.1 1 1
0.05 0.5 0.5
0 0 0
0 2 4 6 0 0.05 0.1 0.15 0.2 0.25
1
1000
0.8
Resistance ()
800
w(t)/D
0.6 600
0.4 400
0.2 200
0 0
0 2 4 6 0 2 4 6
time (s) time (s)
Figure 5.2. Simulation results for testing the Joglekar non-linear drift velocity model with p=1. The top left
plot shows the current and voltage waveforms w. r. t. time, and the top right plot shows the I-V
characteristic. The bottom left plot shows position of the barrier between the titanium oxide layers and the
bottom right plot shows resistance as a function of time. Simulation parameters are, RON=100Ω,
ROFF=1000Ω, D=37nm, µD=10-14m2V-1s-1, w0/D=.2, with a triangle voltage input where f=2Hz and A=.25V.
42
5.2.3 Device Simulation Based on Non-Linear Model 2
Figure 5.3 shows the test results when the drift velocity has a non-linearity
induced by Biolek‘s window function. The results look very similar to the data in Figure
5.2, except that the window function has a slightly stronger effect. The value for was
set to 32nm for this test as opposed to 37nm when using Joglekar‘s window function. The
total thickness of the device was reduced slightly to provide an increase in the memory
effect to compensate for the additional reduction provided by the stronger window
function. It can also be seen that this window function only limits the motion at the
boundary to the change in the state variable is tending towards. This can be seen when
comparing the first 2 seconds of the state variable plots in Figures 5.2 and 5.3. It is harder
to see in the I-V plot because not much detail can be seen when resistance is near the
maximum (ROFF).

0.25 2.5 2.5
0.2 2 2
Current (mA)
Current (mA)
Voltage (V)
0.15 1.5 1.5
0.1 1 1
0.05 0.5 0.5
0 0 0
0 2 4 6 0 0.05 0.1 0.15 0.2 0.25
1
1000
0.8
Resistance ()
800
w(t)/D
0.6 600
0.4 400
0.2 200
0 0
0 2 4 6 0 2 4 6
time (s) time (s)
Figure 5.3. Simulation results for testing the Biolek non-linear drift velocity model with p=1. The top left
bottom right plot shows resistance as a function of time. Simulation parameters are, RON=100Ω,
ROFF=1000Ω, D=32nm, µD=10-14m2V-1s-1,w0/D=.2, with a triangle voltage input where f=2Hz and A=.25V.
43
5.3 Resistance State Analysis Based on Device Models
When implementing a neuromorphic circuit, it is necessary to know how many
different resistance levels are available in a given memristor device. The models that
have been discussed were used to generate data that predicts the number of resistance
states available in a device based on different device parameters. Since this is an analog
device, the definition of a resistance level will not be an on/off relationship. Additionally,
the exponential nature of the resistance drop must be considered when defining a level.
The amplitude and frequency of the input voltage will also have an effect the number of
levels; these however were held constant in the experiments to isolate how device
parameters determine the resistance levels available in the device.
Since the resistance drop is not constant for each pulse applied, a resistance level
has been defined as any state change in ( ) that causes a sufficient increase in current
upon the application of a single voltage pulse. The sufficient increase in current was
given as a percentage increase from the previous current pulse. When looking at the
current and voltage waveforms in Figure 5.3, it can be seen that the first four pulses
hardly changed the device state, and the last four pulses had a much larger impact. The
tolerance percentage decided at what value of ( ) the resistance level changed upon a
single voltage pulse.
5.3.1 Resistance States in the Linear Device Model
Figure 5.4 shows the data collected for testing the linear drift model. The plot on
the left shows the number of resistance levels available as a function of device thickness
when the ratio . The plot on the right shows the same data when
44
. Since no windowing function was employed with this model, the starting
thickness was chosen by finding the minimum whole nanometer thickness where ( )
. In Figure 5.4 it can be seen that tolerances of 5%, 10%, and 15% were considered
as three separate tolerance levels for the increase in peak value for current. This data
relates to the uniformity at which the devices are fabricated. If all of the memristor
devices in a system are very uniform then a smaller current peak differential is required
because the same magnitude voltage pulse is likely to change the resistance of all the
devices by the same amount. If non-uniform devices are fabricated, a larger gap is needed
between resistance levels because internal resistance may change dramatically from one
device to the next.
Linear Memristor Model, Roff/Ron=10 Linear Memristor Model, Roff/Ron=50

9 9
Min Pulse Differental 5% Min Pulse Differental 5%
8 Min Pulse Differental 15% 8 Min Pulse Differental 15%
Number of Resistance Levels Availiable
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
90 95 100 105 110 115 40 45 50 55
D (nm) D (nm)
Figure 5.4. Plot on the left shows number of resistance levels achieved using the linear drift model for
D=90-115nm where RON/ROFF=10 for current pulse differentials given as 5, 10, and 15%. Plot on the right
shows same data for RON/ROFF=50 and D=42-55nm. Other simulation parameters are, RON=100Ω, µD=10-
14 2 -1 -1
m V s , w0/D=.2, with a triangle voltage input where f=4Hz and A=2V.
5.3.2 Resistance States in the Non-Linear Device Models
Figure 5.5 shows the resistance level results for the simulation when using
Joglekar‘s non-linear drift model. The main difference here was that the number of levels
increased initially before the expected decay. This is because at these small thicknesses,
the memristive effect was so large that very few pulses were needed to drive ( )
45
Once ( ) reaches this limit, a negative pulse must be applied or the device will remain
in this state as a linear resistor. The data in Figure 5.6 shows the simulation results for a
case where ( ) so quickly that the number of resistance levels was
reduced. The bottom left plot in Figure 5.6 shows that after about 1.75s, there was no
more room for the oxygen deficient layer to expand and the memristor started to act as a
linear resistor. At this time, the peak current no longer increased with the application of
additional pulses and the I-V characteristic became a straight line with slope equal to
Figure 5.5 shows that when the device thickness was less than 65nm, this effect
occurred as the number of resistance levels decreased as device thickness decreased.
Lastly, Figure 5.7 shows the resistance level data collected for the Biolek window
function. The results are similar to the Joglekar model but the span of device thicknesses
was slightly reduced. Since the window function for the Biolek model had a greater effect
on drift velocity, the maximum number of resistance levels occurred at a lower device
thickness.
Joglekar Memristor Model (p=1), Roff/Ron=10 Joglekar Memristor Model (p=1), Roff/Ron=50
10 10 Min Pulse Differental 5%
Min Pulse Differental 5%
9 9
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
60 80 100 120 30 35 40 45 50
D (nm) D (nm)
Figure 5.5. Plot on the left shows number of resistance levels achieved using the Joglekar non-linear drift
model for D=60-120nm where RON/ROFF=10 for current pulse differentials given as 5, 10, and 15%. Plot on
the right shows same data for RON/ROFF=50 and D=30-50nm. Other simulation parameters are, RON=100Ω,
µD=10-14m2V-1s-1, w0/D=.2, with a triangle voltage input where f=4Hz and A=2V.
46
2 20 20
1.5 15 15
Current (mA)
Current (mA)
Voltage (V)
1 10 10
0.5 5 5
0 0 0
0 1 2 3 0 0.5 1 1.5 2
1 1000
0.8
Resistance ()
800
w(t)/D
0.6 600
0.4 400
0.2 200
0 0
0 1 2 3 0 1 2 3
time (s) time (s)
Figure 5.6. Simulation results for testing the Joglekar non-linear drift velocity model with p=1. The top left
bottom right plot shows resistance as a function of time. Due to the strong memristive effect, device
operates as a linear resistor after 1.5s. Simulation parameters are, RON=100Ω, ROFF=1000Ω, D=50nm,
µD=10-14m2V-1s-1,w0/D=.2, with a triangle voltage input where f=4Hz and A=2V.
Biolek Memristor Model (p=1), Roff/Ron=10 Biolek Memristor Model (p=1), Roff/Ron=50
12 Min Pulse Differental 5% 12 Min Pulse Differental 5%
10 10
8 8
6 6
4 4
2 2
0 0
50 60 70 80 90 100 110 30 35 40 45 50
D (nm) D (nm)
Figure 5.7. Plot on the left shows number of resistance levels achieved using the Biolek non-linear drift
model for D=50-110nm where RON/ROFF=10 for current pulse differentials given as 5, 10, and 15%. Plot on
the right shows same data for RON/ROFF=50 and D=30-50nm. Other simulation parameters are, RON=100Ω,
µD=10-14m2V-1s-1, w0/D=.2, with a triangle voltage input where f=4Hz and A=2V.
5.3.3 Resistance State Comparison
When comparing the number of resistance levels available for the three models, it
can be seen the two non-linear models provided similar results due to boundaries added
47
to reduce drift velocity at the borders. Figure 5.8 shows the results for all three models
with a pulse differential of 5%. The Biolek and Joglekar models show a similar pattern in
the number of resistance levels, but the Biolek model on average provided about one
more level relative to device thickness. The capability of the linear model suffers because
it immediately turns into a linear resistor when ( ) and it will not operate in the
range where the non-linear models provide the maximum number of resistance levels. In
the range the linear model operates correctly, it fit the pattern of the non-linear models
and provided a slight increase in the number of resistance levels.
Looking at the characterization plots, it can be seen that hysteresis size increases
exponentially with each pulse applied to the device. This is because the resistance drop is
linear with respect to the thickness of the doped layer. When the current is calculated
using equation (5.1), it is inversely proportional to the resistance value producing an
asymptotic increase as ( ) approaches This is displayed in Figure 5.9. As the
thickness of the doped layer approached 0 nm, the conductance of the memristor
increased asymptotically. Since this occurs very close to the boundary of the memristor,
the window functions described in [14, 15] reduce this effect.
When comparing these results to the experimental results in [6, 7, and 10], it can
be seen that the exponential increase in hysteresis and peak current is not present in
published device characterization data. The hysteresis was initially large, and then
diminished with each pulse. In addition, it was shown in [7] that the current pulses
increase logarithmically with each voltage pulse as opposed to exponentially.
This method for determining the number of resistance levels can still be used
since there is still non-linear increase in current. Thus applying this technique to the
48
device described in [7] will show that higher differential current pulses occur when
( ) is closer to 0 as opposed to when ( )
Comparison of Models, Roff/Ron=10, Pulse Diff. = 5% Comparison of Models, Roff/Ron=50, Pulse Diff. = 5%
11 11
Linear Model Linear Model
Joglekar Model Joglekar Model
10 10
Biolek Model Biolek Model

9
9
8
8
7
7
6
6
5
5
4
3 4
2 3
40 60 80 100 120 30 35 40 45 50 55
D (nm) D (nm)
Figure 5.8. Comparison of results for resistance level data presented in previous section using a minimum
pulse differential of 5%.
Relationship Between Thickess of Ti0 2-X Layer and Conductance

0.01
Roff/Ron = 10
Roff/Ron = 100
0.008 Roff/Ron = 200
0.006
1/M(w(t))
0.004
0.002
0
0 0.2 0.4 0.6 0.8 1
w(t)/D
Figure 5.9. Device conductance as a function of doped layer thickness when using simulations based on
equation (1).
When comparing the results from all three models in Figure 5.8, it can be seen
that the linear model could not operate in the range where the non-linear models provided
the maximum number of resistance levels. Also, the Biolek model provided a slightly
higher number of levels than the Joglekar model. When looking at the linear model in its
defined region, it provided more resistance levels on average, but it did not provide the
49
maximum number of levels. In all three cases, increasing the ratio reduced the
thickness where the maximum number of resistance levels was observed.
Looking at the resistance level data, an argument could be made stating that much
of the functionality of the memristor is wasted in the areas where the current peak
differential is low. Furthermore, several pulses could be used to change the resistance
state in less sensitive areas to increase the number of resistance levels. This would require
a more complex circuit that would apply a different number or size of voltage pulses
dependent on the device state. As an alternative for increasing the amount of resistance
levels available, circuit designs could be examined that use multiple memristors to model
a single synapse.
5.4 Device Modeling Based on Fabrication Data
The device models described in the previous section do not contain the threshold
property seen in physical memristor devices [6, 7, 10, and 25]. The threshold is defined
as the minimum voltage that is required to change the state of the memristor device. The
physical properties that determine the threshold of the devices are complex and appear to
be different for many published devices. A model that is capable of providing a
programming threshold was made using the data collected from a physical device
characterized in [10].
A simulation was constructed in MATLAB that tests the developed model with a
string of voltage pulses. The data in [10] shows the device‘s reaction to five positive
voltage sweeps, each represented by a separate hysteresis in the I-V curve. The threshold
voltage for each state can also be seen in the characterization data where overlapping
50
lines begin to diverge in the I-V curve. Since five separate loops were displayed in [10],
each one is considered to be the operating region of a resistance state. The simulation is
capable of determining the memristor device state and the resistance of the device
dependent on the voltage applied and the state the device is in.
Figure 5.10 (a) shows the shows the voltage input as a series of pulses generated
with random amplitude and polarity. The voltage amplitude was generated in a range
from 0 to 0.3V, enough for the voltage to be slightly larger than the highest threshold
point according to the data in [10]. Since the data used to generate the simulation only
was available for positive voltage sweeps, it was assumed that a negative pulse affected
the device state in the same way, just in the opposite direction. Figure 5.10 (b) shows the
state of the memristor device corresponding to the voltage signal applied to the device. It
can be seen that not all pulses changed the state of the device because not all of them
reached the threshold voltage. Also, when looking at specific pulses, it can be seen that
the different states require different pulse amplitudes to increase or decrease the state of
the device. For example, when looking at the first pulse on the left and the third pulse
from the right, they were about the same amplitude, but only the pulse on the left changed
the state of the device. This is because the threshold required to move from state 5 to 4 is
greater than the threshold required to move from state 3 to 2. Figure 5.10 (c) shows the
resistance of the device over time. In general, the resistance increased as the state
decreased, where slight changes in the slope of the I-V curve correspond to the noise in
the resistance plot. It should also be noticed that as the state number increased, the
resistance change became smaller, with a negligible resistance differential between states
4 and 5.
51
Input Voltage to Memristor Model
0.3
0.2
0.1
Amplitude (V)
-0.1
-0.2
0 5 10 15 20 25 30 35 40
time (s)
(a)
State of Memristor Based on Voltage Pulses
4.5
State (1 to 5)
3.5
2.5
2
0 5 10 15 20 25 30 35 40
time (s)
(b)
Dynamic Resistance of Memristive Device
700
600
Resistance ( )
500
400
300
200
0 5 10 15 20 25 30 35 40
time (s)
(c)
Figure 5.10. Simulation results for numerically based model that incorporates programming threshold
displaying (a) the voltage input, (b) the memristor state, and (c) the dynamic resistance value.
52
CHAPTER VI:
CIRCUIT DESIGN BASED ON NON-LINEAR DRIFT MODEL
To further model the behavior of the memristor device, circuits have been
simulated that can use voltage pulses to either change, or sense the state of a device. In
this application the memristor is meant to simulate a synapse, so it is ideal that the
memristor can store a number of different resistances. It is also desirable that these
devices will be compatible with CMOS, both in fabrication and circuit design, so
standard 5V rectangular pulses are used as the input waveforms.
6.1 Circuit for Writing to Memristor
6.1.1 Write Circuit Schematic
The proposed memristor write circuit can be seen in Figure 6.1. The circuit has
two pulse inputs and requires a 5V DC supply to operate. When a pulse is applied from
the source V1, MOSFETs M1 and M2 are turned on and current can flow through the
device from the positive to the negative terminal. This creates a positive voltage drop
across the device which causes the state variable to shift upwards, thus decreasing the
resistance. When a pulse is generated at V2, MOSFETs M3 and M4 are turned on and a
negative voltage drop is formed between the positive and negative terminals of the
memristor. This causes the state variable to decrease, lowering the resistance of the
53
memristor. This technique for programming the memristor is useful for developing spike-
based neural system, as each pulse changes the synaptic weight represented by the
memristor. Furthermore, the artificial neuron only needs to be able to generate positive
voltage pulses for this design.
Figure 6.1 MOSFET based memristor write circuit.
6.1.2 Simulation Results for Memristor Write Circuit
The data in Figure 6.2 shows the simulation results for a train of 5V pulses being
applied to the circuit from V1. It can be seen that the state variable w(t) shifts upward
slightly with each pulse applied, and retains its position when the pulsed waveform is
equal to 0. Figure 6.3 shows a second simulation where the pulses are applied to V2, and
the opposite result is obtained.
54
Voltage Drop Across Memristor Current Through Memristor
100 15
80
Voltage (mV)
10
Current (A)
60
40
5
20
0 0
0 5 10 15 0 5 10 15
time (s) time (s)
0.8
w(t)/D
0.6
0.4
0 5 10 15
time (s)
Figure 6.2. Memristor response to write circuit simulation with voltage applied from V1. Top left plot
shows the voltage across the memristor, when the 5V pulses are applied, the top right plot shows the
current in the memristor and the voltage pulse are applied, and the bottom plot shows the shift if the state
variable w(t) relative to the thickness of the device.
Voltage Drop Across Memristor Current Through Memristor

0 0
-20 -1
Voltage (mV)
Current (A)
-40 -2
-60 -3
-80 -4
-100 -5
0 5 10 15 0 5 10 15
time (s) time (s)
0.5
0.4
0.3
w(t)/D
0.2
0.1
0
0 5 10 15
time (s)
Figure 6.3. Memristor response to write circuit simulation with voltage applied from V2. Top left plot
shows the voltage across the memristor, when the 5V pulses are applied, the top right plot shows the
current in the memristor and the voltage pulse are applied, and the bottom plot shows the shift if the state
variable w(t) relative to the thickness of the device.
55
6.2 Circuit for Reading Resistance of a Memristor Device
6.2.1 Read Circuit Schematic
A circuit was also implemented to read the state of the memristor device. This
was done by using an op-amp as a comparator that has a reference voltage set by a static
resistance. The voltage at the negative terminal is compared to the output voltage of the
memristor, and the comparator output determines the state of the memristor. The read
circuit displayed in Figure 6.4 has two comparators. This means that three different states
can be determined from the memristor. This circuit can be extrapolated to show that the
number of resistance levels is equal to one plus the number of comparators. This is true
as long as the voltage differential between the comparators is greater than the noise in the
circuit or the variation in the memristor devices.
56
Figure 6.4 Comparator based read circuit for memristor.
6.2.2 Simulation Results for Memristor Read Circuit
Figure 6.5 shows the results of a simple simulation where pulses were applied to
the device, and the comparator output was examined to determine the state of the
memristor. When comparing the voltage of the memristor to the voltage at the
comparator output, it can be seen that the comparator with the 2.5V reference is on, but
the comparator with the 4V reference is off.
One of the problems with this circuit is that the resistance of the memristor
changes as the read voltage is applied to the device. Looking at the center plot in Figure
6.5, the voltage is slightly increased with every pulse applied. If the memristor were to be
read many times in a row, the comparator with the 4V reference would eventually turn
on, changing the state of the device. This is problem is caused by the use of a device
57
model that does not have a programming threshold. This should not be a problem when
using physical devices since many of them contain programing thresholds. No
information would be lost is the read pulse magnitude did not exceed the programming
threshold for each device. This could be tested in simulation using a model such as the
one proposed in section 5.4, although this model was not programmed in SPICE.
Read Circuit for Memristor
5
Input Voltage (V)
0
0 1 2 3 4 5 6 7
time (s)
Voltage at Memristor Output (V)
0
0 1 2 3 4 5 6 7
time (s)
Comparator Outputs (V)
5 2.5V Comparator Output

4 4V Comparator Output
0
0 1 2 3 4 5 6 7
time (s)
Figure 6.5. Read circuit simulation. The top plot shows the input voltage, the middle plot shows the voltage
generated between the memristor and the 75k resistor, and the bottom plot shows the output of each of the
comparators.
58
CHAPTER VII
CONCLUSION
The initial steps toward developing memristor based systems have been
completed and the results have been demonstrated in the previous chapters. Memristor
devices have been fabricated and characterized, as these are necessary steps toward
developing a robust and reliable fabrication technique. The existing published memristor
device models have been compared and an alternate modeling method has been proposed
that incorporates a programming threshold. Finally, circuits have been developed that
provide the capability to read from and write to memristors.
The data collected from the characterization tests show that the fabricated devices
display a clear hysteresis loop with a zero crossing, characteristic of memristors. For the
most part, the devices were only conductive when the voltage applied was positive, the
exception being UDMEM2 when the Keithley apparatus was used for testing. When
multiple voltage loops were applied in succession, the hysteresis loops started to degrade
after an initial increase in size for both of the test setups. The UDMEM8 device was
tested most successfully, and possessed a greater conductivity when positively biased.
Furthermore, the resistance of the UDMEM2 device was successfully lowered with the
application of voltage pulses, showing promise for the device when modeling neural
functions.
59
The second generation of memristor devices was based on a more complex mask
set that provided a variable device area with the addition of crossbar arrays. The results
from these devices showed a larger hysteresis in some cases. When the conductivity of
the device was asymmetric, the negative region was observed to be more conductive.
This was most likely due to the fact that the TiO2-x layer was below the TiO2 layer,
leading to a device that was reversed when compared to the first generation devices.
The comparison of the existing device models provided information as to how
memristors may react based on different device thicknesses and material resistances.
When comparing the device model simulations to published memristor devices, there was
a discrepancy in the I-V characteristics in the form of an incorrectly shaped hysteresis.
The window functions that were implemented reduce this effect in the extreme case
where ( ) is close to the boundaries, but an exponential increase can still be observed.
The resistance of the fabricated devices published in [7, 25] appears to change
with respect to the magnitude of the voltage input. This may be caused by the metal-
insulator-metal (MIM) structure of memristors, which may introduce a dynamic
resistance component dependent on magnitude of the voltage input [33]. However, the
device models that were compared do not contain a conductivity component dependent
on the magnitude of the input voltage.
Furthermore, the published device characterizations [6, 7, and 10] show a
programming threshold property that was not present in the existing models. As a data
driven solution to this problem, a model was developed directly based on the
characterization published in [10].
60
The write circuit is capable of increasing or decreasing the resistance of a
memristor using a sequence of positive voltage pulses applied to different inputs. The
simulations confirmed that the circuit was operating properly although the process was
slow compared to alternative memory structures. The read circuit was able to determine
the quantized state of a memristor based on a set of comparator blocks. The simulation
showed that the circuit can function although the read pulse is destructive and could
change the state of the memristor over a large series of reads. This would not be a
problem if the memristor device model contained a threshold property and the read pulse
did not exceed the programming threshold.
Future work includes developing memristor devices that operate more predictably
and determining a more reliable fabrication method. Also a more advanced memristor
model will be developed that is capable of modeling published characterization data
much more accurately. This will provide the ability to develop much more accurate
circuit simulations and power analysis based on different types of memristor devices.
Future circuit designs will incorporate memristor arrays to show how these read and write
methods can be applied to several memristors either sequentially or in parallel. These
circuits will then be used to develop larger scale circuit simulations for determining the
performance improvement when utilizing memristors for memory systems or
neuromorphic architectures.
61
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65

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MEMRISTOR DEVICES: FABRICATION, CHARACTERIZATION, SIMULATION,

AND CIRCUIT DESIGN

The School of Engineering of the

In Partial Fulfillment of the Requirements for

Master of Science in Electrical Engineering

AND CIRCUIT DESIGN

Name: Yakopcic, Chris

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