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Advanced Digital Design

Name
Instructors Name
Class
Date
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Table of Contents
1 Introduction.......................................................................................................................3
1.1 Objectives...................................................................................................................3
1.2 Design brief................................................................................................................3
2 Background on FSMs.......................................................................................................4
2.1 Types of Finite State Machine..................................................................................4
2.1.1 Characteristics of Moore Machine –....................................................................4
2.1.2 Characteristics of Mealy Machine –....................................................................4
2.2 Difference Between Mealy Machine and Moore Machine.....................................5
3 Design section...................................................................................................................5
4 VHDL code for the FSM..................................................................................................6
5 Test bench code................................................................................................................8
6 Results.............................................................................................................................10
6.1 Discussion.................................................................................................................10
7 Conclusion.......................................................................................................................10
8 References.......................................................................................................................11
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1 Introduction
A behavior model is a state machine. It is also known as a finite-state machine since it has a
limited number of states (FSM). The machine executes state transitions and creates outputs
based on the current state and a supplied input. States and transitions are the fundamental
components of a state machine. A state is a condition in which a system reacts to subsequent
inputs based on prior inputs. One state is designated as the beginning state; this is where the
machine's execution begins. A state transition specifies the input for which a state is switched
from one state to the other. States and/or transitions provide outputs depending on the kind of
state machine.
1.1 Objectives
Learning VLSI design, ASM design and implementation, and VHDL design, as well as
expert analytic development approaches.
To acquire general and transferable abilities in advanced system design techniques utilizing
industry-standard design tools.
1.2 Design brief
This lab aims to simulate the design shown below with a graphical testbench (also known as a
Test Bench Waveform) using the Xilinx ISE v10.1.03 software. The color schemes of the
simulation should be set to the "Classic" color scheme via the 'Edit' → 'Preferences...' → 'ISE
Simulator (ISim)' → 'Simulation Waveform Colors' menu.

The bubbles in this figure indicate states, while the arrows indicate state transitions. The
arrow labels show the input value corresponding to the state transition. They define for which
input a state change occurs. For example,a andb are the inputs. Idle , proc1, halt , and final are
the states. Idle is the initial state in this case and it is activated when the state machine is
executed. When a=1, the states move from idle to proc1. But when a=0 and b=1, the state
changes from idle to half directly. When a=0, the state changes from proc1 to halt , and
finally, when a=1, the state changes to final. The language that was used in designing the
FSM was VHDL and the Method of implantation or architecture is the Register Transfer
Level (RTL).
The table below shows the truth table of the FSMs.
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Table 1

2 Background on FSMs
 Finite State Machines (FSMs) are computational models based on imaginary machines with
one or more states [1]. Only one state of this machine may be operational at any one moment.
It indicates that the machine must transition from one state to another to complete a task. Any
device that records the state of anything at a particular moment in time is known as a Finite
State Machine [2]. The state will change depending on the inputs, resulting in the output for
the changes performed.
2.1 Types of Finite State Machine
Moore state machines and Mealy state machines are the two types of finite state machines.
The FSM is a Moore state machine when current states dictate the outputs. The following
states will be determined by the current inputs and the current states [3]. Consequently, this
machine will produce outputs dependent on the states that follow. Consequently, after the
state has been transformed, the outputs of this will be utilized right away.
A Mealy state Machine is a machine whose output values are dictated by its present state and
its current inputs [1]. In this machine, just one transition is possible.
2.1.1 Characteristics of Moore Machine –
 The present state is the only determinant of the output.
 When the input changes, so does the output.
 They are slower to react to stimulus
 Minimal hardware is needed for circuit implementation.
 States are allocated to output.
 Designing is easy.
2.1.2 Characteristics of Mealy Machine –
 Both the present state and the current input influence output.
 There is a reduction in the number of states required.
 They respond to inputs more quickly.
 When the input changes, so does the output.
 More hardware is required for circuit implementation.
 Designing is challenging.
 Production of asynchronous output.
 Transitions are used to place the output.
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2.2 Difference Between Mealy Machine and Moore Machine

Parameters Mealy machines
Definition The output of a Mealy
Machine changes depending
on its current condition and
input.
States It has fewer or the same
number of states as the
Moore machine.
Output The output of the Mealy
Machine is placed on the
transition.
Reactions to Inputs A Mealy machine reacts to
inputs faster than a Moore
machine. It usually responds
during the same clock cycle.
Output and State On the current clock, the
asynchronous production of
output changes to
synchronous.
State Requirement A Mealy Machine typically
requires only a few states for
the synthesis process.
Hardware Requirements A Mealy machine can be
built with relatively little
hardware.
Counter The counter cannot be
referred to as a Mealy
Machine.
Design The design process does not
have to be complicated.
Moore machines
The output of a Moore
Machine is entirely
determined by its current
condition [2]. It is
unaffected by the current
input.
It has fewer or the same
states as the Mealy machine.
Moore's machine also
focuses on the transition.
To decode the output of a
Moore Machine, additional
logic is necessary [3]. As a
consequence, the circuit
suffers from long delays.
These typically reply after
one clock cycle.
Both the state and the output
change the synchronous to
its clock edge.
This machine also
necessitates more synthesis
states.
A Moore Machine
necessitates extra hardware.
The counter is known as a
Moore Machine.
It is pretty simple to design.

3 Design section
The Verilog language allows you to construct a module in a variety of ways. Internals of each
module may be described at three levels of abstraction depending on the demands of a design.
The highest level of abstraction is behavioral code, which requires you to merely express the
relationships between inputs and outputs without defining how those interactions will be
implemented. Behavioral descriptions can sometimes be too high-level to be synthesized into
hardware. 
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The lowest level of abstraction is structural code. When developing structural code, you
explain how low-level structures interact to create the desired system. If you want to be able
to control the logic gates that are made, you need to make a structural model.
RTL falls somewhere in the middle. I/O relationships can be explained by how data moves
between hardware registers. The code developed using RTL is easy to implement on the
hardware.
Of the three design methods, RTL was chosen as it works well at this level of design as it
gives a better understanding of how real hardware would behave if it were to be
implemented.

4 VHDL code for the FSM

Figure 1
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Figure 2

Figure 3
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5 Test bench code

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6 Results

Figure 4 test bench simulation results

6.1 Discussion

As seen in the waveform above, the clock signal is set to a constant clock period of 10 ns.
The reset button first resets the finite state machine to the original state, which is an idle state,
so that we are sure when our machine starts, it starts at the idle state. If the reset button is at
logic zero, meaning it is not active, then the machine stays in the idle mode and waits for the
inputs. If input 'a' goes to logic '1' when the machine is in the idle state and input 'b' is at logic
'0', then the machine proceeds to the proc_1 state as shown in the simulation results. When
input "a" is at logic "0" and input "b" is at logic "1" and the machine is at an idle state, then
the machine proceeds to the halt state. When input 'a' goes to logic '1,' and the machine is in
the proc_1 state, then the machine goes to a halt state. When the machine is at a halt and
input "a" goes again to logic "1", the machine proceeds to the final state, and then it moves to
the original state, which is the idle state, and waits for changes in the input again.

7 Conclusion
The design was implemented using the RTL design methodology. The design uses VHDL
language for designing, simulation, verification and testing of the FSM. The waveform for
the FSMs gotten showing all states and transitions. The simulation shows the inputs and the
states. The project output indicates that the task was completed successfully because all the
requirements and conditions were met and verified using the simulated waveforms.
Completing this assignment provided excellent opportunities to learn more about finite state
machines, their types, and applications and employ various modeling methodologies based on
the complexity and requirements of the circuitry. Also, completing this assignment provided
knowledge of the different design options available to design the FSM.
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8 References

[1] S. H. F. J. B. &. S. B. Cassel, "Extending automata learning to extended finite state

machines.," In Machine Learning for Dynamic Software Analysis: Potentials and Limits ,
pp. 149-177, 2018.

[2] J. &. L. J. V. Wiedermann, "Finite state machines with feedback: an architecture

supporting minimal machine consciousness.," In Conference on Computability in
Europe, pp. pp. 286-297, 2019.

[3] A. &. G. A. Bombarda, "An automata-based generation method for combinatorial

sequence testing of finite state machines.," In 2020 IEEE International Conference on
Software Testing, Verification and Validation Workshops, pp. 157-166, 2020.