DIGITAL SYSTEM DESIGN

CEN-422

LAB MANUAL

DEPARTMENT OF COMPUTER ENGINEERING

BAHRIA UNIVERSITY
ISLAMABAD CAMPUS
 LIST OF EXPERIMENTS

Lab No. Title of Experiment

Lab 01 Introduction to Verilog

Lab 02 Designing Multiplexers using Verilog HDL

Lab 03 Designing Flipflops using Verilog HDL

Lab 04 Designing Encoders and Decoders in Verilog HDL

Lab 05 Sequential logic design in Verilog HDL

Lab 06 4 bit Ripple Carry Adder (RCA) design in Verilog HDL

Lab 07 Filter design in Verilog HDL

Lab 08 Basic Building Block Optimization – Carry Select Adder

Lab 09 Basic Building Block Optimization – Carry Look Ahead Adder

(CLA)

Lab 10 Basic Building Block Optimization – Hybrid CLA and RCA design

Lab 11 Basic Building Block Optimization – Barrel Shifter design

Lab 12 Basic Building Block Optimization – Fast Multiplier design – I

Lab 13 Basic Building Block Optimization – Fast Multiplier design - II

Lab 14 Introduction to FPGA

 LAB NO. 5
Sequential Logic Design in Verilog HDL

OBJECTIVE:

In this lab we are going to design a register transfer level circuit in the Sequential
logic domain while inferring feedback registers.

DESCRIPTION:

In digital circuit theory, sequential logic is a type of logic circuit whose output

depends not only on the present value of its input signals but on the past history of
its inputs. This is in contrast to combinational logic, whose output is a function of
only the present input. That is, sequential logic has state (memory) while
combinational logic does not. Or, in other words, sequential logic is combinational
logic with memory.
A synchronous circuit is a digital circuit in which the parts are synchronized by
a clock signal. In a sequential digital logic circuit, data is stored in memory devices
called flip-flops or latches. The output of a flip-flop is constant until a pulse is
applied to its "clock" input, upon which the input of the flip-flop is latched into its
output. In a synchronous logic circuit, an electronic oscillator called
the clock generates a string of pulses. This clock signal is applied to every storage
element, so in an ideal synchronous circuit, every change in the logical levels of its
storage components is simultaneous. These transitions follow the level of change
of a special signal called as the clock. Ideally, the input to each storage element has
reached its final value before the next clock occurs, so the behaviour of the whole
circuit can be predicted exactly. Practically, some delay is required for each logical
operation, resulting in a maximum speed at which each synchronous system can
run.
LAB TASKS:

Implement the following design using Verilog.

DELIVERABLES:

RTL Verilog code and test bench of the design given in the above figure.

Note: Please submit the deliverables in a zip file with the following naming style,
through email at the end of each lab. Also, complete the Lab Journal for the lab
and submit before the coming lab.

DSDLab_05 [Waleed Manzoor].zip

 LAB NO. 6
Filter Design in Verilog HDL

OBJECTIVE:

In this lab we are going to design and understand the working of a Finite Impulse Response
Filter.

DESCRIPTION:

FIR filters are digital filters with finite impulse response. They are also known as non-recursive
digital filters as they do not have the feedback (a recursive part of a filter), even though recursive
algorithms can be used for FIR filter realization.

Finite impulse response

A finite impulse response (FIR) filter is a filter structure that can be used to implement almost
any sort of frequency response digitally. An FIR filter is usually implemented by using a series
of delays, multipliers, and adders to create the filter's output.

Figure shows the basic block diagram for an FIR filter of length N. The delays result in operating
on prior input samples. The hk values are the coefficients used for multiplication, so that the
output at time n is the summation of all the delayed samples multiplied by the appropriate
coefficients.

Figure. The logical structure of an FIR filter

LAB TASK:

Implement a FIR filter as show in the figure using RTL Verilog. You may use
parameter for the filter co-efficient which will be provided in the lab.

DELIVERABLES:
Verilog main module files of the FIR filter as well as the test bench to check
the filter design.

Note: Please submit the deliverables in a zip file with the following naming style,
through email at the end of each lab. Also, complete the Lab Journal for the lab
and submit before the coming lab.

DSDLab_06[Waleed Manzoor].zip