RTL Compiler Multibit flow (Logical and Physical)

with scan and LEC verification

Product Version 13.1

RTL Compiler Multi-bit Flow 1 Product Version 13.1

Copyright Statement

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trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

RTL Compiler Multi-bit Flow 2 Product Version 13.1

Contents
Purpose ..................................................................................................................................................... 4
Audience ................................................................................................................................................... 4
Introduction .............................................................................................................................................. 4
Multibit cell model .................................................................................................................................... 5
Example 1-1 Multibit Flop cell description........................................................................................... 6
RC Multibit synthesis flow (logical) ........................................................................................................... 8
RC Multibit Synthesis Flow (physical) ...................................................................................................... 10
Logic Equivalence Checking (LEC) tips for Multibit flow .......................................................................... 14
Troubleshooting ...................................................................................................................................... 15
Some Important Multibit attributes in RC ............................................................................................... 17

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Purpose
In today’s high performance design power has become a Prime concern. The power
consumed by clocking structure is the dominant part of total power estimation. Given a design,
we can reduce its power consumption by replacing some flip-flops with fewer multi-bit flip-
flops. However, this procedure may affect the performance of the original circuit. Hence, the
flip-flop replacement with timing and placement aware are the necessary requirements in
today’s design.

Audience
This document is intended for design and design-for-test engineers involved in digital designs
who desire to reduce the power using multibit cell. Also Physical aware multibit will reduce
the congestion issues associated with multibit. This document will also help for scan
insertion flow and Logic equivalence checking flow.

Introduction

Power has become a burning issue in modern VLSI design. In modern integrated circuits, the
power consumed by clocking gradually takes a dominant part. A conventional single-bit flip-
flop cell uses an inverter chain with high drive strength to drive the clock signal. Clustering
several such cells and forming a multibit flip-flop can share the drive strength, dynamic power,
and area of the inverter chain, and can even save the clock network power and facilitate the
skew control.

For example, we can eliminate two inverters after merging as shown in the figure below. It
will reduce the total area and power consumption of the flip-flops.

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More importantly, using multi-bit flip-flop can also reduce the number of clock sinks. This will
reduce the wire length of the clock network and the buffers required in the clock net-work to
maintain the slew and balance the skew. Therefore, power consumed by the clock network will
be reduced.

In logical multibit flow, merging of flip flops is done in a logical netlist where it may be difficult
to predict the impact on timing and congestion after placement. There are a lot of flip-flops on a
chip at different locations but we cannot merge every flip-flop due to timing constraint. Physical
MBCI enables merging of single-bit flops into multibit flop using placement based clustering
algorithm. Physical aware merging removes unnecessary jumps in timing which logical merging
is prone to.

Multibit cell model

A multibit cell represents a group of cells with identical functionality. Multibit cells generally have
lower power, similar or better area, and are easier to use for place and route.

RTL Compiler recognizes the following style of components for multibit merging:

 Flops (non-scan and scan) with one or more of the following shared input pins: flop
clock, async_set, async_reset, sync_set, sync_reset, sync_enable

 Latches with one or more shared control pins:o latch gate/enable, async_set,
async_reset

 Three-state cells that share the enable pins

 Combinatorial cells (muxes, inverters, nand, nor, xor, xnor) that share all pins that are
not bundled in the Liberty description.

 State retention (SRPG) cells that share the same retention control pins(s)

RTL Compiler supports the following pin types for multibit sequential cells:
Input pins
Data in
Clock
Async controls (clear, preset)
Sync controls (clear, preset, enable)
Scan input pins (scan data input, scan enable)--for multibit scan cells
Output pins
Data out (q, qbar)
Scan output pin--for multibit scan cells

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Example 1-1 Multibit Flop cell description

cell (dff4) {
area : 1 ;
pin (CLK) {
direction : input ;
capacitance : 0 ;
min_pulse_width_low : 3 ;
min_pulse_width_high : 3 ;
}
bundle (D) {
members(D1, D2, D3, D4);
nextstate_type : data;

direction : input ;
capacitance : 0 ;
timing() {
related_pin : "CLK" ;
timing_type : setup_rising ;
...
}
timing() {
related_pin : "CLK" ;
timing_type : hold_rising ;
intrinsic_rise : 1.0 ;
intrinsic_fall : 1.0 ;
}
}
pin (CLR) {
direction : input ;
capacitance : 0 ;
timing() {
related_pin : "CLK" ;
timing_type : recovery_rising ;
...
}
}
pin (PRE) {
direction : input ;
capacitance : 0 ;
timing() {
related_pin : "CLK" ;
timing_type : recovery_rising ;
...
}
}

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ff_bank (IQ, IQN, 4) {

next_state : "D" ;
clocked_on : "CLK" ;
clear : "CLR " ;
preset : "PRE " ;
clear_preset_var1 : L ;
clear_preset_var2 : L ;
}
bundle (Q) {
members(Q1, Q2, Q3, Q4);
direction : output ;
function : "(IQ)" ;
timing() {
related_pin : "CLK" ;
timing_type : rising_edge;
...
timing() {
related_pin : "PRE" ;
timing_type : preset ;
timing_sense : negative_unate ;
...
}
timing() {
related_pin : "CLR" ;
timing_type : clear ;
timing_sense : positive_unate ;
...
}
}
bundle (QN) {
members(Q1N, Q2N, Q3N, Q4N);
direction : output ;
function : "IQN" ;
timing() {
related_pin : "CLK" ;
timing_type : rising_edge ;
...
}
timing() {
related_pin : "PRE" ;
timing_type : clear ;
...
}
timing() { related_pin
: "CLR" ; timing_type :
preset ;
...
}
} }
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RC Multibit synthesis flow (logical)

In the logical multibit flow, sequential cells are converted into multibit during incremental
synthesis after global mapping. Before global synthesis DFT setup is done and before connecting
scan chains multibit segments are identified.
Following figure (Figure 1-1) highlights the tasks you need add to the generic top-down synthesis
flow to perform multibit cell mapping. Multibit cell mapping occurs during incremental
optimization.

RTL Compiler supports variable bit-widths. If the library has multibit library cells with different bit
widths, all sizes will be considered during multibit cell inferencing. The tool starts merging using
largest bit width first.

By default, multibit mapping is QoR- driven.

Multibit flops can be replaced with either parallel or serial multibit scan cells in the DFT flow .

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START

Libraries
Read Timing libs

HDL Read HDL/Netlist

Elaborate

SDC const Apply constraints

Apply mulitbit constraint

DFT setup, Rule check

Synthesize –to_map

Multibit Synthesize –to_map -incr

mapping
Analyze results

Meet const No

Yes

Run DFT rule check

Identify multibit scan abs

Connect_scan_chain

Task related to generic

Synthesize –to_placed
flow

Meet Const No
Task related to multibit

Task related to DFT

Yes
Export design

End

Figure 1-1 LogicaI Multibit insertion flow in RTL Compiler

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RC Multibit Synthesis Flow (physical)

For physical aware multibit flow, multibit mapping happens after placement in RCP and during
RCP Incremental optimization as shown in Figure 1-2. DFT setup happens after RCP incremental
optimization. The multibit segments are then identified in the design before doing a connect
scan chain. A low effort incremental is then done to legalize and optimize after dft insertion.

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START

Libraries Read Timing libraries

HDL Read HDL/Netlist

Elaborate

SDC const Apply constraints

Setup for DFT

Synthesize –to map

Synthesize –to map -incr

Analyze results

Meet const? No

Yes
Apply multibit constraints r

Synthesize –to placed

Synthesize –to placed -incr

Multibit
mapping
Meet Const ? No

Yes
Identify multibit scan abs

Task related to generic Connect scan chain -physical

flow

Synthesize –to_placed -incr

Task related to multibit
-effort low

Task related to DFT Export design

End

Figure 1-2 Physical aware Multibit insertion flow in RTL Compiler

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Logic Equivalence Checking (LEC) tips for Multibit flow

Conformal LEC will automatically map multibit component, if a synthesis tool adheres to the
following naming conventions, LEC can map all the components in multibit cells automatically by
name. The multibit instance name should be the concatenation (RC default) of all the names of
the registers corresponding the individual bits. The synthesis tool should use '_MB_' (RC default)
as a delimiter to concatenate the individual names. In addition, the synthesis tool should use
'CDN_MBIT_' (RC default) as a common prefix to the multibit instance name. For example, the
multibit instance name for individual bits 'a_reg[0]' and 'a_reg[1]' is
'CDN_MBIT_a_reg[0]_MB_a_reg[1]'.

During module flattening, a multibit instance name 'FLAT/CDN_MBIT_a_reg[0]_MB_a_reg[1]'

becomes 'FLAT_CDN_MBIT_a_reg[0]_MB_a_reg[1]'. With the delimiter _MB_ and the common
prefix 'CDN_MBIT_', LEC can split this multibit instance name into 'FLAT_a_reg[0]' and
'FLAT_a_reg[1]'.

The order of individual names in the concatenated multibit instance name should be consistent
with the pin declaration order in the multibit library cell. For example, if the pin declaration
order of library cells is {D1, D0} and 'a_reg' is associated with 'D0' and 'b_reg' with 'D1', the
multibit instance name should be 'CDN_MBIT_b_reg_MB_a_reg'.

For incomplete mapping (for example, only 2 flip-flops are mapped to a 4-bit cell), the
associated pins should be the foremost pins in the bundle. For example, 'a_reg[0]' and 'a_reg[1]'
are mapped into a 4-bit cell and the pin bundle is {D3, D2, D1, D0}. The associated pins should
be 'D3' and 'D2'.

In case if the user is altering the naming style of MBIT, please use the command below to set it
according to your new MBIT name.

SET MULTIBIT Option

[-Delimiter <string>] [-GROUP <string>]

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Troubleshooting
Problem # 1
How to check if multibit cells are available in library?

Solution
The info about the types of multi-bit cells available is important since the different drive strengths
& the different bit-widths of the flops etc help determine the coverage provided and affect the
QoR.
Before enabling multi-bit cell inferencing in RC through "set_attribute use_multibit_cells true", do
the following.
report multibit_inferencing -lib
RC prints a report in format as shown below: COMMAND: # report multibit_inferencing -lib
==============================================
==============================================
Library : No Combinational Multibit libcell present Library : Sequential Multibit Libcells info
==============================================
Seq_Mbit libcell Avoid Bitwidth
----------------------------------------------
2WDFFX1 false 2
2WSDFFX1 true 2
4WSDFF6X1 false 4
4WDFF6X1 true 4

Problem # 2
How to get verbose messaging of MBCI (multibit) flow in RC?

Solution
You can enable following tcl variable to enable the Debug mode of MBCI flow. set
multibit_opto_debug 1
With this variable set, you can see the debug message with a reason why RC failed to map to a
multi-bit flop in the logfile.

For example:
=====================================================
Replacement trial for bitwidth of 2
Trying to make multibit bank 'CDN_MBIT_u10_MB_u11' out of u10 (DFFQ_X1)
u11 (DFFRPQ_X1)
=====================================================

Please note that this variable will increase the size of the logfile considerably, so should be used
with caution and should not be made part of the default script.

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Problem # 3
After connecting the scan chains, some of the multibit flops are missing in the DFT scan chains
report. These flops are not meant to be excluded from the scan chains (attribute dft_dont_scan not
set). How to tell RC to connect these flops on the scan chain?

Solution
The multibit flops are treated as abstract scan segments. They usually have scan chains defined and
connected in their library cells. These scan segments should be identified as abstract scan segments
prior to connecting the scan chains with this command:

identify_multibit_cell_abstract_scan_segments

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Some Important Multibit attributes in RC

Attribute Default Description

multibit_allow_async_phase_map true Read-write root attribute. Controls whether

asynchronous pins can be interchanged
during multibit cell inferencing. By default,
asynchronous pin phase mapping will be
enabled.

force_merge_seqs_into_multibit_cells false Read-write root attribute. Merges single-bit

sequential instances into an appropriate
multibit sequential instance independent of
the impact on the QoR. When enabled,
multibit cell inferencing will occur even if it
degrades the delay,power, or area QOR of the
design. This is useful for increasing multibit
coverage but might negatively impact the
QoR.
bank_based_multibit_inferencing false Read-write root attribute. Enables predefined
{false | true} multibit cell inferencing (MBCI) without
limiting the multibit mapping to specific
multibit library cells. The tool automatically
finds a suitable multibit cell. Since this
attribute enables predefined multibit cell
inferencing, it implies a forced type of
mapping and is therefore not QoR-driven.

multibit_allow_unused_bits true Read-write root attribute. Controls whether a

mapped multibit instance can have one or
more unused bits. By default, RTL Compiler
will try to merge the single-bit registers to
multibit instances without unused bits. If
during merging, RTL Compiler cannot find a
suitable multibit libcell with a width that
matches the left-over bits of a bus, it will
choose the closest matching width which
leaves the minimum unused bits. If the
attribute is set to false, any merging which
results in unused (undriven/unloaded) bits
will be prevented and thus reduce the
multibit merging coverage.

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multibit_cells_from_different_busses
multibit_prefix_string
multibit_preserve_inferred_instances
multibit_preserved_net_check
multibit_skip_exception_check
multibit_unused_input_value
RTL Compiler Multi-bit Flow
false Read-write root attribute. If this attribute
remains false, only the sequential cells with the
same basename will be merged. If this attribute
is set to true, RTL Compiler can merge single-bit
cells from different banks (also called busses)
into a single, multibit cell. For example, four
single-bit flops:
CDN_MBIT Read-write root attribute. Specifies the prefix
_ to be used to name multibit instances. The
recommended value for the verification flow
is CDN_MBIT_.
false Read-write root attribute. Specifies whether to
preserve multibit instances that are inferred
during incremental optimization. If set to true,
the preserve attribute for all multibit instances
is set to size_delete_ok. This preserve setting
prevents that any optimization step down the
flow breaks the multibit cells. For example,
multibit tristate and combinational cells can
get optimized in many places.
false Read-write root attribute. Controls whether
instances can be merged into multibit
instances if the connected nets are marked
preserved. Set this attribute to true to prevent
multibit merging when any of the nets
connected to the instances are marked
preserved.
true Read-write root attribute. Controls whether
timing exception checks should be skipped and
sequential instances be merged even if they
having timing exceptions. By default, the
exception checks are skipped and merging
happens for flops with idential exceptions.
0 Read-write root attribute. Specifies the value
to which all unconnected input pins in the
multibit cells must be connected. By default,
the unused input pins of multibit cells are
connected to constant 0. If you set the
attribute to none, the input pins will be left
floating.
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multibit_seqs_instance_naming_style concat Read-write root attribute. Controls the naming

of inferred multibit (flops, latches and
tristates) instances. This attribute can have the
following values:

auto: Creates the name of the multibit instance

based on busses of merged instances. If the
instances belong to the same bus, the name of
the multibit instance starts with the bus name
followed by the range of the merged bit-
indices.If the instances belong to different
busses, the name of the multibit instance
contains each bus name followed by the range
of corresponding bit-indices.

concat: Creates the name of the multibit

instance by concatenating the names of merged
instances.

short: Creates the name of the multibit instance

by using the bus name for only the first index of
a multibit cell if all instances belong to the same
bus.If the multibit instance contains single bits
from different busses, the short naming style
has no effect and the concat style is followed.

Multibit_mapping_effort_level concat Read-write root attribute. Controls the effort

level for physical-aware multibit mapping: that
is, controls the tradeoff between multibit
coverage and QoR. This attribute can have the
following values:

auto Balances multibit coverage and QoR t

high Increases multibit coverage but might

low Gives the best QoR.

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