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D Ordering Information
PART NUMBER PACKAGE BRAND
NOTES:
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1.2 30
POWER DISSIPATION MULTIPLIER
0.4 10
0.2
0
0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC , CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
1 0.5
0.2
0.1
THERMAL IMPEDANCE
ZθJC, NORMALIZED
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
SINGLE PULSE DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10-5 10-4 10-3 10-2 10-1 100 101
t, RECTANGULAR PULSE DURATION (s)
500
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
IDM, PEAK CURRENT (A)
CURRENT AS FOLLOWS:
I = I25 175 - TC
100
150
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5 10-4 10-3 10-2 10-1 100 101
t, PULSE WIDTH (s)
200 60
100
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON) 1ms
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
SINGLE PULSE
10ms If R ≠ 0
TJ = MAX RATED TC = 25oC tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
1 1
1 10 100 200 0.001 0.01 0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
60 60
PULSE DURATION = 80µs VGS = 10V
VGS = 5V
DUTY CYCLE = 0.5% MAX
50 VDD = 15V 50
ID, DRAIN CURRENT (A)
VGS = 4V
40 40
30 30
VGS = 3.5V
20 20
PULSE DURATION = 80µs
TJ = 175oC DUTY CYCLE = 0.5% MAX
10 10
TJ = 25oC
VGS = 3V TC = 25oC
TJ = -55oC
0 0
1 2 3 4 5 0 1 2 3 4
VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)
50 2.5
ID = 29A PULSE DURATION = 80µs PULSE DURATION = 80µs
NORMALIZED DRAIN TO SOURCE
ID = 10A
ON RESISTANCE (mΩ)
2.0
ON RESISTANCE
40
ID = 19A
1.5
30
1.0
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
VOLTAGE AND DRAIN CURRENT RESISTANCE vs JUNCTION TEMPERATURE
1.2 1.2
VGS = VDS, ID = 250µA ID = 250µA
1.0
NORMALIZED GATE
1.1
0.8
1.0
0.6
0.4 0.9
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
JUNCTION TEMPERATURE VOLTAGE vs JUNCTION TEMPERATURE
2000 10
6
CRSS = CGD
100
4
WAVEFORMS IN
DESCENDING ORDER:
2 ID = 29A
ID = 19A
VGS = 0V, f = 1MHz ID = 10A
10 0
0.1 1 10 60 0 5 10 15 20 25
VDS , DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
250 150
VGS = 4.5V, VDD = 30V, ID = 18A VGS = 10V, V DD = 30V, ID = 29A
tr
200
SWITCHING TIME (ns)
SWITCHING TIME (ns)
100
150 tf
tr
tf
100
td(OFF) 50
td(OFF)
50
td(ON)
td(ON)
0 0
0 10 20 30 40 50 0 10 20 30 40 50
RGS, GATE TO SOURCE RESISTANCE (Ω) RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
VDS
BVDSS
L tP
VDS
tP
0V IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
VDS
RL VDD Qg(TOT)
VDS
VGS = 10V
VGS Qg(5)
+
VDD
VGS VGS = 5V
-
DUT VGS = 1V
Ig(REF) 0
Qg(TH)
Qgs Qgd
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
td(ON) td(OFF)
RL tr tf
VDS
90% 90%
+
VGS
VDD 10% 10%
- 0
DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAVEFORM
CA 12 8 1.1e-9
CB 15 14 1.1e-9
CIN 6 8 8.5e-10
DBODY 7 5 DBODYMOD
LDRAIN
DBREAK 5 11 DBREAKMOD DPLCAP 5 DRAIN
DPLCAP 10 5 DPLCAPMOD 2
10
RLDRAIN
EBREAK 11 7 17 18 69.6 RSLC1
51 DBREAK
EDS 14 8 5 8 1 +
EGS 13 8 6 8 1 RSLC2
5
ESG 6 10 6 8 1 ESLC 11
51
EVTHRES 6 21 19 8 1 -
EVTEMP 20 6 18 22 1 50 +
-
RDRAIN 17 DBODY
6 EBREAK 18
ESG 8
IT 8 17 1
+ EVTHRES 16
-
+ 19 - 21
LDRAIN 2 5 1e-9 LGATE EVTEMP MWEAK
8
LGATE 1 9 4.4e-9 GATE RGATE + 18 - 6
LSOURCE 3 7 4.5e-9 1 22 MMED
9 20
RLGATE MSTRO
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD LSOURCE
CIN SOURCE
MWEAK 16 21 8 8 MWEAKMOD 8 7 3
RBREAK 17 18 RBREAKMOD 1 RSOURCE
RLSOURCE
RDRAIN 50 16 RDRAINMOD 1.5e-2
RGATE 9 20 3.1 S1A S2A
12 RBREAK
RLDRAIN 2 5 10 13 14 15
17 18
RLGATE 1 9 44 8 13
RLSOURCE 3 7 45
S1B S2B RVTEMP
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3 13 CB 19
CA
RSOURCE 8 7 RSOURCEMOD 9e-3 + + 14 IT -
RVTHRES 22 8 RVTHRESMOD 1 6 5 VBAT
RVTEMP 18 19 RVTEMPMOD 1 EGS EDS +
8 8
- - 8
S1A 6 12 13 8 S1AMOD 22
S1B 13 12 13 8 S1BMOD RVTHRES
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*70),3.5))}
.MODEL DBODYMOD D (IS = 1.3e-12 RS = 7.5e-3 TRS1 = 1e-4 TRS2 = 3e-6 CJO = 1.07e-9 TT = 4.9e-8 N = 1.03 M = 0.5)
.MODEL DBREAKMOD D (RS = 3.5e- 1TRS1 = 1e- 4TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 7.5e-1 0IS = 1e-3 0N = 10 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 2.0 KP = 4 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.1)
.MODEL MSTROMOD NMOS (VTO = 2.34 KP = 43 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.74 KP = 0.13 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 31 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.2e- 3TC2 = -5e-7)
.MODEL RDRAINMOD RES (TC1 = 9e-3 TC2 = 2e-5)
.MODEL RSLCMOD RES (TC1 = 3.5e-3 TC2 = 7e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.8e-3 TC2 = -5.8e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.7e- 3TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.5 VOFF= -2.8)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.8 VOFF= -4.5)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -0.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/70))** 3.5))
}
}
HUF76419T
RTHERM3 CTHERM3
tl CASE
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Rev. H4