CHAPTER 2:

INTEGRATED CIRCUIT FABRICATION

PROCESS
2.1 Remember how single crystal silicon
is formed

2.1.1 Describe how silicon is formed from raw

material
Overview
Important Terms

Die
 Silicon is widely used in semiconductors because it
 remains a semiconductor at higher temperatures than the
semiconductor germanium
 A pure state of it is easily grown in a furnace relau and forms
a better semiconductor/dielectric interface than any other
material.
2.1.2 Describe ultra-pure polysilicon formation
process
Silicon formation from the raw material

BASIC MATERIAL Raw material of wafer, i.e. silicon usually is

(SANDS / SILICON DIOXIDE)
acquired from sands (99.99% pure) melted at
high temperatures.

SILICON REDUCTION Sands heats up with carbon

SiO2 + C Si + CO2

Silicon heats up with hydrochloric acid at

SILICON PURIFICATION
Si + 3HCL SiHCL3 + H2
temperatures 1000˚C yields silicon triklorosilane
and gas hydrogen released from the process.

Silicon triklorosilane heat all with hydrogen at

PRODUCTION ULTRA PURE POLYSILICON temperatures 1000˚C to make ultra pure silicon
ROD
SiHCL3 + H2 Si + 3HCL (99.99999%).
2.1.3 Define single crystal silicon

Silicon crystal structures

SILICON CRYSTAL
STRUCTURE

SINGLE
POLYCRYSTALLINE AMORPHOUS
CRYSTAL
Single crystal (Monocrystalline)
 Ordered crystal structure, with each atom
ideally lying in a pre-determined position
 Has predictable and uniform behavior
 Energy Band (Eg)
 Carrier mobility (µ)
 Resistivity material (ρ)
 Use a 'seed crystal' as origin point of
freezing
Single crystal (Monocrystalline)

 Silicon single crystals and related materials

have a large market in integrated circuits
industry because its
 predictable and uniform behavior
 regular arrangement of silicon atoms
produces a well-defined band structure
Single crystal (Monocrystalline)

Single crystal structure

 Polycrystalline

 Comprise multiple parts of single

terdiri daripada

crystal structure
 Disorganized and scattered bertabur
 Used in IC fabrication as gate material in the
technology of Metal-Oxide-Semiconductor
Field-Effect Transistors (MOSFET)
Polycrystalline
 Amorphous

 Atoms are unorganized

 Do not has fixed arrangement
 Used in IC fabrication as switch element in
Liquid Crystal Display (LCD)
Amorphous
 Crystalline Structure For
IC Fabrication

Single crystal ?
Polycrystalline?
Amorphous?

SINGLE
CRYSTAL
 Crystalline Structure For
IC Fabrication
Distillation & Reduction Crystal growth
Penyulingan & penurunan

Single
Raw material Polycrystalline
crystal
2.1.4 Describe method of growing single crystal
silicon:
Single Crystal Growth
 Crystalline Growth process is carried out to
change the structure of a polycrystalline to
single crystal.
 2 methods:
 Czochralski Method (CZ ) (cho-HRAL-skee )
 Float Zone Method (FZ)

Polycrystalline Single crystal

Crystal growth
 Single Crystal Growth: Czochralski

 A seed crystal is dipped into a crucible of molten

silicon and withdrawn slowly, pulling a cylindrical
single crystal as the silicon crystallizes on the
seed.
 The seed crystal and the crucible are rotated in
opposite directions while this withdrawal process
occurs.
 The processes are repeated until the ingot is
produced.
 Pull rate, melt temperature and rotation rate
control the growth
Single Crystal Growth: Czochralski
 CRYSTALLINE GROWTH : CZOCHRALSKI

Seed down Seed pulling shouldering Growth& withdrawal

Czochralski
 Single Crystal Growth: Czochralski

A puller rod with seed crystal for

growing single-crystal silicon

Crucibles used in
Czochralski method
 Single Crystal Growth: Float zone

The process starts with a high-purity polycrystalline

rod and a monocrystalline seed crystal that are held
face to face in a vertical position and are rotated.
The RF coil's magnetic field induces an electric field in
the rod, heating and melting the interface between the
rod and the seed.
The seed is brought up from below to make contact
with the drop of melt formed at the tip of the poly rod.
Single-crystal silicon forms at the interface, growing
upward as the coils are slowly raised.
Single Crystal Growth: Float zone
Single Crystal Growth: Float zone
 COMPARISON BETWEEN CZ & FZ

Characteristic CZ FZ
Growth speed 1 to 2 3 to 5
(mm/min)
Size Diameter (mm) 150 – 200 100 - 150
Oxygen content > 1 x 1018 < 1 x 1016
(atom/cm3)

Carbon content > 1 x 1017 < 1 x 1016

(atom/cm3)

Metallic Impurity Higher Lower

Content
Crystal structure Single crystal Single crystal
Electrical resistivity 0.01 – 50 Ω/cm 10-200 Ω/cm
2.2 Understand the basic process steps
for wafer preparation
2.2.1 Explain process involved in transforming
silicon ingot into wafer
Overview
 PREPARING WAFER

- UTK DPTKAN DIAMETER YG SERAGAM

Crystal growth
CZ or FZ -KISARAN JONGKONG AKAN MEMBENTUK TEPI WAFER
-PUNARAN DILAKUKAN UNTUK MELICINKAN LAGI
PERMUKAAN WAFER
Diameter grindiing

Flat/ notch

Slicing

Polish

Wafer is ready for fabrication

 PREPARING WAFER

- To get uniform diameter

Crystal growth
CZ or FZ -Grind to shape the wafer edge
-Etching is done to smooth the surface

Diameter grinding

Preparing crystal ingot for grinding

Flat/ notch

Slicing

Polish
Diameter grind

Wafer is ready for fabrication

 PREPARING WAFER

Flat/ notch: For orientation purpose

- Allow consistent alignment
Crystal growth
CZ or FZ

Diameter grinding

Flat/ notch Preparing crystal ingot for

grinding

Slicing

Diameter
Polish grind

Flat grind
Wafer is ready for fabrication
 PREPARING WAFER

Ingot is sliced using diamond saw

Crystal growth
CZ or FZ

Diameter grinding

Flat/ notch

Slicing

Polish

Wafer is ready for fabrication

 PREPARING WAFER

Crystal growth
CZ or FZ

Diameter grinding

Flat/ notch

Slicing Polishing the wafer to smoothes the

uneven surface and makes the wafer
flat and smooth enough to support
Polish
optical photolithography.

Wafer is ready for fabrication

 PREPARING WAFER

Crystal growth
CZ or FZ

Diameter grinding

Flat/ notch

Slicing

Polish

Wafer is ready for fabrication

 PREPARING WAFER

Crystal growth
CZ or FZ

Diameter grinding • Wafer is cleaned and ready for ic

fabrication process

Flat/ notch

Slicing

Polish

Wafer is ready for fabrication

2.2.2 Explain Epitaxial Layer

 Epitaxial layer is a single crystal layer on a single

crystal substrate.
Or
 The deposition of a crystalline overlayer on a
crystalline substrate, where the overlayer is in registry
with the substrate. The overlayer is called an epitaxial
film or epitaxial layer.
( pemendapan lapisan kristal di atas subsrat kristal, di mana lapisan atas tersebut adalah tergolong bersama
substrat tersebut. Lapisan atas ini dikenali sebagai epitaxial film atau epitaxial layer)

 The term epitaxy comes from the Greek roots epi,

meaning "above", and taxis, meaning "in ordered
manner". It can be translated "to arrange upon".(untuk
mengatur di atas)
Why Epitaxy?

 To enhance the performance of discrete bipolar

transistor.
 To improve the performance of dynamic random
access memory devices (RAMs).

Advantages of epitaxial wafers over bulk wafers:

 Offers means of controlling the doping profile
 Epitaxial layers are generally oxygen and carbon free
2.2.3 Explain characteristic of wafer ready for IC
fabrication process such as thickness,
diameter, and wafer surface features
Trend of producing large wafer
Trend of producing large wafer
 Trend of producing large wafer

100000 10
Fab Cost ($M)

Linewidth (nm)
10000

Linewidth (um)
Fab Cost ($M)

1000

100
0.1

10

100mm 150mm 200mm 300mm 450mm

1 0.01
1975 1980 1985 1990 1995 2000 2005 2010 2015 2020 2025
benefits of using larger diameter wafers
2.3 Understand the integrated circuit basic
fabrication process
2.3.1 Explain oxidation process in IC fabrication

OXIDATION VS EPITAXY
OXIDATION - Chemical reaction between silicon and oxygen to produce the
silicon dioxide layer
Silicon dioxide layer(SiO2)

subtrate

It protects the wafer from moisture and other atmospheric contaminants , being scratch,
dust, chemical reaction of contaminants.
Act as insulator during doping process.
Act as dielectric on wafer surface to prevent short circuit between metal layer
SiO2 acts as the active gate electrode in MOS device structure.

EPITAXY - is the deposition pemendapan of epitaxial layer on a single-crystal

silicon substrate (to produce epitaxial layer)
Epitaxial layer (silicon)
Silicon substrate (wafer)
(silicon) -To enhance the performance of discrete bipolar transistor.

Epitaxial layer (Gallium Arsenide) -To improve the performance of dynamic random access memory devices
Silicon substrate (wafer) (RAMs) and CMOS IC
(silicon)
 OXIDATION

Definition:
a. Chemical reaction between silicon and oxygen
to
produce the silicon dioxide layer
silicon+ oxygen  silicon dioxide

b. a process to grow silicon dioxide layer on

substrate surface using high temperature
Silicon dioxide
subtrate
 OXIDATION

Purpose:
 To produce a layer of oxide insulator on
silicon surce
 OXIDATION

Function:
 Protect the wafer surface from being scratch.
 Protect the wafer surface from dust.
 Protect the wafer from chemical reaction of
contaminants.
 Act as insulator during doping process.
 Act as dielectric on wafer surface to prevent short
circuit between metal layer
 OXIDATION

Factors that influence the oxide layer thickness

 Density of impurities
 Temperature
 Reaction time/ period
Methods of oxidation

OXIDATION

WET DRY
OXIDATION OXIDATION
 Wet oxidation
 Wet oxidation is carried out through the combination
of wet vapor with silicon to produce silicon oxide.

 Oxygen gas is flowed to the container with water &

heated to the boiling point

 Chemical reactions involved during the reaction of

silicon with water vapor: Si + 2H2O SiO2 + 2H2

 As a result an insulating layer of SiO2 is formed on

the surface of silicon wafers.
 Wet oxidation
 Fast growth rate
 Result in thick oxide but lower quality
 Dry oxidation
 Pieces of silicon wafers are prepared in a quartz tube.

 Dry oxygen gas flow to the quartz tube and the wafer
is then heated to 1100 ˚ c in the presence of dry
oxygen gas.

 Dry oxygen gas is absorbed slowly over the pieces of

wafer through chemical reactions follows:
Si + O2  SiO2

 As a result an insulating layer of SiO2 is formed on the

surface of silicon wafers.
 Dry oxidation
 Advantages
 Good quality
 Lower growth rate
 results in a higher density oxide
 Oxide layer is thin but durable
2.3.2 Explain doping process in IC fabrication

DOPING
 Process by which silicon atoms in crystal lattice substratum
silicon are replaced with atoms dopant ( type p or n).

 Intentionally introduces impurities into an extremely pure (also

referred to as intrinsic) semiconductor for the purpose of
modulating its electrical properties

 Phosphorus and arsenic are used to develop N-type silicon

 Boron, gallium or indium used to develop P-type silicon

 Phosphorus and arsenic are used to develop
N-type silicon
 Boron, gallium or indium used to develop P-type
silicon
 DOPING
 Function of Doped layer
 Control the resistivity silicon
 Facilitate the flow of current carrier.

 2 methods doping
 Thermal Diffusion (resapan)
 Ion Implantation(Penanaman ion)
 DOPING
Thermal Diffusion

 Thermal Diffusion was accomplished by exposing the

Si wafer to dopant (preposition) then driving it into
the wafer at high temperature by diffusion (drive in).
DOPING
 DOPING
Thermal Diffussion

Predeposition:

Wafer is exposed to dopants

Wafer is heated among temperatures 1000° TO 1200°C
The time, temperature and amount of dopants are under
control.
Impurity will sedimented / collected above the surface of
wafer until achieve a level call solid dissoluble level.
DOPING
Thermal Diffussion
 DOPING
Diffusion

 Advantage :
 its ability to introduce very high concentrations of
dopants into the poly-Si layer, attaining low levels of
resistivity.

 Disadvantage:
 The high processing temperature and its tendency to
increase surface roughness

 Ion Implantation has replaced diffusion in

doping Si
 DOPING
Ion Implantation

 Deposits dopants into the poly-Si layer by directly

bombarding it with high-energy ions of the dopant species.

 This method can produce shallow doped layer with high

density of dopants

 2 parameters which can be controlled exactly is

 Depth of area doped
 Density of Doping Material
 DOPING
Ion Implantation

Magnetic Mass Isolation From Outside View

 DOPING
Ion Implantation

Ion Implantation Figure

 DOPING
Ion Implantation

 High energetic ions is planted to the silicon surface

 Use to produce large scale integrated circuit

 This method can produce highly doped shallow layer

 Depth and density are under control exactly

 Dopant’s Ion beam (boron / phosphorus) is

accelerated with high energy (10-1000V)
 DOPING
Ion Implantation

 A magnetic mass isolation – to separate ions that

are not required.

 Ion beam is then bent and focus to target (wafer)

and penetrating into it.

 The depth of ion penetration depend on

 Acceleration energy
 Concentration of dopant Ion
 DOPING
Ion Implantation

 Advantages
 The accuracy of dopants’ position and density can be
controlled with high precision.
 Thickness of dopants is uniform.
 Use low temperatures at room temperature.
 Atom will doped directly into the wafer’s surface.
 Reduce crystal damage by high temperature.

 Disadvantages
 Cause defect to crystal lattice bashed by dopant atoms
 High cost equipment.
 Production of wafer is limited.
2.3.3 Explain photolithography process in IC
fabrication

PHOTOLITOGRAPHY
PROCESS

 Photolithography is the process of transferring

geometric shapes on a photo mask to the surface
of a silicon wafer.
 This process to selectively remove parts of a thin
film (SiO2) or the bulk of a substrate.

 Photolithography is a process analogous to

developing film in a darkroom.
SEQUENCE OF PHOTOLITHOGRAPHY
PROCESS

Wafer cleaning

Coat with photoresist

Pre -bake to semi-harden the

photoresist
SEQUENCE OF PHOTOLITHOGRAPHY
PROCESS
Remove the photomask. Kemudian
rendam didlm larutan pemunar .
The unexposed part of photoresist is
etched away
Post-Bake in high temperature to harden
the remaining photoresist

Etching (hydrofluoric acid) : the SiO2

layer that uncovered
by polymer layer is etched away

Etching (sulfuric acid): the photoresist

is etched away
 PHOTOLITOGRAPHY
PHOTO MASK

Opaque zone

Transparent zone

 Photo mask is a piece of glass have opaque pattern and

transparent pattern on its surface.

 Opaque pattern act as prevent UV radiance from penetrate photo

mask.

 Transparent pattern allow UV's radiance penetrate photo mask

 PHOTOLITOGRAPHY
PHOTO MASK

Opaque zone

Transparent zone

 Size and position form the pattern of photomask is very precise

 Process of transferring the pattern from photomask to wafer is

known as s photolithography proces
PHOTO MASK

Example of IC photo mask

 PHOTOLITOGRAPHY
PHOTO RESIST LAYER

 There were 2 type photoresist:-

 Positive photoresist( + ve )
 Negative photoresist( - ve )

 Photo resist criteria :-

 It must be stick perfectly on the surface substratum
 Thickness of photoresist must be uniform
 PHOTOLITOGRAPHY
POSITIVE PHOTO RESIST
 Exposed area is removed during etching
 PHOTOLITOGRAPHY
NEGATIVE PHOTO RESIST
 Exposed area is not discarded when etch.
2.3.4 Explain metallization process in IC
fabrication
METALIZATION
CRITERIA

 Metallization is the final step in the wafer processing

sequence.

 Metallization is the process by which the components

of IC’s are interconnected by aluminum conductor.

 Metallization is used to create contacts with the silicon

and to make interconnections on the chip.
2.3.4 Explain metallization process in IC
fabrication
METALIZATION
CRITERIA

 Characteristic of metallization in integrated

circuit.
 Low resistivity
 Easy to be formed
 Easy to be etched to generate pattern
 Easy to stick above the surface as conductor
 Do Not pollute the wiring device
 METALIZATION
METALIZATION PROCESS
 Five technique metallization
 Thermal evaporation
 Electron beam evaporation
 Sprinkle technique
 Deposition technique chemical vapour
 Pemplatan.
 Function
 As surface layer
 Substance as antireverse
 As MOS's electrode gate
 Create adaptation area for surface wafer
 METALIZATION
METALIZATION PROCESS
 Deposition of aluminium to the whole wafer

 Process photolitography perform to generate

layer deep for opening Aluminium.

 Aluminium's etching out from parts which are not

required

 Heating wafer to stick Aluminium to silicon and

oxide layer.
 METALIZATION
METALIZATION MATERIAL
 Metal type that use for metal layer.
 Aluminium
 Titanium
 Platinum
 Gold
 Molibdenum
 Tantalum

 Non-metal for metalization function

 Polisilikon – MOS Gate transistor area

 Copper and Aluminium always use in devices

connection.
METALIZATION
2.3.5 Explain etching process in IC fabrication
ETCHING
DEFINITION
 Etch
 Definite as material removal
 Carve(mengukir) on metal by using acid
 Etching
 Etching is a process in which material is removed from
selected regions of the substrate.
 Remove layer materials as silicon oxide ( SiO2 ), silicon
nitric (Si3N4) and polysillicon that are not required in a
particular place on wafer surface.
 Etching Process
 In forming components of wafer, these materials only
required in certain area only
 Each etching process only remove one types of
material only
 ETCHING
OBJECTIVES
 To remove photo resist and oxide layer on the
wafer surface in the photolithography process

 To remove surface damages during cutting wafer

to remove jagged effects around wafer.

 Remove metal layer which are not required in

metallization
 ETCHING
ETCHER

ETCHANT ETCHED LAYER

HYDROFLUORIC ACID (HF) / NITRIC ACID SiO2

HYDROFLUORIC ACID (HF) SILICON NITRIDE

PHOSPHORIC ACID/ NITRIC / ASETIC ALUMINIUM

NITRIC ACID + HYDROFLUORIC ACID (HF) POLYSILICON

SULFURIC ACID + ASETON + TRIKLOROETERINA PHOTO RESIST

Keperluan Proses Punaran

Saiz pertumbuhan wafer = 400 mm
Saiz kesusutan bahagian muka kurang daripada 0.5 um
 ETCHING

WET DRY
ETCHING ETCHING
 ETCHING
WET ETCHING
• Use liquid chemicals
• highly selective with respect to mask and substrate
• used in the manufacturing of circuits with feature
sizes larger than 3 microns.
• isotropic- etches in all directions at the same rate

Resist

SiO2

Substrate
 ETCHING
WET ETCHING
 Known as under cutting ( happen to targeted material and
its edges)

Undercut

Resist
Overetch Film

Substrate
 ETCHING
WET ETCHING

Wafers are immersed in a tank Operator shown placing a

of liquid reactants cassette of wafers into an acid
bath

Example of wet etching

 ETCHING
DRY ETCHING
 React with chemically reactive gases/ plasma
 Used to define circuit features smaller than 3 microns
 greater control over the process parameters
(e.g. pressure, temperature, gas flow, power).
 Can be isotropy & anisotropy (etch in one direction) -
controllable

Resist

SiO2

Substrate
 ETCHING
DRY ETCHING

Example of dry etching

 ETCHING
ETCHING
 3 situation after the Etching Process

Normal

Over etch

Resist Lifting
 COMPARISION BETWEEN
WET AND DRY ETCHING
WET ETCHING
METHOD Chemical solutions
ADVANTAGE 1. Low cost, easy to
implement
2. High etching rate
3. Good selectivity for most
materials
DISADVANTAGE 1. Inadequate for defining
feature size < 1um
2. Potential of chemical
handling hazards
3. Wafer contamination
issues
DIRECTIONALITY Isotropic
DRY ETCHING
Plasma / ion bombardment
1. Capable of defining
small feature size
1. High cost, hard to
implement
2. Low throughput
3. Poor selectivity
4. Potential radiation
damage
Anisotropic
2.4 Understand fabrication process for
CMOS integrated circuit
 NMOS
Gate(G)
 STRUCTURE
Insulator (SiO2 )
Drain (D) Source (S)
n n
NMOS
P SUBSTRATE

 SYMBOL

VG logic 1, switch ON
VG logic 0, switch OFF
 PMOS
Gate(G)
 STRUCTURE
Insulator (SiO2 )
Drain (D) Source (S)
P P
N SUBSTRATE

• SYMBOL

VG high, switch OFF

VG low, switch ON
2.4.1 Explain the fabrication process sequence of:
a) NMOS transistor
SEQUENCE OF NMOS FABRICATION PROCESS

P SUBSTRATE

Wafer

• P Substrate is produced through the doping process (eg doped

• with trivalent impurities such as boron). It is used as the base layer
• for building devices.
SiO2 layer (thick oxide)

P Substrate
 photoresist
SiO2 (thick oxide)

P Substrate
 UV light

photomask

photoresist
SiO2 layer (thick oxide)

P Substrate
 UV light

photoresist
SiO2 layer (thick oxide)

P Substrate
 Polysilicon layer
SiO2 (Thin oxide )
SiO2 (Thick oxide)

Subsratum
P SubstrateP

• Satu lapisan SiO2 baru setebal 0.1 um diselaput di atas permuka

serpihan.
 UV light

photomask

Polysilicon
Polysilicon layer
SiO2 (Thin oxide )
SiO2 (Thick oxide)

Subsratum
P SubstrateP
 Polysilicon

SiO2 (Thin oxide )

SiO2 (Thick oxide)

Subsratum
P SubstrateP
 Polysilikon

SiO2 (Thick oxide)

Drain Source
Subsratum
P SubstrateP
 UV light

photomask

SiO2 (thick oxide)

P Substrate
 Gate

Drain Source
2.4.1 Explain the fabrication process sequence of:
a) N- well CMOS

SEQUENCE OF
CMOS INVERTER
FABRICATION
PROCESS
 CMOS Fabrication Technology

 P well process
 N well process
 Twin tub process
 Silicon on Insulator process (SOI)
 ** N well process

NMOS PMOS

N+ N+ P+ P+
N Well
P Substrate
 N well process

SiO2 layer (thick oxide)(thick oxide)

SiO2 layer

N Well

P Substrate

• Field oxide growth

• A thick oxide layer is grew on wafer surface.
• An Opening is produced to enable the diffusion of N-well.
 SiO2 layer (thick oxide)

N Well

P Substrate

• Thin oxide is grown over the exposed surface of the chip

 N Well

P Substrate

• Polysilicon layer is deposited on the top of thin oxide layer to

form the gate structure.
• The polysilicon is patterned by photoresist coating and masking.
 masking

N+ N+
N Well

P Substrate

• N-type impurities are diffused to form source and drain

masking

N+ N+ P+ P+
N Well
P Substrate

• P-type impurities are diffused to form source and drain

 N+ N+ P+ P+
N Well
P Substrate

• Contact cuts are formed through etching process.

 NMOS PMOS

N+ N+ P+ P+
N Well
P Substrate

• Metal (Aluminium) is deposited on the surface and etched

selectively to form the desired connection patterns
 P well process

PMOS NMOS

P+ P+ n+ n+
P Well
N Substrate
 P well process

SiO2 layer (thick oxide)(thick oxide)

SiO2 layer

P Well

N Substrate

• Field oxide growth

• A thick oxide layer is grew on wafer surface.
• An Opening is produced to enable the diffusion of p-well.
 SiO2 layer (thick oxide)

P Well

N Substrate

• Thin oxide is grown over the exposed surface of the chip

 P Well

N Substrate

• Polysilicon layer is deposited on the top of thin oxide layer to

to form the gate structure.
• The polysilicon is patterned by photoresist coating and masking.
 masking

P+ P+
P Well

N Substrate

• p-type impurities are diffused to form source and drain

masking

P+ P+ n+ n+
P Well
N Substrate

• n-type impurities are diffused to form source and drain

 P+ P+ n+ n+
P Well
N Substrate

• Contact cuts are formed through etching process.

 PMOS NMOS

P+ P+ n+ n+
P Well
N Substrate

• Metal (Aluminium) is deposited on the surface and etched

selectively to form the desired connection patterns
2.5 Remember current trend in
semiconductor devices
2.5.1 Define Micro-Electro Mechanical System
(MEMS)

MICRO-ELECTROMECHANICAL SYSTEM (MEMS)

 Micro – indicates the small size of MEMS device

( the micrometer / micron – one one-millionth of a meter :
is the base unit of measure in MEMS)

 Electro – refer to electricity, often in form of electrostatic

force.

 Mechanical – mechanical parts

 System – indicates that “electro” and “ mechanical” go
together into a single system on a MEMS device.
 MEMS

MEMS
FABRICATIONS
WHAT IS PROCESS
MEMS
INSIDE MEMS BULK MICROMACHINING

SURFACE
EXAMPLE AND IC MECHANICAL MICROMACHINING
APPLICATION PARTS
LIGA

ADVANTAGE OF
MEMS SENSOR ACTUATOR
 WHAT IS MEMS??
 Micro-Electro-Mechanical Systems (MEMS) is the
integration of mechanical elements, sensors,
actuators, and electronics on a common silicon
substrate through microfabrication technology
 More on “What are MEMS?”

 MEMS devices first took off in the sensor industry.

(pertama dalam industri sensor)

 Most MEMS devices have at least one transducer

element.
 To sense
 To actuate

 Transducer is a device or system that converts one

form of energy to another – force to voltage, voltage
to force, …

Transducer - a device that converts variations in a physical quantity, such as pressure or

brightness, into an electrical signal, or vice versa.
 How Does It Work????
Components:
􀂃 Microelectronic Integrated Circuits (the brains of the
system)
 It receives and processes data, and makes decisions. The
data received comes from the micro-sensors in the MEMS.

􀂃 Micro-Sensors (the eyes and arms)

 They constantly gather data from the surrounding
environment and pass this information on to the
microelectronics for processing

􀂃 Micro-Actuator (the decision-maker)

 Acts as a switch or a trigger to activate an external device. If
this decision is reached, the microelectronics will tell the
micro actuator to activate this device
2.5.2 List MEMS applications
More on MEMS Applications
The goal of an airbag is to slow the passenger's forward motion as evenly as
possible in a fraction of a second. There are three parts to an airbag that
help to accomplish this feat:
The bag itself is made of a thin, nylon fabric, which is folded into the steering
wheel or dashboard or, more recently, the seat or door.

The sensor is the device that tells the bag to inflate (blow up). Inflation
happens when there is a collision force equal to running into a brick wall at
10 to 15 miles per hour (16 to 24 km per hour). A mechanical switch is
flipped when there is a mass shift that closes an electrical contact, telling the
sensors that a crash has occurred. The sensors receive information from an
accelerometer built into a microchip.
2.5.3 List the advantages Of MEMS

Cost
Reliability
Because of the increase in
more reliable than a macro system
micromachining technology, hundreds
of MEMS can be made from a single 8-
Limitless
inch wafer of silicon. Therefore, the cost
Because of the reduced cost and
for a MEMS is very low.
increased reliability, there is almost
no limit to what MEMS can be used for
Size
Since an entire system can be made this
small and in such quantities, prices are
reduced for products which incorporate
this technology. In addition, its size
makes it very easy to incorporate into
almost any environmental
2.6 Understand Cleanroom and
contamination control in wafer
and IC fabrication
 Introduction
 Yield improvement is the biggest challenge in integrated
circuit fabrication.

 Initially, process is focused on producing a wafer with a

yielding die, i.e. a die that works according to the IC
specification. Once, that has been obtained yield steadily
increases.

 The limiter for yield is usually wafer contamination in the

fab. This has become even more important now, since
device dimensions are currently in the nm range.

 Cleanroom technology is designed to minimize this

contamination.
Figure 1: Defects between (a) metal lines and (b) on the surface of a
wafer. Surface defects can affect the growth of new layers while defects
between metal lines can cause electrical shorts.

Adapted from Microchip fabrication

- Peter van Zant.
2.6.1 Explain sources of contamination that affect
the production yield in IC fabrication

 Contaminant types
- Contaminants can be divided into five main
classes.

• Particles
• Metal ions
• Chemicals
• Airborne molecular contaminants
• Contamination
• Particles
 Some common particle sources in the fab are
1. People working in the fab
2. Generated by fab equipment
3. Processing chemicals

In typical integrated circuits, these defects need to be only a few microns

wide to affect the electrical signals and as device dimensions shrink the
size of these killer defects also shrinks.

Adapted from http://www.si2.org/openeda.si2.org/dfmcdictionary/index.php/Random Defects

Figure above: Typical sizes of common contaminants on wafers. These are
all related to wafer handling in the fab. To minimize these defects, wafers are
exposed to the fab environment only under extremely controlled conditions.

Adapted from Microchip fabrication - Peter van Zant.

• Metal ions
 Dopant concentrations in semiconductors are very small, of the
order of 1015 to 1017 ions per cm-3 (typically ppm or ppb).

 Presence of electrically active impurities or contaminants can

alter device performance. These impurities are called mobile
ionic contaminants (MICs). These are ions that have high
mobility in the semiconductor. They can cause failure even after
packaging(they might not be detected during sort).

 Sodium is the most common MIC, which is commonly found in

chemical sources.

 Table 1 shows concentrations of metallic impurities in resist

strippers. The MICs can affect the metal oxide semiconductor
(MOS) junction by modifying the barrier potential. Special low
metal grade chemicals have been developed for use in the
semiconductor industry, to overcome this problem.
Table 1: Trace impurities in a commonly used resist stripper in the fab.
Concentrations are in ppb.

The data values are sourced from Microchip fabrication - Peter van Zant.
• Chemicals

 Another source of contaminants are unwanted chemicals

that contaminate process chemicals and deionized water
that are used in various steps in the fabrication process.

 They can affect the regular processing e.g. contamination

in the etchant can cause non uniform etching or change
the etching rate.

 Chlorine is a common contaminant that is found in these

chemicals.

 Bacteria is another common contaminant that can grow on

unwashed surfaces. These can act as particulate
contaminants and also as a source of metallic ions.
 • Airbone Molecular contaminants
 Airborne molecular contaminants (AMCs) are contaminants
from process tools or chemical delivery systems.

 They enter the fabrication area and cause defects on the

wafers. AMCs can be gases, dopants, process chemicals,
moisture, and/or organics.

 A common source of AMCs is during wafer transfer in the

fab. Wafer transfer and storage usually happens through
FOUPs (front opening universal pods). The FOUP is a
plastic container with grooves for holding wafers and
outgassing of the FOUP can contaminate the wafers.

 Thus, wafers stored in the fab for long time can pick up dust
just by sitting in these FOUPs. One solution is to use
nitrogen purged FOUPs to minimize dust particles.
• Contamination problems and sources

 The presence of contaminants can cause three major

effects:

1. Device yield - this is the most obvious effect and can

be easily be detected. Contaminants can cause the die
to fail electrical tests and thus reduce yield.
2. Device performance - contamination can cause a
lowering of device performance with time. This is a
more serious problem because it causes lowering of
device life.
3. Device reliability - this is the hardest to detect because
this can lead to failure in service. Sometimes, it might
not even be detected during electrical testing during
sort.
2.6.2 Explain the cleanroom concept in wafer and
IC fabrication

 A clean room (or cleanroom) is an enclosed space in

which airborne particulates, contaminants, and
pollutants are kept within strict limits.

 In industry, clean rooms are used in the manufacture

and servicing of hardware such as integrated circuits
( IC s) and hard drive s.

 In biotechnology and medicine, clean rooms are used

when it is necessary to ensure an environment free of
bacteria, viruses, or other pathogens. In addition, the
temperature and humidity may be controlled.
cleanroom
 Why cleanroom?

 Particles kills yield

 IC fabrication must in a clean room
 Artificial environment with low particle counts
 What exactly is cleanroom?

 Cleanroom – are with controlled level of

contamination
o First used for surgery room to avoid bacteria
contamination
o Smaller device needs higher grade clean room
o Less particle, more expensive to build
2.6.2 Explain cleanroom standard
 cleanroom class
 cleanroom class

Illustrates the number of particles per cubit foot of air with different
cleanroom class
 cleanroom class (definition of airborne
particulate)
 cleanroom class
 cleanroom structure
 Gowning Area of a cleanroom