Lesson 2 Combinational Logic Circuits

Binary Logic and Gates Boolean Algebra Standard Forms Map Simplification Tabulation Method NAND and NOR Gates Exclusive-OR Gates Integrated Circuits

Binary Logic
Deals with variables that take on two discrete values and with operation that assume logical meaning. The manipulation and processing of binary information. Uses values, variables and operations:
True is represented by the value 1 (ON). False is represented by the value 0 (OFF).

Binary Logic
Digital circuits are implemented using transistors and interconnections in complex semiconductor devices called integrated circuits. Each basic circuit is referred to as a logic gate.

Basic Logical Operators

AND
Represented by a dot (.) or no operator Will yield 1 if all the inputs are 1

OR
Represented by a plus (+) symbol Will yield 1 if at least one of the inputs is 1

NOT
Represented by a bar or prime () It will complement the input

Other Logic Gates

NAND
Performs the complement of AND Will yield 0 if all the inputs are 1

NOR
Performs the complement of OR Will yield 0 if at least one of the inputs is 1

Buffer
Retains the input value

Other Logic Gates

XOR
Will yield 1 if the inputs are complementing each other

XNOR
Will yield 1 if the inputs are the same Opposite of XOR

Binary Logic
Variables are represented by letters and can have one of two values, either 0 or 1. Operations are functions of one or more variables.
AND is represented by X.Y OR is represented by X + Y NOT is represented by X'

These basic operations can be combined to give expressions.

Switching Circuit
LAMP

1 SW1

1 2 1 SW2

AND gate

Switching Circuit
LAMP

1 2 1

SW1 2 2

1 SW2

OR gate

Switching Circuit
LAMP

SW1 2

NOT gate

2 1

Truth Tables
A means of representing the results of a logic function using a table. They are constructed by defining all possible combinations of the inputs to a function, and then calculating the output for each combination in turn.

Truth Tables
AND X 0 0 1 1 Y 0 1 0 1 Z 0 0 0 1 X 0 0 1 1 OR Y 0 1 0 1 Z 0 1 1 1 NOT X 0 1 Y 1 0

Truth Tables
NAND X 0 0 1 1 Y 0 1 0 1 Z 1 1 1 0 X 0 0 1 1 NOR Y 0 1 0 1 Z 1 0 0 0 Buffer X 0 1 Y 0 1

Truth Tables
XOR X 0 0 1 1 Y 0 1 0 1 Z 0 1 1 0 X 0 0 1 1 XNOR Y 0 1 0 1 Z 1 0 0 1

Assignment 2-1
Construct the equivalent switching circuit of the following gates:
NAND NOR Buffer XOR XNOR

Boolean Algebra
It deals with binary variables and logic operations. In honor of George Boole
English mathematician Published a book introducing the mathematical theory of logic in 1854

Boolean Algebra
Duality Principle
The duality principle of Boolean algebra states that a Boolean equation remains valid if we take the dual of the expressions on both sides of the equals (=) sign. To get the DUAL of a Boolean Expression: Interchange:
o OR = AND o1=0

Boolean Algebra
Identities X+0=X X+1=1 X+X=X X + X = 1 X = X Commutative Law X+Y=Y+X Associative Law X + (Y + Z) = (X + Y) + Z Distributive Law X(Y + Z) = XY + XZ DeMorgans Theorem (X + Y) = XY (XY) = X + Y X + YZ = (X + Y)( X + Z) X(YZ) = (XY)Z XY = YX X.1=X X.0=0 X.X=X X . X = 0

Examples
X + XY = X XY + XY = X X + XY = X + Y (X + Y)(X + Y) = X X(X + Y) = XY

Consensus Theorem
A consensus or redundant term can be eliminated. Examples:
XY + XZ + YZ = XY + XZ and its dual: (X + Y)(X + Z)(Y + Z) = (X + Y)(X + Z)

Consensus Theorem
Proof:
XY + XZ + YZ = XY + XZ + (X + X) YZ = XY + XZ + XYZ + XYZ = XY (1 + Z) + XZ (1 + Y) = XY + XZ

Boolean Functions
An expression formed with binary variables (0 or 1) and its logical operands (logic gates). Example: F = xyz F = AB + CD F = (wx + y) z

Algebraic Manipulation
Original Function: F = XYZ + XYZ + XZ

2 1 2 13 3 4 5 12 1 2 3 12 13

Y Z

2 1 3 2

Algebraic Manipulation
Simplified Function: F = XY + XZ

X Y Z

2 1 3 2 1 3 2 4 6 5

Complement of a Function
It is obtained from an interchange of 1s to 0s and 0s to 1s for the values of F in the truth table. It can be derived algebraically through the use of DeMorgans theorem. The generalized form is to interchange the AND and OR operations and complement each variable and constant. A simpler method is to take the dual of the function and complement each literal.

Example
Find the complement of the following functions:
1. F1 = XYZ + XYZ 2. F2 = X (YZ + YZ)

Seatwork 2-1 (30 minutes)

Simplify the following Boolean expressions to a minimum number of literals:
1. 2. 3.

ABC + ABC + AB ABC + AC BC + B(AD + AD)

4. 5. 6.

(A + B + AB)(AB + AC + BC) ((A + B) + AB)(CD + CD) + (AC) WX(Z + YZ) + X(W + WYZ)

Find the complement of the following expressions:

1. 2. 3.

AB + AB ABC + AC + (AB) (VW + X)Y + Z

4. 5. 6.

WX(YZ + YZ) + WX(Y + Z)(Y + Z) (A + B + C)(AB + C)(A + BC) A(BC + BC) + C(BD + (BD))

Standard Forms
It facilitate the simplification procedures and would result in more desirable logic circuits It contain: Product terms (Minterms)
AND operation Example: xyz

Sum terms (Maxterms)

OR operation Example: x + y + z

Minterms and Maxterms

Minterm
A product term in which all the variables appear exactly once, either complemented or uncomplemented. Has a value of 1 (uncomplemented).

Maxterm
A sum term that contains all the variables in complemented or uncomplemented form. Has a value of 0 (uncomplemented).

Minterms and Maxterms

Characteristic property: Minterms and maxterms represent exactly one combination of the binary variables in a truth table There are 2n distinct minterms/maxterms for n variables

Minterms and Maxterms

X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 Product Term XYZ XYZ XYZ XYZ XYZ XYZ XYZ XYZ X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 Sum Term X+Y+Z X+Y+Z X+Y+Z X+Y+Z X+Y+Z X+Y+Z X+Y+Z X+Y+Z

Minterms for Three Variables

Product X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 Term XYZ XYZ XYZ XYZ XYZ XYZ XYZ XYZ Symbol m0 m1 m2 m3 m4 m5 m6 m7 m0 1 0 0 0 0 0 0 0 m1 0 1 0 0 0 0 0 0 m2 0 0 1 0 0 0 0 0 m3 0 0 0 1 0 0 0 0 m4 0 0 0 0 1 0 0 0 m5 0 0 0 0 0 1 0 0 m6 0 0 0 0 0 0 1 0 m7 0 0 0 0 0 0 0 1

Maxterms for Three Variables

Sum X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 Term X+Y+Z X+Y+Z X+Y+Z X+Y+Z X+Y+Z X+Y+Z X+Y+Z X+Y+Z Symbol M0 M1 M2 M3 M4 M5 M6 M7 M0 0 1 1 1 1 1 1 1 M1 1 0 1 1 1 1 1 1 M2 1 1 0 1 1 1 1 1 M3 1 1 1 0 1 1 1 1 M4 1 1 1 1 0 1 1 1 M5 1 1 1 1 1 0 1 1 M6 1 1 1 1 1 1 0 1 M7 1 1 1 1 1 1 1 0

Example
x 0 0 0 0 1 1 1 1 Input y 0 0 1 1 0 0 1 1 Output z 0 1 0 1 0 1 0 1 F 1 0 1 0 0 1 0 1 F 0 1 0 1 1 0 1 0

Important Properties
1.

There are 2n minterms (maxterms) for n Boolean variables. Any Boolean function can be expressed as a logical sum of minterms (product of maxterms). The complement of a function contains those minterms (maxterms) not included in the original function. A function that includes all the 2n minterms (maxterms) is equal to logic 1 (0).

2.

3.

4.

Sum of Products (Sum of Minterms)

An alternative standard form of expression that contains product terms with any number of literals/variables. Gate structure consists of a group of AND gates followed by an OR gate. Example: F = y + xyz + xy

Product of Sums (Product of Maxterms)

An alternative standard form of expression that is obtained by forming a logical product of sum terms. Gate structure consists of a group of OR gates followed by an AND gate. Example: F = x (y + z) (x + y + z)

Function from Truth Table

X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 F 1 0 1 0 0 0 1 1

SOP form: F = m(0, 2, 6, 7) POS form: F = M(1, 3, 4, 5)

Map Simplification
Karnaugh map, or K-map, is a diagram made up of squares, with each square representing one minterm of the function. It is a straightforward procedure for simplifying Boolean functions up to four variables. But cumbersome to use for functions with five to six variables.

Two-Variable Map
y x 0 1 0 m0 m2 (a) 1 m1 m3 x 0 1 y 0 xy xy (b) 1 xy xy

Three-Variable Map
yz x 0 1 00 01 11 10 x 0 1 yz 00 01 11 10

m0 m4

m1 m5

m3 m7

m2 m6

xyz xyz xyz xyz xyz xyz xyz xyz

(a)

(b)

Four-Variable Map
yz wx

00

01

11

10

yz wx

00

01

11

10

00 01 11 10

m0 m1 m3 m2 m4 m5 m7 m6 m1 m1 m1 m1 m8 m9 m1 m1
1 0 2 3 5 4

00 01 11 10

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

(a)

(b)

Simplification using K-maps

Simplify the following Boolean functions:
1. 2. 3. 4. 5. 6.

F(x, y, z) = m(2, 3, 4, 5) F(x, y, z) = m(3, 4, 6, 7) F(x, y, z) = m(0, 2, 4, 5, 6) F(w, x, y, z) = m(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) F(A, B, C, D) = m(0, 2, 4, 5, 6, 7, 8, 10, 13, 15) F(w, x, y, z) = M(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)

Prime Implicants
A prime implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map. If a minterm in a square is covered by only one prime implicant, that prime implicant is said to be essential.

Prime Implicants
F (A, B, C, D) = (0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15)
CD AB

00

01

11

10

CD AB

00

01

11

10

00 01 11 10

1 1 1 1 1

1 1 1 1

00 01 11

1 1 1 1 1

1 1 1 1

10

Essential prime implicants

Prime Implicants

Selection Rule
Minimize the overlap among prime implicants as much as possible. In particular, in the final solution, make sure that each prime implicant selected includes at least one minterm not included in any other prime implicant selected.

Prime Implicants
Examples:
1. 2.

F(A,B,C,D) = m (0, 1, 2, 4, 5, 10, 11, 13, 15) F(W,X,Y,Z) = WX + WXZ + WYZ + WXY + WXZ

Dont-Care Conditions
Two cases of occurrence:
1. 2.

The input combinations never occur The input combinations are expected to occur, but we do not care what the outputs are in response to these combinations

Functions that have unspecified outputs for some input combinations are called incompletely specified functions. The unspecified minterms of a function are called dont-care conditions.

Simplification with Dont Care Conditions

Example: F(A, B, C, D) = m (1, 3, 7, 11, 15) d(A, B, C, D) = m (0, 2, 5)

Five-Variable Map
F (A, B, C, D, E) = (0, 2, 4, 6, 9, 13, 21, 23, 25, 29, 31)

Seatwork 2-2 (30 minutes)

Simplify the following Boolean functions by finding all prime implicants and essential prime implicants and applying the selection rule:
1. 2. 3. 4. 5.

F(W,X,Y,Z) = m (1, 5, 6, 7, 11, 12, 13, 15) F(W,X,Y,Z) = M (1, 3, 5, 6, 7, 9, 10, 11, 14) F(A,B,C) = AB + AC + BC + ABC F(A,B,C,D) = (A+B+D)(A+D)(A+B+D)(A+B+C+D) F(A, B, C, D, E) = m (0, 1, 4, 5, 16, 17, 21, 25, 29)

Simplifying a Boolean Function through Tabulation (Quine-McCluskey Method)

The tabular method consists of two parts: Finding the all the terms that are candidates for inclusion in the simplified function (prime implicants) Choosing among the prime implicants those that give an expression with the least number of literals Example: F (W, X, Y, Z) = m (0, 1, 2, 8, 10, 11, 14, 15) F (W, X, Y, Z) = m (1, 4, 6, 7, 8, 9, 10, 11, 15)

1. 2.

For the function F(W,X,Y,Z) = m(0,1,2,8,10,11,14,15)

(a) WXYZ 0 1 2 8 10 11 14 15 0000 0001 0010 1000 1010 1011 1110 1111 / / / / / 10, 11 / / 11, 15 / 14, 15 1-11 111/ / 10, 14 1011-10 / / 2, 10 8, 10 -010 10-0 / / F = WXY + XZ + WY 0, 1 0,2 0, 8 (b) WXYZ 00000-0 -000 / / 0,2,8,10 0,8,2,10 10,11,14,15 10,14,11,15 (c) WXYZ -0-0 -0-0 1-11-1-

For the function F(W,X,Y,Z) = m(1,4,6,7,8,9,10,11,15)

(a) 0001 0100 1000 0110 1001 1010 0111 1011 1111 1 4 8 6 9 10 7 11 15 / / / / / / / / / 7, 15 11, 15 (8) (4) 6, 7 9, 11 10, 11 (1) (2) (1) / / 1, 9 4, 6 8, 9 8, 10 (b) (8) (2) (1) (2) / / (c) 8, 9, 10, 11 8, 9, 10, 11 (1, 2) (1, 2)

Decimal 1, 9 (8) 4, 6 (2) 6, 7 (1) 7, 15 (8) 11, 15 (4) 8, 9, 10, 11 (1, 2) 1 / / XYZ WXZ WXY XYZ WYZ / WX 1, 9 4, 6 6, 7 7, 15 11, 15 8,9,10,11 / X

W 0 0 1 1 4 X

X 0 1 1 1 0 6 X X

Y 0 1 1 1 7

Z 1 0 1 1 8 9 X

Term XYZ WXZ WXY XYZ WYZ WX 10 11 15

X X X X X / X / X / X X

Seatwork 2-3 (30 minutes)

Simplify the following Boolean functions by means of the tabulation method:
1.

F (A, B, C, D, E) = m (0, 2, 4, 6, 9, 13, 21, 23, 25, 29, 31) P(A,B,C,D,E,F) = m (6, 9, 13, 18, 19, 25, 27, 29, 41, 45, 57, 61)

2.

NAND and NOR Gates

Used extensively as standard logic gates More popular than AND and OR gates Natural functions for the simplest electronic circuits

Logical Operations with NAND Gates

X Y
1 3 2 1 2

(XY)'' = XY

AND X
1 2 1 3 2 1 2

(X'Y')' = X + Y

OR
1 3

X'

NOT

Graphic Symbols for NAND and NOT Gates

X Y
1 3 2

(XY)'

X'

(a) AND-NOT X' X Y

1 3 2 20 1

X' + Y' (c) NOT

(b) NOT-OR

Procedure for two levels

1. 2. 3.

4.

Simplify the function and express it in sum-ofproducts form. Draw a NAND gate for each product term of the expression that has at least two literals (1st level). Draw a single gate using the AND-NOT or the NOT-OR graphics symbol at the 2nd level, with inputs coming fro outputs of 1st level gates. A term with a single literal requires a NOT at the first level. However, if the single literal is complemented from its original appearance it can be connected directly to an input of the 2nd level NAND gate.

Implementation with NAND Gates

Examples:

1. F = XY + XY + Z 2. F = (AB + AB)E(C + D)

X Y' X' Y Z

1 3 2 4 6 5 2 1 3

F = XY + XY + Z
F

X Y' X' Y

1 3 2 4 6 5 5 4 6

X Y' X' Y Z'

1 3 2 4 6 5 2 1 3

Z' F

General Procedure
Convert all AND gates to NAND gates with AND-NOT graphic symbols. 2. Convert all OR gates with NOT-OR graphic symbols. 3. Check all the bubbles in the diagram. For every bubble that is not counter-acted by another bubble along the same line, insert a NOT gate or complement the input literal from its original appearance.
1.

A B' A' B C D' E A B' A' B C D' E

1 3 2 4 6 4 6 5 1 3 2 10 9 8 12 11 13 5

1 3 2 4

F = (AB + AB)E(C + D)
6 5 6 12 11 3 13 4

4 5 1 3 2

9 8 10 1 2

A B' A' B C D' E

1 3 2 12 11 4 6 5 12 11 13 10 12 11 13 9 8 13 12 11 12 11 13 13

Logical Operations with NOR Gates

2 1

X'

X'

Inverter X Y
2 1 3 1 2

(X + Y)'' = X + Y

OR X
1 2 2 1 3 1 2

(X' + Y') = XY

AND

Graphic Symbols for NOR Gate

X Y
1 3 2

X'Y' = (X + Y)'

(b) NOT-AND X Y
2 1 3

(X + Y)'

(a) OR-NOT

Implementation with NOR Gates

Examples:

1. F = (A + B)(C + D)E 2. F = (AB + AB)E(C + D)

A B C D E' A B C D E' A B C D E'

1 3 2 4 6 5 2 1 3

2 1 3 5 4 6 2 1

F = (A + B)(C + D)E
3

2 1 3 5 4 6 1 2 13

12

A B' A' B C D' E A B' A' B C D' E'

1 3 2 4 6 4 6 5 1 3 2 10 9 8 12 11 13 5

1 3 2 4 6 4 6 5 1 3 2 10 9 8 1 2 12 11 13 5

A B' A' B C D' E'

2 1 3 11 13 5 4 6 9 8 10 9 3 2 1 6 5 4 12 8 10

F = (AB + AB)E(C + D)

Seatwork 2-4 (30 minutes)

The following function is to be implemented with a minimum gate multilevel circuit (three or more levels of gates not counting inverters on the inputs or output). Assume the complements of the inputs are not available.
F(A,B,C,D) = ABCD + ABCD + ABCD + ABCD Use NAND gates only. Use NOR gates only.

Exclusive-OR Gates
XOR is a logical operation that performs the function F = X + Y = XY + XY Equal to 1 if exactly one variable is equal to 1.

Exclusive-OR Gates
XNOR is the complement of the XOR function. Expressed by the function F = X + Y = XY + XY Equal to 1 if both X and Y are equal to 1 or if both are equal to 0. Also known as the equivalence.

Exclusive-OR Gates
Identities:
X+0=X X+X=0 X+Y=X+Y X+1=X X+X=1 X+Y=X+Y

Properties:
Commutative Associative

Odd and Even Function

Odd function is a function that has a value of 1 if the number of 1s in the input is ODD.
Example: XOR

Even function is a function that has a value of 1 if the number of 1s in the input is EVEN.
Example: XNOR

Parity Generation and Checking

The circuit that generates the parity bit in the transmitter is called a parity generator. The circuit that checks the parity in the receiver is called a parity checker.

Truth table for an Even Parity Generator

X 0 0 0 0 1 1 1 1 Three-bit Message Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 Parity bit P 0 1 1 0 1 0 0 1

Boolean functions and logic diagram

X Y Z
1 3 2 1 3 2

P=X+Y+Z

X Y Z P

1 3 2 1 3 1 3 2 2

C=X+Y+Z+P

Seatwork 2-5 (30 minutes)

Construct a 3-bit odd parity generator and checker. Show the following:
Truth table Boolean functions Logic diagram

Integrated Circuits
Levels of Integration
1.

Small-scale integrated (SSI)

Number of gates is usually less than 10 Limited by the number of pins available on the IC

2.

Medium-scale integrated (MSI)

About 10 to 100 gates in a single package Usually performs elementary digital functions (addition)

Integrated Circuits
Levels of Integration
3.

Large-scale integrated (LSI)

Contains between 100 and a few thousand gates in a single package Examples: microprocessors, memory

4.

Very large-scale integrated (VLSI)

Contains several thousands to over 100 million gates in a single package Examples: microprocessors, DSP chips

Digital Logic Families

The circuit technology is referred to as a digital logic family. The primitive circuits in each technology are typically NAND, NOR, and NOT gates. The electronic components used in the construction of the basic circuit usually give the name of the technology.

Most Important Logic Families

RTL DTL TTL ECL MOS CMOS Resistor-transistor logic Diode-transistor logic Transistor-transistor logic Emitter-coupled logic Metal-oxide semiconductor Complementary metal-oxide semiconductor BiCMOS Bipolar complementary metal-oxide semiconductor GaAS Gallium-Arsenide

Most Important Logic Families

RTL and DTL
Earliest logic families obsolete

TTL
Widely used for decades Declining rapidly in use

ECL
Advantageous in systems requiring high-speed operation Rapidly overtaken by CMOS

MOS
For circuits that need high component density

Most Important Logic Families

CMOS
For systems requiring low power consumption Dominant technology

BiCMOS
Combines CMOS with a bit of TTL Used in cases in which CMOS cannot provide adequate current or the necessary speed

GaAS
Used selectively for very high speed circuits

Most Important Parameters

Fan-in specifies the number of inputs available on a gate. Fan-out specifies the number of standard loads that the output of a typical gate can drive without impairing its performance. Noise margin is the maximum external noise voltage superimposed on a normal input value that will not cause an undesirable change in the circuit output.

Most Important Parameters

Power dissipation is the power consumed by the gate and made available from the power supply. Propagation delay is the delay time for the change in value of a signal to propagate from input to output.

Propagation Delay Parameters

The high-to-low propagation time tPHL is the delay measured from the reference voltage on the input voltage IN to the reference voltage on the output voltage OUT, with the output voltage going from H to L. The low-to-high propagation time tPLH is the delay measured from the reference voltage on the input voltage IN to the reference voltage on the output voltage OUT, with the output voltage going from L to H.

Two Models Used During Simulation

Transport delay, the change in an output in response to the change of an input occurs after a specified propagation delay. Inertial delay, the change in an output in response to the change of an input also is delayed by a specified propagation delay. But if the input changes cause the output to change twice in an interval less than the rejection time, then the first of the two output changes does not occur.
The rejection time is a specified value no large than the time delay and is often equal to the time delay.

Quiz #2 Coverage
Simplification of Boolean functions
Boolean algebra Karnaugh map Tabulation method

Implementation of Boolean functions using only NAND or NOR gates