LOAD COMMUTATAED INVERTER

FOR INDUCED DRAFT (ID) FANS

M/S TANGEDCO- NORTH CHENNAI
NCTPS # 1 & 2
2X600 MW

OPERATION AND MAINTENANCE

MANUAL

VOLUME 2(Book2B) OF 4
(PCB DETAILS)

Book1A Book1B Book2A Book2B Book3 Book4

BHARAT HEAVY ELECTRICALS LIMITED

ELECTRONICS DIVISION
MYSORE ROAD, BANGALORE- 560 026

PDF processed with CutePDF evaluation edition www.CutePDF.com

 THIS OPERATION AND MAINTENANCE MANUAL CONSISTS OF 4 VOLUMES

VOLUME 1 : GENERAL DESCRIPTION AND CATALOGS (2 BOOKS)

VOLUME 2 : PCB DETAILS (2 BOOKS)

VOLUME 3 : DRAWINGS (1 BOOK)

VOLUME 4 : TEST REPORTS/ CERTIFICATES (1 BOOK)

THIS VOLUME CONSISTS OF TWO BOOKS :- BOOK - 2A AND BOOK - 2B.

- Cards should not be inserted or removed unless all

power has been removed from the panel.

ED660 XXXX YZZ

ZZ Minor revision code

Y Major revision code

Card Mnemonic

D= Daughter board
N= Analog
X= Transfer
H= Digital

-Examples of XXXX:
HPTF
HMPG
NLCB
NLIB
DLIB
HLCB
HRDA

- The maintenance philosophy of ED660 family of cards

requires trouble shooting to the card level and
problem corrected by card replacement.

CARD TO BE SENT TO SUPPLIERS WORKS FOR REPAIR.

DO NOT ATTEMPT TO TROUBLESHOOT THEM AT SITE.

 CONTENTS
--------

LIST OF CARDS/ DESCRIPTION

--------------------------
SERIAL NOS 1 TO 13 ARE IN VOLUME 2 - BOOK 2A.
SERIAL NOS 14 TO 41 ARE IN VOLUME 2 - BOOK 2B.

01. ED660LCGAA00 STRUCTURED LCI ELECTRONICS MODULE

02. ED660HMPGA00 CPU PCB

03. ED660DMPBA00 EEPROM DAUGHTER PCB

04. ED660HLCBA00 CONTROL INTERFACE PCB

05. ED660HAIAA00 A TO D INTERFACE PCB

06. ED660NSFCA00 SYSTEM FIRING PCB

07. ED660DSFCA00 DAUGHTER BOARD OF SYSTEM FIRING PCB

08. ED660NSFEA00 SYNCHRONOUS FIELD EXCITER PCB

09. ED660DSFEA00 DAUGHTER BOARD OF SYNCHRONOUS

FIELD EXCITER PCB

10. ED660NLCBA00 SIGNAL CONDITIONING PCB

11. ED660DLCBA00 DAUGHTER BOARD OF SIGNAL

CONDITIONING PCB

12. ED660NLIBA00 LOAD INVERTER PCB

13. ED660DLIBA00 DAUGHTER BOARD OF LOAD INVERTER PCB

14. ED660HISAA00 INPUT CONDITIONING PCB

15. ED660HRDAA00 RELAY DRIVER PCB

16. ED660XPENA00 SEM BACKPLANE PCB

17. ED660HNMBA00 NULL MODEM PCB

18. ED660IOMAA00 INPUT/OUTPUT MODULE

 -2-

CONTENTS (contd.)
----------------

19. ED660HROAA00 RELAY OUTPUT PCB IN IOMA

20. ED660HRIAA00 RELAY INPUT PCB IN IOMA

21. ED660XBPGA00 BACKPLANE PCB FOR IOMA

22. ED660XBPHA00 BACKPLANE PCB FOR IOMA

23. ED660DPSAA00 105 V POWER SUPPLY

24. ED660XTFXB00 DISPLAY MODULE DISTRIBUTION PCB

25. ED660NHVLA00 INTERFACE BOARD FOR FIELD EXCITER

26. CE68941CBB001 SYNCHRONOUS FIELD EXCITER MODULE

TYPE SFE

27. ED660XTFHA00 DISTRIBUTION BOARD FOR PULSES (MVB)

28. ED660NTDAA00 NEON INDICATOR PCB IN MVB THYRISTOR

POWER MODULE

29. ED660XPTNA00 ATTENUATOR PCB IN MVB THYRISTOR

POWER MODULE

30. ED660HPTKA00 FIRING CARD IN MVB THYRISTOR

POWER MODULE

-----x-------x-----
 DESCRIPTION

HIGH LEVEL 28V TO 5V

ATTENUATOR AND

BUFFER BOARD.

TITLE SHEET ED660 HlSA A00

OPERATING INSTRUCTIONS

1995 PAGE 1 OF 1

BHARAT H E A W ELECTRICALS LTD.,

ELECTRONICS DIVISION
-
*'MYSORE ROAD, BANGALORE 560 026
INDIA
1
ED 660 HlSA A00

SECTION 1

TABLE OF CONTENTS

SECTION DESCRIPTION

1. Table of contents

2. Description of Operation

3. Engineering Data

4. Elementary Diagram

5. PCB Layout

6. Material List

Page 1 of 1
 ED 660 HlSA A00

DEFlNlTlOEl AND FUNCTION

The ,ASA is a single sized @omplus PWB WWI is used as a high level (28 vdt) aftenuator
and ~ u f f e rboard within the Low Cost LC1 co&rol SEM. The HlSA is designed to indirectly
accent inputs from 105 volt logic when conditioned by two HRlAs used within the OS382010M
module. The major functions of the HlSA are :

3.3 channels of 28 volt level to 5 volt leuel attenuation.

Edfering of the inputs via 4 L-bus addressable bytes.

!?dication of the input levels by a 30 LB) bar graph display.

Two addressable 28 volt relay drivers w h i may be used in system or for test purposes.

an addressable IMOK LED.

Theory of Operation

Input Attenuation

All 39 inputs are conditioned by identical chatits which develop current through a n optical
isolztor when 30 volt levels are imposed at the respective inputs. The nominal current required
of these input signals is 4.5 mA. Current floving through the optical isolator LEDs turns their
o l l t ~ u transistors
t on. Silicon unilateral switches (SUS) in series with the attenuating resistors
provsde a 6 volt hysterisis. The minimum hi* level input voltage is 22 volts. The maximum
low ievel input voltage is 11 volts. The outputs of the optical isolators are feed to buffering
circuits for data bus multiplexing.

LED Annunciation

Eac? of the 30 inputs is annunciated by a single green LED within the LED bar display at
the front edge of the HISA. 28 volt level at the input of. any attenuator circuit will cause
its LED to be iifl~minated.This feature will not function without dc power being
app.ied to the HISA.

L - E u s Buffering

For the purpose of reading the status of the input levels, the 30 attenuator circuits are divided
intc four 8-bit bytes, Each of these bytes, which contain the status information for eight of
the attenuator circuits, may be multiplexed on tothe data bus by proper control signal manipulation.
71.; following table describes the logic required to read each of the four input bytes :

Page 1 of 6
 i
I -.
ED 660 HlSA A00

SECTION 2

CONTROL INPUTS DATA BUS

1 BLCRST OCS OBLA2 OBLAl ORD

0 0 1 1 0 107-100

0 0 1 0 0 IOF-108

0 0 0 1 0 117-110

0 0 0 . 0 0 110-118

I
0 1 X X X HI-Z

0 X X 1 HI-Z

1 X X X HI-Z

Note, tllat in the above table, the address lines that the HISA receives are inverted. The table
shows actual 1-true status.

The HISA requires external address decoding to decode high order address bit into a singal
chip select. This function will be performed by the DS3800HLCB in the LC1 system.

The HlSA will accept end latch three bits of information from the L-bus. The three bits affect
the IMOK LED status an6 the states of hvo relay drivers on the HISA. These bits may be
written to the HlSA via the L-bus at the high nibble (4-bits) of the most significant HlSA address
byte. The following table relates the bits that may be written to their function :

Bit Function Logical 1

7 TSTHl relay turns driver on (PA46)

6 TSTLO relay turris driver on (PA44)

5 not used

4 IMOl< LEE turns iMOK LED on

-

Azd.e:s bits 2 and 1 are both asserted (OBLA2 = 0. OBIA; = 0) for this output address.

Page 2 of 6
 ED 660 HlSA A00

SECTION 2

28 Volt Relay Drivers

Two relay drivers are provided on the HlSA to force all inputs high and low for the purpose
of testing. These drivers are driven by latched inputs from the data bus. Each driver is capable
of driving loads of up to 200mA. Open circuit voltages seen by the driver circuits must not
exceed 28 volts, because an internal flyback diode (to P28) is provided.

The status of the two relay drivers may be changed by writing to the most significant byte
of the HISA. The bit associated with the TSTHl relay driver is bit 7 (most significant). The
bit associated with the TSTLO relay driver is bit 6. Writing a logical 1 to these bit locations
will set the given driver b the on state and force the corresponding output to b e pulled to
the PCOM level. Writing a logical 0 to these locations will reset the given driver to the off
state, allowing the output to float. ResetingIhe HlSA via 1BLCRST (PA06) will reset the drivers
to the off state. Holding the OPAR (PA42) at a logical 0 will disable both of the relay drivers
but will not reset their latch.

IMOK LED
The IMOK LED is accessed just like the bwo relay drivers. Writing a logical 1 to bit 4 of the
high order byte of the HlSA forces the IMOK LED on the front edge of the PWB to become
illuminated. Writing a logical 0 will force he LED to be extinguished. Reseting the HlSA will
extinguish the IMOK LED.

~ ~ J ~ l i c a tData
lon .

There are no burg jumpers, pots, or variable components associated with the HISA. The only
system level variable is the address decoding which is accomplished externally.

Page 3 of 6
SECTION 2

Signal Interface
1

SIGNAL PINOUT INIOUT DESCRIPTION

-
1BLCRST PAOG In I-True.L-BUS Reset

OCS PA08 In 0-True Card Select

OWRD PA02 In 0-True Delayed Write

ORDD PA04 In 0-True Delayed Read

OBlA2 PAGO . In 0-True Address bit 2

i
OBlA1 PASS In 0-True Address bit 1 I
- 3PAR PA42 In 0-True Power Applied Reset II
I1D

I1C
PA38

PA37
In

In
II Attenuated Input I D (HEX)

Attenuated Input 1C (HEX) 1

.11B PAY4 In Attenuated Input 1B (HEX) !
I I1A PA33 In 1 Attenuated Input 1A (HEX)
I
I
i
!
119 Pf-30 in I Attenuated Input 19 (HEX) I
I I I
!
118 PAZY In j kitenuated Input 18 (HEX)
i Ii
117 I p ~ z ~ 111 ! Attenuated Input 17 (HEX) I
! I
. 116 PA25 1 111 ij Atterluated Input 16 ( H U ) I
115
I
FA22 In
I
!! Attenuated Input 15 (HEX) i
114 PA2i I ill
I
i
!I Atienuated Input 14 (HE%)

!
113 PA 1 6
I
1 In 1 Attenuated Input 13 (HEX)
j
112 j Pili i
I
!
111
I

i
i
A:Ir?nuated Inpt~t12 (HEX) i
I
111 PA?4 In
I Attenuated Input 11 (HEX)

.In Attenuated Input 10 (HUC)

In Attenuated Input OF (HEX)

Page 1 of G
 SIGNAL PINOUT IN/OUT DESCRIPTION

IOE PA50 111 Attenuated Input OE (HEX)

IOD PA52 In Attenuated Input OD (HEX)

IOC PA53 In Attenuated Input OC (HEX)

106 PA54 In Attenuated Input 0% (HEX)

IOA PA55 In Attenuated Input OA (HEX)

109 PA57 In Attenuated Input 09 (HEX)

108 PA58 In Attenuated Input 08 (HEX)

I
107 PA59 In Attenuated Input 07 (HEX)

106 PA62 In Attenuated Input 06 (HEX)

105 PA63 In Attenuated Input 05 (HEX)

104 PA65 In Attenuated Input 04 (HEX)

103 PA67 , In Attenuated Input 03 (HEX)

102 PA69 In Attenuated Input CM (HEX)

101 PA7 1 In Attenuated Input (31 (HEX)

100 PA73 In Attenuated Input 00 (HEX)

OBLD7 PA73 Bidir 0-True data bit 7

'.1
'
OBLD6 PA72 B~dir 0-True' data bit 6

OBLDS PA61 Bidir 0-True data bit 5

OBLD4 PA76 Bidir 0-True data bit 4

OBLD3 PA64 B~dir 0-True data bit 3

I 1
OSLO; PA74 B~dir 0-True data bit 2

OBLDl PA66 Bid~r 0-True data bit 1

-

Page 5 of 6
--

SIC. . ~ A L PINOUT INIOUT DESCRIPTION

OBLDO PA68 Bidir 0-True data bit 0

XCOM FA80 Power Isolated Common a

PCOM PA41 Power P28 Common

Page 6 of 6
 ED 660 HlSA A00

SECTION 3

ENGlNEERlNG DATA .

This section contains engineering application information for the ED660HISAA00

Ratings

The HISA's inputs are rated at 28 volts nominal. The maximum threshold for a logical 1 is
21 volts. The minimum threshold for a logical 0 is 10 volts. The load presented by the HlSA
ta a 28 volt level is 4.5 mA.

The relay drivers of the HlSA u e capabk of driving 100 mA loads.

Power Supply Requirements

The HlSA requires P5 and P28 power suppiies for correct operation. The P28 supply is used
only to suppress transients in the test relay driver circuit. No current is drawn from the P28
supply in the steady-state condition.

The P5 power requirements of the HlSA are 500mA typical, and 991mA worst case.

l i m i n g considerations

The HlSA is designed to function with standard L-bus timing with address decoding accomplished
b y HLCB.

Page 1 of 1
 .................... 1
I
HISA I
I
I
I
I
I
LOGIC I
I
ORDD I
I
I
I

ADDRESS
08LA1 DECODE SU1
SELO
!
I I
A21
-. OPAR I
I
I
I TST HI 1 48
I SEW I .

----El
-2
'
--J
'
I j:
e0~i
21 1

1'7
112
.

--
SOLATORS

RLTERS
7 / 8 1
8 BIT
BUFFER
1 ,/8j OBLD3184

OBLD2 74

--- 1.----
-- - 14
-- J3
l I--

48
I
f
::A bL2 1
IOD

IOF I
v

/
D l i 6
OBLDO 1 68
8

----- I
I
J 50 '
IOE
I
52 I IOD
I
omo
1
1
53 /8 / I
I

;
IOC
SOLATORS
/8 8 BTT - ' I
51 108 / 1
BUFFER I
55 1 I OA I
I
I
I I
I
I
I

SOIATOKS
BUFfER
F1L K R S
1- SELO
.. --L@A--
100
(30 XCOlr(
+
4i I PCOM I
-- 4--. - I

- *--- -- --- --- -- --

-- DQN*--_-----
REV, 00 FIRST ISSUE 'TO -
660 IIiISA
~u uou I I ~ AA00
-
L
dwPw I
.BLOCU DIAGRAM
1 REV.
REV, ' 01 --
--
-
-
l-zL__--
CHD,
CHD -- SECTION
SECTION 4..
4.. ?JJNT, ON SH,
-
--- I APDt
APDt PAGE I
PAGE OF 7
I OF 7
6
PCOM

PCOM
 P5

PAGG

5
2.1 K ) (IH:b)
4
P5
P5

DCOM

9 8

107f3 14100

105 15
- 18 106
z
19
9 4BLD4/

PB

5 4

+.
102
.- . -----
5
-' CRN4

! P5
4
6
-18
103 17

L
18 102

'
17
15
'' ,
3

m -7.. <)Bu)l
(C60)
D
OBDS /
OBLD~ /

8 11 9 OBLDO /
z z
1 19

R3 1
101 19 20 100
! ?.22K 8.2" 1

. :. ,;: !
, .-.,
. .,..>,.?!
't:-'

/ 6.01 uf
I

i- -
i
.b -.- -- DCOM
DCOM
1
I P5
CRQ
P5 P5

[W40T] -
OItDL _I

XCOhf
.. e--.-,
-----il DCOM
[~CA~BC]
REV, 01 CHD, SECTION 4
aBHEL EDN I ISOLATED INPUT BOARD I
REV, 02 APD, PAGE 4 OF 7 4CA I
 NMENTARY
--- DIACWU(
ED 660 HlSA A00
REV, 00 flRST ISSUE
REV. 151-7 DRNl BHEL EDN I
rnkl ISOUTED INPUT BOARD
ISOUTED INPUT BOARD
REV, 01 CHDl SECTION 4 N,.LL!BANGALORE' C ~ N T *ON SH* SHiNU,
REV, 02 APDi PAGE 5 OF 7 4EA 4Dk .
REV, 00 FIRST ISSUE DRN, ED 660 HlSA A00
BHEL EDN
ELEMEMTARY
ISOLATED INPUT BOARD '
*
CHD* SECTION 4
ANGALORE CONTI ON SH 4FA [\";AB'
 P5 P5
PA77 4

C2 -- C3 C4 C5 C8 C7 CB C9
(AJO) /- (A60)
0.47uf 0.47uf 0.luf 0.1uf 0.luf 0.1 uf 0.1 uf
PA1 4 DCOM -- OCOM

P5 : PIN 20 OF US-13
PIN 18 OF U3-4
PIN 14 OF U1-2

DCOM: PIN 10 OF U5-13

PIN 8 OF U3-4
PIN 7 OF U1-2

6
PCOM

SPARES

REV, 00 FIRST ISSUE I DRN.

- . .-
1 ED 660 HlSA A00
----.-.. .
I ELEMENTARY DUGRAM
aBHEL EDN 1 ISOLATED 28V INPUT BOARD
REV, 01 CHD, SECllON 4
nurial n n ~ k ON. SH.
REV, 02 APD, PAGE 7 OF 7
, I 4GA I 4FA
 I I I
I I,
SOCKET
CRNO SOCKET SOCKEi
 ED 660 HISA A00

SECTION 6

MATERIAL LIST

POSN DESCRIPTION ADDITIONAL INFO MATERIAL CODE QUANTITY

CN906840 1064 2.00

2 LED HOLDER ED7469 115951 1.00

MC-01-1

4 SOC LED
DL320-31TG

6 RES MTL FLM

0.6W 1OK

7 DIODE ZEN 8.2V

0.4W

8 DIODE RECTIFIER
A14P

9 LED DISPLY
1OSEGMENT
GRN MV54164

10 DIODE IN457A

11 ,LEDYEL

12 CAP ELECT TANT

22MF

13 CAP CERAMIC
0.47MF

Page 1 of 3
SECTION 6

POSN DESCRIPTION ADDITIONAL INFO MATERIAL CODE Quantity

14 CAP CERAMIC
0.1 MF

15 CAP CERAMIC C12, C13, C14, C15, CN9061560578 $0.00

1ONF C16, C17, C18, C19,
C20, C21, C22, C23,
C24, C25, C26, C27,
C28, C29, C30, C31,
C32, C33, C34, C35,
C36, '237, C38, C39,
C40, C41

16 CAP ELECT AL
10MF

17 HSG ASSY DOUBLE PA

ROW IN LINES
533002-1

18 THYRTR2N4987 Q l , Q2, Q3, Q4, CN9066257C16 30.00

Q5, Q6, Q7, Q8,
Q9, QlO, Q l l , Q12,
(213, Q14, (215, (216,
, Q17, (218, Q19, Q20,
Q21, (222, Q23, (224,
Q25

19 TRANSlSTORlRFD Q61, Q62 CN90663924011 2.00

120 POWER
MOSFET

20 RES THK FLM 0.19W RN2, RN5, RN6, CN9066564369 6.00

1OK RN4, RN3, RN1 altCN9066565365

21 RES THK FLM 0.19W RN7, RN10, RN9, CN9066564148 4.00

270R RN8

22 RES MTL FLM 22.1 K R l , R2, R3, R4, R5, CN9060231279 30.00
0.25W R6, R7, R8, R9, R10,
R11, R12, R13, R14,
R15, R17, Ri8, R19,
R20, R21, R22, R23,
R24, R25, R26, R27,
R28, R29, R30

23 RES MTL FLM 0.6W R31, R32, R33, CN9060187083 8.00

1OOR R34, R35, R36, altCN9060186087
R37, R38,

Page 2 of 3
 E D 660 HISA A00

SECTION 6

POSN DESCRIPTION ADDITIONAL INFO MATERIAL CODE QUANTI'N

24 RES MTL FLM 3.92K

0.25W

RES MTL FLM 392H

0.25W

RES MTL FLM 0.6W

1K

IC DGTL
SN74LSOON

IC DGTL
SN74LS 175N

IC DGTL
SN74LS244N

OPTOCOUPLER
H I 1AX-926

TYPE LABEL 369958021 121T19 1.OO

XB

Page 3 of 3