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  • Activity One: Basic Gates: No Name Id Section 1 2 3 4 5 6 7 8

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    This document is a laboratory report from Addis Ababa Science and Technology University that describes three activities involving digital logic gates. The first activity tests basic logic gates like NOT, AND, and OR gates. The second activity examines derived gates like NAND, NOR, XOR, and XNOR. The third activity shows how to create NOT, AND, and OR gates using only NAND gates. Tables of input-output results are provided for each logic gate with discussions of findings.

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    This document is a laboratory report from Addis Ababa Science and Technology University that describes three activities involving digital logic gates. The first activity tests basic logic gates like NOT, AND, and OR gates. The second activity examines derived gates like NAND, NOR, XOR, and XNOR. The third activity shows how to create NOT, AND, and OR gates using only NAND gates. Tables of input-output results are provided for each logic gate with discussions of findings.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    8 views4 pages

    Activity One: Basic Gates: No Name Id Section 1 2 3 4 5 6 7 8

    Uploaded by

    joy
    This document is a laboratory report from Addis Ababa Science and Technology University that describes three activities involving digital logic gates. The first activity tests basic logic gates like NOT, AND, and OR gates. The second activity examines derived gates like NAND, NOR, XOR, and XNOR. The third activity shows how to create NOT, AND, and OR gates using only NAND gates. Tables of input-output results are provided for each logic gate with discussions of findings.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 4

    Addis Ababa Science and Technology University

    College of Electrical and Mechanical Engineering


    Department of Software Engineering
    Digital Logic Design Laboratory Report 1

    No Name Id Section
    1
    2
    3
    4
    5
    6
    7
    8

    Activity One: Basic gates


    1- NOT gates
    Results: Discuss
    Input Output
    0/LOW/FALSE/
    1/HIGH/TRUE/

    2- AND gates
    Results:
    INPUT 1 INPUT 2 OUTPUT Discuss
    0 0
    0 1
    1 0
    1 1

    3- OR gates
    Results:
    INPUT 1 INPUT 2 OUTPUT Discuss
    0 0
    0 1
    1 0
    1 1

    July 28, 2022 1


    Addis Ababa Science and Technology University
    College of Electrical and Mechanical Engineering
    Department of Software Engineering
    Digital Logic Design Laboratory Report 1

    Activity Two: Derived gates


    1- NAND
    Results:
    INPUT 1 INPUT 2 OUTPUT Discuss
    0 0
    0 1
    1 0
    1 1

    2- NOR
    Results:
    INPUT 1 INPUT 2 OUTPUT Discuss
    0 0
    0 1
    1 0
    1 1

    3- X-OR
    Results:
    INPUT 1 INPUT 2 OUTPUT Discuss
    0 0
    0 1
    1 0
    1 1

    4- X-NOR
    Results:
    INPUT 1 INPUT 2 OUTPUT Discuss
    0 0
    0 1
    1 0
    1 1

    July 28, 2022 2


    Addis Ababa Science and Technology University
    College of Electrical and Mechanical Engineering
    Department of Software Engineering
    Digital Logic Design Laboratory Report 1

    Activity Three: Universal Gates- NAND


    1- NOT gate:

    Design Results and Discussion


    Input Output
    0/LOW/FALSE/
    1/HIGH/TRUE/

    2- AND Gate

    Design Results and Discussion


    INPUT 1 INPUT 2 OUTPUT
    0 0
    0 1
    1 0
    1 1

    3- OR Gate:

    Design Results and Discussion


    INPUT 1 INPUT 2 OUTPUT

    0 0
    0 1
    1 0
    1 1

    July 28, 2022 3


    Addis Ababa Science and Technology University
    College of Electrical and Mechanical Engineering
    Department of Software Engineering
    Digital Logic Design Laboratory Report 1

    July 28, 2022 4

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