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■ HIGH SPEED :
fMAX = 67MHz (TYP.) at VCC = 6V
■ LOW POWER DISSIPATION:
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CC =2µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
VNIH = V NIL = 28 % VCC (MIN.)
■ SYMMETRICAL OUTPUT IMPEDANCE: DIP SOP TSSOP
|IOH| = IOL = 4mA (MIN)
■ BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL ORDER CODES
■ WIDE OPERATING VOLTAGE RANGE: PACKAGE TUBE T&R
VCC (OPR) = 2V to 6V
DIP M74HC76B1R
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 76 SOP M74HC76M1R M74HC76RM13TR
TSSOP M74HC76TTR
DESCRIPTION
The M74HC76 is an high speed CMOS DUAL J-K and PRESET (PR) are independent of the clock
FLIP FLOP WITH CLEAR fabricated with silicon and are accomplished by a logic low on the
gate C2MOS technology. corresponding input.
Depending on with the logic level at J and K All inputs are equipped with protection circuits
inputs, this device changes state on the negative against static discharge and transient excess
going transition of clock pulse (CK). CLEAR (CLR) voltage.
TRUTH TABLE
INPUTS OUTPUTS
FUNCTION
CLR PR J K CK Q Q
L H X X X L H CLEAR
H L X X X H L PRESET
L L X X X H H ----
H H L L Qn Qn NO CHANGE
H H L H L H ----
H H H L H L ----
H H H H Qn Qn TOGGLE
H H X X Qn Qn NO CHANGE
X : Don’t Care
LOGIC DIAGRAM
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M74HC76
3/11
M74HC76
DC SPECIFICATIONS
4/11
M74HC76
CAPACITIVE CHARACTERISTICS
5/11
M74HC76
TEST CIRCUIT
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6/11
M74HC76
WAVEFORM 3 : PROPAGATION DELAY, MINIMUM PULSE WIDTH, SETUP AND HOLD TIME
(f=1MHz; 50% duty cycle)
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WAVEFORM 4 : MINIMUM PULSE WIDTH, PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
7/11
M74HC76
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
a1 0.51 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
P001C
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M74HC76
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064
PO13H
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M74HC76
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 1.2 0.047
K 0° 8° 0° 8°
A A2
K L
A1 b e
c E
E1
PIN 1 IDENTIFICATION
1
0080338D
10/11
M74HC76
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