SN54/74LS166

8-BIT SHIFT REGISTERS

The SN54L/ 74LS166 is an 8-Bit Shift Register. Designed with all inputs
buffered, the drive requirements are lowered to one 54 / 74LS standard load.
By utilizing input clamping diodes, switching transients are minimized and
system design simplified.
The LS166 is a parallel-in or serial-in, serial-out shift register and has a 8-BIT SHIFT REGISTERS
complexity of 77 equivalent gates with gated clock inputs and an overriding
clear input. The shift/load input establishes the parallel-in or serial-in mode. LOW POWER SCHOTTKY
When high, this input enables the serial data input and couples the eight
flip-flops for serial shifting with each clock pulse. Synchronous loading occurs
on the next clock pulse when this is low and the parallel data inputs are
enabled. Serial data flow is inhibited during parallel loading. Clocking is done
on the low-to-high level edge of the clock pulse via a two input positive NOR
gate, which permits one input to be used as a clock enable or clock inhibit J SUFFIX
function. Clocking is inhibited when either of the clock inputs are held high, CERAMIC
holding either input low enables the other clock input. This will allow the CASE 620-09
system clock to be free running and the register stopped on command with 16
1
the other clock input. A change from low-to-high on the clock inhibit input
should only be done when the clock input is high. A buffered direct clear input
overrides all other inputs, including the clock, and sets all flip-flops to zero.
• Synchronous Load N SUFFIX
• Direct Overriding Clear PLASTIC
• Parallel to Serial Conversion 16 CASE 648-08
1
PARALLEL PARALLEL INPUTS
SHIFT/ INPUT OUTPUT
VCC LOAD H QH G F E CLEAR D SUFFIX
16 15 14 13 12 11 10 9 SOIC
16
1 CASE 751B-03
SHIFT/ H QH G F E
LOAD
SERIAL INPUT CLEAR ORDERING INFORMATION
CLOCK
A B C D INHIBIT CK SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
1 2 3 4 5 6 7 8 SN74LSXXXD SOIC
SERIAL A B C D CLOCK CLOCK GND
INPUT INHIBIT
PARALLEL INPUTS

FUNCTION TABLE
INPUTS INTERNAL
OUTPUTS OUTPUT
SHIFT/ CLOCK PARALLEL
CLEAR CLOCK SERIAL QH
LOAD INHIBIT A...H QA QB
L X X X X X L L L
H X L L X X QA0 QB0 QH0
H L L ↑ X a...h a b h
H H L ↑ H X H QAn QGn
H H L ↑ L X L QAn QGn
H X H ↑ X X QA0 QB0 QH0

FAST AND LS TTL DATA

5-1
 SN54/74LS166

Typical Clear, Shift, Load, Inhibit, and Shift Sequences

CLOCK

CLOCK INIHIBIT
CLEAR
SERIAL INPUT
SHIFT/LOAD
A H
B L
C H
PARALLEL D L
INPUTS
E H
L
F
G H
H H
OUTPUT QH H H L H L H L H
INHIBIT
SERIAL SHIFT SERIAL SHIFT
CLEAR LOAD
(9)
CLEAR
(1)
SERIAL INPUT
(15)
SHIFT/LOAD
(2)
A
R S
CK
QA
(3)
B

R S
CK
QB
(4)
C
R S
CK
QC
(5)
D
R S
CK
QD
(10)
E
R S
CK
QE
(11)
F
R S
CK
QF
(12)
G
R S
CK
QG
(14)
H
(7) R S
CLOCK CK
(6) (13) Q
CLOCK INHIBIT H

FAST AND LS TTL DATA

5-2
 SN54/74LS166

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High 54, 74 – 0.4 mA
IOL Output Current — Low 54 4.0 mA
74 8.0

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
54 0.7 Guaranteed Input
p LOW Voltage
g for
VIL Input LOW Voltage V
74 0.8 All Inputs

VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VOL Output LOW Voltage VIN = VIL or VIH
74 0.35 0.5 V IOL = 8.0 mA per Truth Table

20 µA VCC = MAX, VIN = 2.7 V

IIH Input HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX
ICC Power Supply Current 38 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

5-3
 SN54/74LS166

TEST TABLE FOR SYNCHRONOUS INPUTS

DATA INPUT
SHIFT/LOAD OUTPUT TESTED
FOR TEST
H 0V QH at tn+1
Serial
4.5 V QH at tn+8
Input

AC WAVEFORMS

tw(clear)
3V
CLEAR INPUT Vref Vref
0V
tn + 1 (SEE NOTE 1) tn + 1
tn tn
3V
CLOCK INPUT Vref Vref Vref Vref
th 0V
tsu
tw(clock) th tsu
3V
DATA Vref Vref Vref
INPUT
(SEE TEST 0V
TABLE)
tPHL tPHL
(clear-Q) tPLH (CLK-Q)
(CLK-Q) VOH
Vref Vref Vref
OUTPUT Q
VOL

NOTE 1. tn = bit time before clocking transition

NOTE 1. tn+1 = bit time after one clocking transition
NOTE 1. tn+8 = bit time after eight clocking transition
NOTE 1. LS166 Vref = 1.3 V.

AC CHARACTERISTICS (TA = 25°C)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C di i
Conditions
fMAX Maximum Clock Frequency 25 35 MHz
tPHL Clear to Output 19 30 ns VCC = 5.0
50V
CL = 15 pF
tPLH 23 35
Clock to Output ns
tPHL 24 35

AC SETUP REQUIREMENTS (TA = 25°C)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
tW Clock Clear Pulse Width 30 ns
ts Mode Control Setup Time 30 ns
VCC = 5
5.0
0V
ts Data Setup Time 20 ns
th Hold Time, Any Input 15 ns

FAST AND LS TTL DATA

5-4