DLP Handout

8/16/22, 7:24 AM
K L Deemed to be University
Department of Computer Science and Engineering-Honors -- KLVZA
Course Handout
2022-2023, Odd Sem
Course Title :DIGITAL LOGIC AND PROCESSORS
Course Code :22EC1101
L-T-P-S Structure : 3-0-2-0
Pre-requisite :
Credits :4
Course Coordinator :SIDDAIAH NALLURI
Team of Instructors :
Teaching Associates :
Syllabus ::CO-1: Design of Processor Modules: Structure of Computer, Microprocessor as programmable
Logic Device, Microcomputer organization, Digital hardware: logic gates and flip-flops, Arithmetic and
Logic Unit functions. Design of Data Processing and Logic Modules: Modeling and design of code
converter, Parity circuits, Encoder / Decoder, Multiplexer / Demultiplexer. CO-2: Design of Memory and
Timing & Control Modules: Modelling of memory and registers using flip-flops, Timing and sequence
control modules using Asynchronous/Synchronous counters, Ring and Johnson counter as timing and
control units. CO-3: Design of Programmable and Reprogrammable Logic Modules: Implementation of
PROM, PLA, PAL, CPLD (Macrocells) and FPGA (CLB) based digital logic modules and their
applications. Verilog HDL implementation for Digital Logic Circuits. CO-4: Design of Optimized Logic
Modules: Boolean laws based optimization; K-Map based optimization, Local and Global Logic and Circuit
optimization techniques, Programmable Logic Device optimization, state diagram based optimization.
Text Books ::1. Stephen Brown, Zvonko Vranesic “Fundamentals of Digital Logic with Verilog Design”
McGraw-Hill., 2nd Edition- 2004. 2. M. Morris Mano, “Digital Logic and Computer Design”, Pearson
publication, 5th Edition – 2013. 3. Ronald J. Tocci, Neal S. Widmer, Gregory L. Moss, “Digital
SystemsPrinciples and Applications”, Prentice Hall, 10th edition-2014. 4. Robert K. Dueck, “Digital
Design with CPLD Applications and VHDL” Delmar Cengage Learning, 2nd Edition-2004
Reference Books :1. Ramesh Gaonkar Penram, “Microprocessor Architecture, Programming and
Applications with 8085” International Publishing, , 5th edition-2009.
2. R.P. Jain, “Modern digital
Electronics”, Tata McGraw Hill, 4th edition-2009. 3. Brain Holdsworth, Clive Woods, “Digital Logic
Design”, Newnes 4th edition-2007.
4. J. Bhasker, “A Verilog HDL Primer”, BS Publications 3rd
edition2013. 5. A Anand Kumar, “Digital Fundamentals”, PHI publication, 4th edition-2016.
6. Digital
Principles and Logic Design by ArijitSaha and Nilotpal Manna Jones & Bartlett Publishers 1st edition-
2007.
7.Microprocessors and interfacing programming and hardware by Douglas V Hall, Tata McGraw Hill
Education Private Limited, 2nd edition-2005.
Web Links :1. https://onlinecourses.nptel.ac.in/noc18_ee33/preview 2. https://www.youtube.com/watch?
v=M3NqOSUZ6VE 3. https://www.youtube.com/watch?v=GQCaMM8m0F0
4.https://www.youtube.com/watch?v=NqX3iE2QYuM 5. https://www.youtube.com/watch?v=blPxcTf4T5Y
6. https://www.youtube.com/watch?v=3ZYJiCcXI70
7.https://drive.google.com/file/d/1lpksgYbRX2kD7LXLk62B-LSnd8tSXz2k/view
8.https://www.youtube.com/watch?v=qqeRUgAvmzQ 9. https://www.youtube.com/watch?v=o1-hj6GKaFY
10. https://www.youtube.com/watch?v=2gI3aC5blfA
COURSE OUTCOMES (COs):
CO Course Outcome (CO) PO/PSO Blooms

NO Taxonomy
1/30
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Level
(BTL)
Understand the structure of a digital computer and design
CO1 combinational circuits for processor using the principles of PO1,PO3 2
Boolean Algebra and gates.
Analyze the operation of latch/flip-flop and design timing and
CO2 PO3,PO2 4
sequence control circuits using flip-flops
Apply the programmable logic and design digital circuits using
CO3 PO1,PO3 3
Programmable logic devices.
Apply the minimization techniques and Construct optimized
CO4 PO1,PO3 3
combinational and sequential logic circuits.
Design of combinational and sequential circuits with logic gates
CO5 PO3,PO5 4
and flip-flops with verification using Verilog HDL tool
COURSE OUTCOME INDICATORS (COIs)::
Outcome Highest
COI-1 COI-2 COI-3 COI-4
No. BTL
Btl-2 Btl-2

Understand the
Understand the
fundamental operation of
CO1 2
hardware and digital combinational logic
blocks of general- modules for
purpose processor processor design
Btl-2

Btl-3 Btl-3
Understand the Btl-4
Apply
the concept of Apply
the concept
the
processor memory Analyze
CO2 4 the sequential logic of sequential logic
cells and timing & operation of Digital
modules for registers modules for control
control units logic Sequential Modules
operation units operation
functions
Btl-2

Btl-3
Understand and Btl-3
Apply
the concept of
the Verilog
construct the Develop
PLD in the design of
CO3 3 Programmable and HDL code for
CPLD(Macrocell)/
Reprogrammable Digital Logic
FPGA(CLB) based
(PLDs/LUT) digital Modules
logic modules
logic cell design
Btl-3
Btl-2 Btl-3

Apply
the optimized
Understand Boolean Apply
K-map
CO4 3 logic methods in
laws and its optimization in
optimization of
Optimization digital design
digital logic circuits
Btl-4

and analysis
Design
CO5 4 of combinational
and sequential logic
circuits
PROGRAM OUTCOMES & PROGRAM SPECIFIC OUTCOMES (POs/PSOs)
Po
Program Outcome
No.
PO1 Engineering Knowledge:Apply the knowledge of mathematics, science, engineering fundamentals,
2/30
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and an engineering specialization to the solution of complex engineering problems.

Problem Analysis: Identify, formulate, review research literature, and analyse complex engineering
PO2 problems reaching substantiated conclusions using first principles of mathematics, natural sciences
and engineering sciences
Design/Development of Solutions: Design solutions for complex engineering problems and design
PO3 system components or processes that meet the specified needs with appropriate consideration for the
public health and safety, and the cultural, societal, and environmental considerations
Conduct Investigations of Complex Problems:Use research-based knowledge and research methods
including design of experiments, analysis and interpretation of data, and synthesis of the information
PO4
to provide valid conclusions for complex problems that cannot be solved by straightforward
application of knowledge, theories and techniques applicable to the engineering discipline.
Modern Tool Usage:Create, select, and apply appropriate techniques, resources, and modern
PO5 engineering and IT tools including prediction and modelling to complex engineering activities with
an understanding of the limitations.
The Engineer and Society:Apply reasoning informed by the contextual knowledge to assess societal,
PO6 health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
Environment and Sustainability:Understand the impact of the professional engineering solutions in
PO7 societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable
development
Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of
PO8
the engineering practice
Individual and Team Work: Function effectively as an individual, and as a member or leader in
PO9
diverse teams, and in multidisciplinary settings.
Communication:Communicate effectively on complex engineering activities with the engineering
PO10 community and with society at large, such as, being able to comprehend and write effective reports
and design documentation, make effective presentations, and give and receive clear instructions
Project Management and Finance: Demonstrate knowledge and understanding of the engineering
PO11 and management principles and apply these to one’s own work, as a member and leader in a team, to
manage projects and in multidisciplinary environments.
Life-long Learning: Recognize the need for, and have the preparation and ability to engage in
PO12
independent and lifelong learning in the broadest context of technological change.
PSO1 An ability to design and develop software projects as well as Analyze and test user requirements.
PSO2 An Ability to gain working Knowledge on emerging software tools and technologies.
Lecture Course DELIVERY Plan:

Book Teaching-
Sess.No. CO COI Topic No[CH No] Learning EvaluationComponents
[Page No] Methods
Course Handout / Outline

the Structure of Computer, T1, Ch:1.3
COI- End Semester
1 CO1 Microprocessor as pp.8-15 R1, Chalk,PPT,Talk
1 Exam,SEM-EXAM1
programmable Logic Ch:1.1 pp.4-
Device.
R1, Ch:1.1
Outline the Microcomputer
COI- pp.8-10 End Semester
2 CO1 organization and Digital Chalk,PPT,Talk
1 Ch:2.1 Exam,SEM-EXAM1
Hardware: logic gates
pp.36-31
COI- T2, Ch:9 End Semester

3 CO1 Digital Hardware: flip-flops Chalk,PPT,Talk
1 pp.367-381 Exam,SEM-EXAM1
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Book Teaching-
[Page No] Methods
COI- concepts of ALU: T2, Ch:9 End Semester

4 CO1 Chalk,PPT,Talk
1 Arithmetic functions pp.367-375 Exam,SEM-EXAM1
COI- T-2 pp.376- ALM,End Semester

5 CO1 ALU :Logic Functions Chalk,PPT,Talk
1 381 Exam,SEM-EXAM1
COI- R6, Ch:3 End Semester

6 CO1 Digital Codes Chalk,PPT,Talk
COI- Data Transmission process R6, Ch:7 End Semester

2 with parity pp.390-395 Exam,SEM-EXAM1
COI- Parity Based Logic Control R6, Ch:7 End Semester

2 modules pp.396-40 Exam,SEM-EXAM1
Develop the Encoder

9 CO1 Decoder; Multiplexer and Chalk,PPT,Talk
Demultiplexer
ALM,End Semester
COI- Encoder and Decoder based R6, Ch:7
10 CO1 Chalk,PPT,Talk Exam,HA,SEM-
2 Logic Control modules pp.380-388
EXAM1
Understand the Flip-flop as

COI- T2, Ch:6.1 End Semester
11 CO2 a Memory and timing Chalk,PPT,Talk
control Unit

12 CO2 Memory Units: Flipflops Chalk,PPT,Talk
COI- Understanding shift T2, Ch:7.2 End Semester

2 modules concept pp.260-263 Exam,SEM-EXAM1
Design of Asynchronous
COI- R6, Ch:12.9 End Semester
14 CO2 &Timing and Control Chalk,PPT,Talk
modules
COI- Design of Synchronous T3, Ch:7.5 ALM,End Semester

3 Timing Control modules pp.280-285 Exam,SEM-EXAM1

16 CO2 Design of Control modules Chalk,PPT,Talk
Design of Asynchronous
17 CO2 Timing and Control Chalk,PPT,Talk
modules
COI- Design of State based R6, Ch:12 End Semester

4 Timing Modules pp.631-660 Exam,SEM-EXAM1
4/30
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Book Teaching-
[Page No] Methods
COI- Design of State based R6, Ch:12 End Semester

4 Control modules pp.661-698 Exam,SEM-EXAM1
Develop the Application ALM,End Semester

COI- R6, Ch:12
20 CO2 Specific Digital Sequential Chalk,PPT,Talk Exam,HA,SEM-
4 pp.631-698
Modules EXAM1
COI- Design of Programmable R6, Ch:8 End Semester

1 Logic cells PROM pp.460-470 Exam,SEM-EXAM2

22 CO3 PAL, PLA Chalk,PPT,Talk
COI- Design of Reprogrammable T1, Ch:3 End Semester

1 Logic Cells pp.109-111 Exam,SEM-EXAM2

24 CO3 LUT Chalk,PPT,Talk
COI- Design of CPLD-Macrocell T4, Ch:8 ALM,End Semester

2 based combinational
logics pp.351-359 Exam,SEM-EXAM2
COI- FPGA-CLB based T1, Ch:3 End Semester

2 combinational ASIC logics pp.109-114 Exam,SEM-EXAM2

27 CO3 architecture of CPLD Chalk,PPT,Talk

28 CO3 FPGA based ALU modules Chalk,PPT,Talk
Development of Verilog
29 CO3 HDL for Combinational Chalk,PPT,Talk
logic functions
Development of Verilog T1, Ch:8,9 ALM,End Semester

COI-
30 CO3 HDL for sequential logic pp.487- Chalk,PPT,Talk Exam,HA,SEM-
3
functions 578,581-665 EXAM2
COI- Construction of optimized R6, Ch:5.5 End Semester

1 digital logic pp.189-
190 Exam,SEM-EXAM2
Applying Boolean
COI- R6, Ch:5.5 End Semester
32 CO4 Theorems for functions and Chalk,PPT,Talk
1 pp.191-
193 Exam,SEM-EXAM2
circuits
Construction of optimized R6, Ch:6.1-

COI- End Semester
33 CO4 digital logic functions
and 6.4
pp.232- Chalk,PPT,Talk
1 Exam,SEM-EXAM2
circuits 236
5/30
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Book Teaching-
[Page No] Methods
Construction of optimized R6, Ch:6.1-

COI- End Semester
34 CO4 digital logic functions
and 6.4
pp.236- Chalk,PPT,Talk
2 Exam,SEM-EXAM2
circuits using K-Map 245
Design of Optimized Digital T2, Ch:2.1-

COI- ALM,End Semester
35 CO4 system (Local and
Global) 2.4 pp.34- Chalk,PPT,Talk
2 Exam,SEM-EXAM2
using Boolean Theorems 43
Design of Optimized Digital T2, Ch:3.1-

COI- End Semester
36 CO4 system (Local and
Global) 3.3 pp.72- Chalk,PPT,Talk
2 Exam,SEM-EXAM2
using K-Maps 77
Construction of optimized
37 CO4 Programmable Logic Chalk,PPT,Talk
Device functions
COI- Construction of state R6, Ch:13 End Semester

3 diagram based pp.699-700 Exam,SEM-EXAM2

39 CO4 optimization logic circuits Chalk,PPT,Talk
Develop the optimized ALM,End Semester

COI- T2, Ch:3
40 CO4 Application Specific
Digital Chalk,PPT,Talk Exam,HA,SEM-
3 pp.72-110
Modules EXAM2
Lecture Session wise Teaching – Learning Plan
SESSION NUMBER : 1
Session Outcome: 1 student able to understand the Outline Structure of Computer, Microprocessor as
programmable Logic Device
Teaching- Active
Time(min) Topic BTL Learning Learning
Methods Methods
--- NOT
5 Attendance 1 Talk APPLICABLE
---
--- NOT
10 Course handout & Discussion on pre-requisite topics 2 PPT APPLICABLE
---
--- NOT
10 Outline the Structure of Computer 2 PPT APPLICABLE
---
--- NOT
20 Microprocessor as programmable Logic Device 2 Chalk APPLICABLE
---
5 Conclusion/Summary 2 Talk --- NOT
6/30
8/16/22, 7:24 AM
APPLICABLE
---
SESSION NUMBER : 2
Session Outcome: 1 Outline of Microcomputer organization and Digital hardware cells
Teaching- Active
Methods Methods
--- NOT
5 Attendance 2 Talk APPLICABLE
---
--- NOT
20 Outline the Microcomputer organization 2 PPT APPLICABLE
---
--- NOT
20 Digital Hardware: logic gates and flip-flops 2 Chalk APPLICABLE
---
--- NOT
5 Conclusion/Summary 2 Talk APPLICABLE
---
SESSION NUMBER : 3
Session Outcome: 1 To understand the Digital Hardware: flip-flops
Teaching- Active
Methods Methods
--- NOT
5 Attendance & Recall of previous session 2 Talk APPLICABLE
---
--- NOT
20 Digital Hardware 2 PPT APPLICABLE
---
--- NOT
20 Flip-flops 2 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 4
Session Outcome: 1 To understand the concepts of ALU: Arithmetic functions
Teaching- Active
Methods Methods
--- NOT
---
20 concepts of ALU 2 PPT --- NOT
APPLICABLE
7/30
8/16/22, 7:24 AM
---
--- NOT
20 Arithmetic functions 2 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 5
Session Outcome: 1 To understand ALU :Logic Functions
Teaching- Active
Methods Methods
--- NOT
---
Group
20 ALU 2 PPT
Discussion
--- NOT
20 Logic Functions 2 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 6
Session Outcome: 1 To understand the concepts of Digital Codes
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 Concepts of Digital Codes 2 PPT APPLICABLE
---
--- NOT
20 Digital Codes 2 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 7
Session Outcome: 1 To understand the Data Transmission process with parity
Teaching- Active
Methods Methods
5 Attendance & Recall of previous session 2 Talk --- NOT
8/30
8/16/22, 7:24 AM
APPLICABLE
---
--- NOT
20 Data Transmission process 2 PPT APPLICABLE
---
--- NOT
20 Data Transmission process with parity 2 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 8
Session Outcome: 1 To understand the Parity Based Logic Control modules
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 Odd Parity Based Logic Control modules 2 PPT APPLICABLE
---
--- NOT
20 Even Parity Based Logic Control modules 2 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 9
Session Outcome: 1 To understand the Development of the Encoder- Decoder; Multiplexer and
Demultiplexer
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 Develop the Encoder- Decoder 2 PPT APPLICABLE
---
--- NOT
20 Develop the Multiplexer and Demultiplexer 2 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 10
9/30
8/16/22, 7:24 AM
Session Outcome: 1 To understand the concepts of Encoder and Decoder based Logic Control modules
Teaching- Active
Methods Methods
--- NOT
---
Quiz/Test
20 Encoder based Logic Control modules 2 PPT
Questions
--- NOT
20 Decoder based Logic Control modules 2 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 11
Session Outcome: 1 To understand the Understand the Flip-flop as a Memory and timing control Unit
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 Understand the Flip-flop as a Memory 2 PPT APPLICABLE
---
--- NOT
20 Understand the Flipflop as timing control Unit 2 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 12
Session Outcome: 1 To understand the concepts of Memory Units: Flipflops
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 Memory Units: Flipflops-SR,D Flipflops 2 PPT APPLICABLE
---
--- NOT
20 Memory Units: Flipflops -JK and T Flipflops 2 Chalk APPLICABLE
---
10/30
8/16/22, 7:24 AM
APPLICABLE
---
SESSION NUMBER : 13
Session Outcome: 1 To Understanding shift modules concept
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 Understanding shift modules concept 2 PPT APPLICABLE
---
--- NOT
20 Different shift modules concept 2 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 14
Session Outcome: 1 To Design the Asynchronous & Timing and Control modules
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 Design of Asynchronous & Timing and Control modules 2 PPT APPLICABLE
---
--- NOT
20 Design of Asynchronous & Timing and Control modules 2 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 15
Session Outcome: 1 To understand and Design of Synchronous Timing Control modules
Teaching- Active
Methods Methods
--- NOT
---
Quiz/Test
20 Design of Asynchronous Timing Control modules 3 PPT
Questions
11/30
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20 Design of Synchronous Timing Control modules 3 Chalk --- NOT

APPLICABLE
---
--- NOT
---
SESSION NUMBER : 16
Session Outcome: 1 To understand the concept and Design of Control modules
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 Design of Control modules 3 PPT APPLICABLE
---
--- NOT
20 Design of Control modules 3 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 17
Session Outcome: 1 To understand the concept and Design of Asynchronous Timing and Control modules
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 Design of Asynchronous Timing and Control modules 3 PPT APPLICABLE
---
--- NOT
20 Design of Asynchronous Timing and Control modules 3 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 18
Session Outcome: 1 To understand and Design of State based Timing Modules
Teaching- Active
Methods Methods
12/30
8/16/22, 7:24 AM
APPLICABLE
---
--- NOT
20 Design of State based Timing Modules 4 PPT APPLICABLE
---
--- NOT
20 Design of various State based Timing Modules 4 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 19
Session Outcome: 1 To understand and Design of State based Control modules
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 Design of State based Control modules 4 PPT APPLICABLE
---
--- NOT
20 Design of State based Control modules 4 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 20
Session Outcome: 1 To understand and Develop the Application Specific Digital Sequential Modules
Teaching- Active
Methods Methods
--- NOT
---
Develop the Application Specific Digital Sequential Group
20 4 PPT
Modules Discussion
--- NOT
Develop the Application Specific Digital Sequential
20 4 Chalk APPLICABLE
Modules
---
--- NOT
---
SESSION NUMBER : 21
Session Outcome: 1 To understand the concept and to Design of Programmable Logic cells PROM
13/30
8/16/22, 7:24 AM
Time(min) Topic BTL Teaching- Active

Learning Learning
Methods Methods
--- NOT
---
--- NOT
20 Concept Programmable Logic cells PROM 2 PPT APPLICABLE
---
--- NOT
20 Design of Programmable Logic cells PROM 2 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 22
Session Outcome: 1 To understand the concept of PAL, PLA
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 Concept PAL, PLA 2 PPT APPLICABLE
---
--- NOT
20 Design of PAL, PLA 2 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 23
Session Outcome: 1 To understand the Design of Reprogrammable Logic Cells
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 Design of Reprogrammable Logic Cells 2 PPT APPLICABLE
---
--- NOT
20 Design of Reprogrammable Logic Cells 2 Chalk APPLICABLE
---
APPLICABLE
14/30
8/16/22, 7:24 AM
---
SESSION NUMBER : 24
Session Outcome: 1 To Understand the concept of LUT
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 LUT 2 PPT APPLICABLE
---
--- NOT
20 LUT 2 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 25
Session Outcome: 1 To understand the Design of CPLD-Macrocell based combinational logics
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 Design of CPLD-Macrocell based combinational logics 2 PPT APPLICABLE
---
--- NOT
20 Design of CPLD-Macrocell based combinational logics 2 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 26
Session Outcome: 1 To Undersand the concept of FPGA-CLB based combinational ASIC logics
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 FPGA-CLB based combinational ASIC logics 2 PPT APPLICABLE
---
15/30
8/16/22, 7:24 AM
20 CLB based combinational ASIC logics 2 Chalk --- NOT

APPLICABLE
---
--- NOT
---
SESSION NUMBER : 27
Session Outcome: 1 To Understand architecture of CPLD
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 To Understand architecture of CPLD 3 PPT APPLICABLE
---
--- NOT
20 To Understand architecture of CPLD 3 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 28
Session Outcome: 1 To understand the concept of FPGA based ALU modules
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 FPGA based ALU modules 3 PPT APPLICABLE
---
--- NOT
20 FPGA based ALU modules 3 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 29
Session Outcome: 1 understand the Development of Verilog HDL for Combinational logic functions
Teaching- Active
Methods Methods
16/30
8/16/22, 7:24 AM
APPLICABLE
---
--- NOT
20 Development of Verilog HDL 3 PPT APPLICABLE
---
--- NOT
Development of Verilog HDL for Combinational logic
functions
---
--- NOT
---
SESSION NUMBER : 30
Session Outcome: 1 Development of Verilog HDL for sequential logic functions
Teaching- Active
Methods Methods
--- NOT
---
Development of Verilog HDL for sequential logic Quiz/Test
20 3 PPT
functions Questions
--- NOT
Development of Verilog HDL for sequential logic
functions
---
--- NOT
---
SESSION NUMBER : 31
Session Outcome: 1 To understand and Construction of optimized digital logic
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 Construction of optimized digital logic 2 PPT APPLICABLE
---
--- NOT
20 Construction of optimized digital logic 2 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 32
Session Outcome: 1 To understand the concept Applying Boolean Theorems for functions and circuits
17/30
8/16/22, 7:24 AM
Time(min) Topic BTL Teaching- Active

Learning Learning
Methods Methods
--- NOT
---
--- NOT
20 Applying Boolean Theorems for functions and circuits 2 PPT APPLICABLE
---
--- NOT
20 Applying Boolean Theorems for functions and circuits 2 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 33
Session Outcome: 1 To understand the Construction of optimized digital logic functions and circuits
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
Construction of optimized digital logic functions and
20 2 PPT APPLICABLE
circuits
---
Construction of optimized digital logic functions and One minute
20 2 Chalk
circuits paper
--- NOT
---
SESSION NUMBER : 34
Session Outcome: 1 To understand the Construction of optimized digital logic functions and circuits using
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 Construction of optimized digital logic functions 2 PPT APPLICABLE
---
--- NOT
Construction of optimized digital logic functions and
circuits using K-Map
---
--- NOT
---
18/30
8/16/22, 7:24 AM
SESSION NUMBER : 35
Session Outcome: 1 To understand the Design of Optimized Digital system (Local and Global) using
Boolean Theorems
Teaching- Active
Methods Methods
--- NOT
---
Brain storming
20 Design of Optimized Digital system 2 PPT
session
--- NOT
Design of Optimized Digital system (Local and Global)
using Boolean Theorems
---
--- NOT
---
SESSION NUMBER : 36
Session Outcome: 1 To understand the Design of Optimized Digital system (Local and Global) using
KMaps
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 2 PPT APPLICABLE
using K-Maps
---
--- NOT
using K-Maps
---
--- NOT
---
SESSION NUMBER : 37
Session Outcome: 1 TO understand the Construction of optimized Programmable Logic Device functions
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
Construction of optimized Programmable Logic Device
20 3 PPT APPLICABLE
functions
---
20 Construction of optimized Programmable Logic Device 3 Chalk --- NOT
19/30
8/16/22, 7:24 AM
functions APPLICABLE
---
--- NOT
---
SESSION NUMBER : 38
Session Outcome: 1 To understand Construction of state diagram based design
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 Construction of state diagram 3 PPT APPLICABLE
---
--- NOT
20 Construction of state diagram based 3 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 39
Session Outcome: 1 To understand the optimization logic circuits
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
20 optimization logic circuits 3 PPT APPLICABLE
---
--- NOT
20 different optimization logic circuits 3 Chalk APPLICABLE
---
--- NOT
---
SESSION NUMBER : 40
Session Outcome: 1 To understand and Develop the optimized Application Specific Digital Modules
Teaching- Active
Methods Methods
APPLICABLE
20/30
8/16/22, 7:24 AM
---
Develop the optimized Application Specific Digital Brain storming
20 3 PPT
Modules session
--- NOT
20 Application Specific Digital Modules 3 Chalk APPLICABLE
---
--- NOT
---
Tutorial Course DELIVERY Plan: NO Delivery Plan Exists
Tutorial Session wise Teaching – Learning Plan
No Session Plans Exists
Practical Course DELIVERY Plan:

Tutorial
Session Topics CO-Mapping
no
1 Realization of Logic Functions using TTL IC’s CO5
2 LED Control Using Universal Gates CO5
3 Combinational Circuit Based Car Security System CO5
4 Participant selection in Competitions Using Multiplexer CO5
5 Random Number Generator for Gaming Using D-Flip- flop CO5
6 Verification of logic gates using Verilog tool CO5
7 Design and verification of full adder using Verilog tool CO5
8 Design and verification of 3-bit Odd parity generator using Verilog tool CO5
9 Verification of Flip flops using Verilog tool CO5
10 Design and verification of 3-bit Synchronous counter using Verilog tool CO5
Practical Session wise Teaching – Learning Plan
SESSION NUMBER : 1
Session Outcome: 1 Student able to Realization of Logic Functions using TTL IC’s
Teaching- Active
Methods Methods
10 Attendance & Experiment Discussion 2 Talk --- NOT
APPLICABLE
21/30
8/16/22, 7:24 AM
---
--- NOT
45 Realization of Logic Functions using TTL IC’s 3 PPT APPLICABLE
---
--- NOT
45 Realization of Logic Functions using TTL IC’s 5 Chalk APPLICABLE
---
SESSION NUMBER : 2
Session Outcome: 1 Student able to perform LED Control Using Universal Gates
Teaching- Active
Methods Methods
--- NOT
10 Attendance & Experiment Discussion 2 Talk APPLICABLE
---
--- NOT
45 LED Control Using Universal Gates 3 PPT APPLICABLE
---
--- NOT
45 LED Control Using Universal Gates 5 Chalk APPLICABLE
---
SESSION NUMBER : 3
Session Outcome: 1 Student able to understand Combinational Circuit Based Car Security System
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
45 Combinational Circuit Based Car Security System 3 PPT APPLICABLE
---
--- NOT
45 Combinational Circuit Based Car Security System 5 Chalk APPLICABLE
---
SESSION NUMBER : 4
Session Outcome: 1 Student able to design Participant selection in Competitions Using Multiplexer
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
45 Participant selection in Competitions Using Multiplexer 4 Chalk APPLICABLE
---
22/30
8/16/22, 7:24 AM
45 Participant selection in Competitions Using Multiplexer 4 PPT --- NOT

APPLICABLE
---
SESSION NUMBER : 5
Session Outcome: 1 Student able to design Random Number Generator for Gaming Using D-Flip- flop
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
Random Number Generator for Gaming Using D-Flip-
flop
---
--- NOT
Random Number Generator for Gaming Using D-Flip-
45 4 PPT APPLICABLE
flop
---
SESSION NUMBER : 6
Session Outcome: 1 Student able to Verify the logic gates using Verilog tool
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
45 Verification of logic gates using Verilog tool 4 Chalk APPLICABLE
---
--- NOT
45 Verification of logic gates using Verilog tool 4 PPT APPLICABLE
---
SESSION NUMBER : 7
Session Outcome: 1 Student is able to design and verification of full adder using Verilog tool
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
45 Design and verification of full adder using Verilog tool 4 Chalk APPLICABLE
---
--- NOT
45 Design and verification of full adder using Verilog tool 4 PPT APPLICABLE
---
23/30
8/16/22, 7:24 AM
SESSION NUMBER : 8
Session Outcome: 1 Student is able to Design and verification of 3-bit odd parity generator using Verilog
tool
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
Design and verification of 3-bit Odd parity generator
using Verilog tool
---
--- NOT
Design and verification of 3-bit Odd parity generator
45 4 PPT APPLICABLE
using Verilog tool
---
SESSION NUMBER : 9
Session Outcome: 1 Student is able to verify Flip flops using Verilog tool
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
45 Verification of Flip flops using Verilog tool 4 Chalk APPLICABLE
---
--- NOT
45 Verification of Flip flops using Verilog tool 4 PPT APPLICABLE
---
SESSION NUMBER : 10
Session Outcome: 1 Student is able to Design and verification of 3-bit Synchronous counter using Verilog
toolg tool
Teaching- Active
Methods Methods
--- NOT
---
--- NOT
Design and verification of 3-bit Synchronous counter
using Verilog tool
---
--- NOT
Design and verification of 3-bit Synchronous counter
45 4 PPT APPLICABLE
using Verilog tool
---
Skilling Course DELIVERY Plan: NO Delivery Plan Exists

24/30
8/16/22, 7:24 AM
Skilling Session wise Teaching – Learning Plan
No Session Plans Exists
WEEKLY HOMEWORK ASSIGNMENTS/ PROBLEM SETS/OPEN ENDEDED PROBLEM-SOLVING EXERCISES

etc:
Assignment Assignment
Week Topic Details co
Type No
COURSE TIME TABLE:
Hour 1 2 3 4 5 6 7 8 9
Day Component
V-S3,V-
V- -
V- V- V-S7,V-S11,V-S22,V- V-S7,V-S11,V- S6,V-
Theory S6,V- -- -- -
S26 S26 S23,V-S32 S22,V-S23,V-S32 S13,V-
S16 -
S16
-
Tutorial -- -- -- -- -- -- -- --
-
Mon -
V- V- -
V- V-
Lab V-S2,V-S20 V-S2,V-S20 V-S8 V-S8 S25,V- S25,V- -
S14 S14
S31 S31 -
-
Skilling -- -- -- -- -- -- -- -- -
-
V-S8,V-S10,V-S11,V- -
V- V-S8,V-S10,V- V-S2,V-
Theory -- S12,V-S16,V-S24,V- V-S2 -- -- -
S9 S12,V-S24,V-S29 S14
S27,V-S29,V-S32 -
-
Tutorial -- -- -- -- -- -- -- -- -
-
Tue
V- V- -
V- V-
S13 S13
S32 S32 -
-
Skilling -- -- -- -- -- -- -- -- -
-
V-S7,V-
V-S1,V-S3,V-S5,V- -
S8,V- V-
Theory -- -- S22,V-S24,V-S25,V- V-S3,V-S5,V-S25 -- -- -
S15,V- S15
S26,V-S30,V-S31 -
S33
-
Tutorial -- -- -- -- -- -- -- -- -
Wed -
V- V- -
V- V-
Lab V-S16 V-S16 V-S4 V-S4 S21,V- S21,V- -
S12 S12
S27 S27 -
-
Skilling -- -- -- -- -- -- -- -- -
-
25/30
8/16/22, 7:24 AM
Thu Theory -- -- V-S4,V-S5,V-S23,V- V-S4,V-S28 V- V- -- -- -

S25,V-S28,V-S29 S10,V- S18 -
S17,V- -
S18
-
Tutorial -- -- -- -- -- -- -- -- -
-
V- V- -
V- V-
S11 S11
S28 S28 -
-
Skilling -- -- -- -- -- -- -- -- -
-
V-S4,V-S14,V-S17,V- V-S14,V-S17,V-
V-S1,V- V- -
S19,V-S20,V-S21,V- S19,V-S20,V-
Theory -- -- S9,V- S1,V- -- -- -
S27,V-S30,V-S31,V- S21,V-S27,V-
S12 S9 -
S33 S30,V-S31,V-S33
-
Tutorial -- -- -- -- -- -- -- -- -
Fri -
V- V- -
V- V- V-
Lab V-S10 V-S10 V-S18 S24,V- S24,V- -
S6 S6 S18
S30 S30 -
-
Skilling -- -- -- -- -- -- -- -- -
-
V-S2,V-S6,V-S15,V- -
V- V-
Theory S18,V-S19,V-S20,V- -- -- -- -- -- -
S13 S13
S21,V-S28 -
-
Tutorial -- -- -- -- -- -- -- -- -
-
Sat
V- V- -
V- V- V-
Lab V-S9 V-S9 V-S17 S23,V- S23,V- -
S5 S5 S17
S29 S29 -
-
Skilling -- -- -- -- -- -- -- -- -
-
-
Theory -- -- -- -- -- -- -- --
-
-
Tutorial -- -- -- -- -- -- -- --
-
Sun
-
Lab -- -- -- -- -- -- -- --
-
-
Skilling -- -- -- -- -- -- -- --
-
REMEDIAL CLASSES:
Supplement course handout, which may perhaps include special lectures and discussions that would be
planned, and schedule notified according
26/30
8/16/22, 7:24 AM
SELF-LEARNING:
Assignments to promote self-learning, survey of contents from multiple sources.

S.no Topics CO ALM References/MOOCS
DELIVERY DETAILS OF CONTENT BEYOND SYLLABUS:
Content beyond syllabus covered (if any) should be delivered to all students that would be planned, and
schedule notified accordingly.
Advanced Topics, Additional Reading, Research
S.no CO ALM References/MOOCS
papers and any
EVALUATION PLAN:
Evaluation Evaluation Assessment Duration

Weightage/Marks CO1 CO2 CO3 CO4 CO5
Type Component Dates (Hours)
End End Semester Weightage 24 6 6 6 6
Semester Exam 180
Summative
Max Marks 100 25 25 25 25
Evaluation
Weightage 16 16
Total= 40
Lab End 120
Semester Exam Max Marks 50 50
%
Semester in Weightage 15 7.5 7.5
In 120
Exam-I Max Marks 50 25 25
Semester
Summative
Semester in Weightage 15 7.5 7.5
120
Evaluation
Exam-II Max Marks 50 25 25
Total= 40
Weightage 10 10
% Lab In Semester
120
Exam Max Marks 50 50
Weightage 4 1 1 1 1
ALM 50
In Max Marks 80 20 20 20 20
Semester Home Weightage 8 2 2 2 2
Formative
Assignment and 50
Evaluation
Textbook Max Marks 40 10 10 10 10
Total= 20
Continuous Weightage 8 8
% Evaluation - Lab 120
Exercise Max Marks 100 100
ATTENDANCE POLICY:
Every
student is expected to be responsible for regularity of his/her
attendance in class rooms and
laboratories, to appear in scheduled
tests and examinations and fulfill all other tasks assigned to
him/her in
every course

student has to maintain a minimum of 85% attendance to
be eligible for appearing in
In
every course,
Semester end examination of the course,
for cases of medical issues and other unavoidable circumstances the
students will be condoned if their attendance is between 75% to 85%
in every course, subjected to
submission of medical certificates,
medical case file and other needful documental proof to the concerned
departments
DETENTION POLICY :
27/30
8/16/22, 7:24 AM
In any course, a student has to maintain a minimum of 85% attendance and In-Semester Examinations to be
eligible for appearing to the Semester End Examination, failing to fulfill these conditions will deem such
student to have been detained in that course.
PLAGIARISM POLICY :
Supplement course handout, which may perhaps include special lectures and discussions
COURSE TEAM MEMBERS, CHAMBER CONSULTATION HOURS AND CHAMBER VENUE DETAILS:
Supplement course handout, which may perhaps include special lectures and discussions
Chamber
Delivery Sections Chamber Chamber Signature
Name of Consultation
Component of Consultation Consultation of Course
Faculty Timings for each
of Faculty Faculty Day (s) Room No: faculty:
day
HABIBULLA
L 5-MA - - - -
KHAN
SIVA GANGA
PRASAD L 1-MA - - - -
Mutchakayala
MADHAV
L 4-MA - - - -
B.T.P
RAVI
L 7-MA - - - -
KALLAKUNTA
RAVI
P 7-MA - - - -
KALLAKUNTA
28-
SURESH
L MA,31- - - - -
NAMGIRI
MA
31-
SURESH
P MA,28- - - - -
NAMGIRI
MA
SIVA KUMAR
L 10-MA - - - -
MUNUSWAMY
SIVA KUMAR
P 10-MA - - - -
MUNUSWAMY
INTHIYAZ
L 15-MA - - - -
SYED
15-
INTHIYAZ
P MA,2- - - - -
SYED
MA
29-
HARI
L MA,6- - - - -
KAKARLA
MA
HARI
P 29-MA - - - -
KAKARLA
2-
SOMLAL
L MA,33- - - - -
JARUPULA
MA
SOMLAL
P 33-MA - - - -
JARUPULA
SRIDHAR L 3- - - - -
28/30
8/16/22, 7:24 AM
MIRIYALA MA,19-
MA
21-
Kali prasad L MA,16- - - - -
MA
16-
MA,3-
Kali prasad P - - - -
MA,21-
MA
17-
NOORBASHA
L MA,8- - - - -
FAZAL
MA
8-
NOORBASHA
P MA,17- - - - -
FAZAL
MA
VENUGOPALA
L 27-MA - - - -
RAO MATCHA
VENUGOPALA
P 27-MA - - - -
RAO MATCHA
12-
SONY KARRA L MA,23- - - - -
MA
23-
MA,12-
SONY KARRA P - - - -
MA,5-
MA
13-
SIDDAIAH
L MA,14- - - - -
NALLURI
MA
13-
SIDDAIAH
P MA,14- - - - -
NALLURI
MA
20-
Midasala Vasuja
L MA,24- - - - -
Devi
MA
24-
Midasala Vasuja
P MA,20- - - - -
Devi
MA
25-
BANDA SAI
L MA,32- - - - -
SANDEEP
MA
32-
BANDA SAI
P MA,25- - - - -
SANDEEP
MA
KONERU
L 26-MA - - - -
SWAPNA
26-
KONERU
P MA,6- - - - -
SWAPNA
MA
9-
VIPUL
L MA,22- - - - -
AGARWAL
MA
VIPUL P 1-MA,9- - - - -
29/30
8/16/22, 7:24 AM
AGARWAL MA,22-
MA
18-
BUKYA
L MA,11- - - - -
BALAJI
MA
18-
BUKYA MA,11-
P - - - -
BALAJI MA,4-
MA
SUMIT
P 19-MA - - - -
BHUSHAN
Sunil Kumar L 30-MA - - - -
Sunil Kumar P 30-MA - - - -
PRIYARANJAN
L 31-MA - - - -
SHARMA
GENERAL INSTRUCTIONS
Students should come prepared for classes and carry the text book(s) or material(s) as prescribed by the
Course Faculty to the class.
NOTICES
Most of the notices are available on the LMS platform.
All notices will be communicated through the institution email.
All notices concerning the course will be displayed on the respective Notice Boards.
Signature of COURSE COORDINATOR

(SIDDAIAH NALLURI)
Signature of Department Prof. Incharge Academics & Vetting Team Member

Department Of DBES-2
HEAD OF DEPARTMENT:

Approval from: DEAN-ACADEMICS

(Sign with Office Seal)

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8/16/22, 7:24 AM

COURSE OUTCOMES (COs):

CO Course Outcome (CO) PO/PSO Blooms

COURSE OUTCOME INDICATORS (COIs)::

PROGRAM OUTCOMES & PROGRAM SPECIFIC OUTCOMES (POs/PSOs)

and an engineering specialization to the solution of complex engineering problems.

Lecture Course DELIVERY Plan:

Course Handout / Outline

COI- T2, Ch:9 End Semester

COI- concepts of ALU: T2, Ch:9 End Semester

COI- T-2 pp.376- ALM,End Semester

COI- R6, Ch:3 End Semester

COI- Data Transmission process R6, Ch:7 End Semester

COI- Parity Based Logic Control R6, Ch:7 End Semester

Develop the Encoder

Understand the Flip-flop as

COI- T2, Ch:7.2 End Semester

COI- Understanding shift T2, Ch:7.2 End Semester

COI- Design of Synchronous T3, Ch:7.5 ALM,End Semester

COI- T3, Ch:7.5 End Semester

COI- Design of State based R6, Ch:12 End Semester

COI- Design of State based R6, Ch:12 End Semester

Develop the Application ALM,End Semester

COI- Design of Programmable R6, Ch:8 End Semester

COI- R6, Ch:8 End Semester

COI- Design of Reprogrammable T1, Ch:3 End Semester

COI- T1, Ch:3 End Semester

COI- Design of CPLD-Macrocell T4, Ch:8 ALM,End Semester

COI- FPGA-CLB based T1, Ch:3 End Semester

COI- T4, Ch:8 End Semester

COI- T4, Ch:8 End Semester

Development of Verilog T1, Ch:8,9 ALM,End Semester

COI- Construction of optimized R6, Ch:5.5 End Semester

Construction of optimized R6, Ch:6.1-

Construction of optimized R6, Ch:6.1-

Design of Optimized Digital T2, Ch:2.1-

Design of Optimized Digital T2, Ch:3.1-

COI- Construction of state R6, Ch:13 End Semester

COI- R6, Ch:13 End Semester

Develop the optimized ALM,End Semester

Lecture Session wise Teaching – Learning Plan

Session Outcome: 1 Outline of Microcomputer organization and Digital hardware cells

Session Outcome: 1 To understand the Digital Hardware: flip-flops

Session Outcome: 1 To understand the concepts of ALU: Arithmetic functions

Session Outcome: 1 To understand ALU :Logic Functions

Session Outcome: 1 To understand the concepts of Digital Codes

Session Outcome: 1 To understand the Data Transmission process with parity

Session Outcome: 1 To understand the Parity Based Logic Control modules

Session Outcome: 1 To understand the concepts of Memory Units: Flipflops

Session Outcome: 1 To Understanding shift modules concept

Session Outcome: 1 To understand and Design of Synchronous Timing Control modules

20 Design of Synchronous Timing Control modules 3 Chalk --- NOT

Session Outcome: 1 To understand the concept and Design of Control modules

Session Outcome: 1 To understand and Design of State based Timing Modules

Session Outcome: 1 To understand and Design of State based Control modules

Time(min) Topic BTL Teaching- Active

Session Outcome: 1 To understand the concept of PAL, PLA

Session Outcome: 1 To understand the Design of Reprogrammable Logic Cells

Session Outcome: 1 To Understand the concept of LUT

Session Outcome: 1 To understand the Design of CPLD-Macrocell based combinational logics

20 CLB based combinational ASIC logics 2 Chalk --- NOT

Session Outcome: 1 To Understand architecture of CPLD