Features Description: LTC3850/LTC3850-1 Dual, 2-Phase Synchronous Step-Down Switching Controller

LTC3850/LTC3850-1
Dual, 2-Phase Synchronous Step-Down

Switching Controller
FEATURES DESCRIPTION
n Dual, 180° Phased Controllers Reduce Required The LTC®3850 is a high performance dual synchronous
Input Capacitance and Power Supply Induced Noise step-down switching regulator controller that drives all
n High Efficiency: Up to 95% N-channel power MOSFET stages. A constant-frequency
n R
SENSE or DCR Current Sensing current mode architecture allows a phase-lockable fre-
n ±1% 0.8V Output Voltage Accuracy quency of up to 780kHz. Power loss and supply noise are
n Phase-Lockable Fixed Frequency 250kHz to 780kHz minimized by operating the two controller output stages
n Supports Pre-Biased Output out of phase.
n Dual N-Channel MOSFET Synchronous Drive
n Wide V Range: 4V to 24V (30V for LTC3850I)
OPTI-LOOP® compensation allows the transient response
IN to be optimized over a wide range of output capacitance
Operation
n Adjustable Soft-Start Current Ramping or Tracking
and ESR values. The LTC3850 features a precision 0.8V
n Foldback Output Current Limiting
reference and a power good output indicator. A wide 4V
n Power Good Output Voltage Monitor
to 24V (28V maximum/30V for LTC3850I) input supply
n 28-Pin 4mm × 4mm, 4mm × 5mm QFN and Narrow
range encompasses most battery chemistries and inter-
mediate bus voltages.
SSOP Packages
n AEC-Q100 Qualified for Automotive Applications Independent TK/SS pins for each controller ramp the
output voltages during start-up. Current foldback limits
APPLICATIONS MOSFET heat dissipation during short-circuit conditions.
n Notebook and Palmtop Computers The MODE/PLLIN pin selects among Burst Mode® opera-
n Portable Instruments tion, pulse-skipping mode, or continuous inductor cur-
n Battery-Operated Digital Devices rent mode and allows the IC to be synchronized to an
n DC Power Distribution Systems external clock.
All registered trademarks and trademarks are the property of their respective owners. Protected The LTC3850 is available in low profile 28-pin 4mm ×
by U.S. patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787,
6304066, 6580258. 4mm, 4mm × 5mm QFN and narrow SSOP packages.
TYPICAL APPLICATION
High Efficiency Dual 3.3V/2.5V Step-Down Converter Efficiency
VIN
7V TO 100 10000
22µF 24V VIN = 12V
4.7µF 50V 95 VOUT = 3.3V EFFICIENCY
VIN PGOOD INTVCC
90
TG1 TG2
0.1µF 0.1µF
85
POWER LOSS (mW)
1000
EFFICIENCY (%)
2.2µH BOOST1 BOOST2 2.2µH

80
SW1 SW2
LTC3850 75
BG1 BG2 2.2k
70
2.2k 500kHz MODE/PLLIN PGND 100
65
ILIM FREQ/PLLFLTR POWER LOSS
60
SENSE1+ SENSE2+
0.1µF RUN1 RUN2 0.1µF 55
VOUT1 SENSE1– SENSE2– VOUT2 50 10
3.3V VFB1 VFB2 2.5V 10 100 1000 10000
5A 63.4k 43.2k 5A
ITH1 ITH2 LOAD CURRENT (mA)
220pF 10nF 220pF
TK/SS1 SGND TK/SS2 38501 TA01b
100µF 20k 20k 100µF

15k 0.1µF 0.1µF 10k 15k
6V 6V
38501 TA01
Rev. D
Document Feedback For more information www.analog.com 1

LTC3850/LTC3850-1
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply Voltage (VIN).......................... 28V to –0.3V SENSE1+, SENSE2+, SENSE1–,

Input Supply Voltage (VIN), SENSE2– Voltages..................................... 5.5V to –0.3V
LTC3850I Only........................................ 30V to –0.3V MODE/PLLIN, ILIM,TK/SS1,TK/SS2, FREQ/PLLFLTR
Input Supply Transient Voltage (VIN) < 500ms, with Voltages.................................................INTVCC to –0.3V
INTVCC ≥ 5V, LTC3850I Only.................. 34V to –0.3V ITH1 , ITH2 , VFB1 , VFB2 Voltages.................. 2.7V to –0.3V
Top Side Driver Voltages INTVCC Peak Output Current.................................100mA
BOOST1, BOOST2................................... 34V to –0.3V Operating Temperature Range (Note 2)....–40°C to 85°C
Switch Voltage (SW1, SW2)........................... 28V to –5V Junction Temperature (Note 3).............................. 125°C
Switch Voltage (SW1, SW2), Storage Temperature Range................... –65°C to 125°C
LTC3850I Only...........................................30V to –5V Lead Temperature (Soldering, 10 sec)
INTVCC , RUN1, RUN2, PGOOD, EXTVCC, (GN Package)..................................................... 300°C
(BOOST1-SW1), (BOOST2-SW2).................. 6V to –0.3V
PIN CONFIGURATION
TOP VIEW TOP VIEW
FREQ/PLLFLTR
RUN1 1 28 FREQ/PLLFLTR
MODE/PLLIN
SENSE1+ 2 27 MODE/PLLIN
SENSE1–
SENSE1+
SENSE1–
RUN1
3 26 SW1
SW1
TG1
TK/SS1 4 25 TG1
28 27 26 25 24 23 22
ITH1 5 24 BOOST1
TK/SS1 1 21 BOOST1
VFB1 6 23 BG1
ITH1 2 20 BG1
SGND 7 22 VIN
VFB1 3 19 VIN
VFB2 8 21 INTVCC VFB2 4 29 18 INTVCC
ITH2 9 20 BG2 ITH2 5 17 BG2
TK/SS2 10 19 PGND TK/SS2 6 16 PGND
SENSE2– 11 18 BOOST2 SENSE2– 7 15 BOOST2
SENSE2+ 12 17 TG2 8 9 10 11 12 13 14
RUN2 13 16 SW2
SENSE2+
RUN2
ILIM
EXTVCC
PGOOD
SW2
TG2
ILIM (EXTVCC)* 14 15 PGOOD
GN PACKAGE UF PACKAGE
28-LEAD NARROW PLASTIC SSOP 28-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 95°C/W TJMAX = 125°C, θJA = 37°C/W, θJC = 2.6°C/W
*PIN 14 = ILIM FOR LTC3850GN, EXTVCC FOR LTC3850GN-1 EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
TOP VIEW
FREQ/PLLFLTR
MODE/PLLIN
SENSE1+
RUN1
SW1
TG1
28 27 26 25 24 23
SENSE1– 1 22 BOOST1
TK/SS1 2 21 BG1
ITH1 3 20 VIN
VFB1 4 19 INTVCC
29
VFB2 5 18 BG2
ITH2 6 17 PGND
TK/SS2 7 16 BOOST2
SENSE2– 8 15 TG2
9 10 11 12 13 14
SENSE2+
RUN2
ILIM
EXTVCC
PGOOD
SW2
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W, EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
Rev. D
2 For more information www.analog.com

LTC3850/LTC3850-1
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3850EGN#PBF LTC3850EGN#TRPBF LTC3850GN 28-Lead Narrow Plastic SSOP –40°C to 85°C
LTC3850EGN-1#PBF LTC3850EGN-1#TRPBF LTC3850GN-1 28-Lead Narrow Plastic SSOP –40°C to 85°C
LTC3850IGN#PBF LTC3850IGN#TRPBF LTC3850GN 28-Lead Narrow Plastic SSOP –40°C to 85°C
LTC3850IGN-1#PBF LTC3850IGN-1#TRPBF LTC3850GN-1 28-Lead Narrow Plastic SSOP –40°C to 85°C
LTC3850EUF#PBF LTC3850EUF#TRPBF 3850 28-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C
LTC3850EUFD#PBF LTC3850EUFD#TRPBF 3850 28-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C
LTC3850IUF#PBF LTC3850IUF#TRPBF 3850 28-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C
LTC3850IUFD#PBF LTC3850IUFD#TRPBF 3850 28-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C
AUTOMOTIVE PRODUCTS**
LTC3850EGN#WPBF LTC3850EGN#WTRPBF LTC3850GN 28-Lead Narrow Plastic SSOP –40°C to 85°C
LTC3850EGN-1#WPBF LTC3850EGN-1#WTRPBF LTC3850GN-1 28-Lead Narrow Plastic SSOP –40°C to 85°C
LTC3850IGN#WPBF LTC3850IGN#WTRPBF LTC3850GN 28-Lead Narrow Plastic SSOP –40°C to 85°C
LTC3850IGN-1#WPBF LTC3850IGN-1#WTRPBF LTC3850GN-1 28-Lead Narrow Plastic SSOP –40°C to 85°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. D
For more information www.analog.com 3

LTC3850/LTC3850-1
ELECTRICAL
The CHARACTERISTICS l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 15V, VRUN1,2 = 5V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loops
VFB1,2 Regulated Feedback Voltage ITH1,2 Voltage = 1.2V; (Note 4) l 0.792 0.800 0.808 V
IFB1,2 Feedback Current (Note 4) –10 –50 nA
VREFLNREG Reference Voltage Line Regulation VIN = 6V to 24V (Note 4) 0.002 0.02 %/V
VLOADREG Output Voltage Load Regulation (Note 4)
Measured in Servo Loop; ∆ITH Voltage = 1.2V to 0.7V l 0.01 0.1 %
Measured in Servo Loop; ∆ITH Voltage = 1.2V to 1.6V l –0.01 –0.1 %
gm1,2 Transconductance Amplifier gm ITH1,2 = 1.2V; Sink/Source 5µA; (Note 4) 2.2 mmho
IQ Input DC Supply Current (Note 5)
Normal Mode VIN = 15V; EXTVCC Tied to VOUT1; VOUT1 = 5V 850 µA
Shutdown VRUN1,2 = 0V 30 50 µA
UVLO Undervoltage Lockout on INTVCC VINTVCC Ramping Down 3 V
UVLOHYS UVLO Hysteresis 0.5 V
DFMAX Maximum Duty Factor In Dropout 96 97.2 %
VOVL Feedback Overvoltage Lockout Measured at VFB1,2 l 0.84 0.86 0.88 V
ISENSE Sense Pin Bias Current (Each Channel) VSENSE1,2 = 3.3V ±1 ±2 µA
ITK/SS1,2 Soft-Start Charge Current VTK/SS1,2 = 0V 0.9 1.3 1.7 µA
VRUN1,2 RUN Pin ON Threshold VRUN1, VRUN2 Rising l 1.1 1.22 1.35 V
VRUN1,2HYS RUN Pin ON Hysteresis 80 mV
VSENSE(MAX) Maximum Current Sense Threshold VFB1,2 = 0.7V, VSENSE1,2 = 3.3V, ILIM = 0V l 20 30 40 mV
(Note 8) VFB1,2 = 0.7V, VSENSE1,2 = 3.3V, ILIM = Float l 40 50 60 mV
VFB1,2 = 0.7V, VSENSE1,2 = 3.3V, ILIM = INTVCC l 60 75 90 mV
TG RUP TG Driver Pull-Up On-Resistance TG High 2.6 Ω
TG RDOWN TG Driver Pull-down On-Resistance TG Low 1.5 Ω
BG RUP BG Driver Pull-Up On-Resistance BG High 2.4 Ω
BG RDOWN BG Driver Pull-down On-Resistance BG Low 1.1 Ω
TG Transition Time: (Note 6)
TG1,2 tr Rise Time CLOAD = 3300pF 25 ns
TG1,2 tf Fall Time CLOAD = 3300pF 25 ns
BG Transition Time: (Note 6)
BG1,2 tr Rise Time CLOAD = 3300pF 25 ns
BG1,2 tf Fall Time CLOAD = 3300pF 25 ns
TG/BG t1D Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time CLOAD = 3300pF Each Driver 30 ns
BG/TG t2D Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time CLOAD = 3300pF Each Driver 30 ns
tON(MIN) Minimum On-Time (Note 7) 90 ns
INTVCC Linear Regulator
VINTVCC Internal VCC Voltage 7V < VIN < 24V 4.8 5 5.2 V
VLDO INT INTVCC Load Regulation ICC = 0mA to 50mA 0.5 2 %
VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive l 4.5 4.7 V
VLDO EXT EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 5V 50 100 mV
VLDOHYS EXTVCC Hysteresis 200 mV
Rev. D

LTC3850/LTC3850-1
ELECTRICAL
The CHARACTERISTICS l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 15V, VRUN1,2 = 5V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Oscillator and Phase-Locked Loop
fNOM Nominal Frequency VFREQ = 1.2V 450 500 550 kHz
fLOW Lowest Frequency VFREQ = 0V 210 250 290 kHz
fHIGH Highest Frequency VFREQ ≥ 2.4V 700 780 860 kHz
RMODE/PLLIN MODE/PLLIN Input Resistance 250 kΩ
IFREQ Phase Detector Output Current
Sinking Capability fMODE < fOSC –13 µA
Sourcing Capability fMODE > fOSC 13 µA
PGOOD Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V ±2 µA
VPG PGOOD Trip Level VFB with Respect to Set Regulated Voltage
VFB Ramping Negative –5 – 7.5 –10 %
VFB Ramping Positive 5 7.5 10 %
Note 1: Stresses beyond those listed under Absolute Maximum Ratings LTC3850GN: TJ = TA + (PD • 95°C/W)
may cause permanent damage to the device. Exposure to any Absolute LTC3850UF: TJ = TA + (PD • 37°C/W)
Maximum Rating condition for extended periods may affect device LTC3850UFD: TJ = TA + (PD • 43°C/W)
reliability and lifetime. Note 4: The LTC3850 is tested in a feedback loop that servos VITH1,2 to a
Note 2: The LTC3850E/LTC3850E-1 are guaranteed to meet performance specified voltage and measures the resultant VFB1,2.
specifications from 0°C to 85°C. Specifications over the –40°C to 85°C Note 5: Dynamic supply current is higher due to the gate charge being
operating temperature range are assured by design, characterization and delivered at the switching frequency. See Applications Information.
correlation with statistical process controls. The LTC3850I/LTC3850I-1 Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
are guaranteed to meet performance specifications over the –40°C to 85°C times are measured using 50% levels.
operating temperature range. Note 7: The minimum on-time condition is specified for an inductor
Note 3: TJ is calculated from the ambient temperature TA and power peak-to-peak ripple current ≥40% of IMAX (see Minimum On-Time
dissipation PD according to the following formulas: Considerations in the Applications Information section).
Note 8: VSENSE(MAX) defaults to 50mV typical for the LTC3850-1.
TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency vs Output Current Efficiency vs Output Current Efficiency and Power Loss
and Mode and Mode vs Input Voltage
100 100 100 2000
VIN = 12V VOUT = 3.3V
90 VOUT = 1.8V 90 BURST IOUT = 2A
BURST
80 80
95 1500
70 70 EFFICIENCY
POWER LOSS (mW)
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
60 DCM DCM
60
50 50 90 1000
40 40 POWER LOSS
30 30 CCM
CCM 85 500
20 20
10 10 VIN = 12V
VOUT = 3.3V
0 0 80 0
10 100 1000 10000 10 100 1000 10000 5 10 15 20 25
LOAD CURRENT (mA) 38501 G01
LOAD CURRENT (mA) INPUT VOLTAGE (V) 38501 G03
38501 G02
CIRCUIT OF FIGURE 14 CIRCUIT OF FIGURE 14 CIRCUIT OF FIGURE 14
Rev. D

LTC3850/LTC3850-1
Load Step Load Step
(Burst Mode Operation) (Forced Continuous Mode)
ILOAD ILOAD
2A/DIV 2A/DIV
200mA TO 2.5A 200mA TO 2.5A
IL IL
2A/DIV 2A/DIV
VOUT VOUT
100mV/DIV 100mV/DIV
AC COUPLED AC COUPLED
38501 G04 38501 G05

40µs/DIV 40µs/DIV
CIRCUIT OF FIGURE 14 CIRCUIT OF FIGURE 14
VIN = 12V, VOUT = 1.8V VIN = 12V, VOUT = 1.8V
Load Step
(Pulse-Skipping Mode) Inductor Current at Light Load
ILOAD FORCED
2A/DIV CONTINUOUS
200mA TO 2.5A MODE
2A/DIV
IL
2A/DIV Burst Mode
OPERATION
VOUT 2A/DIV
100mV/DIV
AC COUPLED PULSE-SKIPPING
MODE
2A/DIV
38501 G06 38501 G07
40µs/DIV 1µs/DIV
CIRCUIT OF FIGURE 14 CIRCUIT OF FIGURE 14
VIN = 12V, VOUT = 1.8V VIN = 12V, VOUT = 1.8V
ILOAD = 100µA
Prebiased Output at 2V Coincident Tracking
RUN1
2V/DIV
VOUT VOUT1, 3.3V
VTK/SS
2V/DIV 3Ω LOAD, 1V/DIV
500mV/DIV
VOUT2, 1.8V
VFB 1.5Ω LOAD
500mV/DIV 1V/DIV
38501 G08 38501 G09
2.5ms/DIV 1ms/DIV
Rev. D

LTC3850/LTC3850-1
Tracking Up and Down Quiescent Current
with External Ramp vs Input Voltage without EXTVCC INTVCC Line Regulation
5 5.25
TK/SS1
5.00
TK/SS2 4
2V/DIV
SUPPLY CURRENT (mA)

4.75
INTVCC VOLTAGE (V)

VOUT1
3.3V 3
3Ω LOAD 4.50
1V/DIV
2 4.25
VOUT2
1.8V
1.5Ω LOAD 4.00
1V/DIV 38501 G10 1
10ms/DIV 3.75
0 3.50
5 10 15 20 25 0 5 10 15 20 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
38501 G11 38501 G12
Current Sense Threshold Maximum Current Sense Threshold Maximum Current Sense
vs ITH Voltage vs Common Mode Voltage Threshold vs Duty Cycle
80 80 100
ILIM = INTVCC ILIM = INTVCC 90
70
CURRENT SENSE THRESHOLD (mV)
CURRENT SENSE THRESHOLD (mV)

60
80 ILIM = INTVCC
ILIM = FLOAT 60
ILIM = FLOAT 70
40
50
VSENSE (mV)
60
ILIM = FLOAT
20 40 50
ILIM = GND
ILIM = GND 30 40
ILIM = GND
0
30
20
–20 20
10
10
–40 0 0
0 0.5 1 1.5 2 0 1 3 2 4 5 0 20 40 60 80 100
VITH (V) VSENSE COMMON MODE VOLTAGE (V) DUTY CYCLE (%)
38501 G13 38501 G14 38501 G15
Maximum Current Sense Voltage vs TK/SS Pull-Up Current

Feedback Voltage (Current Foldback) vs Temperature
80 2.00
MAXIMUM CURRENT SENSE VOLTAGE (mV)
ILIM = INTVCC
70
60 1.75
TK/SS CURRENT (µA)
ILIM = FLOAT
50
40 1.50
ILIM = GND
30
20 1.25
10
0 1.00
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 –50 –25 0 25 50 75 100
FEEDBACK VOLTAGE (V) TEMPERATURE (°C)
38501 G16 38501 G17
Rev. D

LTC3850/LTC3850-1
Shutdown (RUN) Threshold Regulated Feedback Voltage Oscillator Frequency
vs Temperature vs Temperature vs Temperature
1.5 806 900
VFREQ = INTVCC
REGULATED FEEDBACK VOLTAGE (mV)

804 800
1.4
700
RUN PIN VOLTAGE (V)
802
FREQUENCY (kHz)
1.3
600
ON 800
VFREQ = 1.2V
500
1.2
OFF 798
400
1.1
796 300 VFREQ = 0V
1.0 794 200

–50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
38501 G18 38501 G19 38501 G20
Undervoltage Lockout Threshold Oscillator Frequency Shutdown Current

(INTVCC) vs Temperature vs Input Voltage vs Input Voltage
5 420 50
4 40
RISING 410
INPUT CURRENT (µA)

INTVCC VOLTAGE (V)
FREQUENCY (kHz)
3 30
FALLING
400
2 20
390
1 10
0 380 0
–50 –25 0 25 50 75 100 5 10 15 20 25 5 10 15 20 25
TEMPERATURE (°C) INPUT VOLTAGE (V) INPUT VOLTAGE (V)
38501 G21 38501 G22 38501 G23
Shutdown Current Quiescent Current

vs Temperature vs Temperature without EXTVCC
50 5
VIN = 15V
40 4
SHUTDOWN CURRENT (µA)
QUIESCENT CURRENT (mA)
30 3
20 2
10 1
0 0
–50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100
TEMPERATURE (°C) TEMPERATURE (°C)
38501 G24 38501 G25
Rev. D

LTC3850/LTC3850-1
PIN FUNCTIONS (GN/UF/UFD)
RUN1, RUN2 (Pins 1, 13/Pins 26, 9/Pins 27, 10): Run VIN > VEXTVCC at all times. On the GN package, EXTVCC is
Control Inputs. A voltage above 1.2V on either pin turns the optional bonding in place of ILIM for LTC3850-1. In
on the IC. However, forcing either of these pins below 1.2V the LTC3850-1, ILIM will default to 50mV.
causes the IC to shut down that particular channel. There
ILIM (Pin 14, LTC3850 Only/Pin 10/Pin 11): Current
are 0.5µA pull-up currents for these pins. Once the RUN
Comparator Sense Voltage Range Inputs. Tying this pin to
pin rises above 1.2V, an additional 4.5µA pull-up current
SGND, FLOAT or INTVCC sets the maximum current sense
is added to the pin.
threshold to three different levels for each comparator.
SENSE1+, SENSE2+ (Pins 2, 12/Pins 27, 8/Pins 28, 9):
PGOOD (Pin 15/Pin 12/Pin 13): Power Good Indicator
Current Sense Comparator Inputs. The (+) inputs to the
Output. Open-drain logic out that is pulled to ground when
current comparators are normally connected to DCR
either channel output exceeds the ±7.5% regulation window,
sensing networks or current sensing resistors.
after the internal 17µs power bad mask timer expires.
SENSE1–, SENSE2– (Pins 3, 11/Pins 28, 7/Pins 1, 8):
PGND (Pin 19/Pin 16/Pin 17): Power Ground Pin. Connect
Current Sense Comparator Inputs. The (–) inputs to the
this pin closely to the sources of the bottom N-channel
current comparators are connected to the outputs.
MOSFETs, the (–) terminal of CVCC and the (–) terminal
TK/SS1, TK/SS2 (Pins 4, 10/Pins 1, 6/Pins 2, 7): Output of CIN.
Voltage Tracking and Soft-Start Inputs. When one channel
INTVCC (Pin 21/Pin 18/Pin 19): Internal 5V Regulator Output.
is configured to be master of the two channels, a capaci-
The control circuits are powered from this voltage.
tor to ground at this pin sets the ramp rate for the master
Decouple this pin to PGND with a 4.7µF low ESR tantalum
channel’s output voltage. When the channel is configured
or ceramic capacitor.
to be the slave of two channels, the VFB voltage of the
master channel is reproduced by a resistor divider and VIN (Pin 22/Pin 19/Pin 20): Main Input Supply. Decouple
applied to this pin. Internal soft-start currents of 1.3µA this pin to PGND with a capacitor (0.1µF to 1µF). For
charge the soft-start capacitors. applications where the main input power is 5V, tie the VIN
and INTVCC pins together.
ITH1, ITH2 (Pins 5, 9/Pins 2, 5/Pins 3, 6): Current Control
Thresholds and Error Amplifier Compensation Points. BG1, BG2 (Pins 23, 20/Pins 20, 17/Pins 21, 18): Bottom
Each associated channels’ current comparator tripping Gate Driver Outputs. These pins drive the gates of the
threshold increases with its ITH control voltage. bottom N-Channel MOSFETs and swings between PGND
and INTVCC.
VFB1, VFB2 (Pins 6, 8/Pins 3, 4/Pins 4, 5): Error Amplifier
Feedback Inputs. These pins receive the remotely sensed BOOST1, BOOST2 (Pins 24, 18/Pins 21, 15/Pins 22, 16):
feedback voltages for each channel from external resistive Boosted Floating Driver Supplies. The (+) terminal of the
dividers across the outputs. boost-strap capacitors connect to these pins. These pins
swing from a diode voltage drop below INTVCC up to VIN
SGND (Pin 7/Pin 29/Pin 29): Signal Ground. All small-sig- + INTVCC.
nal components and compensation components should
connect to this ground, which in turn connects to PGND TG1, TG2 (Pins 25, 17/Pins 22, 14/Pins 23, 15): Top Gate
at one point. Pin 29 is the Exposed Pad, only available on Driver Outputs. These are the outputs of floating drivers
the UF package. with a voltage swing equal to INTVCC superimposed on
the switch nodes voltages.
EXTVCC (Pin 14, LTC3850-1 Only/Pin 11/Pin 12): External
Power Input to an Internal Switch Connected to INTVCC. SW1, SW2 (Pins 26, 16/Pins 23, 13/Pins 24, 14):
This switch closes and supplies the IC power, bypassing Switch Node Connections to Inductors. Voltage swing
the internal low dropout regulator, whenever EXTVCC is at these pins are from a body diode voltage drop below
higher than 4.7V. Do not exceed 6V on this pin and ensure ground to VIN.
Rev. D

LTC3850/LTC3850-1
PIN FUNCTIONS
MODE/PLLIN (Pin 27/Pin 24/Pin 25): Force Continuous FREQ/PLLFLTR (Pin 28/Pin 25/Pin 26): The Phase-Locked
Mode, Burst Mode, or Pulse-Skipping Mode Selection Loop’s Low-Pass Filter is Tied to This Pin. Alternatively,
Pin and External Synchronization Input to Phase Detector this pin can be driven with a DC voltage to vary the fre-
Pin. Connect this pin to SGND to force both channels into quency of the internal oscillator.
the continuous mode of operation. Connect to INTVCC Exposed Pad (Pin 29, UF/UFD Packages Only): Signal
to enable pulse-skipping mode of operation. Leaving the Ground. Must be soldered to PCB, providing a local
pin floating will enable Burst Mode operation. A clock on ground for the control components of the IC, and be tied
the pin will force the controller into continuous mode of to the PGND pin under the IC.
operation and synchronize the internal oscillator.
FUNCTIONAL DIAGRAM
FREQ/PLLFLTR MODE/PLLIN EXTVCC VIN
VIN
4.7V
+
CIN
– +
F
MODE/SYNC 0.8V 5V
DETECT REG
PLL-SYNC – + INTVCC
INTVCC
F
BOOST
OSC S BURSTEN
TG CB
R Q FCNT
M1
SW L1
ON SWITCH VOUT
3k
LOGIC
+ – AND SENSE+ DB
ICMP IREV ANTI-
SHOOT
– + THROUGH SENSE–
+
RUN COUT
BG
OV
M2
CVCC
ILIM SLOPE COMPENSATION
PGND
PGOOD
INTVCC UVLO
+ 0.74V
1 SLOPE RECOVERY R2
UV VFB
51k ACTIVE CLAMP
ITHB –
VIN SLEEP +
R1
OV
– 0.86V
0.8V – SS + – RUN + SGND
REF EA 1.3µA
– + – + +
0.64V 1.2V
0.55V 0.5µA
38501 FD
CC1 CSS
ITH RC RUN TK/SS
Rev. D

LTC3850/LTC3850-1
OPERATION
Main Control Loop Shutdown and Start-Up (RUN1, RUN2 and TK/SS1,
TK/SS2 Pins)
The LTC3850 is a constant-frequency, current mode step-
down controller with two channels operating 180 degrees The two channels of the LTC3850 can be independently
out-of-phase. During normal operation, each top MOSFET shut down using the RUN1 and RUN2 pins. Pulling either
is turned on when the clock for that channel sets the RS of these pins below 1.2V shuts down the main control
latch, and turned off when the main current comparator, loop for that controller. Pulling both pins low disables
ICMP, resets the RS latch. The peak inductor current at both controllers and most internal circuits, including the
which ICMP resets the RS latch is controlled by the voltage INTVCC regulator. Releasing either RUN pin allows an
on the ITH pin, which is the output of each error ampli- internal 0.5µA current to pull up the pin and enable that
fier EA. The VFB pin receives the voltage feedback signal, controller. Alternatively, the RUN pin may be externally
which is compared to the internal reference voltage by the pulled up or driven directly by logic. Be careful not to
EA. When the load current increases, it causes a slight exceed the Absolute Maximum Rating of 6V on this pin.
decrease in VFB relative to the 0.8V reference, which in The start-up of each controller’s output voltage VOUT is
turn causes the ITH voltage to increase until the average controlled by the voltage on the TK/SS1 and TK/SS2 pins.
inductor current matches the new load current. After the When the voltage on the TK/SS pin is less than the 0.8V
top MOSFET has turned off, the bottom MOSFET is turned internal reference, the LTC3850 regulates the VFB voltage
on until either the inductor current starts to reverse, as to the TK/SS pin voltage instead of the 0.8V reference.
indicated by the reverse current comparator IREV, or the This allows the TK/SS pin to be used to program a soft-
beginning of the next cycle. start by connecting an external capacitor from the TK/SS
pin to SGND. An internal 1.3µA pull-up current charges
INTVCC/EXTVCC Power
this capacitor, creating a voltage ramp on the TK/SS pin.
Power for the top and bottom MOSFET drivers and most As the TK/SS voltage rises linearly from 0V to 0.8V (and
other internal circuitry is derived from the INTVCC pin. beyond), the output voltage VOUT rises smoothly from zero
When the EXTVCC pin is left open or tied to a voltage less to its final value. Alternatively the TK/SS pin can be used to
than 4.7V, an internal 5V linear regulator supplies INTVCC cause the start-up of VOUT to “track” that of another sup-
power from VIN. If EXTVCC is taken above 4.7V, the 5V ply. Typically, this requires connecting to the TK/SS pin an
regulator is turned off and an internal switch is turned external resistor divider from the other supply to ground
on connecting EXTVCC. Using the EXTVCC pin allows the (see the Applications Information section). When the cor-
INTVCC power to be derived from a high efficiency external responding RUN pin is pulled low to disable a control-
source such as one of the LTC3850 switching regulator ler, or when INTVCC drops below its undervoltage lockout
outputs. threshold of 3V, the TK/SS pin is pulled low by an internal
Each top MOSFET driver is biased from the floating boot- MOSFET. When in undervoltage lockout, both controllers
strap capacitor CB, which normally recharges during each are disabled and the external MOSFETs are held off.
off cycle through an external diode when the top MOSFET
Light Load Current Operation (Burst Mode Operation,
turns off. If the input voltage VIN decreases to a voltage
Pulse-Skipping, or Continuous Conduction)
close to VOUT, the loop may enter dropout and attempt
to turn on the top MOSFET continuously. The dropout The LTC3850 can be enabled to enter high efficiency
detector detects this and forces the top MOSFET off for Burst Mode operation, constant-frequency pulse-skip-
about one-twelfth of the clock period every third cycle to ping mode, or forced continuous conduction mode. To
allow CB to recharge. However, it is recommended that a select forced continuous operation, tie the MODE/PLLIN
load be present during the drop-out transition to ensure pin to a DC voltage below 0.8V (e.g., SGND). To select
CB is recharged. pulse-skipping mode of operation, tie the MODE/PLLIN
pin to INTVCC. To select Burst Mode operation, float the
Rev. D

LTC3850/LTC3850-1
OPERATION
MODE/PLLIN pin. When a controller is enabled for Burst Frequency Selection and Phase-Locked Loop
Mode operation, the peak current in the inductor is set to (FREQ/PLLFLTR and MODE/PLLIN Pins)
approximately one-third of the maximum sense voltage The selection of switching frequency is a trade-off
even though the voltage on the ITH pin indicates a lower between efficiency and component size. Low frequency
value. If the average inductor current is higher than the operation increases efficiency by reducing MOSFET
load current, the error amplifier EA will decrease the volt- switching losses, but requires larger inductance and/or
age on the ITH pin. When the ITH voltage drops below capacitance to maintain low output ripple voltage. The
0.5V, the internal sleep signal goes high (enabling “sleep” switching frequency of the LTC3850’s controllers can be
mode) and both external MOSFETs are turned off. selected using the FREQ/PLLFLTR pin. If the MODE/PLLIN
In sleep mode, the load current is supplied by the output pin is not being driven by an external clock source, the
capacitor. As the output voltage decreases, the EA’s output FREQ/PLLFLTR pin can be used to program the control-
begins to rise. When the output voltage drops enough, ler’s operating frequency from 250kHz to 780kHz.
the sleep signal goes low, and the controller resumes A phase-locked loop (PLL) is available on the LTC3850
normal operation by turning on the top external MOSFET to synchronize the internal oscillator to an external clock
on the next cycle of the internal oscillator. When a con- source that is connected to the MODE/PLLIN pin. The con-
troller is enabled for Burst Mode operation, the induc- troller is operating in forced continuous mode when it is
tor current is not allowed to reverse. The reverse current synchronized. A series R-C should be connected between
comparator (IREV) turns off the bottom external MOSFET the FREQ/PLLFLTR pin and SGND to serve as the PLL’s
just before the inductor current reaches zero, preventing loop filter.
it from reversing and going negative. Thus, the controller
operates in discontinuous operation. In forced continuous Power Good (PGOOD Pin)
operation, the inductor current is allowed to reverse at
light loads or under large transient conditions. The peak The PGOOD pin is connected to an open drain of an inter-
inductor current is determined by the voltage on the ITH nal N-channel MOSFET. The MOSFET turns on and pulls
pin, just as in normal operation. In this mode, the effi- the PGOOD pin low when either VFB pin voltage is not
ciency at light loads is lower than in Burst Mode operation. within ±7.5% of the 0.8V reference voltage. The PGOOD
However, continuous mode has the advantages of lower pin is also pulled low when either RUN pin is below 1.2V
output ripple and less interference with audio circuitry. or when the LTC3850 is in the soft-start or tracking phase.
When the VFB pin voltage is within the ±7.5% requirement,
When the MODE/PLLIN pin is connected to INTVCC, the the MOSFET is turned off and the pin is allowed to be
LTC3850 operates in PWM pulse-skipping mode at light pulled up by an external resistor to a source of up to 6V.
loads. At very light loads, the current comparator ICMP The PGOOD pin will flag power good immediately when
may remain tripped for several cycles and force the exter- both VFB pins are within the ±7.5% window. However,
nal top MOSFET to stay off for the same number of cycles there is an internal 17µs power bad mask when either VFB
(i.e., skipping pulses). The inductor current is not allowed goes out of the ±7.5% window.
to reverse (discontinuous operation). This mode, like
forced continuous operation, exhibits low output ripple Output Overvoltage Protection
as well as low audio noise and reduced RF interference
An overvoltage comparator, OV, guards against transient
as compared to Burst Mode operation. It provides higher
overshoots (> 7.5%) as well as other more serious con-
low current efficiency than forced continuous mode, but
ditions that may overvoltage the output. In such cases,
not nearly as high as Burst Mode operation.
the top MOSFET is turned off and the bottom MOSFET is
turned on until the overvoltage condition is cleared.
Rev. D

LTC3850/LTC3850-1
APPLICATIONS INFORMATION
The Typical Application on the first page is a basic LTC3850 SENSE+ and SENSE– Pins
application circuit. LTC3850 can be configured to use either
The SENSE+ and SENSE– pins are the inputs to the current
DCR (inductor resistance) sensing or low value resistor
comparators. The common mode input voltage range of
sensing. The choice between the two current sensing
the current comparators is 0V to 5V. Both SENSE pins
schemes is largely a design trade-off between cost, power
are high impedance inputs with small base currents of
consumption, and accuracy. DCR sensing is becoming
less than 1µA. When the SENSE pins ramp up from 0V
popular because it saves expensive current sensing resis-
to 1.4V, the small base currents flow out of the SENSE
tors and is more power efficient, especially in high current
pins. When the SENSE pins ramp down from 5V to 1.1V,
applications. However, current sensing resistors provide
the small base currents flow into the SENSE pins. The
the most accurate current limits for the controller. Other
high impedance inputs to the current comparators allow
external component selection is driven by the load require-
accurate DCR sensing. However, care must be taken not
ment, and begins with the selection of RSENSE (if RSENSE is
to float these pins during normal operation.
used) and inductor value. Next, the power MOSFETs are
selected. Finally, input and output capacitors are selected. Filter components mutual to the sense lines should be
placed close to the LTC3850, and the sense lines should
Current Limit Programming run close together to a Kelvin connection underneath the
The ILIM pin is a tri-level logic input which sets the maxi- current sense element (shown in Figure 1). Sensing cur-
mum current limit of the controller. When ILIM is either rent elsewhere can effectively add parasitic inductance
grounded, floated or tied to INTVCC, the typical value for and capacitance to the current sense element, degrading
the maximum current sense threshold will be 30mV, the information at the sense terminals and making the
50mV or 75mV, respectively. programmed current limit unpredictable. If DCR sensing
is used (Figure 2b), sense resistor R1 should be placed
Which setting should be used? For the best current limit
accuracy, use the 75mV setting. The 30mV setting will TO SENSE FILTER,
NEXT TO THE CONTROLLER
allow for the use of very low DCR inductors or sense
resistors, but at the expense of current limit accuracy. COUT
The 50mV setting is a good balance between the two. For INDUCTOR OR RSENSE 38501 F01
single output dual phase applications (see Figure 21), use Figure 1. Sense Lines Placement
the 50mV or 75mV setting for optimal current sharing. with Inductor or Sense Resistor
VIN VIN VIN VIN

INTVCC INTVCC
SENSE RESISTOR BOOST

BOOST PLUS PARASITIC INDUCTOR
TG
TG INDUCTANCE
SW L DCR VOUT
SW RS ESL VOUT LTC3850
LTC3850
BG
BG CF • 2RF ≤ ESL/RS PGND
PGND POLE-ZERO
CANCELLATION R1
RF SENSE+
SENSE+
C1* R2
CF
SENSE– SENSE–
SGND RF SGND
38501 F02a 38501 F02b
L R2
FILTER COMPONENTS *PLACE C1 NEAR SENSE+, R1||R2 × C1 = RSENSE(EQ) = DCR
DCR R1 + R2
PLACED NEAR SENSE PINS SENSE– PINS
(2a) Using a Resistor to Sense Current (2b) Using the Inductor DCR to Sense Current
Figure 2. Two Different Methods of Sensing Current
Rev. D

LTC3850/LTC3850-1
close to the switching node, to prevent noise from cou- inductive noise coupled in the sense traces on the PCB.
pling into sensitive small-signal nodes. The capacitor C1 A typical filter consists of two series 10Ω resistors con-
should be placed close to the IC pins. nected to a parallel 1000pF capacitor, resulting in a time
constant of 20ns.
Low Value Resistors Current Sensing
This same RC filter, with minor modifications, can be
A typical sensing circuit using a discrete resistor is used to extract the resistive component of the current
shown in Figure 2a. RSENSE is chosen based on the sense signal in the presence of parasitic inductance.
required output current. For example, Figure 3 illustrates the voltage waveform
The current comparator has a maximum threshold across a 2mΩ sense resistor with a 2010 footprint for
VSENSE(MAX) determined by the ILIM setting. The input the 1.2V/15A converter shown in Figure 18 operating at
common mode range of the current comparator is 0V to 100% load. The waveform is the superposition of a purely
5V. The current comparator threshold sets the peak of resistive component and a purely inductive component.
the inductor current, yielding a maximum average output It was measured using two scope probes and waveform
current IMAX equal to the peak value less half the peak-to- math to obtain a differential measurement. Based on addi-
peak ripple current, ∆IL. To calculate the sense resistor tional measurements of the inductor ripple current and the
value, use the equation: on-time and off-time of the top switch, the value of the
parasitic inductance was determined to be 0.5nH using
VSENSE(MAX) the equation:
RSENSE =
ΔI
I(MAX) + L VESL(STEP) tON • tOFF
2 ESL =
ΔIL tON + tOFF
Because of possible PCB noise in the current sensing
loop, the AC current sensing ripple of ∆VSENSE = ∆IL • If the RC time constant is chosen to be close to the para-
RSENSE also needs to be checked in the design to get a sitic inductance divided by the sense resistor (L/R), the
good signal-to-noise ratio. In general, for a reasonably resulting waveform looks resistive again, as shown in
good PCB layout, a 15mV ∆VSENSE voltage is recom- Figure 4. For applications using low maximum sense
mended as a conservative number to start with, either voltages, check the sense resistor manufacturer’s data
for RSENSE or DCR sensing applications. sheet for information about parasitic inductance. In the
absence of data, measure the voltage drop directly across
For previous generation current mode controllers, the
the sense resistor to extract the magnitude of the ESL
maximum sense voltage was high enough (e.g., 75mV
step and use the equation above to determine the ESL.
for the LTC1628 / LTC3728 family) that the voltage drop
However, do not over-filter. Keep the RC time constant less
across the parasitic inductance of the sense resistor repre-
than or equal to the inductor time constant to maintain a
sented a relatively small error. For today’s highest current
high enough ripple voltage on VRSENSE.
density solutions, however, the value of the sense resistor
can be less than 1mΩ and the peak sense voltage can The above generally applies to high density / high cur-
be as low as 20mV. In addition, inductor ripple currents rent applications where I(MAX) > 10A and low values of
greater than 50% with operation up to 1MHz are becom- inductors are used. For applications where I(MAX) < 10A,
ing more common. Under these conditions the voltage set RF to 10 Ohms and CF to 1000pF. This will provide a
drop across the sense resistor’s parasitic inductance is no good starting point.
longer negligible. A typical sensing circuit using a discrete The filter components need to be placed close to the
resistor is shown in Figure 2a. In previous generations IC. The positive and negative sense traces need to be
of controllers, a small RC filter placed near the IC was routed as a differential pair and Kelvin connected to the
commonly used to reduce the effects of capacitive and sense resistor.
Rev. D

LTC3850/LTC3850-1
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
VSENSE(MAX)
RSENSE(EQUIV) =
ΔI
VESL(STEP) I(MAX) + L
2
VSENSE
20mV/DIV
To ensure that the application will deliver full load cur-
38501 F03 rent over the full operating temperature range, choose
500ns/DIV
the minimum value for the Maximum Current Sense
Figure 3. Voltage Waveform Measured Threshold (VSENSE(MAX)) in the Electrical Characteristics
Directly Across the Sense Resistor.
table (20mV, 40mV, or 60mV, depending on the state of
the ILIM pin).
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given
at 20°C. Increase this value to account for the tempera-
VSENSE
ture coefficient of resistance, which is approximately
20mV/DIV 0.4%/°C. A conservative value for TL(MAX) is 100°C.
38501 F04
To scale the maximum inductor DCR to the desired sense
500ns/DIV
resistor value, use the divider ratio:
Figure 4. Voltage Waveform Measured After the R SENSE(EQUIV)
Sense Resistor Filter. CF = 1000pF, RF = 100Ω. RD =
DCR (MAX) at TL(MAX)

Inductor DCR Sensing
For applications requiring the highest possible efficiency C1 is usually selected to be in the range of 0.047µF to
at high load currents, the LTC3850 is capable of sensing 0.47µF. This forces R1 || R2 to around 2kΩ, reducing
the voltage drop across the inductor DCR, as shown in error that might have been caused by the SENSE pins’
Figure 2b. The DCR of the inductor represents the small ±1µA current.
amount of DC winding resistance of the copper, which can The equivalent resistance R1|| R2 is scaled to the room
be less than 1mΩ for today’s low value, high current induc- temperature inductance and maximum DCR:
tors. In a high current application requiring such an inductor, L
conduction loss through a sense resistor would cost several R1||R2 =
(DCR at 20°C) • C1
points of efficiency compared to DCR sensing.
If the external R1||R2 • C1 time constant is chosen to be The sense resistor values are:
exactly equal to the L/DCR time constant, the voltage drop R1|| R2 R1• RD
across the external capacitor is equal to the drop across R1= ; R2 =
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the RD 1−RD

voltage across the sense terminals for applications where
The maximum power loss in R1 is related to duty cycle,
the DCR is greater than the target sense resistor value. To
and will occur in continuous mode at the maximum
properly dimension the external filter components, the DCR
input voltage:
of the inductor must be known. It can be measured using
a good RLC meter, but the DCR tolerance is not always the
same and varies with temperature; consult the manufactur- PLOSS R1=
( VIN(MAX) − VOUT ) • VOUT
R1
ers’ data sheets for detailed information.
Rev. D

LTC3850/LTC3850-1
Ensure that R1 has a power rating higher than this value. A reasonable starting point is to choose a ripple current
If high efficiency is necessary at light loads, consider this that is about 40% of IOUT(MAX). Note that the largest ripple
power loss when deciding whether to use DCR sensing or current occurs at the highest input voltage. To guarantee
sense resistors. Light load power loss can be modestly that ripple current does not exceed a specified maximum,
higher with a DCR network than with a sense resistor, the inductor should be chosen according to:
due to the extra switching losses incurred through R1. V –V V
However, DCR sensing eliminates a sense resistor, L ≥ IN OUT • OUT
fOSC •IRIPPLE VIN
reduces conduction losses and provides higher efficiency
at heavy loads. Peak efficiency is about the same with
Inductor Core Selection
either method.
Once the inductance value is determined, the type of
To maintain a good signal to noise ratio for the current
inductor must be selected. Core loss is independent of
sense signal, use a minimum ∆VSENSE of 10mV to 15mV.
core size for a fixed inductor value, but it is very depen-
For a DCR sensing application, the actual ripple voltage
dent on inductance selected. As inductance increases,
will be determined by the equation:
core losses go down. Unfortunately, increased inductance
VIN − VOUT VOUT requires more turns of wire and therefore copper losses
ΔVSENSE =
R1•C1 VIN • fOSC will increase.

Ferrite designs have very low core loss and are preferred
Slope Compensation and Inductor Peak Current at high switching frequencies, so design goals can con-
Slope compensation provides stability in constant- centrate on copper loss and preventing saturation. Ferrite
frequency architectures by preventing subharmonic core material saturates “hard,” which means that induc-
oscillations at high duty cycles. It is accomplished inter- tance collapses abruptly when the peak design current is
nally by adding a compensating ramp to the inductor exceeded. This results in an abrupt increase in inductor
current signal at duty cycles in excess of 40%. Normally, ripple current and consequent output voltage ripple. Do
this results in a reduction of maximum inductor peak cur- not allow the core to saturate!
rent for duty cycles > 40%. However, the LTC3850 uses Power MOSFET and Schottky Diode
a patented scheme that counteracts this compensating (Optional) Selection
ramp, which allows the maximum inductor peak current
Two external power MOSFETs must be selected for each
to remain unaffected throughout all duty cycles.
controller in the LTC3850: one N-channel MOSFET for
Inductor Value Calculation the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
Given the desired input and output voltages, the inductor
value and operating frequency fOSC directly determine the The peak-to-peak drive levels are set by the INTVCC
inductor’s peak-to-peak ripple current: voltage. This voltage is typically 5V during start-up
(see EXTVCC Pin Connection). Consequently, logic-level
VOUT ⎛ VIN – VOUT ⎞ threshold MOSFETs must be used in most applications.
IRIPPLE =
VIN ⎜⎝ fOSC •L ⎟⎠ The only exception is if low input voltage is expected (VIN
< 5V); then, sub-logic level threshold MOSFETs (VGS(TH)
Lower ripple current reduces core losses in the inductor, < 3V) should be used. Pay close attention to the BVDSS
ESR losses in the output capacitors, and output voltage specification for the MOSFETs as well; most of the logic
ripple. Thus, highest efficiency operation is obtained at level MOSFETs are limited to 30V or less.
low frequency with a small ripple current. Achieving this,
however, requires a large inductor. Selection criteria for the power MOSFETs include the
on-resistance RDS(ON) , Miller capacitance CMILLER, input
Rev. D

LTC3850/LTC3850-1
voltage and maximum output current. Miller capacitance, or during a short-circuit when the synchronous switch is
CMILLER, can be approximated from the gate charge curve on close to 100% of the period.
usually provided on the MOSFET manufacturers’ data
The term (1 + d) is generally given for a MOSFET in the
sheet. CMILLER is equal to the increase in gate charge
form of a normalized RDS(ON) vs Temperature curve, but
along the horizontal axis while the curve is approximately
d = 0.005/°C can be used as an approximation for low
flat divided by the specified change in VDS. This result is
voltage MOSFETs.
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is The optional Schottky diodes conduct during the dead
operating in continuous mode the duty cycles for the top time between the conduction of the two power MOSFETs.
and bottom MOSFETs are given by: These prevent the body diodes of the bottom MOSFETs
V from turning on, storing charge during the dead time and
Main Switch Duty Cycle = OUT requiring a reverse recovery period that could cost as
VIN
much as 3% in efficiency at high VIN. A 1A to 3A Schottky
V –V
Synchronous Switch Duty Cycle = IN OUT
is generally a good compromise for both regions of oper-
VIN ation due to the relatively small average current. Larger
diodes result in additional transition losses due to their
The MOSFET power dissipations at maximum output cur- larger junction capacitance.
rent are given by:
VOUT Soft-Start and Tracking
PMAIN =
VIN
(IMAX )2 (1+ δ )RDS(ON) +
The LTC3850 has the ability to either soft-start by itself
with a capacitor or track the output of another channel
( VIN )2 ⎛⎜⎝ IMAX
2 ⎠
⎞
⎟ (RDR ) (CMILLER ) • or external supply. When one particular channel is con-
figured to soft-start by itself, a capacitor should be con-
⎡ 1 1 ⎤ nected to its TK/SS pin. This channel is in the shutdown
⎢ + ⎥ • fOSC
⎢⎣ VINTVCC – VTH(MIN) VTH(MIN) ⎥⎦ state if its RUN pin voltage is below 1.2V. Its TK/SS pin is
actively pulled to ground in this shutdown state.
Once the RUN pin voltage is above 1.2V, the channel pow-
V –V ers up. A soft-start current of 1.3µA then starts to charge
PSYNC = IN OUT (IMAX ) (1+ δ )RDS(ON)
2
VIN its soft-start capacitor. Note that soft-start or tracking is

achieved not by limiting the maximum output current of
where d is the temperature dependency of RDS(ON) and the controller but by controlling the output ramp voltage
RDR (approximately 2Ω) is the effective driver resistance according to the ramp rate on the TK/SS pin. Current
at the MOSFET’s Miller threshold voltage. VTH(MIN) is the foldback is disabled during this phase to ensure smooth
typical MOSFET minimum threshold voltage. soft-start or tracking. The soft-start or tracking range is
Both MOSFETs have I2R losses while the topside N-channel defined to be the voltage range from 0V to 0.8V on the
equation includes an additional term for transition losses, TK/SS pin. The total soft-start time can be calculated as:
which are highest at high input voltages. For VIN < 20V C SS
the high current efficiency generally improves with larger t SOFTSTART = 0.8 •
1.3µA
MOSFETs, while for VIN > 20V the transition losses rap-
idly increase to the point that the use of a higher RDS(ON) Regardless of the mode selected by the MODE/PLLIN pin,
device with lower CMILLER actually provides higher effi- the regulator will always start in pulse-skipping mode up
ciency. The synchronous MOSFET losses are greatest at to TK/SS = 0.64V. Between TK/SS = 0.64V and 0.74V, it
high input voltage when the top switch duty factor is low will operate in forced continuous mode and revert to the
Rev. D

LTC3850/LTC3850-1
selected mode once TK/SS > 0.74V. The output ripple is some tradeoffs exist. The ratiometric mode saves a pair
minimized during the 100mV forced continuous mode of resistors, but the coincident mode offers better output
window ensuring a clean PGOOD signal. regulation. This can be better understood with the help
of Figure 7. At the input stage of the slave channel’s error
When the channel is configured to track another supply,
amplifier, two common anode diodes are used to clamp
the feedback voltage of the other supply is duplicated by
the equivalent reference voltage and an additional diode
a resistor divider and applied to the TK/SS pin. Therefore,
is used to match the shifted common mode voltage. The
the voltage ramp rate on this pin is determined by the
top two current sources are of the same amplitude. In the
ramp rate of the other supply’s voltage. Note that the
coincident mode, the TK/SS voltage is substantially higher
small soft-start capacitor charging current is always
than 0.8V at steady state and effectively turns off D1. D2
flowing, producing a small offset error. To minimize this
and D3 will therefore conduct the same current and offer
error, select the tracking resistive divider value to be small
tight matching between VFB2 and the internal precision
enough to make this error negligible.
0.8V reference. In the ratiometric mode, however, TK/SS
In order to track down another channel or supply after equals 0.8V at steady state. D1 will divert part of the bias
the soft-start phase expires, the LTC3850 is forced into current to make VFB2 slightly lower than 0.8V.
continuous mode of operation as soon as VFB is below the
undervoltage threshold of 0.74V regardless of the setting Although this error is minimized by the exponential I-V
on the MODE/PLLIN pin. However, the LTC3850 should characteristic of the diode, it does impose a finite amount
always be set in force continuous mode tracking down of output voltage deviation. Furthermore, when the master
when there is no load. After TK/SS drops below 0.1V, its channel’s output experiences dynamic excursion (under
channel will operate in discontinuous mode. load transient, for example), the slave channel output will
be affected as well. For better output regulation, use the
Output Voltage Tracking coincident tracking mode instead of ratiometric.
The LTC3850 allows the user to program how its out- INTVCC Regulators and EXTVCC
put ramps up and down by means of the TK/SS pins.
Through these pins, the output can be set up to The LTC3850 features an NPN linear regulator that sup-
either coincidentally or ratiometrically track another plies power to INTVCC from the VIN supply. INTVCC pow-
supply’s output, as shown in Figure 5. In the following ers the gate drivers and much of the LTC3850’s internal
discussions, VOUT1 refers to the LTC3850’s output 1 as a circuitry. The linear regulator regulates the voltage at the
master channel and VOUT2 refers to the LTC3850’s output INTVCC pin to 5V when VIN is greater than 6.5V. EXTVCC
2 as a slave channel. In practice, though, either phase can connects to INTVCC through a P-channel MOSFET and can
be used as the master. To implement the coincident track- supply the needed power when its voltage is higher than
ing in Figure 5a, connect an additional resistive divider to 4.7V. Each of these can supply a peak current of 100mA
VOUT1 and connect its midpoint to the TK/SS pin of the and must be bypassed to ground with a minimum of 1µF
slave channel. The ratio of this divider should be the same ceramic capacitor or low ESR electrolytic capacitor. No
as that of the slave channel’s feedback divider shown in matter what type of bulk capacitor is used, an additional
Figure 6a. In this tracking mode, VOUT1 must be set higher 0.1µF ceramic capacitor placed directly adjacent to the
than VOUT2. To implement the ratiometric tracking, the INTVCC and PGND pins is highly recommended. Good
ratio of the VOUT2 divider should be exactly the same as bypassing is needed to supply the high transient currents
the master channel’s feedback divider. By selecting differ- required by the MOSFET gate drivers and to prevent inter-
ent resistors, the LTC3850 can achieve different modes action between the channels.
of tracking including the two in Figure 5. High input voltage applications in which large MOSFETs
So which mode should be programmed? While either are being driven at high frequencies may cause the maxi-
mode in Figure 5 satisfies most practical applications, mum junction temperature rating for the LTC3850 to be
Rev. D

LTC3850/LTC3850-1
VOUT1 VOUT1
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VOUT2 VOUT2
TIME 38501 F03a TIME 38501 F03b
(5a) Coincident Tracking (5b) Ratiometric Tracking
Figure 5. Two Different Modes of Output Voltage Tracking
VOUT1 VOUT2 VOUT1 VOUT2

R3 R1 R3 R1 R3
TO TO TO TO TO
TK/SS2 VFB1 VFB2 TK/SS2 TO VFB2
PIN PIN PIN PIN VFB1 PIN
R4 R2 R4 PIN R4
R2
38501 F06
(6a) Coincident Tracking Setup (6b) Ratiometric Tracking Setup
Figure 6. Setup for Coincident and Ratiometric Tracking
I I
+
D1 D2 EA2
TK/SS2
–
0.8V
D3
VFB2
38501 F07
Figure 7. Equivalent Input Circuit of Error Amplifier
Rev. D

LTC3850/LTC3850-1
exceeded. The INTVCC current, which is dominated by the 1. EXTVCC left open (or grounded). This will cause
gate charge current, may be supplied by either the 5V lin- INTVCC to be powered from the internal 5V regulator
ear regulator or EXTVCC. When the voltage on the EXTVCC resulting in an efficiency penalty of up to 10% at high
pin is less than 4.7V, the linear regulator is enabled. Power input voltages.
dissipation for the IC in this case is highest and is equal 2. EXTVCC connected directly to VOUT. This is the
to VIN • IINTVCC. The gate charge current is dependent normal connection for a 5V regulator and provides
on operating frequency as discussed in the Efficiency the highest efficiency.
Considerations section. The junction temperature can
be estimated by using the equations given in Note 3 of 3. EXTVCC connected to an external supply. If a 5V
the Electrical Characteristics. For example, the LTC3850 external supply is available, it may be used to power
INTVCC current is limited to less than 24mA from a 24V EXTVCC providing it is compatible with the MOSFET
supply in the GN package and not using the EXTVCC supply: gate drive requirements.
TJ = 70°C + (24mA)(24V)(95°C/W) = 125°C 4. EXTVCC connected to an output-derived boost net-
work. For 3.3V and other low voltage regulators,
To prevent the maximum junction temperature from efficiency gains can still be realized by connecting
being exceeded, the input supply current must be EXTVCC to an output-derived voltage that has been
checked while operating in continuous conduction mode
boosted to greater than 4.7V.
(MODE/PLLIN = SGND) at maximum VIN. When the
voltage applied to EXTVCC rises above 4.7V, the INTVCC For applications where the main input power is 5V, tie
linear regulator is turned off and the EXTVCC is con- the VIN and INTVCC pins together and tie the combined
nected to the INTVCC. The EXTVCC remains on as long pins to the 5V input with a 1Ω or 2.2Ω resistor as shown
as the voltage applied to EXTVCC remains above 4.5V. in Figure 8 to minimize the voltage drop caused by the
Using the EXTVCC allows the MOSFET driver and con- gate charge current. This will override the INTVCC linear
trol power to be derived from one of the LTC3850’s regulator and will prevent INTVCC from dropping too low
switching regulator outputs during normal operation and due to the dropout voltage. Make sure the INTVCC voltage
from the INTVCC when the output is out of regulation is at or exceeds the RDS(ON) test voltage for the MOSFET
(e.g., start-up, short-circuit). If more current is required which is typically 4.5V for logic level devices.
through the EXTVCC than is specified, an external Schottky
diode can be added between the EXTVCC and INTVCC pins.
Do not apply more than 6V to the EXTVCC pin and make LTC3850
VIN
RVIN
sure that EXTVCC < VIN. INTVCC 5V
CINTVCC 1Ω
Significant efficiency and thermal gains can be realized +
4.7µF CIN
by powering INTVCC from the output, since the VIN cur-
rent resulting from the driver and control currents will be 38501 F08
scaled by a factor of (Duty Cycle)/(Switcher Efficiency). Figure 8. Setup for a 5V Input

Tying the EXTVCC pin to a 5V supply reduces the junction
temperature in the previous example from 125°C to: Topside MOSFET Driver Supply (CB, DB)
TJ = 70°C + (24mA)(5V)(95°C/W) = 81°C External bootstrap capacitors CB connected to the

BOOST pins supply the gate drive voltages for the top-
However, for 3.3V and other low voltage outputs, addi- side MOSFETs. Capacitor CB in the Functional Diagram
tional circuitry is required to derive INTVCC power from is charged though external diode DB from INTVCC when
the output. the SW pin is low. When one of the topside MOSFETs is
The following list summarizes the four possible connec- to be turned on, the driver places the CB voltage across
tions for EXTVCC: the gate source of the desired MOSFET. This enhances
Rev. D

LTC3850/LTC3850-1
the MOSFET and turns on the topside switch. The switch a factor of 30% to 70% when compared to a single phase
node voltage, SW, rises to VIN and the BOOST pin follows. power supply solution.
With the topside MOSFET on, the boost voltage is above In continuous mode, the source current of the top MOSFET
the input supply: VBOOST = VIN + VINTVCC. The value of the is a square wave of duty cycle (VOUT)/(VIN). To prevent
boost capacitor CB needs to be 100 times that of the total large voltage transients, a low ESR capacitor sized for the
input capacitance of the topside MOSFET(s). The reverse maximum RMS current of one channel must be used. The
breakdown of the external Schottky diode must be greater maximum RMS capacitor current is given by:
than VIN(MAX). When adjusting the gate drive level, the
final arbiter is the total input current for the regulator. If IMAX 1/2
CIN Required IRMS ≈ ⎡⎣( VOUT ) ( VIN – VOUT ) ⎤⎦
a change is made and the input current decreases, then VIN
the efficiency has improved. If there is no change in input
current, then there is no change in efficiency. This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
Undervoltage Lockout used for design because even significant deviations do
not offer much relief. Note that capacitor manufacturers’
The LTC3850 has two functions that help protect the con- ripple current ratings are often based on only 2000 hours
troller in case of undervoltage conditions. A precision of life. This makes it advisable to further derate the capaci-
UVLO comparator constantly monitors the INTVCC voltage tor, or to choose a capacitor rated at a higher temperature
to ensure that an adequate gate-drive voltage is present. than required. Several capacitors may be paralleled to
It locks out the switching action when INTVCC is below meet size or height requirements in the design. Due to
3V. To prevent oscillation when there is a disturbance on the high operating frequency of the LTC3850, ceramic
the INTVCC, the UVLO comparator has 500mV of preci- capacitors can also be used for CIN. Always consult the
sion hysteresis. manufacturer if there is any question.
Another way to detect an undervoltage condition is to The benefit of the LTC3850 2-phase operation can be
monitor the VIN supply. Because the RUN pins have a calculated by using the equation above for the higher
precision turn-on reference of 1.2V, one can use a resistor power controller and then calculating the loss that would
divider to VIN to turn on the IC when VIN is high enough. have resulted if both controller channels switched on at
An extra 4.5µA of current flows out of the RUN pin once the same time. The total RMS power lost is lower when
the RUN pin voltage passes 1.2V. One can program the both controllers are operating due to the reduced overlap
hysteresis of the run comparator by adjusting the values of current pulses required through the input capacitor’s
of the resistive divider. For accurate VIN undervoltage ESR. This is why the input capacitor’s requirement cal-
detection, VIN needs to be higher than 4V. culated above for the worst-case controller is adequate
for the dual controller design. Also, the input protection
CIN and COUT Selection
fuse resistance, battery resistance, and PC board trace
The selection of CIN is simplified by the 2-phase architecture resistance losses are also reduced due to the reduced
and its impact on the worst-case RMS current drawn through peak currents in a 2-phase system. The overall benefit of
the input network (battery/fuse/capacitor). It can be shown a multiphase design will only be fully realized when the
that the worst-case capacitor RMS current occurs when only source impedance of the power supply/battery is included
one controller is operating. The controller with the highest in the efficiency testing. The sources of the top MOSFETs
(VOUT)(IOUT) product needs to be used in the formula below should be placed within 1cm of each other and share a
to determine the maximum RMS capacitor current require- common CIN(s). Separating the sources and CIN may pro-
ment. Increasing the output current drawn from the other duce undesirable voltage and current resonances at VIN.
controller will actually decrease the input RMS ripple cur-
A small (0.1µF to 1µF) bypass capacitor between the chip
rent from its maximum value. The out-of-phase technique
VIN pin and ground, placed close to the LTC3850, is also
typically reduces the input capacitor’s RMS ripple current by
Rev. D

LTC3850/LTC3850-1
suggested. A 2.2Ω – 10Ω resistor placed between CIN the soft-start or tracking up. Under short-circuit condi-
(C1) and the VIN pin provides further isolation between tions with very low duty cycles, the LTC3850 will begin
the two channels. cycle skipping in order to limit the short-circuit current.
In this situation the bottom MOSFET will be dissipating
The selection of COUT is driven by the effective series
most of the power but less than in normal operation. The
resistance (ESR). Typically, once the ESR requirement
short-circuit ripple current is determined by the minimum
is satisfied, the capacitance is adequate for filtering. The
on-time tON(MIN) of the LTC3850 (≈ 90ns), the input volt-
output ripple (∆VOUT) is approximated by:
age and inductor value:
⎛ 1 ⎞ VIN
ΔVOUT ≈IRIPPLE ⎜ ESR +
⎝ 8fCOUT ⎟⎠ ΔIL(SC) = tON(MIN) •
L

where f is the operating frequency, COUT is the output The resulting short-circuit current is:
capacitance and IRIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage 1/3 VSENSE(MAX) 1
ISC = – ΔIL(SC)
since IRIPPLE increases with input voltage. RSENSE 2
Setting Output Voltage Phase-Locked Loop and Frequency Synchronization

The LTC3850 output voltages are each set by an external The LTC3850 has a phase-locked loop (PLL) comprised of
feedback resistive divider carefully placed across the out- an internal voltage-controlled oscillator (VCO) and a phase
put, as shown in Figure 9. The regulated output voltage detector. This allows the turn-on of the top MOSFET of
is determined by: controller 1 to be locked to the rising edge of an external
⎛ R ⎞ clock signal applied to the MODE/PLLIN pin. The turn-on
VOUT = 0.8V • ⎜ 1+ B ⎟ of controller 2’s top MOSFET is thus 180 degrees out-
⎝ RA ⎠
of-phase with the external clock. The phase detector is
To improve the frequency response, a feed-forward an edge sensitive digital type that provides zero degrees
capacitor, CFF , may be used. Great care should be taken phase shift between the external and internal oscillators.
to route the VFB line away from noise sources, such as This type of phase detector does not exhibit false lock to
the inductor or the SW line. harmonics of the external clock.
VOUT
The output of the phase detector is a pair of complemen-
RB CFF
tary current sources that charge or discharge the external
1/2 LTC3850
filter network connected to the FREQ/PLLFLTR pin. The
VFB
relationship between the voltage on the FREQ/PLLFLTR
RA
pin and operating frequency is shown in Figure 10 and
38501 F09 specified in the Electrical Characteristics table. Note that
Figure 9. Setting Output Voltage the LTC3850 can only be synchronized to an external
clock whose frequency is within range of the LTC3850’s
Fault Conditions: Current Limit and Current Foldback internal VCO. This is guaranteed to be between 250kHz and
The LTC3850 includes current foldback to help limit load 780kHz. A simplified block diagram is shown in Figure 11.
current when the output is shorted to ground. If the out- If no clock is applied to MODE/PLLIN pin, the FREQ/
put falls below 50% of its nominal output level, then the PLLFLTR pin will be high impedance.
maximum sense voltage is progressively lowered from
its maximum programmed value to one-third of the maxi- If the external clock frequency is greater than the inter-
mum value. Foldback current limiting is disabled during nal oscillator’s frequency, fOSC , then current is sourced
Rev. D

LTC3850/LTC3850-1
900 Typically, the external clock (on MODE/PLLIN pin)
800 input high threshold is 1.6V, while the input low threshold
700 is 1V.
600
FREQUENCY (kHz)
500
Minimum On-Time Considerations
400 Minimum on-time tON(MIN) is the smallest time duration
300 that the LTC3850 is capable of turning on the top MOSFET.
200 It is determined by internal timing delays and the gate
100 charge required to turn on the top MOSFET. Low duty
0 cycle applications may approach this minimum on-time
0 0.5 1 1.5 2 2.5
FREQ/PLLFLTR PIN VOLTAGE (V) limit and care should be taken to ensure that
38501 F10
Figure 10. Relationship Between Oscillator V

t ON(MIN) < OUT
Frequency and Voltage at the FREQ/PLLFLTR Pin VIN (f)

2.4V
RLP If the duty cycle falls below what can be accommodated
CLP
by the minimum on-time, the controller will begin to skip
FREQ/ cycles. The output voltage will continue to be regulated,
PLLFLTR
MODE/ but the ripple voltage and current will increase.
PLLIN DIGITAL
EXTERNAL
OSCILLATOR
PHASE/
FREQUENCY The minimum on-time for the LTC3850 is approximately
VCO
DETECTOR 90ns, with reasonably good PCB layout, minimum 30%
inductor current ripple and at least 10mV – 15mV ripple
on the current sense signal. The minimum on-time can be
affected by PCB switching noise in the voltage and current
38501 F11
loop. As the peak sense voltage decreases the minimum
Figure 11. Phase-Locked Loop Block Diagram on-time gradually increases to 130ns. This is of particu-
lar concern in forced continuous applications with low
continuously from the phase detector output, pulling ripple current at light loads. If the duty cycle drops below
up the FREQ/PLLFLTR pin. When the external clock fre- the minimum on-time limit in this situation, a significant
quency is less than fOSC , current is sunk continuously, amount of cycle skipping can occur with correspondingly
pulling down the FREQ/PLLFLTR pin. If the external and larger current and voltage ripple.
internal frequencies are the same but exhibit a phase
difference, the current sources turn on for an amount Efficiency Considerations
of time corresponding to the phase difference. The volt- The percent efficiency of a switching regulator is equal to
age on the FREQ/PLLFLTR pin is adjusted until the phase the output power divided by the input power times 100%.
and frequency of the internal and external oscillators are It is often useful to analyze individual losses to determine
identical. At the stable operating point, the phase detec- what is limiting the efficiency and which change would
tor output is high impedance and the filter capacitor CLP produce the most improvement. Percent efficiency can
holds the voltage. be expressed as:
The loop filter components, CLP and RLP, smooth out the cur- %Efficiency = 100% – (L1 + L2 + L3 + ...)
rent pulses from the phase detector and provide a stable input
to the voltage-controlled oscillator. The filter components CLP where L1, L2, etc. are the individual losses as a percent-
and RLP determine how fast the loop acquires lock. Typically age of input power.
RLP = 10k and CLP is 2200pF to 0.01µF.
Rev. D

LTC3850/LTC3850-1
Although all dissipative elements in the circuit produce and higher currents required by high performance digi-
losses, four main sources usually account for most of the tal systems is not doubling but quadrupling the impor-
losses in LTC3850 circuits: 1) IC VIN current, 2) INTVCC tance of loss terms in the switching regulator system!
regulator current, 3) I2R losses, 4) Topside MOSFET tran- 4. Transition losses apply only to the topside MOSFET(s),
sition losses. and become significant only when operating at high
1. The VIN current is the DC supply current given in input voltages (typically 15V or greater). Transition
the Electrical Characteristics table, which excludes losses can be estimated from:
MOSFET driver and control currents. VIN current typi- Transition Loss = (1.7) VIN2 IO(MAX) CRSS f
cally results in a small (<0.1%) loss.
Other “hidden” losses such as copper trace and internal
2. INTVCC current is the sum of the MOSFET driver and battery resistances can account for an additional 5% to
control currents. The MOSFET driver current results 10% efficiency degradation in portable systems. It is very
from switching the gate capacitance of the power important to include these “system” level losses during
MOSFETs. Each time a MOSFET gate is switched from the design phase. The internal battery and fuse resistance
low to high to low again, a packet of charge dQ moves losses can be minimized by making sure that CIN has
from INTVCC to ground. The resulting dQ/dt is a cur- adequate charge storage and very low ESR at the switch-
rent out of INTVCC that is typically much larger than the ing frequency. A 25W supply will typically require a
control circuit current. In continuous mode, IGATECHG minimum of 20µF to 40µF of capacitance having
= f(QT + QB), where QT and QB are the gate charges of a maximum of 20mΩ to 50mΩ of ESR. The LTC3850
the topside and bottom side MOSFETs. 2-phase architecture typically halves this input capacitance
Supplying INTVCC power through EXTVCC from an out- requirement over competing solutions. Other losses
put-derived source will scale the VIN current required including Schottky conduction losses during dead time
for the driver and control circuits by a factor of (Duty and inductor core losses generally account for less than
Cycle)/(Efficiency). For example, in a 20V to 5V applica- 2% total additional loss.
tion, 10mA of INTVCC current results in approximately
Checking Transient Response
2.5mA of VIN current. This reduces the mid-current
loss from 10% or more (if the driver was powered The regulator loop response can be checked by looking at
directly from VIN) to only a few percent. the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
3. I2R losses are predicted from the DC resistances of the
load current. When a load step occurs, VOUT shifts by an
fuse (if used), MOSFET, inductor, current sense resistor.
amount equal to ∆ILOAD (ESR), where ESR is the effective
In continuous mode, the average output current flows
series resistance of COUT . ∆ILOAD also begins to charge or
through L and RSENSE, but is “chopped” between the
discharge COUT generating the feedback error signal that
topside MOSFET and the synchronous MOSFET. If the
forces the regulator to adapt to the current change and
two MOSFETs have approximately the same RDS(ON),
return VOUT to its steady-state value. During this recovery
then the resistance of one MOSFET can simply be
time VOUT can be monitored for excessive overshoot or
summed with the resistances of L and RSENSE to obtain
ringing, which would indicate a stability problem. The
I2R losses. For example, if each RDS(ON) = 10mΩ, RL
availability of the ITH pin not only allows optimization of
= 10mΩ, RSENSE = 5mΩ, then the total resistance is
control loop behavior but also provides a DC coupled and
25mΩ. This results in losses ranging from 2% to 8%
AC filtered closed loop response test point. The DC step,
as the output current increases from 3A to 15A for
rise time and settling at this test point truly reflects the
a 5V output, or a 3% to 12% loss for a 3.3V output.
closed loop response. Assuming a predominantly second
Efficiency varies as the inverse square of VOUT for the
order system, phase margin and/or damping factor can
same external components and output power level. The be estimated using the percentage of overshoot seen at
combined effects of increasingly lower output voltages
Rev. D

LTC3850/LTC3850-1
this pin. The bandwidth can also be estimated by examin- to approximately 25 • CLOAD . Thus a 10µF capacitor would
ing the rise time at the pin. The ITH external components require a 250µs rise time, limiting the charging current
shown in the Typical Application circuit will provide an to about 200mA.
adequate starting point for most applications.
PC Board Layout Checklist
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly When laying out the printed circuit board, the follow-
(from 0.5 to 2 times their suggested values) to optimize ing checklist should be used to ensure proper operation
transient response once the final PC layout is done and of the IC. These items are also illustrated graphically in
the particular output capacitor type and value have been the layout diagram of Figure 12. Figure 13 illustrates the
determined. The output capacitors need to be selected current waveforms present in the various branches of
because the various types and values determine the loop the 2-phase synchronous regulators operating in the
gain and phase. An output current pulse of 20% to 80% continuous mode. Check the following in your layout:
of full-load current having a rise time of 1µs to 10µs will 1. Are the top N-channel MOSFETs M1 and M3 located
produce output voltage and ITH pin waveforms that will within 1cm of each other with a common drain con-
give a sense of the overall loop stability without break- nection at CIN? Do not attempt to split the input decou-
ing the feedback loop. Placing a power MOSFET directly pling for the two channels as it can cause a large reso-
across the output capacitor and driving the gate with an nant loop.
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage 2. Are the signal and power grounds kept separate? The
step resulting from the step change in output current may combined IC signal ground pin and the ground return
not be within the bandwidth of the feedback loop, so this of CINTVCC must return to the combined COUT (–) termi-
signal cannot be used to determine phase margin. This is nals. The VFB and ITH traces should be as short as pos-
why it is better to look at the ITH pin signal which is in the sible. The path formed by the top N-channel MOSFET,
feedback loop and is the filtered and compensated control Schottky diode and the CIN capacitor should have short
loop response. The gain of the loop will be increased leads and PC trace lengths. The output capacitor (–)
by increasing RC and the bandwidth of the loop will be terminals should be connected as close as possible
increased by decreasing CC. If RC is increased by the to the (–) terminals of the input capacitor by placing
same factor that CC is decreased, the zero frequency will the capacitors next to each other and away from the
be kept the same, thereby keeping the phase shift the Schottky loop described above.
same in the most critical frequency range of the feedback 3. Do the LTC3850 VFB pins’ resistive dividers connect to
loop. The output voltage settling behavior is related to the the (+) terminals of COUT? The resistive divider must be
stability of the closed-loop system and will demonstrate connected between the (+) terminal of COUT and signal
the actual overall supply performance. ground. The feedback resistor connections should not
A second, more severe transient is caused by switching be along the high current input feeds from the input
in loads with large (>1µF) supply bypass capacitors. The capacitor(s).
discharged bypass capacitors are effectively put in paral- 4. Are the SENSE+ and SENSE– leads routed together
lel with COUT , causing a rapid drop in VOUT . No regulator with minimum PC trace spacing? The filter capacitor
can alter its delivery of current quickly enough to pre- between SENSE+ and SENSE– should be as close as
vent this sudden step change in output voltage if the load possible to the IC. Ensure accurate current sensing with
switch resistance is low and it is driven quickly. If the ratio Kelvin connections at the sense resistor or inductor,
of CLOAD to COUT is greater than 1:50, the switch rise time whichever is used for current sensing.
should be controlled so that the load rise time is limited
Rev. D

LTC3850/LTC3850-1
TK/SS1 RPU2
VPULL-UP
ITH1 PGOOD PGOOD
VFB1
L1 RSENSE
SENSE1+ TG1 VOUT1
SENSE1– SW1
CB1
M1 M2
PLLLPF BOOST1 D1
ILIM
BG1 1µF
fIN CERAMIC
MODE/PLLIN COUT1
VIN
CVIN RIN
+
RUN1
PGND
RUN2 VIN GND
+
EXTVCC CIN
SGND
+
CINTVCC
SENSE2– INTVCC COUT2

1µF
+
CERAMIC
SENSE2+ BG2
M3 M4
VFB2 BOOST2 D2
CB2
ITH2 SW2
RSENSE
TG2 VOUT2
TK/SS2
L2
38501 F12
Figure 13. Recommended Printed Circuit Layout Diagram
SW1 L1 RSENSE1 VOUT1
D1 COUT1 RL1
VIN
RIN
CIN
SW2 L2 RSENSE2 VOUT2
BOLD LINES INDICATE D2 COUT2 RL2

HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
38501 F13
Figure 12. Branch Current Waveforms

Rev. D

LTC3850/LTC3850-1
5. Is the INTVCC decoupling capacitor connected close its individual performance should both controllers be
to the IC, between the INTVCC and the power ground turned on at the same time. A particularly difficult region
pins? This capacitor carries the MOSFET drivers cur- of operation is when one controller channel is nearing its
rent peaks. An additional 1µF ceramic capacitor placed current comparator trip point when the other channel is
immediately next to the INTVCC and PGND pins can turning on its top MOSFET. This occurs around 50% duty
help improve noise performance substantially. cycle on either channel due to the phasing of the internal
clocks and may cause minor duty cycle jitter.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away Reduce VIN from its nominal level to verify operation
from sensitive small-signal nodes, especially from the of the regulator in dropout. Check the operation of the
opposite channel’s voltage and current sensing feed- undervoltage lockout circuit by further lowering VIN while
back pins. All of these nodes have very large and fast monitoring the outputs to verify operation.
moving signals and therefore should be kept on the Investigate whether any problems exist only at higher out-
“output side” of the LTC3850 and occupy minimum put currents or only at higher input voltages. If problems
PC trace area. If DCR sensing is used, place the top coincide with high input voltages and low output currents,
resistor (Figure 2b, R1) close to the switching node. look for capacitive coupling between the BOOST, SW, TG,
7. Use a modified “star ground” technique: a low imped- and possibly BG connections and the sensitive voltage
ance, large copper area central grounding point on the and current pins. The capacitor placed across the current
same side of the PC board as the input and output sensing pins needs to be placed immediately adjacent to
capacitors with tie-ins for the bottom of the INTVCC the pins of the IC. This capacitor helps to minimize the
decoupling capacitor, the bottom of the voltage feed- effects of differential noise injection due to high frequency
back resistive divider and the SGND pin of the IC. capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
PC Board Layout Debugging for inductive coupling between CIN, Schottky and the top
Start with one controller at a time. It is helpful to use a MOSFET components to the sensitive current and voltage
DC-50MHz current probe to monitor the current in the sensing traces. In addition, investigate common ground
inductor while testing the circuit. Monitor the output path voltage pickup between these components and the
switching node (SW pin) to synchronize the oscilloscope SGND pin of the IC.
to the internal oscillator and probe the actual output volt-
Design Example
age as well. Check for proper performance over the operat-
ing voltage and current range expected in the application. As a design example for a two channel medium cur-
The frequency of operation should be maintained over rent regulator, assume VIN = 12V(nominal), VIN =
the input voltage range down to dropout and until the 20V(maximum), VOUT1 = 3.3V, VOUT2 = 1.8V, IMAX1,2 =
output load drops below the low current operation 5A, and f = 500kHz (see Figure 14).
threshold—typically 10% of the maximum designed cur- The regulated output voltages are determined by:
rent level in Burst Mode operation.
⎛ R ⎞
The duty cycle percentage should be maintained from VOUT = 0.8V • ⎜ 1+ B ⎟
cycle to cycle in a well-designed, low noise PCB imple- ⎝ RA ⎠
mentation. Variation in the duty cycle at a subharmonic Using 20k 1% resistors from both VFB nodes to ground,
rate can suggest noise pickup at the current or volt- the top feedback resistors are (to the nearest 1% standard
age sensing inputs or inadequate loop compensation. value) 63.4k and 25.5k.
Overcompensation of the loop can be used to tame a
poor PC layout if regulator bandwidth optimization is The frequency is set by biasing the FREQ/PLLFLTR pin to
not required. Only after each controller is checked for 1.2V (see Figure 10), using a divider from INTVCC. This
Rev. D

LTC3850/LTC3850-1
VIN
7V TO
22µF 20V
2.2Ω 1µF
50V
4.7µF
D3 D4
M1 VIN PGOOD EXTVCC INTVCC M2
TG1 TG2
0.1µF 0.1µF
L1 L2
SW1 SW2
LTC3850
BG1 BG2 4.12k
6.19k 10k, 1% 1%
1% MODE/PLLIN PGND
ILIM FREQ/PLLFLTR
SENSE1+ SENSE2+
1.33k 0.1µF 0.1µF 1.5k
1% 1%
SENSE1– SENSE2–
33pF 33pF
RUN1 RUN2
VOUT1 VOUT2
3.3V VFB1 VFB2 1.8V
5A 63.4k ITH1 ITH2 25.5k 5A
1% 1800pF 2200pF 1%
TK/SS1 SGND TK/SS2
COUT1 100pF 100pF COUT2
20k 4.75k 3.16k 5.49k 20k
100µF 1% 1% 0.1µF 0.1µF 1% 1% 1% 100µF
X2 X2
38501 F14
L1, L2: COILTRONICS HCP0703
M1, M2: VISHAY SILICONIX Si4816BDY
COUT1, COUT2: TAIYO YUDEN JMK325BJ107MM
Figure 14. High Efficiency Dual 500kHz 3.3V/1.8V Step-Down Converter
voltage will decrease as VIN approaches 5V, lowering the the maximum DC value plus one-half the ripple current,
switching frequency. If a separate 5V supply is connected or 5.725A for Channel 1 and 5.7A for Channel 2.
to EXTVCC, INTVCC will remain at 5V even if VIN decreases. The minimum on-time occurs on Channel 1 at the maxi-
The inductance values are based on a 35% maximum mum VIN, and should not be less than 90ns:
ripple current assumption (1.75A for each channel). The VOUT 1.8V
highest value of ripple current occurs at the maximum t ON(MIN) = = = 180ns
VIN(MAX)f 20V(500kHz)
input voltage:
VOUT ⎛ VOUT ⎞ With ILIM floating, the equivalent RSENSE resistor value
L= ⎜ 1− ⎟ can be calculated by using the minimum value for the
f • ΔIL(MAX) ⎝ VIN(MAX) ⎠
maximum current sense threshold (40mV).
Channel 1 will require 3.2µH, and Channel 2 will require VSENSE(MIN)
1.9µH. The next highest standard values are 3.3µH RSENSE(EQUIV) = =
ΔIL(NOM)
and 2.2µH. At the nominal input voltage (12V), the ripple ILOAD(MAX) +
will be: 2
40mV
V ⎛ V ⎞ ≅ 7mΩ
ΔIL(NOM) = OUT ⎜ 1− OUT ⎟ 1.5A
f •L ⎝ VIN(NOM) ⎠ 5A +
2
Channel 1 will have 1.45A (29%) ripple, and Channel 2 will The equivalent RSENSE is the same for Channel 2.
have 1.4A (28%) ripple. The peak inductor current will be
Rev. D

LTC3850/LTC3850-1
The Coiltronics (Cooper) HCP0703-2R2 (20mΩ DCRMAX The respective values for Channel 2 are R1 = 4.12k, R2 =
at 20°C) and HCP0703-3R3 (30mΩ DCRMAX at 20°C) are 1.5k; and PLOSS R1 = 8mW.
chosen. At 100°C, the estimated maximum DCR values are Burst Mode operation is chosen for high light load effi-
26.4mΩ and 39.6mΩ. The divider ratios are: ciency (Figure 15) by floating the MODE/PLLIN pin. Power
RSENSE(EQUIV) 7mΩ loss due to the DCR sensing network is slightly higher
RD = = = 0.26;
DCRMAX at TL(MAX) 26.4mΩ at light loads than would have been the case with a suit-
able sense resistor (7mΩ). At heavier loads, DCR sensing
7mΩ provides higher efficiency.
and ≅ 0.18
39.6mΩ
The power dissipation on the topside MOSFET can be easily
For each channel, 0.1µF is selected for C1. estimated. Choosing a Siliconix Si4816BDY dual MOSFET
results in: RDS(ON) = 0.023Ω/0.016Ω, CMILLER @ 100pF.
L 2.2µH
R1||R2 = = At maximum input voltage with T(estimated) = 50°C:
(DCRMAX at 20°C)•C1 20mΩ • 0.1µF
3.3V 2
3.3µH
PMAIN = (5) [1+(0.005)(50°C – 25°C)] •
20V
= 1.1k ; and = 1.1k
30mΩ • 0.1µF
5A ⎞
For channel 1, the DCRSENSE filter/divider values are:
(0.023Ω ) + (20V )2 ⎛⎜⎝ ⎟ ( 2Ω ) (100pF ) •
2⎠
R1||R2 1.1k
R1= = ≅ 6.19k; ⎡ 1 1 ⎤
RD 0.18 ⎢⎣ 5 – 2.3 + 2.3 ⎥⎦ ( 500kHz ) = 186mW

R1• RD 6.19k • 0.18
R2 = = ≅ 1.33k A short-circuit to ground will result in a folded back cur-
1−RD 1− 0.18
rent of:
The power loss in R1 at the maximum input voltage is:
(VIN(MAX) − VOUT )• VOUT ISC =
(1/ 3) 50mV – 1 ⎛ 90ns(20V) ⎞ = 2.1A
PLOSS R1= = 0.007Ω 2 ⎜⎝ 3.3µH ⎟⎠
R1
(20V − 3.3V)• 3.3V with a typical value of RDS(ON) and d = (0.005/°C)(20)
= 9mW
6.19k = 0.1. The resulting power dissipated in the bottom
MOSFET is:
20V – 3.3V
100 10 PSYNC = (2.1A )2 (1.125)(0.016Ω)
DCR 20V
90 = 66mW

7mΩ
POWER LOSS (mW)
80 1
which is less than under full-load conditions.
EFFICIENCY (%)
DCR
70
CIN is chosen for an RMS current rating of at least 2A at
60 0.1 temperature assuming only channel 1 or 2 is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
50
EFFICIENCY
output ripple in continuous mode will be highest at the
40
POWER LOSS
0.01
maximum input voltage. The output voltage ripple due to
0.01 0.1 1 10 ESR is approximately:
LOAD CURRENT (mA)
38501 F15
VORIPPLE = RESR (∆IL) = 0.02Ω(1.5A) = 30mVP–P
Figure 15. Design Example Efficiency vs Load
Rev. D

LTC3850/LTC3850-1
TYPICAL APPLICATIONS
VIN
7V TO
2.2Ω 22µF 24V
50V
1µF
4.7µF
D3 VIN PGOOD INTVCC D4
M1 M2
TG1 TG2
0.1µF 0.1µF
L2 L2
SW1 SW2
LTC3850
BG1 BG2
10k
MODE/PLLIN 1%
PGND
ILIM FREQ/PLLFLTR
10Ω 10Ω
SENSE1+ SENSE2+
8mΩ 1000pF 1000pF 8mΩ
SENSE1– SENSE2–
15pF 10Ω 10Ω 10pF
RUN1 RUN2
VOUT1 EXTVCC VOUT2
3.3V VFB1 VFB2 5V
5A 63.4k ITH1 ITH2 105k 5A
1% 1000pF 1000pF 1%
TK/SS1 SGND TK/SS2
+ COUT1 20k 10k 100pF 15k 20k
+ COUT2
3.16k 100pF
1% 1% 0.1µF 0.1µF 1% 1%
220µF 1% 150µF
38501 F16
L1: TDK RLF 7030T-2R2M5R4

L2: TDK ULF10045T-3R3N6R9
COUT1: SANYO 4TPE220MF
COUT2: SANYO 6TPE150MI
Figure 16. 3.3V/5A, 5V/5A Converter Using Sense Resistors
Rev. D

VIN
RVIN 7V TO 14V
10k 10µF
2.2Ω 2x +
2.10k M1 CIN
CSS C4
HAT2168H 180µF
0.1µF 0.1µF
R27 L1
4.02k 0.68µH VOUT1
C6 R1
100pF 2.5V/
43.2k CB1 15A

C10 0.1µF
33pF M2
SENSE1– SENSE1+ RUN1 FREQ/ MODE/ SW1 TG1 D3
C7 PLLFLTR PLLIN CMDSH-3 RJK0301- + COUT1
1000pF R12
R2 DPB 330µF
7.5k TK/SS1 BOOST1
20k 4V
2X
ITH1 BG1
VFB1 VIN
LTC3850 CVIN
VFB2 INTVCC 1µF
C11
1000pF R18 CVCC
4.99k ITH2 BG2 4.7µF
R3
PGND
20k TK/SS2 D4 PGND
COUT2
C12 CMDSH-3 GND
100pF 330µF
SENSE2– BOOST2 4V
+
C15
For more information www.analog.com

M3
47pF 2X
R4 HAT2168H
L2
25.5k SENSE2+ SGND RUN2 ILIM EXTVCC PGOOD SW2 TG2 CB2 VOUT2
0.68µH
0.1µF 1.8V/
20k
C5 15A
R30
25.5k 0.1µF 4.02k
PGOOD
M4
RPG
RJK0301-
100k
DPB
38501 TA02
L1, L2: VISHAY IHLP5050EZ-01 0.68µH
COUT1, COUT2: SANYO 4TPD330M
Figure 17. 2.5V/15A, 1.8V/15A Converter with DCR Sensing and Coincident Rail Tracking
FSW = 350kHz
31
Rev. D
LTC3850/LTC3850-1
32
VIN
10µF 7V TO 14V
C1
2x
1000pF +
C2 CIN
RVIN
0.01µF 180µF
R9 R10 2.2Ω
100Ω 100Ω PLLIN
CSS1 R5 400kHz
0.1µF C4 10k M1
1000pF RJK0305DPB
L1 RSENSE1
C6 0.4µH 0.002Ω
R1 VOUT1
100pF 17.8k CB1 1.5V/15A
0.1µF
SENSE1– SENSE1+ RUN1 FREQ/ MODE/ SW1 TG1 D3 M2 + COUT1

C7
LTC3850/LTC3850-1
R12 PLLFLTR PLLIN CMDSH-3 RJK0301DPB 330µF

1000pF R2 2.5V
5.9k TK/SS1 BOOST1
20k 2X
ITH1 BG1
VFB1 VIN
LTC3850 CVIN
VFB2 INTVCC 1µF
C11
1000pF R18 CVCC
5.9k ITH2 BG2 4.7µF
R3
PGND PGND COUT2
20k TK/SS2 D4
C12 CMDSH-3 GND 330µF
2.5V
+
100pF
SENSE2– BOOST2 2X
M3 L2 RSENSE2
R4 RJK0305DPB 0.4µH 0.002Ω
VOUT2
For more information www.analog.com

CSS2 10k SENSE2+ SGND RUN2 ILIM EXTVCC PGOOD SW2 TG2 CB2 1.2V/15A
0.1µF 0.1µF
C5 M4
1000pF RJK0301DPB
PGOOD
R20 R22 RPG

100Ω 100Ω 100k
38501 F18
L1, L2: VITEC 59PR9875
COUT1, COUT2: 2R5TPE330M9
Figure 18. 1.5V/15A, 1.2V/15A Core-I/O Converter with Sense Resistor Synchronized at 400kHz
Rev. D
LTC3850/LTC3850-1
5V ± 0.5V
1Ω 4.7µF
6.3V
2x
4.7µF
D3 D4
TG1 TG2
0.1µF 0.1µF
L1 L2
SW1 SW2
LTC3850
BG1 BG2 1.2k
1.2k PLLIN 1%
1% MODE/PLLIN PGND
750kHz
ILIM FREQ/PLLFLTR
SENSE1+ SENSE2+
2.94k 0.047µF 0.047µF 4.99k
1% 1%
SENSE1– SENSE2–
47pF 100pF
RUN1 RUN2
VOUT1 VOUT2
1.8V VFB1 VFB2 1.2V
5A 25.5k ITH1 ITH2 10k 5A
1% 2200pF 1nF 2200pF 100pF 1%
TK/SS1 SGND TK/SS2 10nF
COUT1 100pF COUT2
20k 14k
100µF 0.1µF 0.1µF 10k 14k 20k 100µF
1% 1%
X2 1% 1% 1% X2
38501 F19
L1, L2: TOKO FDV0630 0.75µH
Figure 19. 1.8V/5A, 1.2V/5A Core-I/O Converter with a 5V Input Synchronized at 750kHz
2.2Ω
VIN1 VIN2
12V 3.3V
4.7µF 1µF 13.0k 4.7µF
2x
4.7µF 10k
D3 D4
TG1 TG2
0.1µF 0.1µF
L1 L2
SW1 SW2
LTC3850
BG1 BG2 1.2k
3.74k 10k
1%
1% MODE/PLLIN 1%
PGND
ILIM FREQ/PLLFLTR
SENSE1+ SENSE2+
1.40k 0.1µF 0.1µF 4.32k
1% 1%
SENSE1– SENSE2–
47pF 100pF
RUN1 RUN2
VOUT1 VOUT2
2.5V VFB1 VFB2 1.2V
5A 43.2k ITH1 ITH2 10k 5A
1% 2200pF 2200pF 100pF 1%
TK/SS1 SGND TK/SS2
COUT1 100pF COUT2
20k 10k
100µF 0.1µF 3.16k 6.04k 20k 100µF
1% 1% 0.1µF
X2 1% 1% 1% X2
38501 F20
L1: TOKO FDV0630 2.2µH
L2: TOKO FDV0630 0.75µH
Figure 20. 2.5V/5A, 1.2V/5A Core-I/O Converter with Dual Inputs

Rev. D

LTC3850/LTC3850-1
PACKAGE DESCRIPTION
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.386 – .393*
.045 ±.005 (9.804 – 9.982) .033
(0.838)
28 27 26 25 24 23 22 21 20 19 18 17 1615 REF
.254 MIN .150 – .165

.229 – .244 .150 – .157**
(5.817 – 6.198) (3.810 – 3.988)
.0165 ±.0015 .0250 BSC

RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14
.015 ±.004
× 45° .0532 – .0688 .004 – .0098
(0.38 ±0.10)
(1.35 – 1.75) (0.102 – 0.249)
.0075 – .0098 0° – 8° TYP
(0.19 – 0.25)
.016 – .050 .008 – .012 .0250 GN28 REV B 0212

(0.406 – 1.270) (0.203 – 0.305) (0.635)
NOTE: TYP BSC
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Rev. D

LTC3850/LTC3850-1
PACKAGE DESCRIPTION
UF Package
28-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1721 Rev A)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.64 ±0.05
(4 SIDES)
PACKAGE
OUTLINE
0.20 ±0.05
0.40 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 × 45°
4.00 ±0.10 0.75 ±0.05 R = 0.115 CHAMFER
(4 SIDES) R = 0.05 TYP
27 28
TYP
PIN 1 0.40 ±0.05
TOP MARK
(NOTE 6) 1
2
2.64 ±0.10
(4-SIDES)
(UF28) QFN 0106 REVA
0.200 REF 0.20 ±0.05

0.00 – 0.05 0.40 BSC
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
Rev. D

LTC3850/LTC3850-1
PACKAGE DESCRIPTION
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev C)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.50 REF
2.65 ±0.05
3.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 NOTCH
2.50 REF R = 0.20 OR 0.35
R = 0.05 R = 0.115 × 45° CHAMFER
4.00 ±0.10 0.75 ±0.05
TYP TYP
(2 SIDES) 27 28
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6) 1
5.00 ±0.10
3.50 REF
(2 SIDES)
3.65 ±0.10
2.65 ±0.10
(UFD28) QFN 0816 REV C
0.200 REF 0.25 ±0.05

0.00 – 0.05 0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
Rev. D

LTC3850/LTC3850-1
REVISION HISTORY (Revision history begins at Rev C)
REV DATE DESCRIPTION PAGE NUMBER

C 3/11 Updated Switch Voltage (SW1, SW2) LTC3850I only from 30V to –0.3V to 30V to –5V 2
D 1/20 Added AEC-Q100 Qualified Automotive parts 3
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For more by
is granted information www.analog.com
implication or otherwise under any patent or patent rights of Analog Devices. 37
LTC3850/LTC3850-1
TYPICAL APPLICATION
VIN
20k 7V TO 14V
2.55k 10k 2.21k 10µF
+
RUN RJK0305DPB L1 180µF
1nF 0.1µF 2x
7.5k 0.56µH
0.1µF 0.1µF RJK0301DPB

SENSE1– SENSE1+ RUN1 FREQ MODE SW1 TG1
220pF CMDSH-3
TK/SS1 BOOST1
2.2nF
ITH1 BG1
2.74k 2.2Ω
VFB1 VIN
20k
LTC3850
VFB2 INTVCC
1µF VOUT
4.7µF
ITH2 BG2 1.1V/30A
PGND
100µF
+ COUT1
TK/SS2 330µF
CMDSH-3 2x
2.5V
SENSE2– BOOST2 4x
RJK0305DPB L2
0.1µF 0.56µH
SENSE2+ SGND RUN2 ILIM EXTVCC PGOOD SW2 TG2
0.1µF
RJK0301DPB
PGOOD 2.21k
20k 100k
RUN
L1, L2: VISHAY IHLP4040DZ-01 0.56µH 38501 TA04
COUT: SANYO 2R5TPE330M9
FOR SINGLE OUTPUT, DUAL PHASE OPERATION, TIE THE FOLLOWING PINS TOGETHER:
VFB1 TO VFB1 TK/SS1 TO TK/SS2
ITH1 TO ITH2 RUN1 TO RUN2
Figure 21. 1.1V/30A Dual Phase Core Converter, FSW = 400kHz
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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LTC1775
LTC1735 High Efficiency Synchronous Step-Down Switching Regulator Programmable Fixed Frequency from 200kHz to 550kHz
LTC1778 No RSENSE Wide Input Range Synchronous Step-Down Controller Up to 97% Efficiency, 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ (0.9)(VIN),
IOUT Up to 20A
LTC3727A-1 Dual, 2-Phase Synchronous Controller Very Low Dropout; VOUT ≤ 14V, 4V ≤ VIN ≤ 36V
LTC3728 2-Phase 550kHz, Dual Synchronous Step-Down Controller QFN and SSOP Packages, High Frequency for Smaller L and C
LTC3729 20A to 200A PolyPhase® Synchronous Controllers Expandable from 2-Phase to 12-Phase, Uses All Surface Mount
Components
LTC3731 3-Phase, Single Output From 250kHz to 600kHz Synchronous 0.6V ≤ VOUT ≤ 6V, 4.5V ≤ VIN ≤ 32V, IOUT ≤ 60A,
Step-Down Controller Integrated MOSFET Drivers
LTC3773 Triple Output DC/DC Synchronous Controller 3-Phase Step-Down DC/DC Controller,
3.3V ≤ VIN ≤ 36V, Fixed Frequency 160kHz to 700kHz
LTC3810 100V Current Mode Synchronous Step-Down Switching Controller 0.8V ≤ VOUT ≤ 0.93VIN, 6.2V ≤ VIN ≤ 100V, No RSENSE
LTC3826 Low IQ, Dual, 2-Phase Synchronous Step-Down Controller 30µA IQ, 0.8V ≤ VOUT ≤ 10V, 4V ≤ VIN ≤ 36V
LTC3828 Dual, 2-Phase Synchronous Step-Down Controller with Tracking Up to Six Phases, 0.8V ≤ VOUT ≤ 7V, 4.5V ≤ VIN ≤ 28V
LTC3834/ Low IQ, Synchronous Step-Down Controller 30µA IQ, 0.8V ≤ VOUT ≤ 10V, 4V ≤ VIN ≤ 36V
LTC3834-1
LT3845 Low IQ, High Voltage Single Output Synchronous Step-Down DC/ 1.23V ≤ VOUT ≤ 36V, 4V ≤ VIN ≤ 60V, 120µA IQ
DC Controller
Rev. D
38
01/20
www.analog.com
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Features Description: LTC3850/LTC3850-1 Dual, 2-Phase Synchronous Step-Down Switching Controller

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Features Description: LTC3850/LTC3850-1 Dual, 2-Phase Synchronous Step-Down Switching Controller

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LTC3850/LTC3850-1

Dual, 2-Phase Synchronous Step-Down

2.2µH BOOST1 BOOST2 2.2µH

100µF 20k 20k 100µF

Document Feedback For more information www.analog.com 1

Input Supply Voltage (VIN).......................... 28V to –0.3V SENSE1+, SENSE2+, SENSE1–,

ILIM (EXTVCC)* 14 15 PGOOD

2 For more information www.analog.com

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4 For more information www.analog.com

TYPICAL PERFORMANCE CHARACTERISTICS

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38501 G04 38501 G05

Prebiased Output at 2V Coincident Tracking

6 For more information www.analog.com

SUPPLY CURRENT (mA)

INTVCC VOLTAGE (V)

CURRENT SENSE THRESHOLD (mV)

Maximum Current Sense Voltage vs TK/SS Pull-Up Current

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REGULATED FEEDBACK VOLTAGE (mV)

1.0 794 200

Undervoltage Lockout Threshold Oscillator Frequency Shutdown Current

INPUT CURRENT (µA)

Shutdown Current Quiescent Current

QUIESCENT CURRENT (mA)

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VIN VIN VIN VIN

SENSE RESISTOR BOOST

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TIME 38501 F03a TIME 38501 F03b

(5a) Coincident Tracking (5b) Ratiometric Tracking

Figure 5. Two Different Modes of Output Voltage Tracking

VOUT1 VOUT2 VOUT1 VOUT2

(6a) Coincident Tracking Setup (6b) Ratiometric Tracking Setup

Figure 6. Setup for Coincident and Ratiometric Tracking

Figure 7. Equivalent Input Circuit of Error Amplifier

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scaled by a factor of (Duty Cycle)/(Switcher Efficiency). Figure 8. Setup for a 5V Input

TJ = 70°C + (24mA)(5V)(95°C/W) = 81°C External bootstrap capacitors CB connected to the

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Setting Output Voltage Phase-Locked Loop and Frequency Synchronization

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Figure 10. Relationship Between Oscillator V

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SENSE2– INTVCC COUT2

Figure 13. Recommended Printed Circuit Layout Diagram

SW1 L1 RSENSE1 VOUT1

SW2 L2 RSENSE2 VOUT2

BOLD LINES INDICATE D2 COUT2 RL2

Figure 12. Branch Current Waveforms