5 4 3 2 1

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7 H_D#[0..63] VCC_CORE_S0 VCC_CORE_S0
U62B 2 OF 4 U62C
3 OF 4
H_D#0 E22 Y22 H_D#32
H_D#1 D0# D32# H_D#33
F24 D1# D33# AB24 A7 VCC VCC AB20
H_D#2 E26 V24 H_D#34 A9 AB7
H_D#3 D2# D34# H_D#35 VCC VCC
G22 D3# D35# V26 A10 VCC VCC AC7
H_D#4 F23 V23 H_D#36 A12 AC9
D4# D36# VCC VCC
D D

DATA GRP0
DATA GRP2
H_D#5 G25 T22 H_D#37 A13 AC12
H_D#6 D5# D37# H_D#38 VCC VCC
E25 D6# D38# U25 A15 VCC VCC AC13
H_D#7 E23 U23 H_D#39 A17 AC15
H_D#8 D7# D39# H_D#40 VCC VCC
K24 D8# D40# Y25 A18 VCC VCC AC17
H_D#9 G24 W22 H_D#41 A20 AC18
H_D#10 D9# D41# H_D#42 VCC VCC
J24 D10# D42# Y23 B7 VCC VCC AD7
H_D#11 J23 W24 H_D#43 B9 AD9
H_D#12 D11# D43# H_D#44 VCC VCC
H22 D12# D44# W25 B10 VCC VCC AD10
H_D#13 F26 AA23 H_D#45 B12 AD12
H_D#14 D13# D45# H_D#46 VCC VCC
K22 D14# D46# AA24 B14 VCC VCC AD14
H_D#15 H23 AB25 H_D#47 B15 AD15
H_DSTBN#0 D15# D47# H_DSTBN#2 VCC VCC
7 H_DSTBN#0 J26 DSTBN0# DSTBN2# Y26 H_DSTBN#2 7 B17 VCC VCC AD17
H_DSTBP#0 H26 AA26 H_DSTBP#2 B18 AD18
7 H_DSTBP#0 DSTBP0# DSTBP2# H_DSTBP#2 7 VCC VCC
H_DINV#0 H25 U22 H_DINV#2 B20 AE9
7 H_DINV#0 DINV0# DINV2# H_DINV#2 7 VCC VCC
C9 VCC VCC AE10
C10 VCC VCC AE12
H_D#16 N22 AE24 H_D#48 C12 AE13
H_D#17 D16# D48# H_D#49 VCC VCC
K25 D17# D49# AD24 C13 VCC VCC AE15
H_D#18 P26 AA21 H_D#50 C15 AE17
H_D#19 D18# D50# H_D#51 VCC VCC
R23 D19# D51# AB22 C17 VCC VCC AE18
H_D#20 L23 AB21 H_D#52 C18 AE20
H_D#21 D20# D52# H_D#53 VCC VCC
M24 D21# D53# AC26 D9 VCC VCC AF9

DATA GRP1
DATA GRP3
H_D#22 L22 AD20 H_D#54 D10 AF10
H_D#23 D22# D54# H_D#55 VCC VCC
M23 D23# D55# AE22 D12 VCC VCC AF12
H_D#24 P25 AF23 H_D#56 D14 AF14
H_D#25 D24# D56# H_D#57 VCC VCC
P23 D25# D57# AC25 D15 VCC VCC AF15
H_D#26 P22 AE21 H_D#58 D17 AF17
H_D#27 D26# D58# H_D#59 VCC VCC
T24 D27# D59# AD21 D18 VCC VCC AF18
H_D#28 R24 AC22 H_D#60 E7 AF20 1D05V_S0
D28# D60# VCC VCC
C H_D#29
H_D#30
L25
T25
D29# D61# AD23
AF22
H_D#61
H_D#62
E9
E10
VCC
G21 R155 1 2
C
H_D#31 D30# D62# H_D#63 VCC VCCP R146 1
N25 D31# D63# AC23 E12 VCC VCCP V6 2 0R2J-2-GP
H_DSTBN#1 L26 AE25 H_DSTBN#3 E13 J6 0R2J-2-GP TC7
7 H_DSTBN#1 DSTBN1# DSTBN3# H_DSTBN#3 7 VCC VCCP
H_DSTBP#1 M26 AF24 H_DSTBP#3 E15 K6
7 H_DSTBP#1 DSTBP1# DSTBP3# H_DSTBP#3 7 VCC VCCP

SE330U2VDM-6-GP
H_DINV#1 N24 AC20 H_DINV#3 E17 M6
7 H_DINV#1 DINV1# DINV3# H_DINV#3 7 VCC VCCP
E18 VCC VCCP J21

1
V_CPU_GTLREF AD26 R26 COMP0 1 2 E20 K21
TPAD28 TP19 TEST1 GTLREF COMP0 COMP1 R171 VCC VCCP
C23 TEST1 MISC COMP1 U26 1 2 27D4R2F-L1-GP F7 VCC VCCP M21
SCD1U16V2KX-3GP TPAD28 TP22 TEST2 D25 AA1 COMP2 R172 1 2 54D9R2F-L1-GP F9 N21 DY

2
TPAD28 TP20 TEST3 TEST2 COMP2 COMP3 R132 VCC VCCP
C24 TEST3 COMP3 Y1 1 2 27D4R2F-L1-GP F10 VCC VCCP N6
1 2 C296 TEST4 AF26 TEST4
R131 54D9R2F-L1-GP F12 VCC VCCP R21
TPAD28 TP3 TEST5 AF1 E5 H_DPRSTP# F14 R6
TEST5 DPRSTP# H_DPRSTP# 7,19 VCC VCCP
TPAD28 TP21 TEST6 A26 B5 H_DPSLP# F15 T21
DY TEST6 DPSLP#
D24 H_DPWR#
H_DPSLP# 19
F17
VCC VCCP
T6
DPWR# H_DPWR# 7 VCC VCCP
CPU_BSEL0 B22 D6 H_PWRGOOD F18 V21
3 CPU_BSEL0 BSEL0 PWRGOOD H_PWRGOOD 19 VCC VCCP 1D5V_S0
CPU_BSEL1 B23 D7 H_CPUSLP# F20 W21 layout note:
3 CPU_BSEL1 BSEL1 SLP# H_CPUSLP# 7 VCC VCCP
CPU_BSEL2 C21 AE6 PSI# AA7
3 CPU_BSEL2 BSEL2 PSI# PSI# 35
AA9
VCC
B26 C298 place C3 near
VCC VCCA
R145 AA10 VCC VCCA C26 PIN B26

1
SCD01U16V2KX-3GP
AA12 VCC CPU_VID[0..6] 35
BGA479-SKT6-GPU3 1 2 AA13 AD6 CPU_VID0 C303
H_PWRGOOD_R 4 VCC VID0 CPU_VID1 SC10U10V5ZY-1GP
AA15 AF5

2
VCC VID1 CPU_VID2
PLACE C173 close to the TEST4 PIN, 1KR2J-1-GP AA17 VCC VID2 AE5
AA18 AF4 CPU_VID3
make sure TEST3,TEST4,TEST5 trace AA20
VCC VID3
AE3 CPU_VID4
VCC VID4 CPU_VID5
routing is reference to GND and AB9 VCC VID5 AF3
AC10 AE2 CPU_VID6
away other noisy signals AB10
VCC VID6
VCC
B AB12 VCC Length match within B
Resistor Placed AB14 AF7 VCC_SENSE
AB15
VCC VCCSENSE VCC_SENSE 35 25 mils . The trace
within 0.5" of CPU AB17
VCC
width/space/other is
VCC VSS_SENSE
pin. Trace should AB18 VCC VSSSENSE AE7 VSS_SENSE 35 20/7/25 .
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 be at least 25 mils
away from any other
BGA479-SKT6-GPU3 VCC_SENSE 1 2 VCC_CORE_S0
166 0 1 1 toggling signal . R143 100R2F-L1-GP-U
COMP[0,2] trace
VSS_SENSE 1 2
width is 18 mils. R142 100R2F-L1-GP-U
200 0 1 0
COMP[1,3] trace
width is 4 mils .
Close to CPU pin
within 500mils

1D05V_S0
2

Close to CPU
R422
pin AD26 1KR2F-3-GP
<Core Design>
Z0=55 ohm
A A
SCD01U16V2KX-3GP

with in
1 1

V_CPU_GTLREF C602
500mils . Wistron Corporation
1

R423 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
2KR2F-3-GP
2

Title
2

Meron(2/3)-AGTL+/PWR
Size Document Number Rev

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A3
Pamirs-Discrete SC
Date: Tuesday, December 19, 2006 Sheet 5 of 47