Sti5197 Mboard

STi5197-MBoard, STi5189/97-MB
Evaluation boards for low-cost SD TV decoder

using the STi5189/STi5197 SoC
Features
– ATAPI
■ Interfaces supporting digital audio and video – cable and/or satellite RF tuners
applications, including:
■ Diagnostic support:
– HDMI output with CEC support, I2C, dual
– LVDS JTAG
smartcards, infrared receiver, one NIM
– TTL JTAG
– dual RS232 (UART)
– MII/RMII Ethernet and single USB
– S/PDIF input/output, PCM input
Description
– SD video The STi5197-MBoard and STi5189/97-MB
– on-board 32-Mbyte NOR Flash memory provide an STB, iDTV and DVD platform for
– on-board 4-Gbyte NAND Flash low-cost, SD TV applications, using the
– 3 serial Flash devices STi5189/STi5197 SoC.
– DiSEqC 2.0TM interfaces These boards are used for:
– DVB-CI, STEM ■ SoC validation
– LMI, DDR SDRAM 64 Mbytes ■ SoC demonstration
– BTSC RF modulator(a)
■ software application development
a. On MB672 only.
June 2009 8149405 Rev D 1/160

www.st.com 1
Contents STi5197-MBoard, STi5189/97-MB
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Target audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Equipment and software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Electrostatic discharge (ESD) protection . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Product configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Board assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 MB676/MB704 processor board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6 Memory interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6.1 Local memory interface (LMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6.2 Flexible memory interface (FMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6.3 SPI Flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7.1 USB2.0 host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7.2 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7.3 HDMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7.4 Tuners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7.5 I2C interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.8 PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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STi5197-MBoard, STi5189/97-MB Contents
5 MB762 SD generic peripheral board . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.4 Dual serial RS232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.5 Infrared receiver and transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.6 Serial I2C buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.7 Smartcard slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.8 Flexible memory interface (FMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.8.1 STEM FMI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.8.2 FMI support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.9 DVB-CI and transport stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.10 Programming EPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.11 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.11.1 Analog audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.11.2 SPDIFout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.11.3 PCMin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.11.4 PCMout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.12 Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6 MB829 SD modular validation peripheral board . . . . . . . . . . . . . . . . . 28

6.1 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4 Dual serial RS232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.5 Infrared receiver and transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.6 Serial I2C buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.7 Smartcard slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.8 Flexible memory interface (FMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.8.1 STEM FMI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.8.2 FMI support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.9 DVB-CI and transport stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.10 Programming EPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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6.11 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.11.1 Analog audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.11.2 SPDIFout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.11.3 PCMin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.11.4 PCMout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.12 Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Appendix A MB676/MB704 processor board connectors . . . . . . . . . . . . . . . . . . 38

A.1 Connector layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
A.1.1 Bottom assembly connector layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
A.2 Panel layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
A.3 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
A.3.1 ATX power connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
A.3.2 I2C header connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
A.3.3 Power ground isolators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
A.3.4 External USB physical interface connector. . . . . . . . . . . . . . . . . . . . . . . 45
A.3.5 Debug connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
A.3.6 Board to board connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
A.3.7 Single USB2.0 type A connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
A.3.8 External clock connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
A.3.9 MII Ethernet connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
A.3.10 HDMI connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
A.3.11 Satellite tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
A.3.12 Digital cable tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Appendix B MB762 SD generic peripheral board connectors . . . . . . . . . . . . . . 56

B.1 Connector layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
B.2 Front and rear panel layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
B.3 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
B.3.1 DC power socket CN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
B.3.2 LVDS debug type G connector CN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
B.3.3 Video and audio phono connectors CN3 to CN6, CN8 and CN9 . . . . . . 61
B.3.4 Dual SCART connectors CN7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
B.3.5 NIM connector CN10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
B.3.6 HDD power connector CN11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
B.3.7 PCM audio output debug connector CN12 . . . . . . . . . . . . . . . . . . . . . . . 65
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B.3.8 Transport stream data connector CN14 . . . . . . . . . . . . . . . . . . . . . . . . . 66

B.3.9 DVO connector CN15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
B.3.10 JTAG debug (ByteBlaster) connector CN16 . . . . . . . . . . . . . . . . . . . . . . 68
B.3.11 PCM audio input connector CN17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
B.3.12 Smartcard header data connectors CN18/CN19 . . . . . . . . . . . . . . . . . . 69
B.3.13 P6960 series high-density logic probe land pattern CN20 . . . . . . . . . . . 69
B.3.14 ATAPI connector CN21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
B.3.15 DVB-CI connector CN22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
B.3.16 +3V3 I2C blaster connector CN23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
B.3.17 Ethernet MII data connector CN24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
B.3.18 Smartcard sockets CN25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
B.3.19 STEM EMI CN26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
B.3.20 RJ45 Ethernet connector CN27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
B.3.21 Dual RS232 interface CN28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
B.3.22 EMI and PIO peripheral to processor board connectors CN29/CN30 . . 80
B.3.23 RF modulator connector IC11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Appendix C MB829 SD modular validation peripheral board connectors. . . . . 85

C.1 Connector layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
C.2 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
C.2.1 Video and audio phono connectors CN1 to CN9 . . . . . . . . . . . . . . . . . . 87
C.2.2 LVDS debug type G connector CN10 . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
C.2.3 JTAG debug (ByteBlaster) connector CN11 . . . . . . . . . . . . . . . . . . . . . . 89
C.2.4 Dual RS232 interface CN12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
C.2.5 PCM audio output debug connector CN13 . . . . . . . . . . . . . . . . . . . . . . . 90
C.2.6 DVO connector CN14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
C.2.7 PCM audio input connector CN15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
C.2.8 EMI and PIO peripheral to processor board connectors CN16/CN23 . . 92
C.2.9 Transport stream connectors CN24/CN25 . . . . . . . . . . . . . . . . . . . . . . . 97
C.2.10 NIM connector CN26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
C.2.11 ATX power connector CN27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
C.2.12 Smartcard header data connectors CN28/CN29 . . . . . . . . . . . . . . . . . 101
C.2.13 Smartcard sockets CN30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
C.2.14 ATAPI connector CN31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
C.2.15 STEM EMI CN32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
C.2.16 P6960 series high-density logic probe land pattern CN33/CN36 . . . . . 106
C.2.17 DVB-CI connector CN34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8149405 5/160
C.2.18 I2C blaster connector CN35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

C.2.19 Ethernet MII data connector CN37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
C.2.20 RJ45 Ethernet connector CN38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Appendix D MB676 23 x 23 processor board jumpers, option resistors and

switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
D.1 Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
D.2 Option resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
D.3 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Appendix E MB704 15 x 15 processor board jumpers, option resistors and

switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
E.1 Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
E.2 Option resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
E.3 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Appendix F MB762 SD generic peripheral board jumpers, option resistors and

switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
F.1 Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
F.2 Option resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
F.3 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Appendix G MB829 SD modular validation peripheral board jumpers, option

resistors and switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
G.1 Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
G.2 Option resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
G.3 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Appendix H PIO alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Appendix I Hardware configuration guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

I.1 FMI EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
I.1.1 FMI decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
I.1.2 FMI EPLD register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
I.1.3 FMI EPLD register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
I.2 Transport stream EPLD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
I.2.1 TS mode descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6/160 8149405
I.3 EPLD programming instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

I.3.1 Programming EPLDs using the LVDS connection . . . . . . . . . . . . . . . . 152
I.3.2 JTAG chain setup for use with ByteBlaster connector CN16/CN11 . . . 152
I.4 General mode switch settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
I.5 Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
I.6 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
I.7 SPI devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
I.8 I2C devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Appendix J Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
8149405 7/160
Introduction STi5197-MBoard, STi5189/97-MB
1 Introduction
The STi5197-MBoard and STi5189/97-MB are evaluation boards, which enable:

● validation of the STi5189 and STi5197 system-on-chips (SoC)
● software development and evaluation of the STi5189 and STi5197 SoCs and peripheral
applications
The evaluation boards consist of:
● a processor board, described in Chapter 4 on page 13
– for the STi5189/97-MB, this is an MB676 STi5189 or STi5197 23 x 23 processor
board
– for the STi5197-MBoard, this is an MB704 STi5197 15 x 15 processor board
The 15 x 15 processor board is a cut-down of the 23 x 23 processor board. EMI has
been removed (boot from serial Flash only).
● an SD peripheral board
– for Revisions A and B of the evaluation boards, this is an MB762 SD generic
peripheral board, described in Chapter 5 on page 18
– for Revisions C and later of the evaulation boards, this is an MB829 SD modular
validation peripheral board, described in Chapter 6 on page 28
● a power supply, described in Section 3.3 on page 12
A block diagram of the system is shown in Section 3.1: System block diagram on page 11.
The STi5197 and STi5189 SoCs contain an ST40-300 core. For more information, see the
STi5197 datasheet (ADCS 8148435) and the STi5189 datasheet (ADCS 8141465).
1.1 Target audience

The target audience for this datasheet includes:
● software application and validation teams
● marketing
● board manufacturing services (debug)
● field application engineers
● original equipment manufacturers (OEM)
1.2 References
STi5197 datasheet (ADCS 8148435)
STi5189 datasheet (ADCS 8141465)
ST Micro Connect 2 datasheet (ADCS 7912386)
ST40 Micro Toolset user manual (ADCS 7379953)
8/160 8149405
STi5197-MBoard, STi5189/97-MB System overview
2 System overview
Figure 1. STi5197-MBoard, STi5189/97-MB debug setup and interconnection block diagram

Audio outputs HDMI/DTV
monitor
RFin
Ethernet to Ethernet
suitable test device RJ45
STi5197-MBoard
STi5189/97-MB HDMI HDMI
USB2.0
(Upsampled SD)
Windows/Linux PC LVDS Power

debug CVBS/YC/RGB/
development host running socket
USB2.0 YPbPr PAL/NTSC
multiple debug operations SD AV outputs monitor and
audio system
Power or VCR
Ethernet
LVDS cable
ST Micro Connect 2
10baseT
Ethernet connection
(network or point-point)
Table 1. System requirements for using the ST40 Micro Toolset on the board
Component Description Supplier Part number
Supported configuration: Windows 2000/XP OS

Pentium class PC, RedHat Linux Enterprise
PC/Linux V3.0 or higher for Linux development (minimum
Any PC supplier Not applicable
development host Pentium II processor exceeding 300 MHz with
32 Mbytes of RAM, greater than 120 Mbytes
disk free space).
STi5197-MBoard or STi5197-MBoard
STi5197/STi5189 evaluation board. STMicroelectronics
STi5189/97-MB or STi5189/97-MB
Hardware interface from Ethernet to
ST Micro Connect 2 STMicroelectronics STMC2-20/40/200
motherboard under test.
Contact your local
ST40 Micro Toolset Embedded core development toolset. STMicroelectronics
ST sales office
ST40 STLinux distribution and development STMicroelectronics
ST40 STLinux Not applicable
environment. from www.stlinux.com
HDMI/DVi monitor HD ready monitor. Any OEM monitor Not applicable
(Legacy) Monitor with SD, composite video
PAL/NTSC TV Any OEM monitor Not applicable
input, SCART or VGA.
Reference software STi5189/STi5197 software modules STMicroelectronics STAPI
Tuner, QPSK demodulation and FEC for satellite
Packet injector and
or cable bitstream reception, development board STMicroelectronics PI-NIM
front-end (optional)
with STEM or NIM interface.
8149405 9/160
System overview STi5197-MBoard, STi5189/97-MB
2.1 Equipment and software

The following are required:
● an ST Micro Connect 2 (STMC2) with an LVDS cable to link the STMC2 to the board
● a Windows/Linux capable PC
● an Ethernet cable to link the PC to the STMC2 and board
● ST40 Micro Toolset R4.2.1 or later
● ST Micro Connection Package R1.2.1 or later
The STMC2 is a host-target interface that connects to the board’s JTAG port and provides
host software with the ability to start up the board, download programs and debug them on
the target.
For further information on STMC2, please refer to ST Micro Connect 2 datasheet
(ADCS 7912386).
For information on the ST40 toolset, refer to the ST40 Micro Toolset user manual
(ADCS 7379953).
2.2 Electrostatic discharge (ESD) protection

If the board is used in a standalone manner on the workbench, it must be in a static-free
environment, maintaining antistatic precautions at all times. For example, the board must be
placed on a grounded antistatic mat and the user must always wear the wrist strap
connected to the mat.
10/160 8149405
STi5197-MBoard, STi5189/97-MB Product configuration
3 Product configuration
3.1 System block diagram

Figure 2. STi5197-MBoard, STi5189/97-MB system interconnect block diagram
KEY
On the peripheral board
On the processor board
Tuner front Transport stream, see

end Section 5.9 on page 24
Buffer ATAPI
TS DVB-CI
DDR Buffer I/F
LMI
SDRAM
STEM
Buffer I/F
EMI
USB ULPI NAND
Flash
NOR
HDMI DVO Flash
Address
STi5189/STi5197 decoder
2x
smartcards Serial
Flash
2 x RS232 ASC Audio block, see

(D type) Section 5.11 on page 26
AV
Video block, see
Section 5.12 on page 27
JTAG JTAG
IR Infrared
RX
BTSC
modulator(1)
MII Ethernet
(1) On MB762 only.
3.2 Board assembly

The STi5189/STi5197 processor is mounted into a socket on the processor board.
The processor board connects to the SD generic peripheral board by two connectors on the
underside of the PCB. Connectors CN8 and CN9 on the MB704, and connectors CN11 and
CN12 on the MB676, slot into CN29 and CN30 of the MB762 and CN23 and CN16 of the
MB829 peripheral board.
8149405 11/160
Product configuration STi5197-MBoard, STi5189/97-MB
3.3 Power supplies

Power to the processor board is provided from the peripheral board using the board to board
connectors. Any different voltages required are generated using voltage regulators, or
convertors.
The MB762 peripheral board is powered by a +12V DC power socket. This provides +12V,
+5V and +3V3.
The MB829 peripheral board is powered by an ATX power supply. This provides +12V, -12V,
+5V, -5V, +3V3 and +5V standby.
The power supply to the processor board can be isolated and powered by external power
sources for CPUIO (+3V3), ANA (+2V5), CPUINT (+1V) and CPULMI (+2V5 and +3V3
levels). The processor module uses isolating connectors (CN3, CN4, CN5 and CN8 on
MB676 and CN2, CN3, CN4 and CN10 on MB704) to power from an external source.
An ATX power supply connector is also provided on the processor board(a) for stand-alone
use.
a. An ATX power supply is not available on MB704 Revision A boards.
12/160 8149405
STi5197-MBoard, STi5189/97-MB MB676/MB704 processor board
4 MB676/MB704 processor board
The processor board is available to support two package sizes (see Chapter 1: Introduction
on page 8):
● MB676 is a 23 x 23 STi5189 or STi5197 processor board
● MB704 is a 15 x 15 STi5197 processor board
Warning: On the MB704, if the socket is overtightened when the

processor is changed, the board may stop working. The
recommended torque is 0.226 Nm or 22.6 cNm.
The processor board is mounted on top of the SD peripheral board and connects through
two board to board connectors.
The main components and functions on the processor board are:
● a socketed SoC, either:
– STi5197, see the STi5197 datasheet (ADCS 8148435)
– STi5189, see the STi5189 datasheet (ADCS 8141465)
● cable tuner front end
● satellite tuner front end (MB676 only)
● SPI Flash with enhanced security features
● LMI memory interface, 64 Mbytes DDR SDRAM
● interfaces
– USB2.0
– HDMI
● ATX power supply connector for stand-alone use (not on MB704 revision A boards)
A block diagram of the processor board is shown in Figure 3.
Figure 3. Block diagram of the processor board
Tuner front
ends
SPI
Flash
SPI
DDR LMI
SDRAM
Processor
board
USB ULPI
HDMI DVO
8149405 13/160
MB676/MB704 processor board STi5197-MBoard, STi5189/97-MB
4.1 Power supply

The SD peripheral board provides regulated +12V, +5V and +3V3 supplies to the
MB676/MB704 processor board, through the board to board connectors, CN11/CN8 and
CN12/CN9. These voltage levels are passed through the board and used to power various
devices.
● The +12V supply provides power to the +8V audio power supply isolator.
● The +5V supply is stepped down to produce a voltage level of +2V5.
● The +3V3 supply provides power to the processor (CPUIO).
● The +3V3 supply is stepped down to produce an adjustable output voltage or a fixed
output voltage of +1V. This is controlled by the jumper J11, see Section D.1: Jumpers
on page 111.
Alternatively, the +1V power supply can be sourced from a regulator integrated in the
STi5189/STi5197 device.
● The +3V3 supply is stepped down to +1V2 to power the HDMI controller chip.
● The +3V3 supply is stepped down to provide +1V8 to power the USB controller chip.
Alternatively, the USB can be powered from the +2V5 supply stepped down to +1V8
using a low-cost diode option. This is selectable with the jumper J17.
● The LMI I/O (CPULMI) interface is powered using either the +3V3 supply for SDRAM or
the +2V5 supply for DDR.
When the processor board is used in standalone mode, the +12V, +5V and +3V3 supplies
are provided directly to the processor board through the ATX power connector CN1/CN16.
Revision A of the MB704 processor board does not have an ATX power connector.
4.2 Reset
The reset sources are:
● power on reset
● JTAG reset
● SW1 reset
● reset out from the SD peripheral board
These reset sources are combined to generate the following resets:
● Ethernet (MII connector)
● USB Phy
● HDMI Phy
● down to SD peripheral board
● STi5189/STi5197
● SPI Flash
On the MB676 only, each of the above may also be individually activated using an I2C write
to the corresponding bit of the PIO expander device.
The power on reset uses an ST power management device, to generate the reset signal
towards the STi5189/STi5197.
14/160 8149405
4.3 Clocks
One 30 MHz crystal is available to support the VCXO functionality.
An external clock can also be connected through CN14 on MB676 or CN12 on MB704.
4.4 Interrupts
The memory mapped EMI EPLD controls and masks the interrupts. The interrupt sources
are:
● DVB-CI card
● scart switch
● HDMI from processor board
● USB VBUS overcurrent from processor board
For further information on interrupts, please refer to Appendix I: Hardware configuration
guide on page 138.
4.5 Debug
A standard JTAG connector is provided for stand-alone use or as an alternative to the LVDS
connection interface on the peripheral board.
4.6 Memory interfaces

The STi5189/STi5197 provides the following host memory interfaces:
● local memory interface (LMI)
● flexible memory interface (FMI)(a)
● SPI Flash memory
4.6.1 Local memory interface (LMI)

The STi5189/STi5197 integrates a 16-bit wide SDR/DDR SDRAM interface. The processor
board is fitted with a 64-Mbyte device arranged as 8M x 16-bit x 4 banks.
4.6.2 Flexible memory interface (FMI)

The FMI(a) is a general-purpose interface for attaching Flash and peripherals. It is described
in Section 5.8 on page 22.
4.6.3 SPI Flash memory interface

The STi5189/STi5197 provides a seamless interface to the serial Flash using the SPI
protocol.
Three serial Flash devices are available, one on the processor boards and two on the
peripheral board. These are selectable by jumpers.
a. This is not available for the MB704 STi5197 15 x 15 processor board.
8149405 15/160
MB676/MB704 processor board STi5197-MBoard, STi5189/97-MB
4.7 Interfaces
The following interfaces are accessible through connectors on the processor board:
● USB2.0
● MII/RMII Ethernet (MB704 only)
● HDMI
● QAM cable tuner
● QPSK satellite tuner (MB676 only)
● I2C
4.7.1 USB2.0 host

A USB2.0 type A connector and a USB3317 Phy are provided on the processor board.
A 100-pin T&MT connector is also provided on the MB676 to allow an external USB Phy to
be connected.
4.7.2 Ethernet
The MB704 provides a header to support an external MII/RMII Ethernet Phy. An on-board
LAN8700 Phy and an RJ45 Ethernet connector are provided on the SD peripheral board.
4.7.3 HDMI
An on-board Silicon Images 9024 HDMI Phy provides an upsampled SD to HD output at
resolutions of up to 1080p. A standard HDMI connector is provided.
4.7.4 Tuners
The processor board provides the following tuners:
● QAM cable tuner
● QPSK satellite tuner (only available on the MB676)
4.7.5 I2C interfaces

There are three I2C connectors on the processor board. These are used for the PIO
expander, HDMI controller and QPSK debug interface.
The MB676 has an additional LNB controller and the MB704 has an additional connector
provided for QAM debug purposes.
16/160 8149405
4.8 PIO
PIO signals can be assigned alternative functions. This enables the silicon to be configured
for different architectures. Some PIO pins can be programmed as:
● inputs and outputs
● alternative functions
A complete list of PIO assignments is available in the STi5197 datasheet (ADCS 8148435).
The PIO functions used by the board are given in Appendix H on page 136.
Inputs connected to the alternative function input are permanently connected to the input
pin. Output signals from a peripheral are only connected when the PIO bit is configured into
either push pull or open drain driver, alternative function mode.
Some alternative function signals are available on more than one PIO port.
In addition to the multiplexing on the PIO pins, other pin multiplexing is used to provide
different signal options, which depend on the device application.
8149405 17/160
MB762 SD generic peripheral board STi5197-MBoard, STi5189/97-MB
5 MB762 SD generic peripheral board
Note: This peripheral board is used for Revisions A and B of the STi5197-MBoard and
STi5189/97-MB evaluation boards.
The main features of the MB762 SD generic peripheral board are:
● dual RS232 (COM0 and COM1)
● infrared receiver and transmitter
● I2C
● dual smartcard
● FMI, which provides access to:
– NAND Flash
– NOR Flash
– ATAPI
● DVB-CI transport stream
● updating EPLDs
● SPDIF input and outputs to phono connectors
● two channel PCM audio outputs to phono connectors
● NIM interface
● SPI serial Flash
● BTSC modulator
● digital audio (PCM, SPDIF)
● analog audio
● video (SD) outputs to phonos and SCART
● Ethernet using LAN8700 Phy
A block diagram of the SD generic peripheral board is shown in Figure 4.
18/160 8149405
STi5197-MBoard, STi5189/97-MB MB762 SD generic peripheral board
Figure 4. Block diagram of MB762 SD generic peripheral board
Transport stream, see

Buffer ATAPI
TS
DVB-CI
Buffer I/F
STEM
Buffer I/F
EMI
NAND
Flash
NOR
Flash
STi5189/STi5197 Address
decoder
2x
smartcards
Serial
Flash
2 x RS232 ASC
(D type) Audio block, see
AV
Video block, see
JTAG JTAG Section 5.12 on page 27
IR Infrared
BTSC RX
modulator
MII/RMII Ethernet
5.1 Power supply

The SD generic peripheral board is powered by a +12V DC power socket. Main voltage
levels of +5V and +3V3 are derived from this +12V DC input.
Voltage levels of +3V3, +5V and +12V are supplied to the processor board through the
board to board connectors.
8149405 19/160
5.2 Resets
Individual reset outputs on the SD generic peripheral board are as follows:
● MII reset
● STEM reset
● transport stream connector reset
● NIM reset
● ATAPI reset
● DVBCI reset
● smartcard reset
The reset sources for the MB762 are:
● power-on reset
● LVDS JTAG reset
● front panel reset switch
● processor board
There are also software controlled resets programmable using an FMI EPLD mapped
register (only available on the STi5189/97-MB):
● NIM
● transport stream connector
● ATAPI
● STEM
● NOR Flash
● DVB-CI
● PCMDAC
5.3 Interrupts
The SD generic peripheral board is responsible for multiplexing interrupts from the following
sources:
● HDMI (processor board)
● USB VBUS overcurrent (processor board)
● STEM (x2)
● ATAPI
● DVB-CI
● SCART
These interrupts are then multiplexed by the FMI EPLD onto three interrupt lines which go to
the STi5189/STi5197 on the processor module.
guide on page 138.
20/160 8149405
5.4 Dual serial RS232

Dual RS232 ports (RS232 COM0 and RS232 COM1) with flow control are provided. RXD,
TXD, RTS and CTS signals are supported with a suitable RS232 convertor chip.
5.5 Infrared receiver and transmitter

Support for one infrared receiver/transmitter module is provided on the peripheral board with
a frequency of 36 KHz.
5.6 Serial I2C buses

I2C buses are required for:
● cable and/or satellite tuner with LNB
● EEPROM
● SCART switch
● PIO expander
● HDMI
● MB762 NIM cards and NIM LNB controller
● optional transport stream connector
● optional DVO connector
● optional PCM audio connector
Three I2C interfaces from three separate SSC communications modules within the SoC are
supported by the MB762 modular interface. Two of these are available for general use, the
other is dedicated to the on-chip QPSK demodulator. Only 2-wire I2C is supported. In
addition, a separate I2C host interface is required for debug access to the QAM cable
demodulator from an external initiator, through an I2C to STBus interface. This is multiplexed
into one of the GPIO banks and is active by default when the chip is reset.
A separate dedicated I2C interface is provided from the STi5189/STi5197 for the main
control of the tuner(s). Extra debug access is provided on the MB704 Revision B boards with
options to connect to an external initiator or one of the other PIO controlled I2C buses
The I2C connectors use a 2 x 4-way header (pin 1 removed) as used by the +3V3 I2C
parallel port interface. The connectivity of I2C is shown in Figure 5.
8149405 21/160
Figure 5. I2C connectivity
Processor board MB762 peripheral board
STi5189/STi5197
SSC2 SCART
SSC0
USB to I2C
convertor QAM debug EEPROM
daughter port
HDMI
card
PIO
expander
Tuner(s) NIM/LNB
LNB
5.7 Smartcard slots

Support for dual smartcards is provided on the peripheral board (CN25). The top smartcard
(smartcard 0) supports both ICAM and standard smartcard formats. The bottom smartcard
(smartcard 1) only supports standard smartcard format.
5.8 Flexible memory interface (FMI)

The FMI is a general-purpose interface for attaching Flash and peripherals which support:
● NOR Flash
● NAND Flash
● external bus master support through BUSREQ/BUSGNT signals
● ATAPI (PIO mode only)
● DVB-CI
Up to four banks are available. Each bank has a dedicated strobe timing configuration and
chip select signal. The FMI memory map is shown in Table 2. For further information, refer
to Appendix I: Hardware configuration guide on page 138.
As this mapping is controlled by the EPLD, it is possible to re-map devices to different banks
for special requirements.
Table 2. Board FMI memory map

Bank Function
Bank 0
32-Mbyte NOR Flash or 4-Gbyte NAND Flash (selectable through jumpers/EPLD)
(boot area)
Bank 1 ATAPI and EPLD
Bank 2 DVB-CI
Bank 3 STEM
22/160 8149405
5.8.1 STEM FMI interface

The STEM FMI board interface is an external 16-bit, general purpose interface. It can be
used to plug in additional memory and peripheral devices, and to allow probing of the FMI
bus.
5.8.2 FMI support

Information on FMI support is given in Section 4.6: Memory interfaces on page 15.
The FMI system block diagram is shown in Figure 6.
Figure 6. FMI system block diagram
EMI
CN11/CN8
CN29
EPLD
IC21 STEM
EMI
Board to board connectors
TTL ATAPI
buffers
SoC
FMI NAND DVB-CI
Flash
NOR
CN12/CN9
Flash
CN30
STEM
FMI
8149405 23/160
5.9 DVB-CI and transport stream

A single DVB-CI card is supported on the board. The primary tuner stream leads to TSOUT.
This output is then routed to the DVB-CI slot to provide a decoded CA stream to TSIN.
All transport stream signal are routed through an EPLD to allow routing of any source
transport stream signals to any destination transport stream signals, either individually or in
parallel. Routing configurations are coded in the EPLD and the options are chosen by the
config switches.
The transport stream interface is supported by a single ST-NIM2.1 interface. The ST-NIM2.1
provides power and LNB control circuitry suitable for various tuner NIM modules and the
PI-NIM packet injector board.
The transport stream and DVB-CI block diagram is shown in Figure 7.
Figure 7. Transport stream and DVB-CI block diagram
MB762 peripheral board Processor board
TS IDC header Tuner
Integrated
ST-NIM QAM/QPSK
demodulator
EPLD STi5189/STi5197
TSIN
TSOUT
DVB-CI
Config Software
switches transport stream
24/160 8149405
5.10 Programming EPLDs

This board has two EPLDs, these are:
● FMI (IC23)
● transport stream (IC24)
For more information on the EPLDs, refer to Appendix I: Hardware configuration guide on
page 138.
The EPLDs can be updated or programmed remotely. There are two different methods of
programming the EPLDs.
● Connection from the PC to an Altera ByteBlaster interface. This interface connects to
the EPLD connector (CN16) through a ribbon cable, see Figure 8.
● Alternatively the STMC2 is connected directly to the LVDS type G connector (CN2)
using an LVDS cable, see Figure 9. This is the fastest and easiest method of
programming the EPLDs and is described in the ST Micro Connect 2 datasheet
(ADCS 7912386).
Figure 8. EPLD ByteBlaster programming connectivity
Altera ByteBlaster
TTL connector
to EPLD connector
2 x 5-way (CN16)
Figure 9. EPLD STMC2 programming
EPLD connector (CN16)
ST Micro Connect 2
LVDS cable connects to LVDS

port (CN2/CN10) on the MB762
LVDS cable
8149405 25/160
5.11 Audio
The following audio sources are available:
● analog audio
● SPDIFout
● PCMin
● PCMout
Figure 10. Audio block diagram
SPDIF SPDIFout
Audio dual
SCART-TV
STi5189/ phono
STi5197
SCART
DAC
SCART-AUX
switch
PCMout DAC Phono
PCMout header
PCMin PCMin header
5.11.1 Analog audio

Audio phono connectors are provided, after being buffered using Op-Amp circuitry.
5.11.2 SPDIFout
The SPDIF output is provided with an RCA/phono socket. The output can be connected to
an external decoder and amplifier system.
5.11.3 PCMin
A header on the MB762 can be used to input PCM to the STi5189/STi5197.
5.11.4 PCMout
A PCM DAC is supported by the board with left and right phono outputs located on the rear
panel.
26/160 8149405
5.12 Video
Four video DACs are supported by this board. One of these DACs is designed with
high-drive capabilities to allow unbuffered connection. The other three DACs require
buffering which is done by the SCART switch (IC22).
The high-drive output is connected to both the SCART switch and a phono connector for
direct connection to a TV.
The following video configurations are possible:
● Composite + SVideo (YC)
● Composite + Component(YUC)
● RGB (+sync)
● SVideo + composite1 + composite2
Figure 11. Video block diagram
STi5189/
STi5197 SCART-TV
SCART
DENC
switch
SCART-AUX
HDMI Video CVBS out

filters phono
IDC
DVO header
8149405 27/160
MB829 SD modular validation peripheral board STi5197-MBoard, STi5189/97-MB
6 MB829 SD modular validation peripheral board
Note: This peripheral board is used for Revisions C and later of the STi5197-MBoard and
STi5189/97-MB evaluation boards.
The main features of the SD modular validation peripheral board are:
● dual RS232 (COM0 and COM1)
● infrared receiver and transmitter
● I2C
● dual smartcard
● FMI, which provides access to:
– NAND Flash
– NOR Flash
– ATAPI
● DVB-CI transport stream
● updating EPLDs
● SPDIF input and outputs to phono connectors
● two channel PCM audio outputs to phono connectors
● NIM interface
● SPI serial Flash
● digital audio (PCM, SPDIF)
● analog audio
● video (SD) outputs to phonos
● Ethernet using LAN8700 Phy
A block diagram of the SD modular validation peripheral board is shown in Figure 12.
28/160 8149405
STi5197-MBoard, STi5189/97-MB MB829 SD modular validation peripheral board
Figure 12. Block diagram of MB829 SD modular validation peripheral board
Transport stream, see

Buffer ATAPI
TS
DVB-CI
Buffer I/F
STEM
Buffer I/F
EMI
NAND
Flash
NOR
Flash
STi5189/STi5197 Address
decoder
2x
smartcards
Serial
Flash
2 x RS232 ASC
(D type) Audio block, see
AV
Video block, see
JTAG JTAG Section 6.12 on page 37
IR Infrared
RX
MII Ethernet
6.1 Power supply

The SD modular validation peripheral board is powered by a standard ATX power supply.
The power supply provides the board with +12V, -12V, +5V, -5V, +3V3, +5V standby.
A front panel switch (SW6) is used to switch the power supply on or off.
A signal from the processor module can also turn the power supply on or off. This is
connected to the LVDS JTAG debug device, allowing remote power cycling of the board, for
validation purposes. This power supply enable signal is isolated by a jumper (J10) to only
use the front panel switch.
Voltage levels of +3V3, +5V and +12V are supplied to the processor board through the
board to board connectors.
8149405 29/160
6.2 Resets
Individual reset outputs on the SD modular validation peripheral board are as follows:
● MII reset
● STEM reset
● transport stream connector reset
● NIM reset
● ATAPI reset
● DVB-CI reset
● smartcard reset
The reset sources for the MB829 are:
● power-on reset
● LVDS JTAG reset
● front panel reset switch
● processor board
There are also software controlled resets programmable using an FMI EPLD mapped
register (only available on the STi5189/97-MB):
● NIM
● transport stream connector
● ATAPI
● STEM
● NOR Flash
● DVB-CI
● PCMDAC
6.3 Interrupts
The SD modular validation peripheral board is responsible for multiplexing interrupts from
the following sources:
● HDMI (processor board)
● USB VBUS overcurrent (processor board)
● STEM (x2)
● ATAPI
● DVB-CI
These interrupts are then multiplexed by the FMI EPLD onto three interrupt lines which go to
the STi5189/STi5197 on the processor module.
guide on page 138.
6.4 Dual serial RS232

Dual RS232 ports (RS232 COM0 and RS232 COM1) with flow control are provided. RXD,
TXD, RTS and CTS signals are supported with a suitable RS232 convertor chip.
30/160 8149405
6.5 Infrared receiver and transmitter

Support for one infrared receiver/transmitter module is provided on the peripheral board with
a frequency of 36 KHz.
6.6 Serial I2C buses

I2C buses are required for:
● cable and/or satellite tuner with LNB
● EEPROM
● PIO expander
● HDMI
● MB829 NIM cards and NIM LNB controller
● optional transport stream connector
● optional DVO connector
● optional PCM audio connector
Three I2C interfaces from three separate SSC communications modules within the SoC are
supported by the MB829 modular interface. Two of these are available for general use, the
other is dedicated to the on-chip QPSK demodulator. Only 2-wire I2C is supported. In
addition, a separate I2C host interface is required for debug access to the QAM cable
demodulator from an external initiator, through an I2C to STBus interface. This is multiplexed
into one of the GPIO banks and is active by default when the chip is reset.
A separate dedicated I2C interface is provided from the STi5189/STi5197 for the main
control of the tuner(s). Extra debug access is provided on the MB704 Revision B boards with
options to connect to an external initiator or one of the other PIO controlled I2C buses
The I2C connectors use a 2 x 4-way header (pin 1 removed) as used by the +3V3 I2C
parallel port interface. The connectivity of I2C is shown in Figure 13.
Figure 13. I2C connectivity
STi5189/STi5197
SSC2 EEPROM
SSC0
USB to I2C
convertor QAM debug
daughter port
HDMI
card
PIO
expander
Tuner(s) NIM/LNB
LNB
8149405 31/160
6.7 Smartcard slots

Support for dual smartcards is provided on the peripheral board (CN30). The top smartcard
(smartcard 0) supports both ICAM and standard smartcard formats. The bottom smartcard
(smartcard 1) only supports standard smartcard format.
6.8 Flexible memory interface (FMI)

The FMI is a general-purpose interface for attaching Flash and peripherals which support:
● NOR Flash
● NAND Flash
● external bus master support through BUSREQ/BUSGNT signals
● ATAPI (PIO mode only)
● DVB-CI
Up to four banks are available. Each bank has a dedicated strobe timing configuration and
chip select signal. The FMI memory map is shown in Table 3. For further information, refer
to Appendix I: Hardware configuration guide on page 138.
As this mapping is controlled by the EPLD, it is possible to re-map devices to different banks
for special requirements.
Table 3. Board FMI memory map

Bank Function
Bank 0
32-Mbyte NOR Flash or 4-Gbyte NAND Flash (selectable through jumpers/EPLD)
(boot area)
Bank 1 ATAPI and EPLD
Bank 2 DVB-CI
Bank 3 STEM
6.8.1 STEM FMI interface

The STEM FMI board interface is an external 16-bit, general purpose interface. It can be
used to plug in additional memory and peripheral devices, and to allow probing of the FMI
bus.
6.8.2 FMI support

Information on FMI support is given in Section 4.6: Memory interfaces on page 15.
The FMI system block diagram is shown in Figure 14.
32/160 8149405
Figure 14. FMI system block diagram
EMI
CN11/CN8
CN16
EPLD
IC18 STEM
EMI
Board to board connectors

TTL ATAPI
buffers
SoC
FMI NAND DVB-CI
Flash
NOR
CN12/CN9
Flash
CN23
STEM
FMI
8149405 33/160
6.9 DVB-CI and transport stream

A single DVB-CI card is supported on the board. The primary tuner stream leads to TSOUT.
This output is then routed to the DVB-CI slot to provide a decoded CA stream to TSIN.
All transport stream signal are routed through an EPLD to allow routing of any source
transport stream signals to any destination transport stream signals, either individually or in
parallel. Routing configurations are coded in the EPLD and the options are chosen by the
config switches.
The transport stream interface is supported by a single ST-NIM2.1 interface. The ST-NIM2.1
provides power and LNB control circuitry suitable for various tuner NIM modules and the
PI-NIM packet injector board.
The transport stream and DVB-CI block diagram is shown in Figure 15.
Figure 15. Transport stream and DVB-CI block diagram
MB829 peripheral board Processor board
TS IDC header Tuner
Integrated
ST-NIM QAM/QPSK
demodulator
EPLD STi5189/STi5197
TSIN
TSOUT
DVB-CI
Config Software
switches transport stream
34/160 8149405
6.10 Programming EPLDs

This board has two EPLDs, these are:
● FMI (IC18)
● transport stream (IC19)
For more information on the EPLDs, refer to Appendix I: Hardware configuration guide on
page 138.
The EPLDs can be updated or programmed remotely. There are two different methods of
programming the EPLDs.
● Connection from the PC to an Altera ByteBlaster interface. This interface connects to
the EPLD connector (CN11) through a ribbon cable, see Figure 16.
● Alternatively the STMC2 is connected directly to the LVDS type G connector (CN10)
using an LVDS cable, see Figure 17. This is the fastest and easiest method of
programming the EPLDs and is described in the ST Micro Connect 2 datasheet
(ADCS 7912386).
Figure 16. EPLD ByteBlaster programming connectivity
Altera ByteBlaster
TTL connector
to EPLD connector
2 x 5-way (CN11)
Figure 17. EPLD STMC2 programming
ST Micro Connect 2
EPLD connector (CN11)
LVDS cable connects to LVDS

port (CN10) on the MB829
LVDS cable
8149405 35/160
6.11 Audio
The following audio sources are available:
● analog audio
● SPDIFout
● PCMin
● PCMout
Figure 18. Audio block diagram
SPDIF SPDIFout
STi5189/
STi5197
DAC Audio dual

phono
PCMout DAC Phono
PCMout header
PCMin PCMin header
6.11.1 Analog audio

Audio phono connectors are provided, after being buffered using Op-Amp circuitry.
6.11.2 SPDIFout
The SPDIF output is provided with an RCA/phono socket. The output can be connected to
an external decoder and amplifier system.
6.11.3 PCMin
A header on the MB829 can be used to input PCM to the STi5189/STi5197.
6.11.4 PCMout
A PCM DAC is supported by the board with left and right phono outputs located on the rear
panel. A header can also be used to access PCMout directly.
36/160 8149405
6.12 Video
Four video DACs are supported by this board. One of these DACs is designed with
high-drive capabilities to allow unbuffered connection. The other three DACs require
buffering.
The high-drive output is connected to a phono connector for direct connection to a TV.
The following video configurations are possible:
● Composite + SVideo (YC)
● Composite + Component(YUC)
● RGB (+ sync)
● SVideo + composite1 + composite2
Figure 19. Video block diagram
STi5189/
STi5197
DENC Video CVBS out
filters phono
Video RGB out (phono)

HDMI buffers
Component out
IDC
DVO header
8149405 37/160
MB676/MB704 processor board connectors STi5197-MBoard, STi5189/97-MB
Appendix A MB676/MB704 processor board connectors
This appendix describes the connectors for both the MB676 23 x 23 processor board and
the MB704 15 x 15 processor board.
A.1 Connector layouts

The connector placements on the two processor boards are shown in Figure 20 and
Figure 21.
Figure 20. MB676 23 x 23 processor board top assembly connector layout

:
A
JTAG debug USB PHY

connector connector
C165
CN9
R180
C1
C166
IC19
R21
IC15
R181
R112
R113
TP18
Top Assembly Placement Drawing
R22 R23
H5
R24
H1
R182
TP82
C117
R114
J18
TP24 TP22 TP20 TP23 TP21 TP19
C13
C118
R115
R1
C119
J17
J1
C168 C167
CN1
IC16
R183
IC6
CN13
C169
R186
R184
R185 C171
TP27 TP28 TP25 TP26

R117
R26 R25
C170
D1
R116 TP83
TP84
C14 TP1
C15
TP68
USB Type A
TP69 TP29
R27
R119
IC7
R121
IC20
connector J2 TP30
ATX power
Board Title:
TP31
TP2
R123
IC8
TP100
connector
L6
TP32
J3
D2
C172
C175
C173
L7
CN10
R188
R189
R187
C120 R124
C177
C174
IC9
C176
R68
R71
R74
R72
R73
R75
R70
D5
C122 R69
TP70
C121
SW2
SW3
C123
C124
D3
D4
L9
TP71
R125
IC21
R28
R29
R190 R76
R191 R193 R192 R127 R126 C125
C126
TP3
R30
C127 TP33
R31
R32
J20
J21
J19
R77
R
CN3 CN4 CN5

7
C128
8
H6 H3
TP72
R128 TP34
L1
TP73
C22
C23
TP85
R129
C24
IC17
R132
R130
C178
R131 TP86
R134
R133
C25
TP87
C179
L10
C2
C26
C28
TP88
External clock C3 Power ground

J4
C4
C5
C129
input IC22 TP89
J22
TP74
TP75
TP35
TP36
IC10 isolators
C6
IC1
C29
R135
R137
R136
R138
C180
C33
TP37
C181
R34
R35
XT2
J23
C38
R139 R85 R86 R82 R84 R83

L2
C35
Iss:
C36
D6
L11 TP101
R87 TP38
R88 R89 R90 R93 R92 R91

R94
1
L3
C37
R195
C131
C130
R194
C133
Tuner can with

C132
C7
CN16
C135
R141
R140
R95
C134
C182
R96
R36
C84
L12
integrated satellite CN14

R97
R142
C183
J24
R37
C137
C136
TP39 TP42 TP41 TP40
C184
R98
C52
C8
R2
C185 L13
R38
R143
TP43
R99
C42
C138
tuner
R144
R100
C186
R39
IC23
TP44
SW1
C188
C187
C140
C139
R40
IC2
08/09/2008
R102
R101
C50
R145
C142
C141
R44
R146 R42
R104
C144
TP45
R151 R154
R147 C54
R46
C143 R148
C87
R149 R150 R152

R49
C9
C145
C146
C88 C93
Date:
R153
IC3
R155
CAN1
R50
TP76
R156
R157
R158
LD1
TP4
TP5
IC12
R4
R51
R5
R159
R3
R52
R160
TP6
R161
R53
R164
R162 R163
C147
R6
TP58 TP57 TP55 TP52 TP50 TP49 TP53 TP46 TP48 TP56 TP47 TP54 TP51
R106
C149 C148
IC11
C150
R9
C96 R8 R7
R10
C100
C99
C101
L4
L5
J13
TP8 TP7
IC24
TP12 TP11 TP9 TP10
J12
IC4
IC13
Digital cable R54
R11
TP13
R56
R108 R107 C103 C61
C62
tuner I2C 1
C10
J6 J5
XT1
C106 C107
connector
R169
TP14
TP15
TP90
C155
R109
TP16
R59
R196 R199
C189
R197
R198
R12 R13
J14
TR3
C108
J25
R61 R60 R14
1 of 2
R62 R15
C156
J7 J8
R170
I2C 2 (QPSK)
R200
Page:
C109
TR5
R201
TR4
TP91
TR6
C190
L8 C157
TP92
TR2
C192 connector
R202
R204
R205
D7
C193
J9 J10
R203
C158 CN6 CN7 CN2

R16
R206
CN15
TP102 TP93 TP95 TP94

J11
I2C 3
J15
Document Number:
D9
R171
R172
R208
C195
R173
C196
C197
R174
R207
C194
HDMI
DRW1666
connector
R176
TP65
R175
R17
C65
R19
R20
R18
TP96
TP77
TP97
R110
connector C159 TP98

C162
IC26 TP78
C160 R177
IC5
TP79 TP80
C69
C68
C66
C67
TP66
IC28
IC27
C198
C199
C200
C70
C161
C12
R209
C115
C76
C75
C74
C73
C72
TP99
C163 R178 C114 TP67

TP17
TR1
C77
C201
C78
STMicroelectronics Ltd.
This Drawing and the information herein, is not to
C202
TP81
without the prior written permission of STMicroel
H7 H4
J26
R179
R210
C79
TP103
C205
C203
L14
C204
C80
R211
Power ground
CN8
TP104
IC18
C81
C207
C206
C208
C164
isolator
J27 J16
R64
R66
IC14 R67
H2
38/160 8149405
STi5197-MBoard, STi5189/97-MB MB676/MB704 processor board connectors
Figure 21. MB704 15 x 15 processor board top assembly connector layout
JTAG UDI debug MII Ethernet

connector connector
C41
R2 TP1
R3
LD1
TP2
R10
R18
R12
R17
R11
R16
R15
R14
R13
H5 H1
C106
LD4
R517
R19
R516
IC7
TP7 TP9 TP11 TP13 TP8 TP10 TP12
C1
R52
CN11
R51
R53
C147
CN16
IC4
C16
R20
R22
R21
R98
R94
R95
R99
R96
R97
R54
TP78
ATX power
TP101
C14
R172
R173
C107
IC8 IC5
C108
C109
connector
TP107
R55
C42
C15
J10
IC16
R100
TP14
TP31 TP30
C146
TP15
R101
TP51
R56
R25
R26
R27
R28
R23
R24
R29
IC23
R155
TP102
R174
C145
R31
R30
J22
R102
CN7
TP52
C95
TP16
J2
R103
R57
R58
TP87
R156
R175
TP88
TP39
R32
R176
R177
R178
IC14 R33
C74
TP79
R179
R59 R34
R180
C112 R35
IC11 IC6
R181
Type A USB
R36
J17
R157
R60 R37
R104
R105
R106
R107
R182
TP53
R61 R38
D1
TP54
CN1
IC9
TP55
TP89
R183
C113
IC17 R39
J16
R184
J23
R62 R40
R185
R186
R187
R189
R188
R42
I2C 1
R41
R63
C96
C97
R158
R43
R64 R44
C114
IC15
R159 R160
R65
R66
R45
R46 TP3
connector
CN2 CN3 CN4
C21
C43 C144
LD2
R108
SW1
C44 C17
C148
TP33
J18
C19
J21
J20
J19
TP56
H6 C75
H3
TP57 TP58
C76
C24
C20
R47
C5
R161
R162
Power ground
IC12 J11
C3
C4
C139
IC26
C115
TP108
isolators
C149
C23
C6
C22
L1
IC1
LD9
R515
TP59
L2
TP60
LD10
R164
C26
C27
C45
C25
L3 C29
C47
TP61
TP40
R67
TP41
R142
C48
C53
C50
C51
C54
C49
C52
C78
TP17
TP62
TP63
IC25
R68
R69
TP18 TP21 TP20 TP19
R70
TP42
Tuner can with

R71
TP43
C2
R72
C79
TR2
integrated QAM
C80
R73
TP44
R75
cable tuner
R77
C84
C86
R78
TP22
J12
IC10
R79
R80
TP46 TP45 TP47 TP27 TP26 TP29 TP28 TP23 TP105 TP32 TP104 TP25 TP24
C103
TP65
C100
C101
R145
R148
R146
R147
R88
R86
R82
R84
R83
R85
R93
R89
R90
R81
R87
R91
R92
TP64
R143
C150
R524
R523
C7
C151
C60 J3
TP4 TP5
IC22
L7
TP38 TP103
LD8
LD16
R519
LD15
R518
R513
L6
External
J7 J4
LD19
LD18
R194
R527
R526
R166
C116 C102
R212
R213
TP90
C118 C117
J13
clock input R190 R191 C90 R149

R144
TR3 R192 R193

TP91
IC27
C37
R214
C119
I2C 2 (QPSK)
C89
R196
L4
R525 R195
TR4 XT1
C152
QAM I2C connector

J8 J5
TR5
C140
C122
R215 R216
connector CN5
J14
R217
J24
J25
CN12
TR6
CN13
C120
R197
R200
R199
I2C 3
D2
J9 J6
R198
J1
R4
R218
TP95 TP94 TP93 TP92
J15
C104
D4
connector
R206
R202
R201
C123
C124
C125
R205
C141
R204
R203
CN6
R207
C9
C8
R5
R7
R8
R6
R167
HDMI connector
TP96
TP97
C126
TP98
IC18 TP67 TP68 TP69

TP66
IC2
C127
R208
C18
C61
C10
C62
C63
IC20
IC19
C11
C128
C130
C129
C64
C131
R9 R1
C12 TP6
C65
C66
R209
C70
C68
C67
C69
TR1
IC3
C121
C39
C132 TP80
C71
TP49
C133
TP70 TP71
R151
TP72
H7 H4
R168
R210
C142
C72 C40
TP100
C134
C143
L5
C135
TP73
R211
R152
CN10
IC13
TP99
TP81
TP50
IC21
R169 TP82
C73
C138
C137
TP83
C136 R170 TP84

TP74
R153
LD17
TP85
TP75
R514
R171 TP86
TP76
H2
TP77
R154
C105 C13
Power ground
isolators
Note: Figure 21 shows assembly connector layout for the MB704 revision B board.
A.1.1 Bottom assembly connector layout

On the bottom (solderside) of both boards are two connectors, CN11 and CN12 for the
MB676, and CN8 and CN9 for the MB704. These are used for connecting to the SD
peripheral board MB762 (for Revision A and B boards) or MB829 (for Revision C or later
boards).
8149405 39/160
A.2 Panel layout

The front panel of the processor board is screwed in to the rear panel of the MB762 SD
generic peripheral board as shown in Section B.2: Front and rear panel layout on page 57.
The MB676 front panel is shown in Figure 22 and the MB704 front panel is shown in
Figure 23.
Figure 22. Display of MB676 23 x 23 processor board front panel
MB676 - STi5197 23x23 Processor Board

R
S/N:
BUILD:
Sat Tuner
Cable Tuner
HDMI
Figure 23. Display of MB704 15 x 15 processor board front panel
40/160 8149405
A.3 Connectors
The connectors that are fitted on the processor boards are shown in Table 4 and Table 5.
Table 4. Internal connectors

Connector number
Type of connector Reference
MB676 MB704
ATX power connector CN1 CN16(1) Section A.3.1 on page 42

QPSK I2C connector 2 CN2 CN5 Section A.3.2 on page 43
Power GND isolator connector +2V5 CN3 CN3 Section A.3.3 on page 44
Power GND isolator connector +3V3 CPUIO CN4 CN2 Section A.3.3 on page 44
Power GND isolator connector +2V5 (DDR) CN5 CN4 Section A.3.3 on page 44
I2C connector 1 CN6 CN1 Section A.3.2 on page 43
QAM I2C connector - CN13 Section A.3.2 on page 43
2C
I connector 3 CN7 CN6 Section A.3.2 on page 43
Power GND isolator connector +1V CPU
CN8 CN10 Section A.3.3 on page 44
internal
External USB physical interface connector CN9 - Section A.3.4 on page 45
Debug connector CN10 CN11 Section A.3.5 on page 47
CN11 CN8
Board to board connectors Section A.3.6 on page 48
CN12 CN9
External clock generator CN14 CN12 Section A.3.8 on page 53
MII Ethernet connector - CN7 Section A.3.9 on page 53
1. Not available on MB704 Revision A boards.
Table 5. Front panel external connectors

Connector number
MB676 MB704
USB type A connector CN13 CN14 Section A.3.7 on page 52

HDMI connector CN15 CN15 Section A.3.10 on page 54
Satellite tuner CN16 - Section A.3.11 on page 55
Digital cable tuner IC24 IC22 Section A.3.12 on page 55
8149405 41/160
A.3.1 ATX power connector

Note: This connector is not present on the MB704 Revision A processor board.
The ATX power connector is CN1 on the MB676 and CN16 on the MB704.
A standard ATX power supply is used to provide different voltage levels to the board. This
board-mounted Molex connector is a 20-pin mini-fit jr type.
Figure 24. ATX power connector
1 10
11 20
Viewed from above PCB
Table 6. ATX power connector pin allocation

Pin Description Pin Description
1 +3V3_A 11 +3V3_C
2 +3V3_B 12 -12V
3 GND_A 13 GND_D
4 +5V_A 14 notPS_ON
5 GND_B 15 GND_E
6 +5V_B 16 GND_F
7 GND_C 17 GND_G
8 PW_OK 18 -5V
9 +5VSB 19 +5V_C
10 +12V 20 +5V_D
42/160 8149405
A.3.2 I2C header connectors

These are 2 x 4-way pin post PTH header connectors. Shroudless, with a pitch of 2.54 mm.
The MB676 has the following I2C connectors:
● QPSK I2C connector 2 (CN2)
● I2C connector 1 (CN6)
● I2C 3 connector (CN7)
The MB704 has the following I2C connectors:
● on-board QAM I2C connector (CN13)
Figure 25. I2C header connectors
7 1
8 2
Table 7. I2C header connectors pin allocation

1 Removed for polarization 2 VCC

3 USER1 4 SDA
5 USER2 6 SCL
7 USER3 8 GND
8149405 43/160
A.3.3 Power ground isolators

There are four power ground isolators on each processor board.
The MB676 has connectors CN3, CN4, CN5 and CN8. These are identical to connectors
CN3, CN2, CN4, CN10 on the MB704.
Four 6-pin headers. 2 x 3-way, polarized straight header connector with a pitch of 2.54 mm
Figure 26. Power ground isolator connector
1 5
2 6
Table 8. Power ground isolator pin allocation (CN3)

1 +2V5 4 GND_ISOL
2 2V5_ANA 5 +2V5
3 GND_BRD 6 2V5_ANA
Table 9. Power ground isolator pin allocation (CN4 on MB676, CN2 on MB704)
1 +3V3 4 GND_ISOL
2 CPUIO 5 +3V3
3 GND_BRD 6 CPUIO
1 +2V5 (DDR) 4 GND_ISOL

2 CPULMI 5 +2V5 (DDR)
3 GND_BRD 6 CPULMI
1 +1V 4 GND_ISOL
2 CPUINT 5 +1V
3 GND_BRD 6 CPUINT
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A.3.4 External USB physical interface connector

Note: This connector is only present on the MB676 processor board.
This is connector CN9 on the MB676.
A 100-pin connector for use with an external USB PHY.
Figure 27. External USB physical interface connector
50 1
Viewed from side of PCB
Table 12. External USB physical interface allocation

1 2
3 4
5 6
7 NC 8
9 10
11 12
13 14 NC
15 TP69 16
17 notRESET_ULPI 18
19 20
21 22
23 24
NC
25 26
27 28 +5V
29 30
NC
31 ULPI_DATA7_T 32
33 ULPI_DATA5_T 34 ULPI_DATA3_T
35 36 ULPI_DATA1_T
37 NC 38
NC
39 40
8149405 45/160
Table 12. External USB physical interface allocation (continued)

41 42
NC
43 44
45 TP29 46 NC
47 NC 48
49 GND 50
51 52 ULPI_REFCLK
NC
53 54
55 TP68 56
57 58
59 60
NC
61 62
63 NC 64
65 66
67 68
69 70 ULPI_DIR
71 ULPI_NXT 72
73 74
75 76 NC
77 NC 78
79 80
81 82 ULPI_DATA6_T
83 ULPI_DATA4_T 84 NC
85 ULPI_DATA2_T 86 ULPI_DATA0_T
87 88 NC
89 90 ULPI_CLK
91 92
NC
93 NC 94
95 96 ULPI_STP_t
97 98
NC
99 100
46/160 8149405
A.3.5 Debug connector

This connector is CN10 on the MB676 and CN11 on the MB704.
A 20-pin connector provides a debug function.
Figure 28. Debug connector
19 1
20 2
Table 13. Debug connector pin allocation

Even pins GND 11 TCK

1 RESERVED 13 TDI (data into the board)
3 TRIGOUT 15 TDO (data out of the board)
5 TRIGIN 17 notRST_JTAG
7 notASEBRK 19 notTRST
9 TMS
8149405 47/160
A.3.6 Board to board connectors

These connectors are CN11 and CN12 on the MB676 and CN8 and CN9 on the MB704.
Connection between the processor board and the SD peripheral board is by two Samtec
128-pin connectors.
The connectors interface directly with two Samtec 120-pin connectors on the top surface of
the SD generic peripheral board (MB762).
CN11/CN8 (EMI) on the processor board connects to CN29 on the MB762 peripheral board
and CN23 on the MB829 peripheral board.
CN12/CN9 (PIO) on the processor board connects to CN30 on the MB762 peripheral board
and CN16 on the MB829 peripheral board.
Figure 29. Board to board connector
2 128
1 127
Viewed from below PCB
Note: In Table 14, shaded cells represent pins that are only available on MB676. They are not
connected on the MB704.
.
Table 14. Board to board connector CN11/CN8

1 VID_GND0 2 AUD_GND0
3 VDAC_XOUT 4 ADAC_VBG
7 VDAC_UOUT 8 ADAC_AOL
11 NC 12 NC
15 VDAC_WOUT 16 ADAC_AOR
19 VDAC_VOUT 20 SPDIF
23 EMI_ADDR24 24 FMI_ADDR25
25 EMI_ADDR23_DVOCLK 26 FMI_ADDR5
27 FMI_ADDR21_DVODATA1 28 FMI_ADDR22_DVODATA0
29 EMI_ADDR3 30 FMI_ADDR20_DVODATA2
48/160 8149405
Table 14. Board to board connector CN11/CN8 (continued)

31 EMI_ADDR7 32 notFMICSD
33 notFMICSC 34 FMI_ADDR17_DVODATA4
35 EMI_ADDR6 36 FMI_ADDR8
37 notFMICSB 38 notFMIBAA_DVBCILORD
39 notFMICSA_SPICS 40 FMI_ADDR18
41 FMI_ADDR4 42 FMI_ADDR19_DVODATA3
43 FMI_ADDR10 44 FMI_ADDR9
47 notFMIBE1 48 notFMIBE0_DVBCILOWR
51 FMI_NANDWAIT 52 FMI_ADDR15
53 FMI_ADDR12 54 FMI_ADDR16_DVODATA5
55 FMI_DATA1 56 notFMIOE
57 FMI_RDnotWR 58 FMI_DATA14_DVBCI2
59 FMI_DATA7 60 FMI_DATA15_DVBCI1
61 FMI_DATA6 62 FMI_DATA12_DVBCI_RESET
63 FMI_DATA13_DVBCI_CD1 64 FMI_DATA5
65 FMI_DATA3 66 FMI_DATA4
67 FMI_WAIT 68 notFMILBA
71 FMI_DATA10 72 FMI_ADDR1
75 FMI_DATA0 76 NAND_RBN2
77 TSOINDATA7 78 TSOINDATA6
79 TSOINBITORBYTECLK 80 TSOINPACKETCLK
81 TSOINDATA5 82 TSOINBITORBYTECLKVALID
83 TSOINERROR 84 TSOINDATA4
89 TS0OUTERROR 90 TS0OUTPACKETCLK
91 TS0OUTBITORBYTECLK 92 TS0OUTBITORBYTECLKVALID
93 TS0OUTDATA4 94 TS0OUTDATA5
8149405 49/160

101 NANDCSN2 102 NANDCSN3

103 DCU_TCK 104 notMODULERESETIN
105 DCU_TDO 106 DCU_TDI
107 DCU_notTRST 108 DCU_TMS
109 AUX_TMS 110 AUX_TCK
111 DCU_notASEBRK 112 DCU_TRIGGEROUT
113 DCU_TRIGGERIN 114 DCU_DEBUGMODESEL
115 SPARE4 116 SPARE5
119 AUX_TDUP 120 AUX_TDDOWN
121 SCRN1 122 SCRN2
123 SCRN3 124 SCRN4
125 SCRN5 126 SCRN6
127 SCRN7 128 SCRN8
.
Table 15. Board to board connector CN12/CN9

1 2
3 4
5 +5V 6 +5V
7 8
9 10
11 NC 12 NC
13 14
15 16
17 +3V3 18 +3V3
19 20
21 22
23 NC 24
25 26
27 28
+12V NC
29 30
31 32
33 NC 34
35 SC0DATAOUT 36 SC0DATAIN
50/160 8149405

37 SC0EXTCLK 38 SC0CLK
39 SPI_DATAIN 40 PCMLRCLKOUT
41 SPI_DATAOUT 42 SC0RESET
43 SPI_CLK 44 FDMAREQ1
45 PCMLRCLKIN 46 PCMDATAOUT
47 ASC3_RXD 48 SC0CMDVCC
49 SC0VPP 50 FDMAREQ0
51 ASC3_TXD 52 PCMSCLKOUT
53 PCMDATAIN 54 FPRESET
55 SC0DETECT 56 SC1CLK
57 SCART2_BI_LED2 58 DVODATA0
59 DVO_DATA7 60 DVODATA1
61 OSD_ACTIVE_DVOCLK 62 ASC2CTS
63 DVO_DATA6 64 DVODATA2
65 SCART1_BI_LED1 66 ASC2RTS
67 IRB_OUT 68 DVODATA3
69 SC1DATAOUT 70 ASC2RXD
71 IRB_IN 72 DVODATA4
73 CLK27 74 ASC2TXD
75 INTUP0 76 SC1DETECT
77 SSC0_SCLKINOUT 78 SC1DATAIN
79 DVBCI_2 80 HSYNC
81 SC1EXTCLK 82 DMAREQ1
83 INTUP1 84 SC1RESET
85 AUXCLKOUT 86 LED_DRIVE
87 FMIFLASHCLK 88 SC1CMDVCC
89 SC1VPP 90 VSYNC
91 INTUP2 92 KEY_CTRL
93 HSYNC_EN 94 VSYNC_EN
95 DVBCI_CD1 96 DMAREQ0
notRSTOUT_GPIO_LOCAL_
97 SSC1CLK 98
RESET
99 ASC3_CTS 100 PCMMCLK
101 ASC3_RTS 102 SPI_CS_YC3
103 PCMSCLKIN 104 SSC0_MTSR_DINOUT
8149405 51/160

105 YC2 106 SSC1DATAINOUT

107 DVBCI_RESET 108 DVBCI_BUSGNT
109 INTDOWN0 110 DVBCI_BUSREQ
111 NANDCSN1 112 INTDOWN1
113 NANDRBN1 114 NANDRBN3
115 116
117 +5V 118 +5V
119 120
121 122
123 124
GND GND
125 126
127 128
A.3.7 Single USB2.0 type A connector

Surface mount, single USB2.0 type A connector.
Figure 30. USB2.0 connector
1 2 3 4
Viewed from front panel
Table 16. USB2.0 connector pin allocation

1 VBUS 3 DP
2 DM 4 GND
52/160 8149405
A.3.8 External clock connector

Vertical PCB mounting, SMB socket (male).
Figure 31. External clock connector
1 2
Table 17. External clock connector pin allocation

1 CLKIN 2 GND
A.3.9 MII Ethernet connector

Surface mount, vertical male connector. Double row of 20 pins with a pitch of 1.27 mm.
Mates with FFSD connector.
Note: The location of pin 1 on the connector is identified on the same side as the notched blade of
the connector.
Figure 32. MII Ethernet connector
39 1
40 2
Table 18. MII Ethernet connector pin allocation

1 2
3 NC 4 NC
5 6
7 MII_COL 8 MII_CRS
9 MII_TXD0 10 MII_TXD1
13 GMII_TXD4 14 GMII_TXD5
15 GMII_TXD6 16 GMII_TXD7
8149405 53/160
Table 18. MII Ethernet connector pin allocation (continued)

17 NC 18 MII_TXEN
19 MII_TXCLK 20 NC
21 MII_RXCLK 22 MII_RXER
23 MII_RXDV 24 NC
25 MII_RXD0 26 MII_RXD1
29 GMII_RXD4 30 GMII_RXD5
31 GMII_RXD6 32 GMII_RXD7
33 NC 34 MII_MDC
35 MII_MDIO 36 notRESET
37 notINT 38 RMIIMODE
39 GMIIMODE 40 NC
A.3.10 HDMI connector

This connector is CN15 on both the MB676 and the MB704.
A male, 19-pin connector.
The high-definition multimedia interface is a trademark of HDMI Licensing, LLC.
Figure 33. HDMI connector
HDMI
HDMI cable
Table 19. HDMI connector pin allocation

1 TX2P (D2+) 11 GND (CKS)

2 GND (D2S) 12 CK-
3 TX2N (D2-) 13 HDMI_CEC (CEC)
4 TX1P (D1+) 14 NC
5 GND (D1S) 15 SCL
6 TX1N (D1-) 16 SDA
7 TX0P (D0+) 17 GND
8 GND (D0S) 18 +5V
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Table 19. HDMI connector pin allocation

9 TX0N (D0-) 19 HDMI_HPD (HPG)

10 CK+
A.3.11 Satellite tuner

Vertical PCB mounting, SMB socket (male).
Figure 34. Satellite tuner
1 2
Table 20. Satellite tuner pin allocation

1 RF_IN 2 GND
A.3.12 Digital cable tuner

The digital cable tuner is IC24 on the MB676 and IC22 on the MB704.
The tuner input is fed into the female connector. The male connector provides an output as
a loop-through of the input.
Figure 35. Digital cable tuner

MB676 front panel MB704 front panel
GND
GND GND
Female
(cable input)
Female Male
GND
(cable input) (cable output)
Male
(cable output) Viewed from front panel
Table 21. Digital cable tuner pin allocation

Female Input Male Loop-through
8149405 55/160
MB762 SD generic peripheral board connectors STi5197-MBoard, STi5189/97-MB
Appendix B MB762 SD generic peripheral board

connectors
B.1 Connector layout

The connector placements on the SD generic peripheral board are shown in Figure 36.
Figure 36. SD generic peripheral board top assembly connector layout
ATAPI PCM I2C DVO HDD power DC socket

connector connector connector connector power connector
Smartcard
connectors PIO/PWR connector
LVDS debug connector
RF modulator connector
STEM EMI FMI/TS/AV connector

connector
SPDIF phono connector

CVBS phono connector
L audio DAC phono connector
R audio DAC phono connector
PCMCIA
card EPLD ByteBlaster connector
connector
TV ouput and AUX input
SCART connectors
RJ45 PCM output debug connector
Ethernet
connector L PCM audio phono connector
R PCM audio phono connector
Transport stream connector
NIM connector
Dual RS232 Ethernet data

connectors connector
56/160 8149405
STi5197-MBoard, STi5189/97-MB MB762 SD generic peripheral board connectors
B.2 Front and rear panel layout

The front and rear panels of the SD generic peripheral board assembly are shown in
Figure 37 and Figure 38.
The processor board panel (see Section A.2 on page 40) screws into the rear panel of the
SD generic peripheral board.
Figure 37. Front panel assembly
Figure 38. Rear panel assembly
Processor board panel
8149405 57/160
B.3 Connectors
The connectors that are fitted on the MB762 SD generic peripheral board are shown in
Table 22, Table 23 and Table 24.

Connector
number
NIM connector CN10 Section B.3.5 on page 63

HDD power connector CN11 Section B.3.6 on page 65
PCM audio output debug connector CN12 Section B.3.7 on page 65
Transport stream connector CN14 Section B.3.8 on page 66
Digital video output connector CN15 Section B.3.9 on page 67
JTAG EPLD debug connector (ByteBlaster) CN16 Section B.3.10 on page 68
PCM input connector CN17 Section B.3.11 on page 68
Smartcard 1 header connector CN18 Section B.3.12 on page 69
Smartcard 0 header connector CN19 Section B.3.12 on page 69
High density logic probe pattern connector CN20 Section B.3.13 on page 69
ATAPI connector CN21 Section B.3.14 on page 71
+3V3 I2C blaster connector CN23 Section B.3.16 on page 73
Ethernet MII connector CN24 Section B.3.17 on page 74
STEM EMI connector CN26 Section B.3.19 on page 76
CN29
Board to board connectors Section B.3.22 on page 80
CN30

Connector
number
DVB-CI card slot connector CN22 Section B.3.15 on page 72

Dual smartcard interface connector CN25 Section B.3.18 on page 75
Ethernet RJ45 connector CN27 Section B.3.20 on page 78
Dual RS232 (1 male and 1 female) connectors CN28 Section B.3.21 on page 79
Table 24. Rear panel external connectors

Connector
number
DC power socket connector CN1 Section B.3.1 on page 59

LVDS debug connector CN2 Section B.3.2 on page 60
SPDIF phono connector CN3 Section B.3.3 on page 61
CVBS phono connector CN4 Section B.3.3 on page 61
Left audio DAC phono connector CN5 Section B.3.3 on page 61
58/160 8149405
Table 24. Rear panel external connectors (continued)

Connector
number
Right audio DAC phono connector CN6 Section B.3.3 on page 61

TV output and AUX input SCART connectors CN7 Section B.3.3 on page 61
Left PCM audio phono connector CN8 Section B.3.3 on page 61
Right PCM audio phono connector CN9 Section B.3.3 on page 61
RF antenna and TV connector IC11 Section B.3.23 on page 84
B.3.1 DC power socket CN1

A +12V DC, 2.5 A input jack socket connector from RS electronics.
For DC use only.
Figure 39. DC power socket
2 1
Viewed from rear panel
Table 25. DC power socket pin allocation

(1)
1 GND 2 +VIN
1. Male jack connector pin.
8149405 59/160
B.3.2 LVDS debug type G connector CN2

A 68-pin connector for debug functions.
Figure 40. LVDS debug type G connector
34 1
68 35
Table 26. LVDS debug type G connector pin allocation

1 LVDS_SPAREIN+ 35 LVDS_SPAREIN-
2 LVDS_EPLD_TDI+ 36 LVDS_EPLD_TDI-
3 LVDS_TRIGIN+ 37 LVDS_TRIGIN-
4 LVDS_EPLD_TMS+ 38 LVDS_EPLD_TMS-
5 LVDS_USERIN+ 39 LVDS_USERIN-
6 LVDS_EPLD_TCK+ 40 LVDS_EPLD_TCK-
7 LVDS_TMS+ 41 LVDS_TMS-
8 LVDS_EPLD_TDO+ 42 LVDS_EPLD_TDO-
9 LVDS_USEROUT+ 43 LVDS_USEROUT-
10 LVDS_EPLD_SPARE1+ 44 LVDS_EPLD_SPARE1-
11 LVDS_TRIGOUT+ 45 LVDS_TRIGOUT-
13 LVDS_TDO+ 47 LVDS_TDO-
15 GND 49
GND
16 LVDSBUF_notEN 50
17 51
+5V_LVDS +5V_LVDS
18 52
19 LVDS_CLKOUT+ 53 LVDS_CLKOUT-
20 GND 54 GND
21 LVDS_CLKIN+ 55 LVDS_CLKIN-
22 GND 56 GND
23 LVDS_TDI+ 57 LVDS_TDI-
24 LVDS_MODE_SEL+ 58 LVDS_MODE_SEL-
25 LVDS_notRESET+ 59 LVDS_notRESET-
60/160 8149405
Table 26. LVDS debug type G connector pin allocation (continued)

26 NC 60 NC
27 LVDS_notTRST+ 61 LVDS_notTRST-
28 62
29 63
30 NC 64 NC
31 65
32 66
33 67
GND GND
34 68
B.3.3 Video and audio phono connectors CN3 to CN6, CN8 and CN9
These phono connectors output video or audio signals. Pin 2 is always grounded and the
other phono output pin 1 differs, depending on whether the phono is a video or an audio
connector. More information is given in Table 27.
Figure 41. Video and audio phono connectors
1 2
Table 27. Video and audio phono connector pin allocation

Connector Pin 1 Pin 2
CN3 SPDIF phono SPDIFOUT

CN4 CVBS phono CVBS_DALC
CN5 left audio DAC phono LOUT_TV
GND
CN6 right audio DAC phono ROUT_TV
CN8 left PCM audio phono AOUT_L
CN9 right PCM audio phono AOUT_R
8149405 61/160
B.3.4 Dual SCART connectors CN7

SCART-TV supports upstream to TV and SCART-AUX supports downstream to VCR.
Figure 42. Dual SCART connectors
20 18 16 14 12 10 8 6 4 2 Shield
SCART-TV
19 17 15 13 11 9 7 5 3 1
20 18 16 14 12 10 8 6 4 2 Shield
SCART-AUX
19 17 15 13 11 9 7 5 3 1
Table 28. Dual SCART connector pin allocation

1 AUDIO_OUT_R 2 AUDIO_IN_R
3 AUDIO_OUT_L 4 AUDIO_GND
5 BLUE_GND 6 AUDIO_IN_L
7 BLUE 8 FUNCTION_SWITCH
9 GREEN_GND 10 Reserved 1
11 GREEN 12 Reserved 2
13 RED_GND 14 COMM_GND
15 RED 16 BLANKING
17 VIDEO_GND 18 BLANKING_GND
19 VIDEO_OUT 20 VIDEO_IN
62/160 8149405
B.3.5 NIM connector CN10

One 84-pin connector. The connector is made up from two separate female connectors:
● a SAMTEC 28-pin
● a SAMTEC 54-pin
The two connectors are arranged, and the pins are numbered, as shown in Figure 43.
Pins 15 and 57 are not available.
Figure 43. NIM connector

15
42 16 14 1
84 58 56 43
RSM-127-02-xx 57 RSM-114-02-xx
Table 29. NIM connector pin allocation

1 LNBRF 43 Key1
2 GNDA1 44 VCORESEL_COM
3 GNDA2 45 VCORESEL_1V2
5 LNBSUPPLY5V 47 RESERVED1
6 GNDA4 48 RESERVED2
7 GNDA5 49 SRX
8 GNDA6 50 DRX
9 VCC3V3A 51 ITX
10 GNDA7 52 QTX
11 GNDA8 53 ETX
12 VCORE_A1 54 VCORE_A2
13 ANALOG5V 55 CTX
14 VTUNE32V 56 OOB_RESERVED
15 Key3 57 Key4
16 DISEQCRX 58 RESERVED3
17 ADDRESS0 59 ADDRESS1
18 DISEQCTX 60 RESERVED4
19 OP1 61 RESERVED5
20 OP0 62 RESERVED6
8149405 63/160
Table 29. NIM connector pin allocation (continued)

21 OP2 63 RESERVED7
22 GNDD1 64 GNDD4
23 VCORE_D1 65 VCORE_D3
24 PACKETCLK 66 PACKETCLK_2
25 BYTECLKVALID 67 BYTECLKVALID_2
26 BYTECLK 68 BYTECLK_2
27 ERROR 69 ERROR_2
28 GNDD2 70 GNDD5
30 DATA7 72 DATA7_2
31 DATA6 73 DATA6_2
32 DATA5 74 DATA5_2
33 DATA4 75 DATA4_2
34 DATA3 76 DATA3_2
35 DATA2 77 DATA2_2
36 DATA1 78 DATA1_2
37 DATA0 79 DATA0_2
38 GNDD3 80 GNDD6
39 VCC3V3D 81 RESERVED8
40 SCL 82 SCL_2
41 SDA 83 SDA_2
42 notRESET 84 Key2
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B.3.6 HDD power connector CN11

An auxiliary 4-pin power connector is used to provide power to the HDD.
Figure 44. HDD power connector
1 4
Table 30. HDD power connector pin allocation

1 +12V 2 GND
3 GND 4 +5V
B.3.7 PCM audio output debug connector CN12

A 2 x 8-way, 16-pin connector provides PCM audio debug output.
Figure 45. PCM audio output debug connector
15 1
16 2
Table 31. PCM audio output debug connector pin allocation

Even pins GND 9 PCMDACPCMCLK

1 TP27 11 TP24
3 PCMDACLRCLK 13 +5V
5 PCMDACSCLK 15 TP22
7 PCMDACDATA
8149405 65/160
B.3.8 Transport stream data connector CN14

A 20-pin connector provides transport stream data output.
Figure 46. Transport stream data connector
19 1
20 2
Table 32. Transport stream data connector pin allocation

1 SDA 2 SCL
3 notRST 4 NC
5 DATA0 6 DATA1
7 DATA2 8 DATA3
9 DATA4 10 NC
11 DATA5 12 DATA6
13 DATA7 14 NC
15 TSERROR 16 TSCLK
17 TSVALID 18 NC
19 TSPACKETCLK 20 AS1
66/160 8149405
B.3.9 DVO connector CN15

A 26-pin, surface mount, vertical male connector. Double row of 13 pins, 1.27 mm pitch with
polarity.
Figure 47. DVO connector
25 1
26 2
Table 33. DVO connector pin allocation

1 DVODATA0 2
3 DVODATA1 4
5 DVODATA2 6 NC
7 DVODATA3 8
9 GND 10
11 DVODATA4 12 GND
13 GND 14 DVOCLK
15 DVODATA5 16 GND
17 DVODATA6 18 +3V3
19 DVODATA7 20 I2CSCLDVO
21 GND 22 NC
23 DVOHSYNC 24 I2CSDADVO
25 DVOVSYNC 26 +5V
8149405 67/160
B.3.10 JTAG debug (ByteBlaster) connector CN16

A 10-pin connector, provides a JTAG standard debug ByteBlaster interface. A 2 x 5-way
vertical terminal strip, surface mount, shrouded pin header connector, with an alignment pin
pitch of 2.54 mm.
Figure 48. JTAG debug (ByteBlaster) connector
9 1
10 2
Table 34. JTAG debug (ByteBlaster) connector pin allocation

1 DCCLK_TCK 2 GND1
3 CONFDONE_TD0 4 VCC
5 notCONFIG_TMS 6 NC_AUXTD0
7 notSTATUS_NC 8 NC_notTRST
9 DATA0_TDI 10 GND2
B.3.11 PCM audio input connector CN17

A 2 x 8-way, 16-pin connector provides PCM audio input.
Figure 49. PCM audio input connector
15 1
16 2
Table 35. PCM audio input connector pin allocation

Even pins GND 9 PCMCLK

1 TP77 11 I2CSCLPCMIN
3 PCMLRCLKIN 13 TP43
5 PCMSCLKIN 15 I2CSDAPCMIN
7 PCMDATAIN
68/160 8149405
B.3.12 Smartcard header data connectors CN18/CN19

Two 8-pin vertical post PTH header connectors provide smartcard data.
Figure 50. Smartcard header data connector
8 1
Table 36. Smartcard header data connector pin allocation

Pin Description(1) Pin Description
1 SCnDATAOUT 5 SCnRESET
2 SCnDATAIN 6 SCnCMDVCC
3 SCnEXTCLK 7 SCnVPP
4 SCnCLK 8 SCnDETECT
1. Where n=0 for CN19 and n=1 for CN18.
B.3.13 P6960 series high-density logic probe land pattern CN20

A 27-channel, Tektronix P6960 series high-density logic probe land pattern.
Figure 51. P6960 series logic probe land pattern

A27 A1
B27 B1
Table 37. P6960 series logic probe land pattern pin allocation
Pin row A Description Pin row B Description
1 BUFF_DVBDATA3 1 GND
2 BUFF_DVBDATA5 2 BUFF_DVBDATA4
3 GND 3 BUFF_DVBDATA6
5 BUFF_DVBADDR10 5 notDVBCE
6 GND 6 notDVBIOOE
7 TP110 (CK1+) 7 GND
8 TP111 (CK1-) 8 BUFF_DVBADDR11
9 GND 9 notDVBIORD
8149405 69/160
Table 37. P6960 series logic probe land pattern pin allocation (continued)
10 BUFF_DVBADDR9 10 GND
11 BUFF_DVBADDR8 11 notDVBIOWR
12 GND 12 BUFF_DVBADDR13
14 notDVBINTR 14 notDVBIOWE
17 notDVBRESET 17 BUFF_DVBADDR6
19 notDVBWAIT 19 GND
20 BUFF_DVBADDR4 20 TP116 (CK2-)
21 GND 21 TP117 (CK2+)
23 notDVBREG 23 BUFF_DVBADDR2
70/160 8149405
B.3.14 ATAPI connector CN21

A 2 x 20-way, 40-pin connector provides ATAPI data.
Figure 52. ATAPI connector
39 1
40 2
Table 38. ATAPI connector pin allocation

1 notRESET 2 GND
3 DD7 4 DD8
5 DD6 6 DD9
7 DD5 8 DD10
9 DD4 10 DD11
11 DD3 12 DD12
13 DD2 14 DD13
15 DD1 16 DD14
17 DD0 18 DD15
19 GND 20 Reserved
21 DMARQ 22
23 notDIOW 24 GND
25 notDIOR 26
27 IORDY 28 SPSYNC_CSEL
29 notDMACK 30 GND
31 INTRQ 32 notIOCS16
33 DA1 34 notPDIAG
35 DA0 36 DA2
37 notCS0 38 notCS1
39 notDASP 40 GND
8149405 71/160
B.3.15 DVB-CI connector CN22

A 68-pin DVB-CI connector. Single DVB-CI connector, supports type I, II cards. Single port,
right angle, top mount, through hole, 68-pin, with eject (right side).
Figure 53. DVB-CI connector
34 1
68 35
Table 39. DVB-CI connector pin allocation

1 NC 35 NC
2 DATA3 36 notCD1
3 DATA4 37 TS_OUT_DATA3
7 notCE1 41 TS_OUT_DATA7
8 NC 42 notCE2
9 notOE 43 NC
10 A11 44 notIORD
11 A9 45 notIOWR
12 A8 46 TS_IN_STRT
13 A13 47 TS_IN_DATA0
15 notWE 49 TS_IN_DATA2
16 notIREQ 50 TS_IN_DATA3
17 VCC1 51 VCC0
18 VPP1 52 VPP0
19 TS_IN_VAL 53 TS_IN_DATA4
20 TS_IN_CLK 54 TS_IN_DATA5
23 A6 57 TS_OUT_CLK
24 A5 58 CARD_RESET
72/160 8149405
Table 39. DVB-CI connector pin allocation (continued)

25 A4 59 notWAIT
26 A3 60 NC
27 A2 61 notREG
28 A1 62 TS_OUT_VAL
29 A0 63 TS_IN_STRT
33 notIOIS16 67 notCD2
34 NC 68 NC
B.3.16 +3V3 I2C blaster connector CN23

An 8-pin header provides I2C interfaces.
Figure 54. +3V3 I2C blaster connector
4 1
8 5
Table 40. I2C connector pin allocation

1 Removed for polarization 5 USER2(1)

2 VCC 6 SCL
3 USER1(1) 7 USER3(1)
4 SDA 8 GND
1. Connected to NIM reset.
8149405 73/160
B.3.17 Ethernet MII data connector CN24

A 40-pin connector provides Ethernet data output.
Figure 55. Ethernet MII data connector
39 1
40 2
Table 41. Ethernet MII data connector pin allocation

1 GND 2 GND
3 4
+3V3 +5V
5 6
7 MII_COL 8 MII_CRS
13 GMII_TXD4 (NC) 14 GMII_TXD5 (NC)
17 GND 18 MII_TX_EN
19 MII_TXCLK 20 GND
21 MII_RXCLK 22 MII_RX_ER
23 MII_RX_DV 24 GND
29 GMII_RXD4 (NC) 30 GMII_RXD5 (NC)
33 GND 34 MII_MDC
37 notINT 38 RMII_MODE
39 GMII_MODE 40 GND
74/160 8149405
B.3.18 Smartcard sockets CN25

Two 10-pin smartcard sockets. Dual smartcard connector, friction contacts, through hole,
normally closed detection switch.
Figure 56. Smartcard socket
1 4
11 14 9 10
Indicates pins 11-20
of bottom smartcard
19 20 (smartcard 1)
15 18
5 8
Top smartcard viewed from above PCB
Table 42. Smartcard socket pin allocation

1 GNDC 11 GNDC
2 SC0VPP 12 SC1VPP
3 IO 13 IO
4 AUX2 14 AUX2
5 VCC 15 VCC
6 RST 16 RST
7 CLK 17 CLK
8 AUX1 18 AUX1
9 GNDC 19 GNDC
10 PRES/notPRES 20 PRES/notPRES
8149405 75/160
B.3.19 STEM EMI CN26

A 140-pin surface mount board to board connector plug.
Figure 57. STEM EMI connector
140 71
70 1
Table 43. STEM EMI connector pin allocation

1 notBS 71 notFRAME
2 SDRAM_CLK 72 notCAS
3 SDRAM_CLKEN 73 notRESET
4 MEZZ_PRESENT0 74 MEZZ_PRESENT1
5 GND 75 GND
6 DACK2 76 DACK3
7 DACK0 77 DACK1
8 DRAK0 78 DRAK1
9 DREQ0 79 DREQ1
10 GND 80 GND
11 MEMWAIT 81 AUX_CLK
12 +3V3 (VCC) 82 +3V3 (VCC)
13 MEMGRANTED 83 MEMREQ
14 notINTR0 84 notINTR1
15 GND 85 GND
16 FLASH_CLK 86 FBAA
17 GND 87 GND
18 notWR 88 notOE
19 GND 89 GND
20 notCS0 90 notCS1
21 GND 91 GND
22 A25 92 A24
23 A23 93 A22
24 +3V3 (VCC) 94 +3V3 (VCC)
25 A21 95 A20
76/160 8149405
Table 43. STEM EMI connector pin allocation (continued)

26 A19 96 A18
27 GND 97 GND
28 A17 98 A16
29 A15 99 A14
30 +3V3 (VCC) 100 +3V3 (VCC)
31 A13 101 A12
32 A11 102 A10
33 GND 103 GND
34 A9 104 A8
35 A7 105 A6
36 +3V3 (VCC) 106 +3V3 (VCC)
37 A5 107 A4
38 A3 108 A2
39 GND 109 GND
40 A1_notBE3 110 A0_notBE2
41 notBE1 111 notBE0
42 GND 112 GND
43 D31 (NC) 113 D30 (NC)
44 D29 (NC) 114 D28 (NC)
45 GND 115 +5V VCC
46 D27 (NC) 116 D26 (NC)
47 D25 (NC) 117 D24 (NC)
48 GND 118 GND
49 D23 (NC) 119 D22 (NC)
50 D21 (NC) 120 D20 (NC)
51 GND 121 +5V VCC
52 D19 (NC) 122 D18 (NC)
53 D17 (NC) 123 D16 (NC)
54 GND 124 GND
55 D15 125 D14
56 D13 126 D12
57 GND 127 +5V VCC
58 D11 128 D10
59 D9 129 D8
60 GND 130 GND
8149405 77/160

61 D7 131 D6
62 D5 132 D4
63 GND 133 +5V VCC
64 D3 134 D2
65 D1 135 D0
66 GND 136 GND
67 MPX_CLK 137 ALE_notRAS
68 GND 138 GND
69 139
+12 V (VCC) +12 V (VCC)
70 140
B.3.20 RJ45 Ethernet connector CN27

An RJ45 connector provides a 10/100 BaseT Ethernet physical layer (PHY) interface.
Figure 58. Ethernet connector

Ethernet
LED2 LED1
Table 44. Ethernet connector pin allocation

MDI_2CT MDI_3CT
1 7
+2V5_GMII +2V5_GMII
MDI_2- MDI_3+
2 8
MDIC_N MDID_P
MDI_2+ MDI_3-
3 9
MDIC_P MDID_N
MDI_1+ MDI_0-
4 10
MDIB_P MDIA_N
MDI_1- MDI_0+
5 11
MDIB_N MDIA_P
MDI_1CT MDI_0CT
6 12
+2V5_GMII +2V5_GMII
LED1 indicates Ethernet activity. LED2 indicates 100Base Tx Ethernet protocol.
78/160 8149405
LED output functions are user selectable. Up to two LED functions at one time. The LED
output functions are:
● activity
● full duplex
● 10BASE T or 100BASE TX Ethernet transmit protocol
● transmit, receive
B.3.21 Dual RS232 interface CN28
Figure 59. RS232 connectors
1 5
COM1
Female
6 9
5 1
COM0
Male
9 6
Table 45. RS232 connector pin allocation

1 NC 6 NC
2 RX 7 RTS
3 TX 8 CTS
4 NC 9 NC
5 GND
8149405 79/160
B.3.22 EMI and PIO peripheral to processor board connectors CN29/CN30

Connection between the SD generic peripheral board and processor board is by two
Samtec 2 x 120-pin connectors.
These connectors interface directly with two Samtec 2 x 128-pin connectors on the bottom
surface of the processor board.
Connector CN29 on the peripheral board connects to either CN11 on the MB676 or CN8 on
the MB704.
the MB704.
Figure 60. SD generic peripheral board to processor board connector
2 120
1 119
Table 46. Peripheral board to processor board EMI connector CN29

1 VIDGND0 2 AUDGND0
5 VIDGND1 6 AUDGND1
9 VIDGND2 10 AUDGND2
11 NC 12 NC
23 FMIADDR24 24 FMIADDR25
25 FMIADDR23_DVOCLK 26 FMIADDR5
27 FMIADDR21_DVODATA1 28 FMIADDR22_DVODATA0
29 FMIADDR3 30 FMIADDR20_DVODATA2
31 FMIADDR7 32 notFMICSD
33 notFMICSC 34 FMIADDR17_DVODATA4
80/160 8149405
Table 46. Peripheral board to processor board EMI connector CN29 (continued)
notFMIBAA_DVBCIIORD_
37 notFMICSB 38
FMIRDnotWR2
39 notFMICSA_SPICS 40 FMIADDR18
47 notFMIBE1 48 notFMIBE0_DVBCIIOWR
51 FMINANDWAIT 52 FMIADDR15
55 FMIDATA1 56 notFMIOE
57 FMIRDnotWR 58 FMIDATA14_DVBCI2
59 FMIDATA7 60 FMIDATA15_DVBCI1
61 FMIDATA6 62 FMIDATA12_DVBCIRESET
63 FMIDATA13_DVBCICD1 64 FMIDATA5
65 FMIDATA3 66 FMIDATA4
67 FMIWAIT 68 notFMILBA
71 FMIDATA10 72 FMIADDR1
75 FMIDATA0 76 NANDRBN2
77 TS0INDATA7 78 TS0INDATA6
79 TS0INBITORBYTECLK 80 TS0INPACKETCLK
81 TS0INDATA5 82 TS0INBITORBYTECLKVALID
83 TS0INERROR 84 TS0INDATA4
TS0OUTERROR_SC0CLK_ TS0OUTPACKETCLK_
89 90
SC0FSCLK0 SC0DATAIN_SSC1MRSTDINOUT
TS0OUTBITORBYTECLK_ TS0OUTBITORBYTECLKVALID_
91 92
SC0DATAOUT_SSC0DATAINOUT SC0EXTCLK_IRBPPMOUT
TS0OUTDATA5_SC0DIR_
93 TS0OUTDATA4_SC0DETECT 94
SC0notSETVPP
TS0OUTDATA6_SC0CMDVCC_ TS0OUTDATA7_SC0RESET_
95 96
ASC0CTS_SC0notSETVCC ASC0RTS
TS0OUTDATA0_SC1POWER_ TS0OUTDATA1_SC1RESET_
97 98
TV0DENC_ASC1CTS VSYNC_ASC1RTS
8149405 81/160
TS0OUTDATA3_SC1DATAINOUT_
99 TS0OUTDATA2_SC1CLK_HSYNC 100
PIXCLK
101 NANDSCN2 102 NANDSCN3
.
Table 47. Peripheral board to processor board PIO connector CN30

1 2
3 4
5 +5V 6 +5V
7 8
9 10
11 NC 12 NC
13 14
15 16
17 +3V3 18 +3V3
19 20
21 22
23 NC 24
25 26
27 28
+12V NC
29 30
31 32
33 NC 34
82/160 8149405
Table 47. Peripheral board to processor board PIO connector CN30 (continued)
47 ASC3RXD 48 SC0CMDVCC
51 ASC3TXD 52 PCMSCLKOUT
SEVEN_SEG_DISPLAY4_
57 SCART_2_BILED2 58
DVODATA0
SEVEN_SEG_DISPLAY3_
59 DVODATA7 60
DVODATA1
SEVEN_SEG_DISPLAY2_
63 DVODATA6 64
DVODATA2
65 SCART_1_BILED1 66 ASC2RTS
SEVEN_SEG_DISPLAY1_
67 IRB_OUT 68
DVODATA3
SEVEN_SEG_DISPLAY0_
71 IRB_IN 72
DVODATA4
73 CLK27 74 ASC2TXD
79 GPIO_DVBCI_2 80 HSYNC
89 SC1VPP 90 VSYNC
93 HSYNCEN 94 VSYNCEN
97 SSC1CLK 98 notRSTOUT_LOCAL_RESET
99 ASC3CTS 100 PCMMCLK
101 ASC3RTS 102 SPI_CS_YC3
8149405 83/160

115 116
117 +5V 118 +5V
119 120
B.3.23 RF modulator connector IC11

This BTSC RF modulator is the interface between NTSC-M, PAL-M system modulator and a
television. The RF modulator has two female connectors.
Figure 61. RF modulator connector
GND GND
1 2
Table 48. RF modulator connector pin allocation

1 RF_OUTPUT 2 ANTENNA_IN
84/160 8149405
STi5197-MBoard, STi5189/97-MB MB829 SD modular validation peripheral board connectors
Appendix C MB829 SD modular validation peripheral

board connectors
C.1 Connector layout

The connector placements on the SD modular validation peripheral board are shown in
Figure 62.
Figure 62. SD modular validation peripheral board top assembly connector layout
ATX power PCM DVO PCM audio

connector header header debug
J10
C1
J8
CN27
L17
TP79
CN14 H1
TP80
SW6
C195
H13
CN15 CN13 PCM audio

R256 R174 TP62 TP61 TP59 TP60 TP1
R150
C249 C90
C217
R82
R84
R83
IC23
C196
C177
C91 TP3 TP2
C2
TP63 TP38
C92 C3
C94
R85
R86
R87
CN1
C140
C139 TP4
R151
C93 R1
C6
output phono
TP39
C95
C7
R2
C5
L9
C4
IC14
IC13
R3
H11 L10 C8 L1
C9
IC39 IC38 IC30
C10
R209
R208
C96
C12
C13
C221
C220
C222
R4
C11
C218
TP116
TP64
R5
C219 R152 R153 R88 C14
C178 R154
IC1
CN2
R175 R89
CN28
C197 R90
R6
R94
R91
R92
R93
R95
C97
R155 R156
C144
C145
C146
C141
C143
C142
C98
C100
C99
IC31
TP5 R7
C15
Dual smartcard IC24
C16
TP65
H7 H2
TP6
IC40
R157
CN16
C224
C225
R212
R213
R210
R215
R214
R217
C223
R211
R216
C179
C198
TR4
R219
connector Audio DAC

R218
C148
C150
C147
C149
C102
C101
C103
R96
TR5
C226
R176
R221 R220 TP81

R223
R222
C151
C18
C230
C229
C228
R97 C17
CN3
C199
IC32
C227
R224
IC33
output phono
C19
C20
C231
CN29
IC34
IC42
IC2
C22
C21
CN4
IC41 CVBS output
C232
C234
C233
R226
R227
R228
R225
R229
R231
R230
ATAPI R302
R257
R258
R232 R233
C24
C23
IC46
TP164
C250
TR6
R259 C235 D1 R8
CN5 phono
header
C251
IC45 TR7
R260
C253
C252
R261
C254
R303
TP117
J20
TP165
R304
CN17
TP134 TP135 R177
C304
J14
CN31
TP119 TP118
TP136 CN18
R305 TP137
R234 TP82
CN6
C152
RBG video
TP120
C255 R178
IC47 IC49 IC50
IC43
CN32
R235
C257 C256
C105
C104
C236
R98
R99
C237
R179
C259 C258
R306
LD14
TP139 TP138
C260 C238 CN19

L11
C106
TP166
R307
C261 C25
C240
C239
output phonos
R122
IC48
R308
C262 C241
R100
CN7
C263
CN20
R123
R101
C264
C305
R103 R102
LD15
C265
CN21 R104
R124
IC16
C110
C109
C107
C306
R309
C26
C266 C242 R105

C267
C108
STEM EMI
CN22
R236
TP25
L12 C27
SPDIF output
R262
CN8
TP140
R263
C268 C243 TP83

R108
C270 C269
TP40
C307
R237 TP84
R106
R107
TP26 TP27
connector
R238 R180
R239 TP85
R240
C271 C272
R181 R9
CN23
TR1
phono
R182
TP121
R183 C28 R10
C274 C273 C275 C244
R11 C29
R184
CN9
R264 TP86 C30
R12
L2
R266 R265
TR2
R241
R267
C31
C32
TP87 TP88
R268
C245
R185
TP28 TP29
R269 TP141
C276
TP142
R270
R109
TP89
TP90
C33
R271
TP143
TP144
J11 R13
TP145
C308
C278 C277
R273 R272
H8 H3
Board to board
TP146
TP147
R186
R275 R274 R14
LD1
TP148
R15
TR3
R276
R277
TP149
TP150
R16 R17
R18
TP151
TP152
TP122
TP153
R110 R19
CN10
TP154
C200 R20
R278 C34
TP155
R187
R279
TP156
R280 R21
IC3
R281 TP158 TP157
R282
connectors
R22
R283
LD11
TP123
C35
TP124
TP8 R23
C36
IC35
R310 TP125 R24
IC5
R311
TP9
C153
C154
C111
IC4
R26 R25
TP126
J15
C202
C201
C37
TR8 C38
TP91
R312
R284 TP92 R27

IC6
H14
TP10
C280
IC25
STMC2 LVDS
C279 R28
TR9
TP93
LD16
TP127 TP11
R29 C39
TP94
R30
IC7
TP128 R188 TP95 TP12
R242
TP13
R313 C155
TP96 R189 R32 R31
J19
R125
TP129
TP97 TP14
R33 R34
TP98
R285 C112 C40

LD17 TP15
connector
TR10
IC8
R35 R36
TP99
C156
R126
C113 R37 R38

C203
TP16
TP100
C41
C309
TP101
C114 TP17
C42
R190
C157
R158
L3
TP130
TP18
C43
IC9
TP41
R39
R127
C115
R159
R128
C44
R129
R191
R41
R43
R40
R42
TP102
R160
C180
R161
R162 C45
R192
IC18
TP103
J9
C159
C160
H4
R130 C158
R131
H12
C116
IC26
R45
R44
R46
J2
R132
R136
CN33
EPLD ByteBlaster
C181
PCMCIA card C161

R135 R133 R134
R47
R193
R137
R138
TP104
IC22
R194
R139
SW1
C204
C205
C206
TP105
TP47 TP51 TP50 TP49 TP48
R140
connector connector
IC36
TP106
R48
TP73 TP72 TP68 TP67 TP66 TP70 TP71 TP69 TP52

C207
C208
CN11
R52
R51
R50
R49
C209 C182
SW2
TP107
TP109
R195 TP108
TP74
R53
TP110
R196
R197
C183
TP111
C210
R115 R114 R113 R112 R111
J6
C117
TP112
J1
TP53
SW3
R198
TP54
TP113
TP55
C118
TP19 TP7
TP56
TP75
C185
C184
R141
R199
R200
R54
R201
IC27
R142
C46
C48
C211 C186
R56
R55
TP114
H9
R163
SW4
TP76
C162 C119
R143
C212
C187
LD3
LD2
R57
C47
C163
R164
C120
TP115
C213
L4
R244
R245
R246
TP77
C214
SW5
TP78
R165 C121
R243 R202
J17
J16
C246
R58
CN12
R59
R64
R63
R62
R61
R60
IC19
CN34
C49
C123
C122
C164
IC10
LD9
LD8
LD7
LD6
LD5
LD4
R65
R314
Dual RS232
CN37
L18
L19
TP159
C50
C281
L20
J3
RJ45 Ethernet
CN36
IC20
C53
R67
C124
R66 C52 C51
TP160
connector
TP161
R69
C282
R286 R68
C54
R289 R291
C287
C284 C283 R287

IC11
C285 C286 R288

R290
R70
connector
C289
TP20
C56
CN24
C288
C55
C291
R294
C290 R292 R293
J4
R295 C293
C247
R296
R71
C59
R73
IC51
C292 R72 C57 C58
IC44
C294
L21
R297
TP162
C297
C296
Transport stream
C295
R247
R315 C298
R248
R298
R249
C188
C299
J7
C61
TP21
C60
R299
LD12
CN25
C300
R251
R300
LD13
C165
headers
C62
C248 R250
C189 D7
C301 C302
L13
TP22
L5
TP132 TP131
C63
L6 H5
D4
TP163
C64
L22
R74
C215
R203
R204
R205
TP32 TP33 TP31

R116
C65 C66
R253
R252
J12
L15
LD10
TP34 TP35
J13
XO2 XO1 L16
D2 D3
R117
IC37
CN35
LD19
LD18
C67
R301 R254 R118
IC12
TP36 TP24 TP23

TP57
C190
C68
R144
C303
C191
R75
C126
C125
C128
C127
C130
C129
C69
C166 C73 C70 C72 C71

D6
R120 R119 R121

C75 C76 C74
C192
R206
R207
C167
D5
CN26 NIM connector

R145
TP168
C168
C169
R166 C193
R167
R76
R146
R168
TP167
C171
IC28
R148
R169 C170 R147

R255
C172
R149
C216
C194
L14
R171 R173
TP133 R170
C77
J18
C174
C135
R80
C132
C131
C133
C134
R172
C80
C79 R77
C173 C78
C176
R79
L7
C136
C81 R78
C83
C82
R81
C137
L8
J5
C84
C85
C86
C175 TP37
C87
C89
C138
TP58
H6
C88
H15 H10
8149405 85/160
MB829 SD modular validation peripheral board connectors STi5197-MBoard, STi5189/97-MB
C.2 Connectors
The connectors that are fitted on the MB829 SD modular validation peripheral board are
shown in Table 49, Table 50 and Table 51.

Connector
number
JTAG EPLD debug connector (ByteBlaster) CN11 Section C.2.3 on page 89

PCM audio debug connector CN13 Section C.2.5 on page 90
Digital video output connector CN14 Section C.2.6 on page 91
PCM header connector CN15 Section C.2.7 on page 92
CN16
Board to board connectors Section C.2.8 on page 92
CN23
Debug transport stream connector CN24 Section C.2.9 on page 97
Control and data transport stream connector CN25 Section C.2.9 on page 97
NIM2.1 connector CN26 Section C.2.10 on page 98
ATX power connector CN27 Section C.2.11 on page 100
Smartcard 1 header connector CN28 Section C.2.12 on page 101
Smartcard 0 header connector CN29 Section C.2.12 on page 101
ATAPI connector CN31 Section C.2.14 on page 102
STEM EMI connector CN32 Section C.2.15 on page 103
High density logic probe pattern connector CN33 Section C.2.16 on page 106
2C
I blaster connector CN35 Section C.2.18 on page 108
High density logic probe pattern connector CN36 Section C.2.16 on page 106
Ethernet MII connector CN37 Section C.2.19 on page 109

Connector
number
Dual smartcard connector CN30 Section C.2.13 on page 101

DVB-CI card slot connector CN34 Section C.2.17 on page 107
Ethernet RJ45 connector CN38 Section C.2.20 on page 110
86/160 8149405
Table 51. Rear panel external connectors

Connector
number
Left PCM audio phono connector CN1 Section C.2.1 on page 87

Right PCM audio phono connector CN2 Section C.2.1 on page 87
Left audio DAC phono connector CN3 Section C.2.1 on page 87
Right audio DAC phono connector CN4 Section C.2.1 on page 87
CVBS phono connector CN5 Section C.2.1 on page 87
Red video output phono CN6 Section C.2.1 on page 87
Blue video output phono CN7 Section C.2.1 on page 87
Green video output phono CN8 Section C.2.1 on page 87
SPDIF phono connector CN9 Section C.2.1 on page 87
LVDS debug connector CN10 Section C.2.2 on page 88
Dual RS232 (1 male and 1 female) connectors CN12 Section C.2.4 on page 90
C.2.1 Video and audio phono connectors CN1 to CN9

These phono connectors output video or audio signals. Pin 2 is always grounded and the
other phono output pin 1 differs, depending on whether the phono is a video or an audio
connector. More information is given in Table 52.
Figure 63. Video and audio phono connectors
1 2
Table 52. Video and audio phono connector pin allocation

Connector Pin 1 Pin 2
CN1 left PCM audio phono AOUT_L

CN2 right PCM audio phono AOUT_R
CN3 left audio DAC phono LOUT_TV
CN4 right audio DAC phono ROUT_TV
CN5 CVBS phono CVBS_DALC GND
CN6 Red video output phono OUT1
CN7 Blue video output phono OUT2
CN8 Green video output phono OUT3
CN9 SPDIF phono SPDIFOUT
8149405 87/160
C.2.2 LVDS debug type G connector CN10

A 68-pin connector for debug functions.
Figure 64. LVDS debug type G connector
34 1
68 35
Table 53. LVDS debug type G connector pin allocation

1 LVDS_SPAREIN+ 35 LVDS_SPAREIN-
2 LVDS_EPLD_TDI+ 36 LVDS_EPLD_TDI-
3 LVDS_TRIGIN+ 37 LVDS_TRIGIN-
4 LVDS_EPLD_TMS+ 38 LVDS_EPLD_TMS-
5 LVDS_USERIN+ 39 LVDS_USERIN-
6 LVDS_EPLD_TCK+ 40 LVDS_EPLD_TCK-
7 LVDS_TMS+ 41 LVDS_TMS-
8 LVDS_EPLD_TDO+ 42 LVDS_EPLD_TDO-
9 LVDS_USEROUT+ 43 LVDS_USEROUT-
11 LVDS_TRIGOUT+ 45 LVDS_TRIGOUT-
13 LVDS_TDO+ 47 LVDS_TDO-
15 GND 49
GND
16 LVDSBUF_notEN 50
17 51
+5V_LVDS +5V_LVDS
18 52
19 LVDS_CLKOUT+ 53 LVDS_CLKOUT-
20 GND 54 GND
21 LVDS_CLKIN+ 55 LVDS_CLKIN-
22 GND 56 GND
23 LVDS_TDI+ 57 LVDS_TDI-
24 LVDS_MODE_SEL+ 58 LVDS_MODE_SEL-
25 LVDS_notRESET+ 59 LVDS_notRESET-
88/160 8149405
Table 53. LVDS debug type G connector pin allocation (continued)

26 NC 60 NC
27 LVDS_notTRST+ 61 LVDS_notTRST-
28 62
29 63
30 NC 64 NC
31 65
32 66
33 67
GND GND
34 68
C.2.3 JTAG debug (ByteBlaster) connector CN11

A 10-pin connector, provides a JTAG standard debug ByteBlaster interface. A 2 x 5-way
vertical terminal strip, surface mount, shrouded pin header connector, with an alignment pin
pitch of 2.54 mm.
Figure 65. JTAG debug (ByteBlaster) connector
9 1
10 2
Table 54. JTAG debug (ByteBlaster) connector pin allocation

1 DCCLK_TCK 2 GND1
3 CONFDONE_TD0 4 VCC
5 notCONFIG_TMS 6 NC_AUXTD0
7 notSTATUS_NC 8 NC_notTRST
9 DATA0_TDI 10 GND2
8149405 89/160
C.2.4 Dual RS232 interface CN12
Figure 66. RS232 connectors
1 5
COM1
Female
6 9
5 1
COM0
Male
9 6
Table 55. RS232 connector pin allocation

1 NC 6 NC
2 RX 7 RTS
3 TX 8 CTS
4 NC 9 NC
5 GND
C.2.5 PCM audio output debug connector CN13

A 2 x 8-way, 16-pin connector provides PCM audio debug output.
Figure 67. PCM audio output debug connector
15 1
16 2
Table 56. PCM audio output debug connector pin allocation

Even pins GND 9 PCMDACPCMCLK

1 TP27 11 TP24
3 PCMDACLRCLK 13 +5V
5 PCMDACSCLK 15 TP22
7 PCMDACDATA
90/160 8149405
C.2.6 DVO connector CN14

A 26-pin, surface mount, vertical male connector. Double row of 13 pins, 1.27 mm pitch with
polarity.
Figure 68. DVO connector
25 1
26 2
Table 57. DVO connector pin allocation

1 DVODATA0 2
3 DVODATA1 4
5 DVODATA2 6 NC
7 DVODATA3 8
9 GND 10
11 DVODATA4 12 GND
13 GND 14 DVOCLK
15 DVODATA5 16 GND
17 DVODATA6 18 +3V3
19 DVODATA7 20 I2CSCLDVO
21 GND 22 NC
23 DVOHSYNC 24 I2CSDADVO
25 DVOVSYNC 26 +5V
8149405 91/160
C.2.7 PCM audio input connector CN15

A 2 x 8-way, 16-pin connector provides PCM audio input.
Figure 69. PCM audio input connector
15 1
16 2
Table 58. PCM audio input connector pin allocation

Even pins GND 9 PCMCLK

1 TP77 11 I2CSCLPCMIN
3 PCMLRCLKIN 13 TP43
5 PCMSCLKIN 15 I2CSDAPCMIN
7 PCMDATAIN
C.2.8 EMI and PIO peripheral to processor board connectors CN16/CN23

Connection between the SD modular validation peripheral board and processor board is by
two Samtec 2 x 120-pin connectors.
These connectors interface directly with two Samtec 2 x 128-pin connectors on the bottom
surface of the processor board.
the MB704.
the MB704.
Figure 70. SD modular validation peripheral board to processor board connector
2 120
1 119
92/160 8149405
Table 59. Peripheral board to processor board PIO connector CN16

1 2
3 4
5 +5V 6 +5V
7 8
9 10
11 NC 12 NC
13 14
15 16
17 +3V3 18 +3V3
19 20
21 22
23 NC 24
25 26
27 28
+12V NC
29 30
31 32
33 NC 34
47 ASC3RXD 48 SC0CMDVCC
51 ASC3TXD 52 PCMSCLKOUT
SEVEN_SEG_DISPLAY4_
57 SCART_2_BILED2 58
DVODATA0
SEVEN_SEG_DISPLAY3_
59 DVODATA7 60
DVODATA1
SEVEN_SEG_DISPLAY2_
63 DVODATA6 64
DVODATA2
65 SCART_1_BILED1 66 ASC2RTS
8149405 93/160
SEVEN_SEG_DISPLAY1_
67 IRB_OUT 68
DVODATA3
SEVEN_SEG_DISPLAY0_
71 IRB_IN 72
DVODATA4
73 CLK27 74 ASC2TXD
79 GPIO_DVBCI_2 80 HSYNC
89 SC1VPP 90 VSYNC
93 HSYNCEN 94 VSYNCEN
97 SSC1CLK 98 notRSTOUT_LOCAL_RESET
99 ASC3CTS 100 PCMMCLK
101 ASC3RTS 102 SPI_CS_YC3
115 116
117 +5V 118 +5V
119 120
.
Table 60. Peripheral board to processor board EMI connector CN23

1 VIDGND0 2 AUDGND0
5 VIDGND1 6 AUDGND1
94/160 8149405
11 NC 12 NC
25 FMIADDR23_DVOCLK 26 FMIADDR5
27 FMIADDR21_DVODATA1 28 FMIADDR22_DVODATA0
31 FMIADDR7 32 notFMICSD
33 notFMICSC 34 FMIADDR17_DVODATA4
notFMIBAA_DVBCIIORD_
37 notFMICSB 38
FMIRDnotWR2
39 notFMICSA_SPICS 40 FMIADDR18
47 notFMIBE1 48 notFMIBE0_DVBCIIOWR
51 FMINANDWAIT 52 FMIADDR15
55 FMIDATA1 56 notFMIOE
57 FMIRDnotWR 58 FMIDATA14_DVBCI2
59 FMIDATA7 60 FMIDATA15_DVBCI1
61 FMIDATA6 62 FMIDATA12_DVBCIRESET
63 FMIDATA13_DVBCICD1 64 FMIDATA5
67 FMIWAIT 68 notFMILBA
71 FMIDATA10 72 FMIADDR1
75 FMIDATA0 76 NANDRBN2
8149405 95/160
79 TS0INBITORBYTECLK 80 TS0INPACKETCLK
81 TS0INDATA5 82 TS0INBITORBYTECLKVALID
83 TS0INERROR 84 TS0INDATA4
TS0OUTERROR_SC0CLK_ TS0OUTPACKETCLK_
89 90
SC0FSCLK0 SC0DATAIN_SSC1MRSTDINOUT
TS0OUTBITORBYTECLK_ TS0OUTBITORBYTECLKVALID_
91 92
SC0DATAOUT_SSC0DATAINOUT SC0EXTCLK_IRBPPMOUT
TS0OUTDATA5_SC0DIR_
93 TS0OUTDATA4_SC0DETECT 94
SC0notSETVPP
TS0OUTDATA6_SC0CMDVCC_ TS0OUTDATA7_SC0RESET_
95 96
ASC0CTS_SC0notSETVCC ASC0RTS
TS0OUTDATA0_SC1POWER_ TS0OUTDATA1_SC1RESET_
97 98
TV0DENC_ASC1CTS VSYNC_ASC1RTS
TS0OUTDATA3_SC1DATAINOUT_
99 TS0OUTDATA2_SC1CLK_HSYNC 100
PIXCLK
101 NANDSCN2 102 NANDSCN3
96/160 8149405
C.2.9 Transport stream connectors CN24/CN25

Two 20-pin connectors provides transport stream data output.
CN24 is the debug transport stream, CN25 is control and data and is shared with the NIM
transport stream.
Figure 71. Transport stream data connector
19 1
20 2
Table 61. Transport stream data connector pin allocation

1 SDA 2 SCL
3 notRST 4 NC
5 DATA0 6 DATA1
7 DATA2 8 DATA3
9 DATA4 10 NC
11 DATA5 12 DATA6
13 DATA7 14 NC
15 TSERROR 16 TSCLK
17 TSVALID 18 NC
19 TSPACKETCLK 20 AS1
8149405 97/160
C.2.10 NIM connector CN26

One 84-pin connector. The connector is made up from two separate female connectors:
● a SAMTEC 28-pin
● a SAMTEC 54-pin
The two connectors are arranged, and the pins are numbered, as shown in Figure 72.
Pins 15 and 57 are not available.
Figure 72. NIM connector
15
42 16 14 1
84 58 56 43
57
Table 62. NIM connector pin allocation

1 LNBRF 43 Key1
2 GNDA1 44 VCORESEL_COM
5 LNBSUPPLY5V 47 RESERVED1
6 GNDA4 48 RESERVED2
7 GNDA5 49 SRX
8 GNDA6 50 DRX
9 VCC3V3A 51 ITX
10 GNDA7 52 QTX
11 GNDA8 53 ETX
12 VCORE_A1 54 VCORE_A2
13 ANALOG5V 55 CTX
14 VTUNE32V 56 OOB_RESERVED
15 Key3 57 Key4
16 DISEQCRX 58 RESERVED3
17 ADDRESS0 59 ADDRESS1
18 DISEQCTX 60 RESERVED4
19 OP1 61 RESERVED5
20 OP0 62 RESERVED6
98/160 8149405
Table 62. NIM connector pin allocation (continued)

21 OP2 63 RESERVED7
22 GNDD1 64 GNDD4
24 PACKETCLK 66 PACKETCLK_2
25 BYTECLKVALID 67 BYTECLKVALID_2
26 BYTECLK 68 BYTECLK_2
27 ERROR 69 ERROR_2
28 GNDD2 70 GNDD5
30 DATA7 72 DATA7_2
31 DATA6 73 DATA6_2
32 DATA5 74 DATA5_2
33 DATA4 75 DATA4_2
34 DATA3 76 DATA3_2
35 DATA2 77 DATA2_2
36 DATA1 78 DATA1_2
37 DATA0 79 DATA0_2
38 GNDD3 80 GNDD6
39 VCC3V3D 81 RESERVED8
40 SCL 82 SCL_2
41 SDA 83 SDA_2
42 notRESET 84 Key2
8149405 99/160
C.2.11 ATX power connector CN27

A standard ATX power supply is used to provide different voltage levels to the board. This
board-mounted Molex connector is a 20-pin mini-fit jr type.
Figure 73. ATX power connector
1 10
11 20
Table 63. ATX power connector pin allocation

1 +3V3_A 11 +3V3_C
2 +3V3_B 12 -12V
3 GND_A 13 GND_D
4 +5V_A 14 notPS_ON
5 GND_B 15 GND_E
6 +5V_B 16 GND_F
7 GND_C 17 GND_G
8 PW_OK 18 -5V
9 +5VSB 19 +5V_C
10 +12V 20 +5V_D
100/160 8149405
C.2.12 Smartcard header data connectors CN28/CN29

Two 8-pin vertical post PTH header connectors provide smartcard data.
Figure 74. Smartcard header data connector
8 1
Table 64. Smartcard header data connector pin allocation

Pin Description(1) Pin Description
1 SCnDATAOUT 5 SCnRESET
2 SCnDATAIN 6 SCnCMDVCC
3 SCnEXTCLK 7 SCnVPP
4 SCnCLK 8 SCnDETECT
1. Where n=0 for CN29 and n=1 for CN28.
C.2.13 Smartcard sockets CN30

Two 10-pin smartcard sockets. Dual smartcard connector, friction contacts, through hole,
normally closed detection switch.
Figure 75. Smartcard socket
1 4
11 14 9 10
Indicates pins 11-20
of bottom smartcard
19 20 (smartcard 1)
15 18
5 8
Top smartcard viewed from above PCB
Table 65. Smartcard socket pin allocation

1 GNDC 11 GNDC
2 SC0VPP 12 SC1VPP
3 IO 13 IO
4 AUX2 14 AUX2
5 VCC 15 VCC
6 RST 16 RST
8149405 101/160
Table 65. Smartcard socket pin allocation (continued)

7 CLK 17 CLK
8 AUX1 18 AUX1
9 GNDC 19 GNDC
10 PRES/notPRES 20 PRES/notPRES
C.2.14 ATAPI connector CN31

A 2 x 20-way, 40-pin connector provides ATAPI data.
Figure 76. ATAPI connector
39 1
40 2
Table 66. ATAPI connector pin allocation

1 notRESET 2 GND
3 DD7 4 DD8
5 DD6 6 DD9
7 DD5 8 DD10
9 DD4 10 DD11
11 DD3 12 DD12
13 DD2 14 DD13
15 DD1 16 DD14
17 DD0 18 DD15
19 GND 20 Reserved
21 DMARQ 22
23 notDIOW 24 GND
25 notDIOR 26
27 IORDY 28 SPSYNC_CSEL
29 notDMACK 30 GND
31 INTRQ 32 notIOCS16
33 DA1 34 notPDIAG
35 DA0 36 DA2
102/160 8149405
Table 66. ATAPI connector pin allocation (continued)

37 notCS0 38 notCS1
39 notDASP 40 GND
C.2.15 STEM EMI CN32

A 140-pin surface mount board to board connector plug.
Figure 77. STEM EMI connector
140 71
70 1
Table 67. STEM EMI connector pin allocation

1 notBS 71 notFRAME
2 SDRAM_CLK 72 notCAS
3 SDRAM_CLKEN 73 notRESET
4 MEZZ_PRESENT0 74 MEZZ_PRESENT1
5 GND 75 GND
6 DACK2 76 DACK3
7 DACK0 77 DACK1
8 DRAK0 78 DRAK1
9 DREQ0 79 DREQ1
10 GND 80 GND
11 MEMWAIT 81 AUX_CLK
12 +3V3 (VCC) 82 +3V3 (VCC)
13 MEMGRANTED 83 MEMREQ
14 notINTR0 84 notINTR1
15 GND 85 GND
16 FLASH_CLK 86 FBAA
17 GND 87 GND
18 notWR 88 notOE
19 GND 89 GND
20 notCS0 90 notCS1
8149405 103/160

21 GND 91 GND
22 A25 92 A24
23 A23 93 A22
24 +3V3 (VCC) 94 +3V3 (VCC)
25 A21 95 A20
26 A19 96 A18
27 GND 97 GND
28 A17 98 A16
29 A15 99 A14
30 +3V3 (VCC) 100 +3V3 (VCC)
31 A13 101 A12
32 A11 102 A10
33 GND 103 GND
34 A9 104 A8
35 A7 105 A6
36 +3V3 (VCC) 106 +3V3 (VCC)
37 A5 107 A4
38 A3 108 A2
39 GND 109 GND
40 A1_notBE3 110 A0_notBE2
41 notBE1 111 notBE0
42 GND 112 GND
43 D31 (NC) 113 D30 (NC)
44 D29 (NC) 114 D28 (NC)
45 GND 115 +5V VCC
46 D27 (NC) 116 D26 (NC)
47 D25 (NC) 117 D24 (NC)
48 GND 118 GND
49 D23 (NC) 119 D22 (NC)
50 D21 (NC) 120 D20 (NC)
51 GND 121 +5V VCC
52 D19 (NC) 122 D18 (NC)
53 D17 (NC) 123 D16 (NC)
54 GND 124 GND
55 D15 125 D14
104/160 8149405

56 D13 126 D12

57 GND 127 +5V VCC
58 D11 128 D10
59 D9 129 D8
60 GND 130 GND
61 D7 131 D6
62 D5 132 D4
63 GND 133 +5V VCC
64 D3 134 D2
65 D1 135 D0
66 GND 136 GND
67 MPX_CLK 137 ALE_notRAS
68 GND 138 GND
69 139
+12 V (VCC) +12 V (VCC)
70 140
8149405 105/160
C.2.16 P6960 series high-density logic probe land pattern CN33/CN36

A 27-channel, Tektronix P6960 series high-density logic probe land pattern.
Figure 78. P6960 series logic probe land pattern

A27 A1
B27 B1
Table 68. P6960 series logic probe land pattern pin allocation
5 BUFF_DVBADDR10 5 notDVBCE
6 GND 6 notDVBIOOE
7 TP110 (CK1+) 7 GND
8 TP111 (CK1-) 8 BUFF_DVBADDR11
9 GND 9 notDVBIORD
11 BUFF_DVBADDR8 11 notDVBIOWR
14 notDVBINTR 14 notDVBIOWE
17 notDVBRESET 17 BUFF_DVBADDR6
19 notDVBWAIT 19 GND
20 BUFF_DVBADDR4 20 TP116 (CK2-)
21 GND 21 TP117 (CK2+)
23 notDVBREG 23 BUFF_DVBADDR2
106/160 8149405
Table 68. P6960 series logic probe land pattern pin allocation (continued)
C.2.17 DVB-CI connector CN34

A 68-pin DVB-CI connector. Single DVB-CI connector, supports type I, II cards. Single port,
right angle, top mount, through hole, 68-pin, with eject (right side).
Figure 79. DVB-CI connector
34 1
68 35
Table 69. DVB-CI connector pin allocation

1 NC 35 NC
2 DATA3 36 notCD1
7 notCE1 41 TS_OUT_DATA7
8 NC 42 notCE2
9 notOE 43 NC
10 A11 44 notIORD
11 A9 45 notIOWR
12 A8 46 TS_IN_STRT
15 notWE 49 TS_IN_DATA2
16 notIREQ 50 TS_IN_DATA3
17 VCC1 51 VCC0
18 VPP1 52 VPP0
19 TS_IN_VAL 53 TS_IN_DATA4
8149405 107/160
Table 69. DVB-CI connector pin allocation (continued)

20 TS_IN_CLK 54 TS_IN_DATA5
23 A6 57 TS_OUT_CLK
24 A5 58 CARD_RESET
25 A4 59 notWAIT
26 A3 60 NC
27 A2 61 notREG
28 A1 62 TS_OUT_VAL
29 A0 63 TS_IN_STRT
33 notIOIS16 67 notCD2
34 NC 68 NC
C.2.18 I2C blaster connector CN35

An 8-pin header provides I2C interfaces.
Figure 80. I2C blaster connector
4 1
8 5
Table 70. I2C connector pin allocation

1 Removed for polarization 5 USER2(1)

2 VCC 6 SCL
3 USER1(1) 7 USER3(1)
4 SDA 8 GND
1. Connected to NIM reset.
108/160 8149405
C.2.19 Ethernet MII data connector CN37

A 40-pin connector provides Ethernet data output.
Figure 81. Ethernet MII data connector
39 1
40 2
Table 71. Ethernet MII data connector pin allocation

1 GND 2 GND
3 4
+3V3 +5V
5 6
7 MII_COL 8 MII_CRS
17 GND 18 MII_TX_EN
19 MII_TXCLK 20 GND
21 MII_RXCLK 22 MII_RX_ER
23 MII_RX_DV 24 GND
33 GND 34 MII_MDC
37 notINT 38 RMII_MODE
39 GMII_MODE 40 GND
8149405 109/160
C.2.20 RJ45 Ethernet connector CN38

An RJ45 connector provides a 10/100 BaseT Ethernet physical layer (PHY) interface.
Figure 82. Ethernet connector
LED1 LED2
Table 72. Ethernet connector pin allocation

MDI_2CT MDI_3CT
1 7
+2V5_GMII +2V5_GMII
MDI_2- MDI_3+
2 8
MDIC_N MDID_P
MDI_2+ MDI_3-
3 9
MDIC_P MDID_N
MDI_1+ MDI_0-
4 10
MDIB_P MDIA_N
MDI_1- MDI_0+
5 11
MDIB_N MDIA_P
MDI_1CT MDI_0CT
6 12
+2V5_GMII +2V5_GMII
LED1 indicates Ethernet activity. LED2 indicates 100Base Tx Ethernet protocol.

LED output functions are user selectable. Up to two LED functions at one time. The LED
output functions are:
● activity
● full duplex
● 10BASE T or 100BASE TX Ethernet transmit protocol
● transmit, receive
110/160 8149405
STi5197-MBoard, STi5189/97-MB MB676 23 x 23 processor board jumpers, option resistors and
Appendix D MB676 23 x 23 processor board jumpers,

option resistors and switches
This appendix contains the following sections:

● Section D.1: Jumpers
● Section D.2: Option resistors on page 116
● Section D.3: Switches on page 117
D.1 Jumpers
The MB676 processor board includes the jumpers listed in Table 73. The default
configuration layout of the jumpers can be seen in Figure 83 on page 115.
Table 73. Jumper settings

Jumper Description Default
ATX power supply remote power on.

J1 On = ATX power supply (if connected) turned on Off
Off = ATX power off
J2 Ground test point. Do not fit
Reset out to MB762/MB829.
A On = enabled On
Off = isolated
B
C Reserved Do not fit
D
USB VBUS overcurrent detect to Int2 isolator.
E On = enabled Off
J3
Off = isolated
F Reserved Do not fit
Reset from MB762/MB829.
G On = enabled
Off = disabled
On
FMI Flash clock isolator.
H On = enabled
Off = isolated
+8V audio power supply isolator.
J4 On = enabled On
Off = isolated
8149405 111/160
MB676 23 x 23 processor board jumpers, option resistors and switches STi5197-MBoard,
Table 73. Jumper settings (continued)

A PIO4_5 SC1CMDVCC isolator.

B PIO4_5 DVODATA5 isolator.
C PIO4_2 SC1EXTCLK isolator.
D PIO4_2 DVODATA2 isolator. On = enabled
J5 On
E PIO3_7 DVOCLK isolator. Off = isolated
F PIO3_2 SSC1DATAINOUT isolator.

G PIO0_6 SC0VPP isolator.
H PIO0_5 SC0CMDVCC isolator.
A PIO0_2 SC0EXTCLK isolator.
B PIO0_0 SC0DATAOUT isolator.
C PIO1_3 ASC2RXD isolator.
D AUXCLKOUT isolator. On = enabled
J6 On
E PIO2_5 IRB_IN isolator. Off = isolated
F PIO2_5 ASC3_RTS isolator.

G PIO2_2 ASC3_CTS isolator.
H PIO2_2 PCMSCLKOUT isolator.
A PIO0_3 SC0CLK isolator.
B PIO0_1 SC0DATAIN isolator.
C PIO1_2 ASC2TXD isolator.
D PIO1_5 ASC2CTS isolator. On = enabled
J7 On
E PIO1_5 CLK27 isolator. Off = isolated
F PIO2_1 ASC3_RXD isolator.

G PIO2_1 PCMLRCLKOUT isolator.
H PIO2_1 BILED2 isolator.
A PIO4_6 DVODATA6 isolator.
B PIO4_6 SC1VPP isolator.
C PIO4_3 SC1CLK isolator.
J8 On
E PIO4_0 SC1DATAOUT isolator. Off = isolated
F PIO4_0 DVODATA0 isolator.

G PIO3_4 INTUP1 isolator.
H PIO3_4 HSYNC isolator.
112/160 8149405

A PIO0_4 SC0RESET isolator.

B PIO0_7 SC0DETECT isolator.
C PIO1_1 FDMAREQ1 isolator.
D PIO1_4 ASC2RTS isolator. On = enabled
J9 On
E PIO2_0 PCMDATAOUT isolator. Off = isolated
F PIO2_0 ASC3_TXD isolator.

G PIO2_0 BILED1 isolator.
H PIO1_0 FDMAREQ0 isolator.
A PIO4_7 SC1DETECT isolator.
B PIO4_7 DVODATA7 isolator.
C PIO4_4 SC1RESET isolator.
J10 On
E PIO4_1 SC1DATAIN isolator. Off = isolated
F PIO4_1 DVODATA1 isolator.

G PIO3_3 SSC1CLK isolator.
H PIO3_3 VSYNCEN isolator.
1V supply.
J11 1-2 = variable by R4 2-3
2-3 = fixed
Main clock source.
J12 1-2 = on-board crystal 1-2
2-3 = other source selected by J24
J13 Isolator for analog 1V0 power to front end tuner. On
J14 Isolator for analog 2V5 power to front end tuner. On
A PIO2_6 PCMDATAIN isolator. On
B QAM_POW_IN to PIO2_7 isolator Off
C PIO2_7 PCMLRCLKIN isolator.
On = enabled
D PIO2_7 IRB_OUT isolator.
Off = isolated
E PIO2_7 FPRESET isolator. On
J15
F PIO3_0 INTUP0 isolator.
G PIO3_0 VSYNC isolator.
Interrupt 0 loopback.
H On = loopback for standalone use Off
Off = MB762/MB829 connected
8149405 113/160

PIO3_6 MB762/MB829 Front Panel LED

A
isolator.
B PIO3_6 DVBCI_BUSGNT isolator.
C PIO2_4 PCMSCLKIN isolator.
D PIO3_1 INTUP2 isolator. On = enabled
J16 On
Off = isolated
E PIO1_6 I2C bus SCL isolator.
F PIO1_6 SSC0_SCLKINOUT isolator.
G PIO1_7 I2C bus SDA isolator.
H PIO1_7 SSC0_MTSR_DINOUT isolator.
USB3317 +1V8 source select.
J17 1-2 = voltage regulator 1-2
2-3 = low cost diode option
USB3317 reset.
A 1-2 = device disabled (held in reset) 2-3
2-3 = normal operation
J18
USB3317 clock source select.
B 4-5 = AuxClock 5-6
5-6 = on-board crystal oscillator
PROCSPIDATAOUT isolator.
J19 On = enabled On
Off = isolated
PROCSPIDATAIN isolator.
J20 On = enabled On
Off = isolated
PROCSPICLK ISOLATOR.
J21 On = enabled On
Off = isolated
Serial Flash device select.
J22 1-2 = on-board Atmel AT45 1-2
2-3 = MB762/MB829 serial Flash
TMU clock.
J23 1-2 = pull down Do not fit
2-3 = pull up
Alternate clock source.
J24 1-2 = external clock from CN14 1-2
2-3 = FE_CLKOUT
1.0V source.
J25 2-3 = from on-chip regulator 1-2
1-2 = from board regulator
J26 Ground test point Do not fit
114/160 8149405

A PIO3_2 DVBCI_CD1 isolator.

B PIO3_5 DVBCI_BUSREQ isolator.
On = enabled
C PIO3_5 HSYNCEN isolator.
Off = isolated
D PIO2_3 PCMMCLK isolator.
J27 On
E PIO3_3 DVBCI_RESET isolator.
F NANDCSn1 isolator.
G NANDRBn1 isolator.
H NANDRBn3 isolator.
Figure 83. Default configurations of the jumpers
1-2 2-3
Not fitted Do not fit Fitted 1 2 3 1 2 3
A 1-2, 2-3
B 4-5, 5-6 Not fitted
A B 1 2 3
1 4
2 5
3 6
Jumper can be fitted to pin 1, 2 or 3

(whichever is most convenient)
8149405 115/160
D.2 Option resistors

The MB676 processor board includes the resistors listed in Table 74. The default
configuration layout of the resistors can be seen in Figure 84.
Table 74. Option resistor settings

Resistor Description Default
I2C PIO expander address A2 select.

R3 1-2 = pull up
2-3 = pull down
R6 1-2 = pull up
2-3 = pull down
I2C PIO expander address A0 select. 1-2
R10 1-2 = pull up
2-3 = pull down
USB TMT connector resert sense
R27 1-2 = inverted
2-3 = non-inverted
R77 FMI mode select: FMI boot bank size 1. Must be high.
SYS_CLOCKOSC load capacitor pull up/down select.
R109 1-2 = +2V5_ANA 2-3
2-3 = Ground
DCT70700 Tuner CAS.
R169 1-2 = +5V_ANA_CAB
2-3 = GND
HDMI HSYNC select.
R171 1-2 = use embedded 1-2
2-3 = use SoC HSYNC
HDMI VSYNC select.
R173 1-2 = use embedded
2-3 = use SoC VSYNC
LNBH23 I2C address select pin.
R190 1-2 = high 2-3
2-3 = low
HDMI SII9024 I2C address select.
R209 1-2 = pull high 1-2
2-3 = pull low
116/160 8149405
Figure 84. Default configurations of the resistors
1-2 2-3
D.3 Switches
The MB676 processor board has a number of switches that control many aspects of the
board operation. Information on the switches is given in Table 75. A quad switch is shown in
Figure 85.
Table 75. Option switch settings

Switch Description Default
Board master reset push button

SW1 - Resets all devices on MB676 and MB762/MB829, N/A
sends reset to the SoC.
FMIADDR[20]. NAND Flash address type.
1 0(On) = Long addressing On (0)
1(Off) = Short addressing
2 FMIADDR[22:21]. Boot mode.
00(On,On) = Parallel NOR, 01(ON,OFF)=NAND,
SW2 On (0)
3 10(Off,On) = Serial
11(Off,Off) = Reserved
FMIADDR[23]. Reset period.
4 0(On) = 200 ms stretch Off (1)
1(Off) = Normal
FMIADDR[1]. Boot bank size.
1 0(On) = 16-bit On (0)
1(Off) = 8-bit
FMIADDR[3]. NAND Flash offset remap.
2 0(On) = Reserved
1(Off) = Remap
SW3 Off (1)
FMIADDR[18]. Serial Flash type.
3 0(On) = Older Atmel devices
1(Off) = All other devices
FMIADDR[19]. NAND Flash page type.
4 0(On) = Small On (0)
1(Off) = Large
8149405 117/160
Figure 85. Configuration switch options
Note: In Figure 85, switches 1 and 2 are OFF and switches 3 and 4 are ON.
118/160 8149405
Appendix E MB704 15 x 15 processor board jumpers,


● Section E.1: Jumpers
● Section E.2: Option resistors on page 123
● Section E.3: Switches on page 124
E.1 Jumpers
The MB704 processor board includes the jumpers listed in Table 76. The default
configuration layout of the jumpers can be seen in Figure 86 on page 122.

1V supply
J1 1-2 = variable by R4 2-3
2-3 = fixed
Reset to MB762/MB829
A On = enabled
Off = disabled
B DVBCI_BUSGNT / PIO3_6 isolator
C PCM_SCLKIN / PIO2_4 isolator
D INTUP2 / PIO3_1 isolator
J2 SSC0_SCLK for MB704 / PIO1_6 On
E
isolator
On = enabled
SSC0_SCLK for MB762/MB829 / Off = isolated
F
PIO1_6 isolator
SSC0_DINOUT for MB704 / PIO1_7
G
isolator
SSC0_DINOUT for MB762/MB829 /
H
PIO1_7 isolator
A SC1 detect / PIO4_7 isolator
B DVO_DATA7 / PIO4_7 isolator
C SC1_CMDVCC / PIO4_5 isolator
D PIO4_5 isolator On = enabled
J4 On
E SC1_CLK / PIO4_3 isolator Off = isolated
F DVO_DATA3 / PIO4_3 isolator

G SC1_DATAIN / PIO4_1 isolator
H DVO_DATA1 / PIO4_1 isolator
8149405 119/160

A DVO_DATA6 / PIO4_6 isolator

B SC1_VPP / PIO4_6 isolator
C SC1_RESET / PIO4_4 isolator
D DVO_DATA4 / PIO4_4 isolator On = enabled
J5 On
E SC1_EXTCLK / PIO4_2 isolator Off = isolated
F DVO_DATA2 / PIO4_2 isolator

G SC1_DATAOUT / PIO4_0 isolator
H DVO_DATA0 / PIO4_0 isolator
A PCM_MCLK / PIO2_3 isolator
B MB762/MB829 reset out
On = enabled
J6 F DVBCI_CD1 / PIO3_2 isolator On
Off = isolated
G SSC1_DATAINOUT / PIO3_2 isolator
H VSYNC_EN / PIO3_2 isolator
A DVBCI_RESET / PIO3_3 isolator
B SSC1_CLK / PIO3_3 isolator
C VSYNC / PIO3_0 isolator
D SC0_RESET / PIO0_4 isolator On = enabled
J7 On
E SC0_DETECT / PIO0_7 isolator Off = isolated
F SC0_EXTCLK / PIO0_2 isolator

G ASC2_RXD / PIO1_3 isolator
H FDMA_REQ1 / PIO1_1 isolator
A DVO_CLK / PIO3_7 isolator
B SC0_VPP / PIO0_6 isolator
C SC0_CMDVCC / PIO0_5 isolator
D SC0_CLK / PIO0_3 isolator On = enabled
J8 On
E ASC2_TXD / PIO1_2 isolator Off = isolated
F SC0_DATAIN / PIO0_1 isolator

G ASC2_CTS / PIO1_5 isolator
H CLK27 / PIO1_5 isolator
120/160 8149405

A INTUP1 / PIO3_4 isolator

B HSYNC / PIO3_6 isolator
FMI_FLASHCLK / FMI Flash clock
C
isolator
D HSYNC_EN / PIO3_5 isolator On = enabled
J9 On
GPIO_DVBCI_BUSREQ / PIO3_5 Off = isolated
E
isolator
F SC0_DATAOUT / PIO0_0 isolator
G ASC2_RTS / PIO1_4 isolator
H AUX_CLKOUT isolator
Serial Flash device select
J10 1-2 = on-board ATMEL 2-3
2-3 = MB762/MB829 serial Flash
J11 8 Volt audio power supply isolator On
1V source
J12 1-2 = from board regulator 1-2
2-3 = from on-chip regulator
Main clock source
J13 1-2 = on board crystal 1-2
2-3 = external clock through CN12
A ASC3_TXD / PIO2_0
B PCM_DATAOUT / PIO2_0
C IRB_IN / PIO2_5 isolator
D ASC3_RTS / PIO2_5 isolator On = enabled
J14 On
E PCM_DATAIN / PIO2_6 isolator Off = isolated
F PCM_LRCLKIN / PIO2_7 isolator

G IRB_OUT / PIO2_7 isolator
H FP_RESET / PIO2_7 isolator
8149405 121/160

A ASC3_RXD / PIO2_1
B PCM_LRCLKOUT / PIO2_1
C FDMA_REQ0 / PIO1_0 On = enabled
On
D ASC3_CTS / PIO2_2 Off = isolated
E PCM_LRCLKOUT / PIO2_2
J15 F INTUP0 / PIO3_0
Interrupt 0 loopback (HDMI)
G On = loopback for standalone use Do not fit
Off = through MB762/MB829 EPLD
QAM POWER_IN
H On = connect to PIO3_0 Off
Off = disabled
USB3317 1V8 source select
J17 1-2 = voltage regulator 1-2
2-3 = low cost diode option
TMU clock
J18 1-2 = pull up Do not fit
2-3 = pull down
J19 PROC_SPI_DATAIN isolator
On = enabled
J20 PROC_SPI_DATAOUT isolator On
Off = isolated
J21 PROC_SPI_CLK isolator
USB3317 clock source select
J22 1-2 = auxillary clock 2-3
2-3 = on-board crystal oscillator

1-2 2-3
Not fitted
1 2 3
Jumper can be fitted to pin 1, 2 or 3

(whichever is most convenient)
122/160 8149405
E.2 Option resistors

The MB704 processor board includes the resistors listed in Table 77. The default
configuration layout of the resistors can be seen in Figure 87.


R20 1-2 = pull up
2-3 = pull down
R21 1-2 = pull up 1-2
2-3 = pull down
R22 1-2 = pull up
2-3 = pull down
SYS_CLOCKOSC load capacitor pull up/down select.
R144 1-2 = +2V5_ANA
2-3 = Ground
2-3
DCT70701 tuner CAS.
R194 1-2 = +5V_ANA
2-3 = Ground
HDMI HSYNC select.
R202 1-2 = use embedded
2-3 = use SoC HSYNC
HDMI VSYNC select.
R204 1-2 = use embedded 1-2
2-3 = use SoC VSYNC
HDMI SII9024 I2C address select.
R209 1-2 = pull high
2-3 = pull low
1-2 2-3
8149405 123/160
E.3 Switches
The MB704 processor board has only one option switch setting which is shown in Table 78.
There is no default configuration.

Board master reset button, resets all devices on MB704

SW1 N/A
and MB762/MB829, sends reset to SoC.
124/160 8149405
STi5197-MBoard, STi5189/97-MB MB762 SD generic peripheral board jumpers, option resistors
Appendix F MB762 SD generic peripheral board jumpers,


● Section F.1: Jumpers
● Section F.2: Option resistors on page 127
● Section F.3: Switches on page 128
F.1 Jumpers
The MB762 SD generic peripheral board includes the jumpers listed in Table 79. The default
configuration layouts of the jumpers are shown in Figure 88.

J1 12V power
Do not fit
J2 External connection to drive power on/off
Include processor module in EPLD JTAG chain
J3 On = bypass module On
Off = include module EPLDs in JTAG chain
J4 5V power Do not fit
NIM VCORE remote/local sense select
J5 On = sense controlled by MB762 On
Off = sense controlled by NIM
J6 Ground Do not fit
CVBS routing
J7 1-2 = through SCART switch to SCART 1-2
2-3 = through buffer to phono
SPI EEPROM CS source select
A 1-2 = EPLD_notSPICS 2-3
2-3 = PIO_SPICS
J9
SPI EEPROM select
B 4-5 = M25P80 4-5
5-6 = M25P32
NAND Flash write protect
J10 On (0) = protected Off
Off (1) = unprotected
J11 3V power
J12 Do not fit
Ground
J13
8149405 125/160
MB762 SD generic peripheral board jumpers, option resistors and switches STi5197-MBoard,

J14 ATAPI not DASP isolation jumper On

J15 12V power
J17 5V power
Ethernet PHY clock select
J18 1-2 = crystal 2-3
2-3 = MII PHY clock
Enable RS232 port 0
J20 On = enabled
Off = disabled
On
Enable RS232 port 1
J21 On = enabled
Off = disabled
IR input enable
J22 On = disabled Off
Off = enabled
1-2 2-3
A 1-2, 2-3
B 4-5, 5-6
A B
1 4
2 5
3 6
126/160 8149405
F.2 Option resistors

The MB762 SD generic peripheral board includes the resistors listed in Table 80. The
default configuration layouts of the resistors are shown in Figure 89.

SMUTE pull up/down select

R82 1-2 = pull up
2-3 = pull down
1-2
NIM I2C address 1 select
R86 1-2 = high
2-3 = low
R90 1-2 = high
2-3 = low
I2C EEPROM address E1 select
R108 1-2 = pull up
2-3 = pull down
R109 1-2 = pull up 2-3
2-3 = pull down
R110 1-2 = pull up
2-3 = pull down
Transport stream I2C address select
R135 1-2 = high
2-3 = low
CVBS buffer/direct select
R142 1-2 = unbuffered
2-3 = buffered
NANDWAIT1 pull up/down select
R176 1-2 = pull up
2-3 = pull down
R178 1-2 = pull up 1-2
2-3 = pull down
R179 1-2 = pull up
2-3 = pull down
R180 1-2 = pull up
2-3 = pull down
8149405 127/160
MB762 SD generic peripheral board jumpers, option resistors and switches STi5197-MBoard,
Table 80. Option resistor settings (continued)

I2
LNBH23 C address select
R213 1-2 = high 1-2
2-3 = low
Smartcard 0 presence detect active state select
R258 1-2 = notPRES
2-3 = PRES
2-3
R269 1-2 = notPRES
2-3 = PRES
ATAPI interrupt active high or low pull up/down select
R286 1-2 = pull down 1-2
2-3 = pull up
1-2 2-3
F.3 Switches
The MB762 SD generic peripheral board has a number of switches that control many
aspects of the board operation. Information on the switches is given in Table 81. A quad
switch is shown in Figure 90.

1
2
SW1 FMI EPLD config (7:4) switch On
3
4
1
2
3
4
128/160 8149405
Table 81. Option switch settings (continued)

1
2
3
4
1
2
SW4 Transport stream EPLD config (3:0) switch On
3
4
1
2
SW5 Transport stream EPLD config (7:4) switch On
3
4
SW6 Front panel reset push button
SW7
SW8 N/A
Front panel user push button
SW9
SW10
8149405 129/160
MB829 SD modular validation peripheral board jumpers, option resistors and switches STi5197-
Appendix G MB829 SD modular validation peripheral

board jumpers, option resistors and switches

● Section G.1: Jumpers
● Section G.2: Option resistors on page 132
● Section G.3: Switches on page 133
G.1 Jumpers
The MB829 SD modular validation peripheral board includes the jumpers listed in Table 82.
The default configuration layouts of the jumpers are shown in Figure 91.


Include processor module in EPLD JTAG chain
J2 1-2 = Include module EPLDs in JTAG chain 2-3
2-3 = Bypass module
Enable RS232 port 0
J3 On = enabled
Off = disabled
Enable RS232 port 1
J4 On = enabled On
Off = disabled
NIM VCORE remote/local sense select
J5 On = sense controlled by MB829
Off = sense controlled by NIM
J6 Ground
Do not fit
J7 Ground
SPI EEPROM CS source select
A 1-2 = EPLD_notSPICS 2A-3A
2-3 = PIO_SPICS
J8
SPI EEPROM select
B 1-2 = M25P80 2B-3B
2-3 = M25P32
NAND Flash write protect.
J9 On (0) = protected Off
Off (1) = unprotected
Enable/disable remote power On/Off
J10 On = enabled On
Off = disabled, uses SW6 only
130/160 8149405
STi5197-MBoard, STi5189/97-MB MB829 SD modular validation peripheral board jumpers, option

J11 ATAPI notDASP isolation jumper On

J12 Ground
J13 +12V power
J14 Ground
J15 Ground
Do not fit
J16 5V power
J17 12V power
J18 3V power
J19 3V power
IR input enable
J20 On = disabled Off
Off = enabled
1-2 2-3
A 1-2, 2-3
B 4-5, 5-6
A B
1 4
2 5
3 6
8149405 131/160
G.2 Option resistors

The MB829 SD modular validation peripheral board includes the resistors listed in Table 83.
The default configuration layouts of the resistors are shown in Figure 92.

SMUTE pull up/down select

R6 1-2 = pull up 1-2
2-3 = pull down
Transport stream header (CN24) I2C address select
R69 1-2 = high
2-3 = low
2-3
Transport stream header (CN25) I2C address select
R71 1-2 = high
2-3 = low
R75 1-2 = high 1-2
2-3 = low
R79 1-2 = high
2-3 = low
R82 1-2 = pull up
2-3 = pull down
2-3
R83 1-2 = pull up
2-3 = pull down
R84 1-2 = pull up
2-3 = pull down
NandWait1 pull up/down select
R137 1-2 = pull up
2-3 = pull down
R138 1-2 = pull up
2-3 = pull down
1-2
R139 1-2 = pull up
2-3 = pull down
R140 1-2 = pull up
2-3 = pull down
132/160 8149405
Table 83. Option resistor settings (continued)

I2
LNBH23 C address select
R169 1-2 = high 1-2
2-3 = low
R208 1-2 = notPRES
2-3 = PRES
2-3
R222 1-2 = notPRES
2-3 = PRES
ATAPI interrupt active high or low pull up/down
R240 1-2 = pull down 1-2
2-3 = pull up
1-2 2-3
G.3 Switches
The MB829 SD modular validation peripheral board has a number of switches that control
many aspects of the board operation. Information on the switches is given in Table 84. A
quad switch is shown in Figure 93.

FMI EPLD config (7:4) switch

Config4 - SPI_notHOLD.
1
On = Active, Off = Inactive
Config5 - SPI_notPROT.
2
SW1 On = Active, Off = Inactive
On
Config6 - Smartcard 0 reset invert.
3
Off = Invert, On = No invert
Config7 - Smartcard 0 data link.
4
Off=data in + out linked.
8149405 133/160
Table 84. Option switch settings (continued)


Config8 - Smartcard 0 voltage.
1
On = 3V, Off = 5V
Config9 - Smartcard 1 reset invert.
2
SW2 Off = Invert, On = No invert
On
Config10 - Smartcard 1 data link.
3
Off = data in + out linked.
Config11 - Smartcard 1 voltage.
4
On = 3V, Off = 5V
Config0 - NOR/NAND boot select.
1
On = NOR, Off = NAND
SW3
2 Config1 - DACmode(0) On
3 Config2 - DACmode(1)
4 Config3 - Unused
Transport stream EPLD config (3:0) switch
TS mode software/switch controlled.
1 Off
On = software, Off = Switch
SW4 2 Unused.
3 Unused.
On
Serial data input swap.
4
On = D0/D7 swapped, Off = No swap
Transport stream EPLD config (7:4) switch
1 TS Mode(0) On
SW5 2 TS Mode(1)
Off
3 TS Mode(2)
4 TS Mode(3) On
SW6 Front panel power On/Off push button
N/A
SW7 Front panel reset push button
134/160 8149405
8149405 135/160
PIO alternate functions STi5197-MBoard, STi5189/97-MB
Appendix H PIO alternate functions
The following tables show the PIO alternate functions used by the board for PIO0 to PIO4.
A complete list of PIO assignments is in the STi5197 datasheet (ADCS 8148435).
Table 85. PIO functions for PIO0

Bit Function Alternate function 1 Alternate function 2 Alternate function 3
SC0_DATAOUT/
0 ICAM_SC0_C4_DINOUT
ASC0_TXD
SC0_DATAIN/
1 ICAM_SC0_C7_DINOUT
ASC0_RXD
2 SC0_CG_EXTCLK ICAM_SC0_C8_DINOUT
3 SC0_CG_CLK ICAM_SC0_CG_CLK
4 SC0_RESET ICAM_SC0_RESET
5 SC0_COMD_VCC ICAM_SC0_notSETVCC
6 SC0_DIR/ASC0_notOE ICAM_SC0_notSETVPP
7 SC0_DETECT ICAM_SC0_DETECT

0 QPSK_I2C_CLOCK_IN
QPSK_I2C_DATA_
1
INPUT
2 ASC2_TXD
3 ASC2_RXD
4 ASC2_RTS
5 ASC2_CTS
6 SSC0_SCLKINOUT
7 SSC0_MTSR_DINOUT
136/160 8149405
STi5197-MBoard, STi5189/97-MB PIO alternate functions

0 ASC3_TXD PCM_DATAOUT
1 ASC3_RXD PCM_LRCLKOUT
2 ASC3_CTS PCM_SCLKOUT
3 GPIO/DVBCI_RESET PCM_MCLK
4 GPIO/DVBCI_CD1 PCM_SCLKIN
5 ASC3_RTS IRB_PPM_IN
6 PCM_DATAIN
7 IRB_PPM_OUT PCM_LRCLKIN

0 EXTINT0(1) PAD_VSYNC
(2)
1 GPIO EXTINT2
2 SSC2_MTSR_DINOUT
3 SSC2_SCLKINOUT PAD_VSYNC_EN
4 EXTINT1 PAD_HSYNC
5 GPIO/DVBCI_BUS_REQ PAD_HSYNC_EN
6 GPIO/DVBCI_BUS_GNT
7 DVO output clock
1. EXTINT0 is used for HDMI interrupt.
2. GPIO is used for USB VBUS overcurrent detect. A wire modification may be required on some MB704 board variants if this
feature is required.

SC1_DATAINOUT/
0 DVO_DATA
ASC1_TXD
1 DVO_DATA ASC1_RXD
SC1_CG_EXTCLK/
2 DVO_DATA
ASC1_RTS
3 DVO_DATA SC1_CG_CLK
4 DVO_DATA SC1_RESET
5 DVO_DATA SC1_COMD_VCC
6 DVO_DATA SC1_DIR/ASC1_notOE
7 DVO_DATA SC1_DETECT
8149405 137/160
Hardware configuration guide STi5197-MBoard, STi5189/97-MB
Appendix I Hardware configuration guide
The MB829 and MB762 peripheral boards have two EPLD devices. These split the board
functions into two parts, FMI (see Section I.1) and transport stream (see Section I.2 on page
147).
For the FMI, an Altera EPM3256AQC208-7N EPLD device is used. This is IC23 on the
MB762, or IC18 on the MB829. This device controls:
● FMI memory devices: NAND, NOR and STEM
● audio modes (PCM DAC)
● DVBCI modes
● ATAPI
● peripheral device resets
● TS EPLD software modes
● configuration switch inputs
● smartcard
● SPI control
● interrupts
For the transport stream, an Altera EPM3256ATC144-10N EPLD device is used. This is
IC24 on the MB762, or IC19 on the MB829. This device controls the transport stream MUX
and Ethernet modes.
I.1 FMI EPLD

This section provides information on the FMI EPLD. It includes:
● Section I.1.1: FMI decoding
● Section I.1.2: FMI EPLD register map on page 139
● Section I.1.3: FMI EPLD register descriptions on page 140
I.1.1 FMI decoding

Table 90 details the FMI address decoding map for the FMI EPLD.
Note: There is no FMI present on the MB704.
Table 90. FMI address decoding for FMI EPLD

FMI bank Address Mapping
Bank 0 (FMI_CSA) 0xA0000000 - 0xA23FFFFF NOR/NAND Flash

0xA2400000 - 0xA24FFFFF FMI EPLD registers
Bank 1 (FMI_CSB) 0xA2500000 - 0xA27FFFFF ATAPI device
0xA2800000 - 0xA3FFFFFF Reserved
Bank 2 (FMI_CSC) 0xA4000000 - 0xA4FFFFFF DVBCI
138/160 8149405
STi5197-MBoard, STi5189/97-MB Hardware configuration guide
Table 90. FMI address decoding for FMI EPLD (continued)

FMI bank Address Mapping
0xA5000000 - 0xA5BFFFFF Reserved

0xA5C00000 - 0xA5DFFFFF STEM 0
Bank 3 (FMI_CSD)
0xA5E00000 - 0xA5FFFFFF STEM 1
0xA6000000 - 0xA7FFFFFF Reserved
I.1.2 FMI EPLD register map

In addition to basic control logic, the FMI EPLD has a set of registers mapped to a region of
FMI memory to allow software control of various functions. A summary of these registers is
given in Table 91 and more detail is provided in Section I.1.3 on page 140.
Note: These registers are only available on systems using an MB676 processor board.
Table 91. FMI EPLD registers

Register Description Address Reset RW
Ident Stores EPLD version number 0xA2400000 Ident RO

Test Test register 0xA2408000 0xC3 RW
Switch0 Status of external mode switches 0xA2410000 Ext(1) RO
Switch1 Status of external mode switches 0xA2418000 Ext(1) RO
Reset Individual reset of peripheral devices 0xA2420000 0x00 RW
(1)
Smartcard Controls smartcard hardware settings 0xA2428000 Ext RW
DVBCI control Controls DVBCI functions 0xA2448000 0x00 RW
TS EPLD Controls various functions in the Transport EPLD 0xA2438000 0x00 RW
Misc control Controls miscellaneous functions 0xA2440000 0x00 RW
SPI control Controls SPI functions 0xA2448000 0x00 RW
Audio control Controls audio functions 0xA2450000 Ext(1) RW
Allows FMI address bits 25:24 to be set. For use with NOR
Address control 0xA2458000 0x00 RW
Flash (bit 24 only) or STEM interface.
Interrupt status Shows status of incoming peripheral interrupts(2) 0xA2480000 Ext(1) RO
Interrupt mask Masks various interrupts 0xA2488000 0x00 RW
Sets interrupt priority (maps to 1 of 3 hardware interrupt
SCART interrupt 0xA2490000 0x00 RW
lines)(3)
DVBCI interrupt Sets interrupt priority (maps to 1 of 3 hardware interrupt lines) 0xA2498000 0x00 RW
ATAPI interrupt Sets interrupt priority (maps to 1 of 3 hardware interrupt lines) 0xA24A0000 0x00 RW
STEM0 interrupt Sets interrupt priority (maps to 1 of 3 hardware interrupt lines) 0xA24A8000 0x00 RW
STEM1 interrupt Sets interrupt priority (maps to 1 of 3 hardware interrupt lines) 0xA24B0000 0x00 RW
Down2 interrupt 0xA24B8000 0x00 RW
lines)(4)
8149405 139/160
Table 91. FMI EPLD registers (continued)

Register Description Address Reset RW

Down1 interrupt 0xA24C0000 0x00 RW
lines)(2)
Down0 interrupt 0xA24C8000 0x00 RW
lines). This is the HDMI interrupt from the processor module.
1. A reset value of “Ext” denotes a register whose initial value at reset depends on the logic status of device signals or
switch/jumper settings.
2. This register is not implemented on the MB762.
3. This register is not implemented on the MB829.
4. This register is not currently implemented on either the MB762 or MB829.
I.1.3 FMI EPLD register descriptions

Ident register
This read-only ident register contains both the board revision (3 bits) and EPLD revision
(5 bits).
Table 92. Ident register bits

Data bit Register description
D(7:5) Board revision: 000 = A, 001 = B, and so on.

D(4:0) EPLD revision: 00000 = 00, 00001 = 01, 00010 = 02, and so on.
Test register
This read/write register is used to test EMI accesses. It resets to 0x55. When written to, it
returns the inverse value of the write.
Table 93. Test register bits

Data bit Register description Value at reset
D(7:0) Reads inverse value of what is written 11000011 bin
Switch0 register
This read-only register gives the status of switches SW1 and SW3.
See Table 116: MB762/MB829 mode switches on page 153 for switch functions.
Table 94. Switch 0 register bits

D7 SW1-4 switch position. 0 = ON, 1 = OFF SW1-4

140/160 8149405
Table 94. Switch 0 register bits (continued)


Switch1 register
This read-only register gives the status of switch SW2.
See Table 116: MB762/MB829 mode switches on page 153 for switch functions.
Table 95. Switch 1 register bits

D[7:4] Reserved 0000 bin

Reset register
This read/write register allows individual peripheral devices to be reset.
The corresponding reset active low output to the device is the inverse of the register bit.
Writing a “1” to the corresponding bit holds the device in reset. Writing a “0” brings the
device out of reset. The default value is “0”, that is, all devices active.
All devices are held in reset during an EPLD reset or power on reset.
Table 96. Reset register bits

D7 MB762 reserved, MB829 TSEPLD_notRESET. 0

D6 PCMDAC_notRESET. Reset to AK43881 audio DAC. 0
D5 DVB_notRESET. 0
D4 NORFLASH_notRESET. 0
D3 STEM_notRESET. 0
D2 ATAPI_notRESET. 0
D1 TSCONN_notRESET. 0
D0 NIM_notRESET. 0
8149405 141/160
Smartcard register
This read/write register allows various different smartcard hardware configurations to be set
by software.
Table 97. Smartcard register bits

D7 Reserved 0
D6 Smartcard B 5Vnot3V. 1 = 5V, 0 = 3V. SW2-4
Smartcard B data link
D5 SW2-3
1=data in and data out bridged. 0= not bridged.
D4 Smartcard B reset invert. 1=inverted, 0=not inverted SW2-2
D3 Reserved 0
D2 Smartcard A 5Vnot3V. 1 = 5V, 0 = 3V. SW2-1
Smartcard A data link.
D1 SW1-4
1=data in and data out bridged. 0= not bridged.
D0 Smartcard A reset invert. 1=inverted, 0=not inverted SW1-3
DVBCI control register

This read/write register allows DVBCI control signals to be set up by software.
Table 98. DVBCI control bits


D4 DVBCI address and data buffer enable. 1= enabled, 0=disabled 0
D3 DVB_VCC3EN 0
D2 DVB_VCC5EN 0
D1 DVB_EN1 0
D0 DVB_EN0 0
TS EPLD register
This read/write register controls different modes for the transport EPLD.
See Section I.2: Transport stream EPLD on page 147 for definition of TSMode bits.
Table 99. TS EPLD register bits


D4 NOR or NAND Flash select: 0 = NOR Flash, 1 = NAND Flash SW3-1
D[3:0] TSMODE[3:0] 0000bin
142/160 8149405
Misc control register
Table 100. Misc control register bits


D4 BTSC modulator loop control (MB762 only). SW3-4
D3 LVDS spare 3 (MB762 only) 0
D2 LVDS spare 2 0
D1 LVDS spare 1 0
D0 NOR Flash VPEN signal. 1= enabled, 0= disabled 0
SPI control register

This read/write register allows SPI control signals to be set up by software.
Note: The board jumper settings may need to be changed to allow this register control of the serial
Flash devices.
Table 101. SPI control register bits


D2 SPI_notPROT SW1-2
D1 SPI_notHOLD SW1-1
D0 SPI_notEPLDCS 0
Audio control register

This read/write register allows various different audio configurations to be set up by
software.
The reset value is dependant on the settings of SW3-2 and SW3-3.
● When both switches are ON, the default value is 0x0B (00001011 bin).
● For any other combination of switch settings, the default value is 0x04 (00000100 bin).
Section I.6: Audio on page 155 provides more details.
Table 102. Audio control register bits


D4 Audio DAC DEM signal SW3-3, SW3-2
D3 Audio DAC ACKS signal SW3-3, SW3-2
D2 Audio DAC SMUTE signal SW3-3, SW3-2
D1 Audio DAC DIF1 signal SW3-3, SW3-2
D0 Audio DAC DIF0 signal SW3-3, SW3-2
8149405 143/160
Address control register

This read/write register allows FMI address bits [25:24] to be controlled by software.
Table 103. Address control register bits

D[7:2] Reserved 000000

D1 FMI address bit 25 0
D0 FMI address bit 24 0
Interrupt status register

This read-only register allows the status of the various peripheral interrupt inputs to the
EPLD to be read by software.
Note: The value in the register is the inverse of the actual incoming interrupt signal.
Table 104. Interrupt status register bits

D7 SCART interrupt 0
D6 DVBCI interrupt 0
D5 ATAPI interrupt 0
D4 STEM1 interrupt 0
D3 STEM0 interrupt 0
(1)
D2 INTDOWN2 0
D1 INTDOWN1(2) 0
D0 INTDOWN0 HDMI interrupt from processor module. 0
1. Not implemented.
2. Not available on the MB762.
Interrupt mask register

This read/write register allows individual interrupts to be enabled by software. Setting the
corresponding bit to “1” enables that interrupt. Setting the bit to “0” disables the interrupt. All
interrupts are disabled by default.
Table 105. Interrupt mask register bits

D7 SCART interrupt (active low) 0

D6 DVBCI interrupt (active low) 0
D5 ATAPI interrupt (active low) 0
D4 STEM1 interrupt (active low) 0
D3 STEM0 interrupt (active low) 0
144/160 8149405
Table 105. Interrupt mask register bits (continued)

(1)
D2 INTDOWN2 (active high) 0
D1 INTDOWN1 (active high)(2) 0
INTDOWN0 (active low). HDMI interrupt from processor
D0 0
module.
1. Not implemented.
2. Not available on the MB762.
SCART interrupt priority register

This read/write register sets which INTUP[n] maps to this interrupt.
Note: This is available on MB762 only.
Table 106. SCART interrupt priority register bits


00 = map to INTUP0
01 = map to INTUP1
D[1:0] 00 bin
10 = map to INTUP2
11= reserved (maps to nothing).
DVBCI interrupt priority register

Table 107. DVBCI interrupt priority register bits


00 = map to INTUP0
01 = map to INTUP1
D[1:0] 00 bin
10 = map to INTUP2
ATAPI interrupt priority register

Table 108. ATAPI interrupt priority register bits


00 = map to INTUP0
01 = map to INTUP1
D[1:0] 00 bin
10 = map to INTUP2
8149405 145/160
STEM0 interrupt priority register

Table 109. STEM0 interrupt priority register bits


00 = map to INTUP0
01 = map to INTUP1
D[1:0] 00 bin
10 = map to INTUP2
STEM1 interrupt priority register

Table 110. STEM1 interrupt priority register bits


00 = map to INTUP0
01 = map to INTUP1
D[1:0] 00 bin
10 = map to INTUP2
Up2 interrupt priority register

Table 111. Up2 Interrupt priority register bits


00 = map to INTUP0
01 = map to INTUP1
D[1:0] 00 bin
10 = map to INTUP2

Table 112. Up1 interrupt priority register bits


00 = map to INTUP0
01 = map to INTUP1
D[1:0] 00 bin
10 = map to INTUP2
146/160 8149405

Table 113. Up0 interrupt priority register bits


00 = map to INTUP0
01 = map to INTUP1
D[1:0] 00 bin
10 = map to INTUP2
I.2 Transport stream EPLD

Ethernet and transport stream are shared functions on the same pins. Figure 94 is a block
diagram of the transport stream and Ethernet subsystem.
Figure 94. Transport stream and Ethernet MUXing overview
Config switches
Peripheral
board Ethernet
(STi5197/89) LAN8700
Address S/W TS EPLD
FMI
Decode Config
TS Out NIM
TS In
DVBCI
CableCARD
Debug TS header
(MB829)
The different modes of operation are handled by the transport stream EPLD (TS EPLD) and
are selectable using switch SW5 or using software. Table 114 details the different mode bit
and switch settings.
To set the mode bits using switch SW5, SW4-1 should be set to the OFF position.
To set the mode bits using software, SW4-1 should be set to the ON position.
Setting the mode bits using software is only possible with an MB676 processor module, as
the MB704 module (STi5197 15x15) does not have FMI. The mode bits are set by a
software write through an FMI access to the TS EPLD register using the FMI EPLD.
The different modes are illustrated in Section I.2.1.
8149405 147/160
Table 114. TS mode/Ethernet selection

SW5-4 or SW5-3 or SW5-2 or SW5-1 or
Mode Description
bit3 bit2 bit1 bit0
0000 OFF (0) OFF (0) OFF (0) OFF (0) TSOUT to TSIN loopback
0001 OFF (0) OFF (0) OFF (0) ON (1) TSOUT to TSIN through DVBCI
0010 OFF (0) OFF (0) ON (1) OFF (0) NIM to TSIN
0011 OFF (0) OFF (0) ON (1) ON (1) NIM to TSIN through DVBCI
0100 OFF (0) ON (1) OFF (0) OFF (0) NIM to TSIN and TSOUT
1001 ON (1) OFF (0) OFF (0) ON (1) MII Ethernet mode and serial TSin
1010 ON (1) OFF (0) ON (1) OFF (0) RMII Ethernet mode and parallel TSin
I.2.1 TS mode descriptions

Mode 0000 - TSout to TSin loopback
TS mode register = 0x00, SW5 = OFF OFF OFF OFF.
Figure 95. TSout to TSin loopback
Debug TS header
(MB829)
TS EPLD
Peripheral board
(STi5197/89) Ethernet
LAN8700
TS Out
NIM
TS In
DVBCI
CableCARD
148/160 8149405
Mode 0001 - TSout to TSin through DVBCI

TS mode register = 0x01, SW5 = OFF OFF OFF ON.
Figure 96. TSout to TSin through DVBCI
Debug TS header
(MB829)
TS EPLD
Peripheral board
LAN8700
TS Out
NIM
TS In
DVBCI
CableCARD
Mode 0010 - NIM to TSin

TS mode register = 0x02, SW5 = OFF OFF ON OFF.
Figure 97. NIM to TSin
Debug TS header
(MB829)
TS EPLD
Peripheral board
LAN8700
TS Out
NIM
TS In
DVBCI
CableCARD
8149405 149/160
Mode 0011 - NIM to TSin through DVBCI

TS mode register = 0x03, SW5 = OFF OFF ON ON.
Figure 98. NIM to TSin through DVBCI
Debug TS header
(MB829)
TS EPLD
Peripheral board
LAN8700
TS Out
NIM
TS In
DVBCI
CableCARD
Mode 0100 - NIM to TSin and TSout

TS mode register = 0x04, SW5 = OFF ON OFF OFF.
Figure 99. NIM to TSin and TSout
Debug TS header
(MB829)
TS EPLD
Peripheral board
LAN8700
TS Out
NIM
TS In
DVBCI
CableCARD
150/160 8149405
Mode 1001 - MII Ethernet and serial TSin

TS mode register = 0x09, SW5 = ON OFF OFF ON.
Figure 100. MII Ethernet and serial TSin
Debug TS header
(MB829)
TS EPLD
Peripheral board
LAN8700
TS Out
NIM
TS In
DVBCI
CableCARD
Mode 1010 - RMII Ethernet and Parallel TSin

TS mode register = 0x0A, SW5 = ON OFF ON OFF.
Figure 101. RMI Ethernet and parallel TSin
Debug TS header
(MB829)
TS EPLD
Peripheral board
LAN8700
TS Out
NIM
TS In
DVBCI
CableCARD
8149405 151/160
I.3 EPLD programming instructions

The EPLDs can be programmed using two different methods:
● LVDS connector from the ST Micro Connect 2
This is the simplest, and more commonly used, method. The LVDS host interface
connection can be used to program the EPLD chain using an STMC2 and the
associated software. The connector is CN2 for the MB762, or CN10 for the MB829.
See Section I.3.1: Programming EPLDs using the LVDS connection.
● Altera ByteBlaster interface
An Altera ByteBlaster/ByteBlaster II cable is connected to the parallel port of the PC
and the JTAG chain connector on the board, CN16 on the MB762 or CN11 on the
MB829. The programming is done using the Quartus programmer tool installed on the
PC. See Section I.3.2: JTAG chain setup for use with ByteBlaster connector
CN16/CN11 for the programmer setup.
I.3.1 Programming EPLDs using the LVDS connection

The following are required to program EPLDs using the LVDS connection:
● ST Micro Connect 2 with LVDS to LVDS cable
● ST Micro Connection software R1.2.1 or higher
● JBC programming file (.jbc file)
To program the EPLDs, run the command:
epldprog --convertor STMC_Type_G <STMC2 name> <board>.jbc
I.3.2 JTAG chain setup for use with ByteBlaster connector CN16/CN11
To program the EPLDs using the Altera ByteBlaster interface, a ByteBlaster or ByteBlasterII
cable can be used.
In the Quartus programmer tool, DEVICE_1 and DEVICE_2 must be setup as follows:
DEVICE_1: EPLD device type (EPM3256AQ208)
(source_disk\source_dir\fmi_epld.pof)
DEVICE_2: EPLD device type (EPM3256ATC144)
(source_disk\source_dir\ts_epld.pof)
Note: When using the .jbc programming file, there is only a single file which holds the JTAG
chain sequence as well as the programming information for each of the three EPLDs.
152/160 8149405
I.4 General mode switch settings

Table 115 and Table 116 detail the board switch options.
Note: The MB704 does not have any option switches.
Table 115. MB676 mode switches

Switch Function On (0) Off (1)
SW2-1 NAND Flash address type. Long addressing Short addressing

SW2-2 SW2-2 On, SW2-3 On = NOR
Boot mode. Select processor boot SW2-2 On, SW2-3 Off = SPI
SW2-3 device. SW2-2 Off, SW2-3 On = NAND
SW2-2 Off, SW2-3 Off = MPX
SW2-4 Reset period. 200 ms stretch Normal
SW3-1 Boot device width. 16-bit 8-bit
SW3-2 NAND Flash offset remap. Reserved Remap
SW3-3 Serial Flash type. Older Atmel only ST + other Atmel
SW3-4 NAND Flash page size. Small Large
Table 116. MB762/MB829 mode switches

SW1-1 SPI_notHOLD Hold active/asserted Inactive/deasserted

SW1-2 SPI_notPROT Write protect Read/write allowed
SW1-3 Smartcard 0 reset invert No reset inversion Reset inverted
Data out linked to data
SW1-4 Smartcard 0 data link No data out/in link
in
SW2-1 Smartcard 0 voltage 3 volts 5 volts
SW2-2 Smartcard 1 reset invert No reset inversion Reset inverted
Data out linked to data
SW2-3 Smartcard 1 data link No data out/in link
in
SW2-4 Smartcard 1 voltage 3 volts 5 volts
SW3-1 Flash device select NOR NAND
SW3-2
Audio DAC mode. See Section I.6: Audio on page 155
SW3-3
RF modulator loop control (MB762
SW3-4 LoopCtrl = low LoopCtrl = high
only)
SW4-1 TSmode control TS EPLD register SW5
SW4-2 Unused
SW4-3 Unused
NIM D7 linked to
SW4-4 Serial data input swap NIM serial data from D0
STi5197 D0
8149405 153/160
Table 116. MB762/MB829 mode switches (continued)

SW5-1
SW5-2
TS Mode. See Section I.2.1: TS mode descriptions on page 148 for details.
SW5-3
SW5-4
I.5 Video
On the MB762, video out is available through:
● SCART as composite video or RGB
● a single phono connector (CN4) as composite video
The jumper J7 selects the routing of the composite out (CVBS) video signal.
Figure 102. MB762 video diagram

Processor
board
XOUT CVBS Filter CVBS

Jumper Phono
options
SCART Out
STV6417
UOUT Red / C SCART
switch
Green / Y SCART In
VOUT
WOUT Blue
RF modulator
(BTSC)
On the MB829, the SCART switch and BTSC modulator have been removed, see
Figure 103. CN5 has the CVBS output, and CN6, CN7 and CN8 are used for RGB or
component video out.
154/160 8149405
Figure 103. MB829 video diagram

Processor
board
XOUT CVBS Filter CVBS CVBS

options phono
Red / C Red/Cr
UOUT phono
Video
Green / Y buffer Green/Y
VOUT
phono
WOUT Blue Blue/Cb
phono
I.6 Audio
Two default audio mode settings can be set using a combination of SW3-2 and SW3-3.
When SW3-2 and SW3-3 are both ON:
● Audio register default value = 0x0B (00001011 bin)
● I2S mode, de-emphasis off, audio mode, mute disabled
● DEM = 0, ACKS = 1, SMUTE = 0, DIF1 = 1, DIF0 = 1
For any other combination of SW3-2 and SW3-3:
● Audio register default value = 0x04 (00000100 bin)
● DEM = 0, ACKS = 0, SMUTE = 1, DIF0 = 0, DIF0 = 0
Other settings can be achieved by writing a value directly to the Audio Control register
For a full description of the settings, see the STi5197 datasheet (ADCS 8148435) and
STi5197 programming manual (ADCS 8148435).
8149405 155/160
I.7 SPI devices

Three SPI serial Flash devices are available, one on the processor board and two on the
peripheral board. These are:
● Atmel AT45DB321 32-Mbit on the processor board
● ST M25P80 8-Mbit on the peripheral board
● ST M25P32 32-Mbit on the peripheral board
Figure 104 shows the routing of the SPI chip select through jumpers, to control which device
is active. Jumpers Ja, Jb and Jc are detailed in Table 117.
Figure 104. MB704/MB829 SPI Flash devices: chip select configuration
Processor board (MB704) Peripheral board
EPLD
STi5197 control M25P80
SPI_notCS
Ja
Jb Jc
AT45 M25P32
Table 117. SPI_notCS selection jumpers

Jumper Function Board reference Setting
Select AT45 device or peripheral 1-2 = AT45

Ja MB704 J10
board devices 2-3 = Peripheral board
1-2 = notCS from EPLD
Peripheral board SPI_notCS
Jb MB829 J8-A 2-3 = notCS from the
source select
processor board
Peripheral board serial device 1-2 = M25P80 device

Jc MB829 J8-B
select 2-3 = M25P32 device
156/160 8149405
I.8 I2C devices

The I2C connectivity for the boards is described in Section 5.6: Serial I2C buses on page 21.
Table 118 shows an example of the I2C bus devices and addresses for the MB704
processor with MB762 peripheral boards system.
Note: The SCART device is not present on the MB829.
Table 118. I2C bus devices and addresses

Default
Device Bus Possible addresses
address
PCF8575 PIO expander (MB704) SSC0 0x4E/4F 0x40 - 0x4F

0x76/0x77 0x76/77, 0x72/73
SII9024 HDMI encoder (MB704) SSC0 0xC4/0xC5 0xC4/C5, 0xC0/C1
0x7E/0x7F 0x7E/7F, 0x7A/7B
NIM socket (MB762) SSC0 Varies Device dependant
LNBH23 (MB762) SSC0 0x16/0x17 0x16/17, 0x14/15
See STi5197 datasheet
STi5197 internal QAM decoder (MB704) QAM 0x38/0x39
(ADCS 8148435)
DCT7070x QAM demodulator (MB704) QAM 0xC0/0xC1 0xC0/C1, OxC6/C7
I2C EEPROM SSC1 0xA0/0xA1 0xA0 - 0xAF
STV6417 SCART switch SSC1 0x96/0x97 0x96/0x97
8149405 157/160
Glossary STi5197-MBoard, STi5189/97-MB
Appendix J Glossary
ATAPI Advanced technology attachment packet interface

ATX Advanced technology extended (motherboard type)
BGA Ball grid array (type of integrated circuit)
BTSC Broadcast television systems comittee (multichannel television surround)
CVBS Composite video blanking synchronization
DAA Direct access arrangement
EMI External memory interface
EPLD Electrically programmable logic device
FPGA Field programmable gate array
HD High definition
HDMI High definition multimedia interface/high-density multichip interconnect
LMI Local memory interface
LVDS Low voltage differential signalling
MAFE Modem analog front end
Mbs Megabits per second
MCM Multi chip module
MII Media independent interface
NIM Network interface module
PCI Peripheral component interconnect
PCMCIA Peripheral component microchannel interconnect architecture
RMII Reduced media independent interface
SATA Serial advanced technology attachment (hard disk interface)
SD Standard definition
STEM Set top expansion module
TS Transport stream
UART Universal asynchronous receiver-transmitter
VHDCI Very high density cable interconnect
158/160 8149405
STi5197-MBoard, STi5189/97-MB Revision history
Revision history
Table 119. Document revision history

Date Revision Changes
Added information to Appendix I: Hardware configuration

16-Jun-2009 D
guide on page 138.
Updated throughout for Revision C and later boards. Added
details of the MB829 peripheral board.
Added:
– Chapter 6: MB829 SD modular validation peripheral
board on page 28
21-May-2009 C – Appendix C: MB829 SD modular validation peripheral
board connectors on page 85
– Appendix G: MB829 SD modular validation peripheral
board jumpers, option resistors and switches on
page 130
Updated Section 2.1: Equipment and software on page 10.
Corrected system requirements in Chapter 2: System
overview on page 9.
Replaced incorrect mention of DCU with JTAG in
Chapter 3, Figure 2 on page 11 and Chapter 5, Figure 4 on
page 19.
Added the warning to Chapter 4: MB676/MB704 processor
14-Jan-2009 B
board on page 13.
Updated Figure 5: I2C connectivity on page 22.
Updated smartcard descriptions in Section 5.7: Smartcard
slots on page 22.
Added Appendix I: Hardware configuration guide on
page 138 (information will be completed when available).
15-Dec-2008 A Initial release
8149405 159/160
STi5197-MBoard, STi5189/97-MB
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Evaluation boards for low-cost SD TV decoder

June 2009 8149405 Rev D 1/160

4 MB676/MB704 processor board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 MB762 SD generic peripheral board . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6 MB829 SD modular validation peripheral board . . . . . . . . . . . . . . . . . 28

Appendix A MB676/MB704 processor board connectors . . . . . . . . . . . . . . . . . . 38

Appendix B MB762 SD generic peripheral board connectors . . . . . . . . . . . . . . 56

B.3.8 Transport stream data connector CN14 . . . . . . . . . . . . . . . . . . . . . . . . . 66

Appendix C MB829 SD modular validation peripheral board connectors. . . . . 85

C.2.18 I2C blaster connector CN35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Appendix D MB676 23 x 23 processor board jumpers, option resistors and

Appendix E MB704 15 x 15 processor board jumpers, option resistors and

Appendix F MB762 SD generic peripheral board jumpers, option resistors and

Appendix G MB829 SD modular validation peripheral board jumpers, option

Appendix H PIO alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Appendix I Hardware configuration guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

I.3 EPLD programming instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Appendix J Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

The STi5197-MBoard and STi5189/97-MB are evaluation boards, which enable:

1.1 Target audience

Figure 1. STi5197-MBoard, STi5189/97-MB debug setup and interconnection block diagram

Windows/Linux PC LVDS Power

Supported configuration: Windows 2000/XP OS

2.1 Equipment and software

2.2 Electrostatic discharge (ESD) protection

3.1 System block diagram

On the processor board

Tuner front Transport stream, see

2 x RS232 ASC Audio block, see

3.2 Board assembly

3.3 Power supplies

a. An ATX power supply is not available on MB704 Revision A boards.

4 MB676/MB704 processor board

Warning: On the MB704, if the socket is overtightened when the

Figure 3. Block diagram of the processor board

4.1 Power supply

4.6 Memory interfaces

4.6.1 Local memory interface (LMI)

4.6.2 Flexible memory interface (FMI)

4.6.3 SPI Flash memory interface

a. This is not available for the MB704 STi5197 15 x 15 processor board.

4.7.1 USB2.0 host

4.7.5 I2C interfaces

5 MB762 SD generic peripheral board

Figure 4. Block diagram of MB762 SD generic peripheral board

Transport stream, see

5.1 Power supply

5.4 Dual serial RS232

5.5 Infrared receiver and transmitter

5.6 Serial I2C buses

Figure 5. I2C connectivity

Processor board MB762 peripheral board

5.7 Smartcard slots

5.8 Flexible memory interface (FMI)

Table 2. Board FMI memory map

5.8.1 STEM FMI interface

5.8.2 FMI support

Figure 6. FMI system block diagram

Processor board MB762 peripheral board

5.9 DVB-CI and transport stream

Figure 7. Transport stream and DVB-CI block diagram