EE8691-Embedded systems

UNIT – I

INTRODUCTION TO EMBEDDED SYSTEMS

 Introduction to Embedded systems

 Structural units in Embedded Processor

 Selection of Processor and Memory devices

 DMA

 Memory management methods

 Timer and counting devices

 Watchdog timer

 Real Time Clock

 In circuit Emulator

 Target hardware debugging

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INTRODUCTION TO EMBEDDED SYSTEMS

SYSTEM:
A system is a way of working, organizing or doing one or many tasks according to a fixed
plan, program, or set of rules.

A computer is a system that has the following or more components.

1. A microprocessor
2. A large memory comprising the following two kinds:
(a) Primary memory (semiconductor memories - RAM, ROM and
fast accessible caches)
(b) Secondary memory (magnetic memory located in hard disks,
diskettes and cartridge tapes and optical memory in CD-
ROM)
3. Input units like keyboard, mouse, digitizer, scanner, etc.
4. Output units like video monitor, printer, etc.
5. Networking units like Ethernet card, front-end processor-based
drivers, etc.
6. I/O units like a modem, fax cum modem, etc.

EMBEDDED SYSTEM:

An embedded system is a system that has embedded software and computer hardware,
which makes it a system dedicated for an application or specific part of an application or
product or a part of a larger system.

Embedded systems are electronic devices that incorporate microprocessors within their
implementations. The main purposes of the microprocessor are to simplify system design
and provide flexibility. Having a microprocessor in the device mean s that removing bugs.
making modifications or adding new features are only matters of rewriting the software that
controls the device. Unlike PCs. however, embedded systems may not have a disk drive and
so the software is often stored in a read -only memory (ROM) chip: this means that modifying
the software requires either replacing or "reprogramming" the ROM.

Meaning of REAL TIME:

Real-time systems process events, Events occurring on system inputs cause other events to
occur as system outputs. Examples of input events include such things as the detection of a
telephone ring signal the application of force to the brake pedal of a car, or the opening of a
microwave oven's door. The output events produced in response to these input events might
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be to take the phone line "off-hook," to apply hydraulic pressure to the automobile's brake
system and to turn off the microwave oven.

One of the primary design goals of real-time systems is minimizing response time. A soft
real-time system is one that is designed to compute the response as fast as possible but
doesn't have an explicit deadline. If a deadline is imposed, the system is known as a hard
real-time system. Keeping response times of hard real-time systems within the given
deadlines is always important or the entire system may fail to operate properly. For example,
an antilock braking system must detect and respond to loss of traction within a few
milliseconds; a delay of one or two seconds would be intolerable and potentially deadly.

Classification of Embedded System:

 Small Scale Embedded system:

Designed with a single 8 or 16 bit microcontroller and has little software and hardware
complexities.
Example: Automatic chocolate vending machine, washing machine, children toys etc

 Medium Scale Embedded system:

Designed with a single or few 16 or 32 bit microcontroller and has medium software
and hardware complexities.
Example: Banking system, video game etc

 Large scale Embedded system:

Designed with more 32 bit microcontroller and is more complex.
Example: Mobile phone, Security products etc.
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Characteristics of Embedded system

 Real time and multi rate operations define the ways in which the system works, reacts to
events, interrupts and schedules the system functioning in real time.
 Complex algorithms.
 Complex graphic user interfaces.
 Dedicated functions.
Constraints of an Embedded System:

 Available system memory.

 Available processor speed.
 The need to limit power dissipation when running the system continuously in cycles of (‘wait
for events, run, stop, wake up and sleep’).

Components of an Embedded System:

An embedded system consists of three main components.

1. It embeds hardware similar to a computer.(CPU, memory and other peripherals)
2. It embeds main application software.
3. It embeds a RTOS (Real Time Operating System) which is optional.
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Fig: Components of Embedded System Hardware

It consists of one or more of the following components.

 Processor:
This could be either a microprocessor, microcontroller or DSP processor based on
the application but more commonly microcontrollers are used.

A processor is the heart of the embedded system. A processor has two essential units:
Program Flow Control Unit (CU) and Execution Unit (EU). The CU includes a fetch unit for
fetching instructions from the memory. The EU has circuits that implement the instructions
pertaining to data transfer operations and data conversion from one form to another. The EU
includes the Arithmetic and Logical Unit (ALU) and also the circuits that execute instructions
for a program control task, say, halt, interrupt, or jump to another set of instructions. It can
also execute instructions for a call or branch to another program and for a call to a function.

A processor runs the cycles of fetch and execute. The instructions, defined in the processor
instruction set, are executed in the sequence that they are fetched from the memory. A
processor is mostly in the form of an IC chip; alternatively, it could be in core form in an ASIC
or at a SoC. Core means a part of the functional circuit on the VLSI chip.

An embedded system processor chip or core can be one of the following.

1. General Purpose Processor (GPP):

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a. Microprocessor.
b. Microcontroller.
c. Embedded Processor.
d. Digital Signal Processor (DSP).
e. Media Processor.
2. Application Specific System Processor (ASSP) as additional
processor
3. Multiprocessor system using General Purpose processors (GPPs)
and Application Specific Instruction Processors (ASIPs)
4. GPP core (s) or ASIP core (s) integrated into either an Application
Specific Integrated Circuit (ASIC), or a Very Large Scale Integrated
Circuit (VLSI) circuit or an FPGA core integrated with processor
unit(s) in a VLSI (ASIC) chip.

For a system designer, the following are important considerations when selecting a
processor:
1. Instruction set.
2. Maximum bits in an operand (8 or 16 or 32) in a single arithmetic
or logical operation.
3. Clock frequency in MHz and processing speed in Million
Instructions Per Second (MIPS).
4. Processor ability to solve the complex algorithms used in meeting
the deadlines for their processing.

 Memory:
This could be either primary (ROM,RAM) or secondary memory(CDROM)

Fig: Various forms of memories in the system.

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Other Peripherals
 A power supply source/ charge pump
 Clock for synchronizing all system units with processor
 System timer and Real Time Clock(RTC) to schedule various tasks for real time
programming
 Reset, Power up to reset internally and externally.
 Watch dog timer (WDT) resets the system after a predefined time out. It helps in rescuing
the system if a fault develops and the program gets stuck.
 A system connects to external physical devices through parallel/ serial I/O ports. A system
often networks to other devices through an I/O bus. Eg I2C, SPI, USB, CAN etc.
 Demux and Mux for multiple channels
 ADC/ DAC unit.
 Interrupt handlers.
 I/O units such as screen, modem, fax cum modem etc.
 Input units such as keyboard, mouse, digitizer, scanner etc.
 Output units such as LCD, video monitor, printer etc.
 Networking units such as an Ethernet card, front end processor based server, bus drivers
etc.
 An operating system that has general purpose user and application software in the
secondary memory.
EMBEDDED COMPUTORY APPLICATIONS:

Small scale Embedded System:

 Automatic chocolate vending machine
 Stepper motor controllers for a robotic system
 Washing or cooking systems
 Keyboard controller
 CD drive or Hard disk drive controller
 Multitasking toys.
 Digital storage system
 Spectrum analyzer
 Remote controller of TV
 Biomedical systems such as ECG LCD display.
Medium scale Embedded System:
 Computer networking system
 Banking system
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 Entertainment system
 Communication system
 Video games
 Image filtering, processing etc.

Sophisticated/ Large scale Embedded System

 Mobile smart phones
 Mobile Computer
 Embedded system for Wireless LAN
 Security products

Exemplary applications of each type of embedded system.

Designing an embedded System on a VLSI Chip.

1. Embedded SoC (System on Chip) and ASIC (Application Specific Integrated Circuit) and
examples of their applications. These use (i) Application Specific Instruction Processor
(ASIP), (ii) Intellectual Property (IP) core, (iii) Field Programmable Gate Arrays (FPGA) core
with single or multiple processor units on an ASIC chip.

2. Smart card, an example of the units of an embedded System on a Chip (SoC).

CASE STUDIES OF SOME EMBEDDED APPLICATIONS:

1) Automatic Chocolate Vending Machine (ACVM):

Figure shows the diagrammatic representation of ACVM. Assume that ACVM has following
components:
1. It has keypad on the top of the machine. That enables a child to interact with it when
buying a chocolate. The owner can also command and interact with the machine.
2. It has an LCD display unit on the top of the machine. It displays menus, text entered
into the ACVM and pictograms, welcome, thank you and other messages. It enables the child
as well as the ACVM owner to graphically interact with the machine. It also displays time and
date.
3. It has a coin insertion slot and a mechanical coin sorter so that child can insert coins
to buy a chocolate.
4. It has a delivery slot so that child can collect the chocolate and coins, if refunded.
 It has an internet connection port using a USB based wireless modem so that owner can
know status of the ACVM sales from a remote location.
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Structural units of Embedded Processor

1. Memory Address Register (MAR): It holds the address of the byte or

word to be fetched from external memories. Processor issues the address of instruction or
data to MAR before it initiates fetch cycle.
2. Memory Data Register (MDR): It holds a byte or word fetched (or to sent)
from an external memory or IO address.
3. System Buses:
a. Internal Bus: It internally connects all the structural units inside the
processor. Its width can be 8, 18, 32, 48 or 64 bits.
b. Address Bus: An external bus that carries the address from MAR to
memory as well as to IO devices and other units of system.
c. Data Bus: An external bus that carries, during a read or write operation,
the bytes for instruction or data from or to an address. The address is determined by MAR.
d. Control Bus: An external set of signals to carry control signals to
processor or memory or device.
4. Bus Interface Unit (BIU): An interface unit between processor‘s internal
units and external buses.
5. Instruction Register (IR): It sequentially takes instruction codes (opcode)
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to execution unit of processor.

6. Instruction Decoder (ID): It decodes the instruction received at the IR and
passes it to processor CU.
7. Control Unit (CU): It controls all the bus activities and unit functions
needed for processing.
8. Application Register Set (ARS)
9. A set of on chip registers used during processing of instructions of an
application program.
a. A register window.
b. A subset of registers with each subset storing static variables of a
software routine or
c. A register file associated to a unit such as ALU or FLPU.
10. Arithmetic Logic Unit (ALU): A unit to execute arithmetic or logic
instructions according to the current instruction present at IR.
11. Program Counter (PC):
It generates an instruction cycle by sending the address defined by it to memory through
MAR. It auto increments as the instructions are fetched regularly and sequentially. It is called
instruction pointer in 80 x 86 processors.

12. Stack Pointer (SP): A pointer for an address, which corresponds to a

stack-top in memory.

ADVANCED PROCESSOR’S STRUCTURAL UNITS:

Advanced processor circuits consist of RISC architecture.
It executes most of the instruction in single clock cycle by using multiple register sets,
windows and files and by reducing the dependency on the external memory access for data.
A RISC has only few addressing modes for arithmetic and logic instructions. It contains the
floating point unit.
Pipelining allows a processor to overlap the execution of several instructions, so that more
instructions can be executed in the same period of time.
Example: DSP processors TMS320C6000, Davinci processor,
OMAP processor etc.
1. Instruction Level Parallelism Unit (ILP):
For instruction level parallelism, the multistage pipeline processing, multiline superscalar
processing and dual, quad or multicore processing speeds up the performance from one
instruction per clock cycle.
2. Instruction Queue (IQ):
It is a queue of instruction so that the IR does not have to wait for the next instruction after
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one has been processed.

3. Prefetch Control Unit (PFCU):

A unit that controls the fetching of data into the I and D. caches in advance from the memory
units. The instructions and data are delivered when needed by the processor‘s execution
units. The processor does not have to fetch data just before executing the instruction. Pre-
fetching unit improves performance by fetching instruction and data in advance for
processing.
1. Instruction Cache (I-Cache):
It sequentially stores, like an instruction queue, the instruction in FIFO mode. It lets the
processor execute instructions at great speed using PFCU compare to external system
memories, which are accessed at relatively much slower speeds.
2. Branch Target Cache (BT Cache):
It facilitates ready availability of the next instruction – set when a branch instruction like jump,
loop or call is encountered. Its fetch unit foresees a branching instruction at the I-Cache.
3. Data Cache (D-Cache):
It stores the pre-fetched data from external memory. A data cache generally holds both the
key (address) and value (word) together at a location. It also stores write through data when
so configured. Write through data means data from the execution unit that transfer through
the cache to external memory addresses.
4. Memory Management Unit (MMU):
It manages the memories such that the instructions and data are readily available for
processing.
5. System Register Set (SRS):
It is a set of registers used while processing the instructions of the supervisory system
program.
6. Floating Point Processing Unit (FLPU):
A unit separate from ALU for floating point processing, which is essential in processing
mathematical function fast in a microprocessor or DSP.
7. Floating Point Register set (FRS):
A register set dedicated for storing floating point numbers in a standard format and used by
FLPU for its data and stack.
8. Multiply and Accumulate Unit (MAC):
There is also a MAC unit for multiplying coefficients of a series and accumulating these
during computations

9. Atomic Operation Unit:

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It lets a user (compiler) instruction, when broken into a number of processor instruction called
atomic operations, finish before an intercept of a process occurs. This prevents problems
from arising out of shared data between various routines and tasks.

Selection of Processor and Memory devices:

• Processor selection:

• A processor, operate at higher clock speed, processes more instructions per second.

• High computing performance when there exists 1. pipeline 2. superscalar 3.prefetch cache
unit, caches, register files and MMU, RISC architecture

• Fast context switching in a multitasking system

• Power efficient embedded system requires a processor that has programmable auto
shutdown feature for its units

• Burst mode accesses external memories fast

• Atomic operation unit provides hardware solution to shared data problems

•
Program information are the instructions i.e. opcodes that are to be executed by the
processor. Generally they are stored in a non-volatile memory that is mapped directly to the
address space of the processor. Or they might be stored in external memories (say as files in
a partition) and loaded on to a volatile memory just prior to execution of the program.
Data memory can be used to store primarily two kind of information. One is relating to the
intermediate data being processed- for e.g. a variable storing a value during course of
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execution of an algorithm or a Process Control Block in an OS etc. The other is the Stack
which is used by the processor to store its return functions and local variables. In either case
the memory type is volatile.

Memory Types

The primary differentiation of the memory is based on the volatility i.e. whether the stored
data is retained after power cycling the device.  Accordingly, the memory can be either
Volatile memory or a non-volatile memory.

Volatile memory

Volatile memories can hold their contents only when power is continuously applied to the
memory devices. As soon as the power is removed, the contents in the memories are lost.
The primary usage is to store the data/stack as well as storing the program instructions.
Examples of volatile memories include static RAM, dynamic RAM and static dynamic RAM.
Generally the volatile memories used are of type Random Access Memory (RAM) i.e. data at
any address in the memory can be accessed by giving the address in the address bus of the
memory. Primarily the volatile memory is divided in to two types:
SRAM – Static Random Access Memory
The static RAM is a type of memory that uses bi-stable latching circuitry to store each bit.
Due to the design, the memories need not be refreshed. Thus the data stored will be static till
the duration of power being applied to the RAM.
The primary advantage of SRAM is its speed. Fast SRAMs can operate on par with the
processor speed enabling access times equal to a clock cycle used by the microprocessor.
Synchronous SRAMs are the preferred way of implementing Instruction and Data caches in a
processor system. Further since there is no need for specialized controllers to refresh the
RAM, they are easier to use with low end microcontrollers.
The down side is that the density of the SRAMs is comparatively lower than the DRAMs. Also
the cost is comparatively higher.
DRAM – Dynamic Random Access Memory
DRAM stores each bit in a storage cell consisting of capacitor and transistors. Since
capacitors lose their charges quickly they need to be recharged. So by design, each bit in the
DRAM must be refreshed periodically to maintain its contents and hence the name
“Dynamic”. Due to the structural simplicity (only one transistor and a capacitor per bit), DRAM
can be packed much denser than SRAM.
Even though they need specialized controller to take care of refreshing, their higher density
provides a higher cost to memory ratio compared to SRAM’s.
The most popular type of DRAM used in the SDRAM.
SDRAM – Static Dynamic Random Access Memory
SDRAM is a type of DRAM that ‘Synchronous’ with the system bus. The device needs a
SDRAM controller typically a part of the SoC for it to function properly. The data is organized
as row and column and an internal state machine that takes care of fetch and refresh logic.
High speed varieties of SDRAM include DDR, DDR2, and DDR3. DDR – Double Data Rate
RAMs can transfer data on both edges of the clock and hence the name. DDR2/DDR3 has
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higher data width and different power requirements even though internally they operate at the
same rates as DDR.

Non-volatile memory

Non-volatile memories will retain their contents even when the power to the memory device is
removed. This makes them better choice for storing the data that are to be retrieved after the
system is restarted. The configurations settings are typically stored in the non-volatile
memory. They are typically slower than volatile memory and require complex procedures for
reading and writing.
Though there are many other kinds of technologies such as Disk-On-Chip, SSD, MMC Cards
etc, are available, the most common non-volatile memories found in embedded systems are
as follows
 Flash memory
 EEPROM
 SD cards

Flash memory
Flash memory is a most commonly used type of non volatile memory in the embedded
system for their durability and larger number of erase cycles.
Microcontroller unit mostly contains flash memory on which the programs are written for
execution. Since flash memory is integrated on-chip with the microcontroller, its usage
become easier. Flash memory is generally sector/block erasable, which means one
sector/block of the memory can be erased at a time in which each bit erased is moved to a
state ‘1’. When it is written, the state is changed from ‘1’ to ‘0’.
•
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TYPES OF MEMORIES
Memory can be classified into
 Primary memory (ROM, RAM)
 Secondary memory (CDROM)
Secondary memory is not used in embedded applications.

ROM:
Read Only Memory. This is used to store non volatile information. ROM is available in
various forms like
 Masked ROM
 OTP ROM
 EPROM
 EEPROM
 Flash

In general, ROM is used to store boot strap programs, BIOS (Basic Input and Output
system) programs, vector addresses of interrupts etc.
Masked ROM:
 This is built from a circuit that has r inputs, n ouputs and 2 r combinational circuits.
 Appropriate masking gives the desired set of outputs at each combinational circuit.
Certain links fuse and others that are masked do not fuse.

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 The embedded software designer after testing and debugging provides to a

manufacturing foundry a file having a table of desired output bits for the various
combination of input bits. A program called locator creates this table.
 Normally, one time masking is very high. Cost effective for bulk users.
 Doesn’t need a device programmer.

EPROM, E2PROM, Flash and OTP ROM:

Special versions of ROM such as EPROM, E 2PROM, Flash and OTP ROM are used
with the help of a device programmer.

 EPROM is an ultraviolet ray erasable and device programmer Programmable Read only
Memory. Erasing the device means restoring 1 each bit in the cell arrays at each ROM
address.
 EEPROM is an electrically erasable Programmable Read only Memory. Erasing during
an application program run is done by sending all eight bits as 1s for the write in the
presence of input Vpp called programming voltage and short duration write pulse. Erasing
of a byte must precede the write. Examples are a) Storing current date and time b) Storing
port status etc
 Flash memory is a form of EEPROM in which the sector of bytes can be erased in a
flash. The advantage over EEPROM is that the erasing of many bytes simultaneously
saves time in each erase cycle that preceeds the write cycles. The sisadvantage is that
once a sector is erased, each byte writes into it again one by one and takes long time. A
new version of flash to avoid this drawback is Boot back flash. Examples are a) Storing
pictures b) Storing messages and contacts in a mobile phone.
 An OTP ROM once written is not erasable. Examples include a) Smart card identity
number and user’s personal information, b) ATM card or credit card details etc.

RAM
Random Access Memory. RAM stores the variables during a program run and stores
the stack. It stores the input and output buffers, for example for speech and image. It can
also store the application program and data when the ROM image is stored in a
compressed format in an embedded system and decompression is done before the actual
run of the system.
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Types of RAM
 SRAM is used most commonly for designing caches
 DRAM is used in high performance computers or high memory density systems.
 EDO RAM is used in systems with buses to the device operating with clock rates up to
100 MHz and a zero wait state is needed between two fetches.
 SDRAM synchronizes the read operations and keeps the next work while the previous
one is being fetched.
 RDRAM accesses in burst the four successive words in a single fetch and thus gives
above 1 GHz performance of the system.
 Parametrized distributed RAM is the one where RAM is distributed in various system
subuints.
 Parametrized block RAM is used when a specific block of the RAM is dedicated for use
by a subunit only.

To summarize, a system memory may be present as

 Internal / External RAM for temporary data and stack.
 Internal / External ROM/ PROM/ EEPROM/ Flash memory for storing application
program, system status, images, songs, video etc.
 RAM memory buffers at ports.
 CACHES (in pipelined and superscalar processors).This hold the copies of instruction
and data in advance from primary memory and storing results temporarily during
processing.
 Memory stick or card for large storage of images, songs, video etc.

Memory Management
 Memory management is the act of managing computer memory at the system level. The
essential requirement of memory management is to provide ways to dynamically allocate
portions of memory to programs at their request, and free it for reuse when no longer
needed.
 Embedded systems often have small memory and are required to run a long time, so
memory management is a major concern when developing real-time applications.

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 The memory management function keeps track of the status of each memory location,
either allocated or free. It determines how memory is allocated among competing
processes, deciding who gets memory, when they receive it, and how much they are
allowed. When memory is allocated it determines which memory locations will be
assigned. It tracks when memory is freed or unallocated and updates the status.

Memory Selection

Selection of suitable memory is very much essential step in high performance applications,
because the challenges and limitations of the system performance are often decided upon
the type of memory architecture.
Systems memory requirement depend primarily on the nature of the application that is
planned to run on the system. Memory performance and capacity requirement for low cost
systems are small, whereas memory throughput can be the most critical requirement in a
complex, high performance system.
Following are the factors that are to be considered while selecting the memory devices,
 Speed
 Data storage size and capacity
 Bus width
 Latency
 Power consumption
 Cost

SRAM’s have lower data storage and capacity hence they are suitable for lower end
systems where as SDRAM for higher end systems with complex requirements.
Among the high speed types of SDRAM, DDR2 memory modules can have memory
capacities from 256MB to 4GB capacities. Most of the DDR2 memory chips come in FBGA
(Fine Ball Grid Array) package. The package allows higher memory densities in smaller
space with better electrical properties. DDR2 memory uses 1.8V for power, resulting in
lower power and cooler operation, whereas the DDR uses 2.5V.
Further there are variations of DDR available that are fine tuned for particular applications.
For example, the Graphic DDR (GDDR) memory is designed for higher performance than
the standard DDR memory. To achieve this, they operate at additional voltage of 2.0V. But
the capacity of GDDR memory devices in comparison to DDR tends to be reduced
typically from 256Mb to 512Mb. This enables them to be used in resource intensive video
cards. On the other end of the spectrum, Mobile DDR (MDDR) memory devices are
optimized for low power applications such as battery operated and handheld devices. In
deep power down (DPD) mode of operation, their current can go as low as 10uA.
The data rates are defined by the RAM manufacturer and are based on various factors
such as CAS latency, RAS-CAS delay etc. Even a increase of 0.5 cycle, can impact a
change of up to 10% of speed.

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Again, these high speed varieties of SDRAM needs careful PCB layout with signal integrity
considerations including presence of suitable terminations.
Obviously a 32-bit width memory can fetch more data in a same cycle as a 16 bit memory.
Thus more the data width, better the transfer rate, provided the data line support is
available.
Another factor, when going for non-volatile programmable storage, is deciding the
programming model. For example, it could be ISP (In-System Programming) that allows
programming the flash but needs the application to be stopped at that time. Or it could be
IAP (In-Application Programming) that will allow re-programming of the memory even
when the application firmware is running. This is determined by the memory architecture.
Nowadays many microcontrollers support both the options and ISP is used for
manufacturing and IAP is appropriate for field updates.
Though nowadays the memory controllers available in the SoC primarily dictate the
selection of the memory devices, we believe this blog provides a good insight about
various memory technologies, their application and selection. In the next blog, we will
analyze about the power supply design in an embedded system.
DMA (Direct Memory Access):

• Direct memory access (DMA) is a mode of data transfer between the memory and I/O
devices. This happens without the involvement of the processor. We have two other

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methods of data transfer, programmed I/O and Interrupt driven I/O. Let’s revise each and
get acknowledge with their drawbacks.
• In programmed I/O, the processor keeps on scanning whether any device is ready for data
transfer. If an I/O device is ready, the processor fully dedicates itself in transferring the
data between I/O and memory. It transfers data at a high rate, but it can’t get involved in
any other activity during data transfer. This is the major drawback of programmed I/O.
• In Interrupt driven I/O, whenever the device is ready for data transfer, then it raises
an interrupt to processor. Processor completes executing its ongoing instruction and
saves its current state. It then switches to data transfer which causes a delay. Here, the
processor doesn’t keep scanning for peripherals ready for data transfer. But, it is fully
involved in the data transfer process. So, it is also not an effective way of data transfer.
• The above two modes of data transfer are not useful for transferring a large block of data.
But, the DMA controller completes this task at a faster rate and is also effective for transfer
of large data block.
• 3 Modes in DMA:
• Burst Mode: Here, once the DMA controller gains the charge of the system bus, then it
releases the system bus only after completion of data transfer. Till then the CPU has to
wait for the system buses.
• Cycle Stealing Mode: In this mode, the DMA controller forces the CPU to stop its
operation and relinquish the control over the bus for a short term to DMA controller.
After the transfer of every byte, the DMA controller releases the bus and then again
requests for the system bus. In this way, the DMA controller steals the clock cycle for
transferring every byte.
• Transparent Mode: Here, the DMA controller takes the charge of system bus only if
the processor does not require the system bus.
Working of DMA:
• Whenever an I/O device wants to transfer the data to or from memory, it sends the DMA
request (DRQ) to the DMA controller. DMA controller accepts this DRQ and asks the CPU
to hold for a few clock cycles by sending it the Hold request (HLD).
• CPU receives the Hold request (HLD) from DMA controller and relinquishes the bus and
sends the Hold acknowledgement (HLDA) to DMA controller.

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• After receiving the Hold acknowledgement (HLDA), DMA controller acknowledges I/O
device (DACK) that the data transfer can be performed and DMA controller takes the
charge of the system bus and transfers the data to or from memory.
• When the data transfer is accomplished, the DMA raise an interrupt to let know the
processor that the task of data transfer is finished and the processor can take control over
the bus again and start processing where it has left.
Memory Management Methods
 Single contiguous allocation
 Partitioned allocation
 Paged Memory Management
 Segmented Memory Management

Single contiguous allocation

 Single allocation is the simplest memory management technique.
 All the computer's memory, usually with the exception of a small portion reserved for the
operating system, is available to the single application. 
 MS-DOS is an example of a system which allocates memory in this way. An embedded
system running a single application might also use this technique.
 A system using single contiguous allocation may still multitask by swapping the contents
of memory to switch among users. Early versions of the Music operating system used this
technique.

Partitioned allocation
 Partitioned allocation divides primary memory into multiple memory partitions, usually
contiguous areas of memory. Each partition might contain all the information for a specific
job or task. Memory management consists of allocating a partition to a job when it starts
and un allocating it when the job ends.
 Partitioned allocation usually requires some hardware support to prevent the jobs from
interfering with one another or with the operating system. The IBM System/360 used a
lock-and-key technique. Other systems used base and bounds registers which contained
the limits of the partition and flagged invalid accesses.

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 Partitions may be either static, that is defined at Initial Program Load (IPL) or boot time or
by the computer operator, or dynamic, that is automatically created for a specific job.
 Partitions may be relocatable using hardware typed memory.

Paged memory management

 Paged allocation divides the computer's primary memory into fixed-size units called page
frames, and the program's virtual address space into pages of the same size. The
hardware memory management unit maps pages to frames. The physical memory can be
allocated on a page basis while the address space appears contiguous.
 Usually, with paged memory management, each job runs in its own address space.
Paged memory can be demand-paged when the system can move pages as required
between primary and secondary memory.

Segmented memory management

 Segmented memory is the only memory management technique that does not provide
the user's program with a 'linear and contiguous address space. Segments are areas of
memory that usually correspond to a logical grouping of information such as a code
procedure or a data array. Segments require hardware support in the form of a segment
table which usually contains the physical address of the segment in memory, its size, and
other data such as access protection bits and status (swapped in, swapped out, etc.)
 Segmentation allows better access protection than other schemes because memory
references are relative to a specific segment and the hardware will not permit the
application to reference memory not defined for that segment.
 It is possible to implement segmentation with or without paging. Without paging support
the segment is the physical unit swapped in and out of memory if required. With paging
support the pages are usually the unit of swapping and segmentation only adds an
additional level of security.
 Addresses in a segmented system usually consist of the segment id and an offset
relative to the segment base address, defined to be offset zero.

Dynamic Memory Allocation

The task of fulfilling an allocation request consists of locating a block of unused memory of
sufficient size. Memory requests are satisfied by allocating portions from a large pool of
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memory called the heap or free store. At any given time, some parts of the heap are in
use, while some are "free" (unused) and thus available for future allocations.
The memory management system must track outstanding allocation to ensure that they
do not overlap and no memory is lost as a memory leak (chunking). Types of Heap
management are
 Heap Fragmentation [Internal / External]
 Heap Compaction
Heap Fragmentation
 Fragmentation is a phenomenon in which storage space is used inefficiently, reducing
capacity or performance and often both. The exact consequences of fragmentation
depend on the specific system of storage allocation in use and the particular form of
fragmentation.
 When a computer program requests blocks of memory from the computer system, the
blocks are allocated in chunks. When the computer program is finished with a chunk, it can
free the chunk back to the system, making it available to later be allocated again to
another or the same program. The size and the amount of time a chunk is held by a
program varies. During its lifespan, a computer program can request and free many
chunks of memory.
 When a program is started, the free memory areas are long and contiguous. Over time
and with use, the long contiguous regions become fragmented into smaller and smaller
contiguous areas. Eventually, it may become impossible for the program to obtain large
contiguous chunks of memory.
Internal Fragmentation
 Due to the rules governing memory allocation, more computer memory is
sometimes allocated than is needed. For example, memory can only be provided to
programs in chunks divisible by 4, 8 or 16, and as a result if a program requests perhaps
23 bytes, it will actually get a chunk of 32 bytes. When this happens, the excess memory
goes to waste. In this scenario, the unusable memory is contained within an allocated
region. This arrangement, termed fixed partitions, suffers from inefficient memory use -
any process, no matter how small, occupies an entire partition. This waste is
called internal fragmentation
 Unlike other types of fragmentation, internal fragmentation is difficult to reclaim; usually
the best way to remove it is with a design change.
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External fragmentation
 External fragmentation arises when free memory is separated into small blocks and is
interspersed by allocated memory. It is a weakness of certain storage allocation
algorithms, when they fail to order memory used by programs efficiently. The result is that,
although free storage is available, it is effectively unusable because it is divided into pieces
that are too small individually to satisfy the demands of the application.
 The term "external" refers to the fact that the unusable storage is outside the allocated
regions.

Heap Compaction
If a request is made and no sufficient memory is available, heap compaction is done. In
this, the entire list of free locations is scanned and adjacent areas are merged. The
disadvantage is that the system becomes non-deterministic.

Timer and counting Devices:

 Timer is a very common and useful peripheral. It is a device that counts the regular interval
(δT) clock pulse at its input. The counts are stored and incremented on each pulse. It has
output bits for the period of counts. The counts multiplied by interval δT gives the time.
 Number of counting the interval x δT = Time
 Timer is a programmable device, (i.e) the time period can be adjusted by writing specific
bit patterns to some of the registers called timer-control registers.
 A counter is more general version of the timer. It is a device that counts the input for
events that may occur at irregular or regular intervals. The count gives the number of input
events or pulses, since it was last read.
 The simple timer has a 16 bit up counter which increments with each input clock pulse is
shown in figure (a). Thus the output value ‗Cnt‘ represents the number of pulses, since
the counter was last reset to zero. An additional output ‗top‘ indicates when the terminal
count has been reached. It may go high for a predetermined time as set by the
programmable control word inside the timer unit. The count can be loaded by the external
program.

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The figure (b) provides the structure of another timer where a multiplexer is used to
choose between an internal clock and external clock. The mode bit when set or reset
decided the selection. For internal clock (Clk) it behaves like the timer in Figure (a). For the
external coun- in (Cnt-in) it just counts the number of occurrences.
Watch dog Timer:
It is a timing device that resets the system after a predefined time out. It starts after a few
clock cycles from power up. After restart, system works normally, if any failure occurs in
past.
A watch dog timer is a piece of hardware that can be used to automatically detect software
abnormalities and reset the processor if any. It is based on the counter that counts down
from some initial value to zero.
The watchdog timer is a chip external to the processor. However, it could also be included
within the same chip as the CPU. This is done in many microcontrollers.
The process of restarting the watch dog timer‘s counter is sometimes called
“Kicking the dog”.

Real Time Clock:

It is a clock that keeps track of the time even when computer is turned off. Real time clocks
(RTC) run on a special battery that is not connected to the normal power supply. In
contrast, clocks that are not real time do not function when the computer is off. Do not

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confuse a computer‘s real time clock with its CPU clock. The CPU clock regulates the
execution of instructions.
Real time clock provides system clock and it has a number of applications. It is a clock that
generates system interrupts at preset intervals. An Interrupt Service Routine (ISR)
executes on each tick or timeout or overflow of this clock. Once the device
started, it never resets or never reloaded to another value. Example: DS1307 chip is a real
time clock integrated circuit.
Consider the block diagram shown below. The Arduino UNO is used for reading
time from DS1307 and display it on 16X2 LCD. DS1307 sends time/data using 2 lines to
Arduino. A buzzer is also used for alarm indication, which beeps when alarm is activated.

In circuit Emulator:
In Circuit Emulator is the most expensive way to debug your hardware. It takes a special
processor that physically takes place of the normal processor. This special processor
allows software access to the internal operation of the processor.

Target Hardware Debugging:

Most of these debugging techniques can be applied to any microcontroller since they do
not use any specific tools.
There are many ways to debug hardware, they are,
1. ICE (In Circuit Emulator)
2. ICD (In Circuit Debug)
3. Simulation
4. Serial RS-232
5. LCD
6. LED
7. Hardware pins
8. Logic Analyzer
7. ICD (In Circuit Debug): The next best thing to ICE is ICD (In Circuit Debug). This is for
PIC microcontroller. BDM (Background Debug Mode) is for non PIC microcontroller. For
ICD the processor has a small amount of built-in hardware that can halt the processor

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when the program reaches a specific address. The software can then read back all the
registers and processor state.
8. Simulation: With a source code simulator you can step through the high level language
code and see its effect on memory and variables without having to look at the assembler
code directly. This let you focus on high level language operation and let you concentrate
on the problem you are trying to solve. One great advantage of simulator is that you do not
have to wait to download and program the target processor. So you can cut out the time
consuming programming just by using the simulator.
9. Serial RS232: New microcontrollers have a built-in UART which gives virtually free debug
tool that uses minimum resources and need very little software coding. For debug output
you need to connect the UART output in TX to a suitable level translator circuit a MAX 232
chip. You may even get away with direct connection to the input of your PC serial port –
using a translator chip will always work.
LCD: An LCD (Liquid crystal Display) gives a convenient way of displaying debugging
information. It is also useful for many different applications that need a text display output.
It is a module that displays text characters and a common screen size is 2 rows of 16
characters. Most LCD modules use the HD44780 controller chip which is why LCD
routines built into high level language always work.
LED: Using an LED as a microcontroller ―alive‖ indicator. Even though
it is such a simple thing to blink an LED on and off it is extremely useful as a debugging
tool as you can tell at a glance whether the code you just downloaded is working
sometimes you can will incorrectly set parameter on the programming software or compiler
which will stop the code dead.
The LED indicator gives a quick health check for your microcontroller which is easy to see.
Pin Debugging: This is the simplest and rudest debugging method using any available
port pin. Simply set and reset this pin at any point in the code that you want to monitor. It
has minimal impact on the code speed or size and can give you the following information.
You can tell if the code is active. It gives you the repetition rate
It gives you the routine time length (if you set the pin at the start and reset it at the end).
Logic Analyzer: This tool attaches to the pins you want to observe and captures the
waveforms displaying multiple traces on a single display. It uses a trigger module that can
be set to activate the combinations of the input signals or on their length. So you can
trigger on specific patterns or on glitches or both.
For non-microcontroller based systems where the data and address bus are exposed, a

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logic analyzer can show the address and data organised into hex words i.e. readable.
Some can disassemble the instruction showing what the processor was doing at the
trigger point.
For a microcontroller based system the logic analyzer can be useful in examining
peripheral operation. Example: for debugging the SPI or I 2C buses some logic analyzers
also have built in support for these protocols.
Another use of the logic analyzer is to capture output over a long period of time depending
on the memory capacity of the logic analyzer.

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