CA

HW 3

Qs 1: For a sd instruction;

ALUSrc = 1
MemtoReg = don’t care
RegWrite = 0
MemRead = 0
MemWrite = 1
PCsrc = 0
ALU operation = 00
Branch = 0

Justification:

The alusrc signal is 1 since we need to select immdata as ouput of mux for
store instruction and alusrc acts as selection line so is inserted. Since there is no
beq instruction branch is zero PCsrc is 0, not asserted. The MemRead and
MemWrite signals access memory since in a sd instruction data is being written
to memory and not read from memory memwrite signal is 1 and memread is 0.
Finally, since no data is being written on the destination register RegWrite is
also 0. The ALUOp field for branch is set for ADD to add the offset and rs1
(ALU control = 0010). The MemtoReg field is irrelevant as the RegWrite signal
is 0: since the register is not being written, the value of the data on the register
data write port is not used. Thus, the entry MemtoReg is don’t care.
Qs 2:

(a) shortest possible clock period for non pipelined implementations =

200+100+150+150+200+100 = 900 ps

(b) shortest possible clock period for pipelined implementation; pipelining

reduces overall time to the time of the longest stage which is, 200ps.

(c) it will take 5x900 = 4500 ps

(d) it will take 1200 ps for first instruction. The other 4 are in parallel = 200 x 4
= 800 ps. So total time taken for pipelined implementation of 5 instructions
without hazards is: 1200 + 800 = 2000 ps

(e) due to 2 data hazards we have 2 extra instructions in our pipeline so total
time now = 2000 + (200 x 2) = 2400 ps
Qs 3:

(a) Data hazards are listed below in stages:

1st stage: ld x2, 8(x31)

add x3, x1, x2

2nd stage: add x3, x1, x2

sd x3, 24(x31)

3rd stage: add x4, x1, x2

add x5, x1, x4

4th stage: add x5, x1, x4

sd x5, 32(x31)

contents are stored in x3 in the address calculated but x3 isnt calculated itself
until 3rd stage.

(b):

(C):