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SEMICONDUCTOR TECHNICAL DATA by MTP60N06HD/D

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   Motorola Preferred Device

   

N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
This advanced high–cell density HDTMOS power FET is 60 AMPERES
designed to withstand high energy in the avalanche and commuta- 60 VOLTS
tion modes. The new energy efficient design also offers a RDS(on) = 0.014 OHM
drain–to–source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies, 
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a Dis-
crete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature D

G
CASE 221A–06, Style 5
TO–220AB
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain–Source Voltage VDSS 60 Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc
Gate–Source Voltage — Continuous VGS ± 20 Vdc
— Non–Repetitive (tp ≤ 10 ms) VGSM ± 30 Vpk

Drain Current — Continuous ID 60 Adc

— Continuous @ 100°C ID 42.3
— Single Pulse (tp ≤ 10 µs) IDM 180 Apk
Total Power Dissipation PD 150 Watts
Derate above 25°C 1.0 W/°C

Operating and Storage Temperature Range TJ, Tstg – 55 to 175 °C

Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C EAS 540 mJ
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 60 Apk, L = 0.3 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case RθJC 1.0 °C/W
— Junction to Ambient RθJA 62.5

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

E–FET, Designer’s and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS
Motorola, Inc. 1995 Power MOSFET Transistor Device Data 1
MTP60N06HD
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (3) V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 250 µAdc) 60 — —
Temperature Coefficient (Positive) — 71 — mV/°C
Zero Gate Voltage Drain Current IDSS µAdc
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125°C) — — 100
Gate–Body Leakage Current IGSS nAdc
(VGS = ± 20 Vdc, VDS = 0 Vdc) — — 100
ON CHARACTERISTICS (1)
Gate Threshold Voltage (Cpk ≥ 3.0) (3) VGS(th) Vdc
(VDS = VGS, ID = 250 µAdc) 2.0 3.0 4.0
Threshold Temperature Coefficient (Negative) — 7.0 — mV/°C
Static Drain–to–Source On–Resistance (Cpk ≥ 3.0) (3) RDS(on) Ohm
(VGS = 10 Vdc, ID = 30 Adc) — 0.011 0.014
Drain–to–Source On–Voltage (VGS = 10 Vdc) VDS(on) Vdc
(ID = 60 Adc) — — 1.0
(ID = 30 Adc, TJ = 125°C) — — 0.9
Forward Transconductance gFS mhos
(VDS = 5.0 Vdc, ID = 30 Adc) 15 20 —
DYNAMIC CHARACTERISTICS
Input Capacitance Ciss — 1950 2800 pF
(VDS = 25 Vdc, VGS = 0 Vdc,
Output Capacitance Coss — 660 924
f = 1.0 MHz)
Transfer Capacitance Crss — 147 300
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time td(on) — 14 26 ns
Rise Time (VDD = 30 Vdc, ID = 60 Adc, tr — 197 394
VGS = 10 Vdc,
Turn–Off Delay Time RG = 9.1 Ω) td(off) — 50 102
Fall Time tf — 124 246
Gate Charge QT — 51 71 nC
(See Figure 8)
(VDS = 48 Vdc, ID = 60 Adc, Q1 — 12 —
VGS = 10 Vdc) Q2 — 24 —
Q3 — 21 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage VSD Vdc
(IS = 60 Adc, VGS = 0 Vdc)
— 0.99 1.2
(IS = 60 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.89 —
Reverse Recovery Time trr — 60 — ns
(See Figure 15)
(IS = 60 Adc, VGS = 0 Vdc, ta — 36 —
dIS/dt = 100 A/µs) tb — 24 —
Reverse Recovery Stored Charge QRR — 0.143 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance LD nH
(Measured from contact screw on tab to center of die) — 3.5 —
(Measured from the drain lead 0.25″ from package to center of die) — 4.5 —
Internal Source Inductance LS nH
(Measured from the source lead 0.25″ from package to source bond pad) — 7.5 —
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values. Max limit – Typ
Cpk =
3 x SIGMA

2 Motorola TMOS Power MOSFET Transistor Device Data

 MTP60N06HD
TYPICAL ELECTRICAL CHARACTERISTICS

120 120
VGS = 10 V 8V 7V VDS ≥ 10 V
100 100

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

9V
80 TJ = 25°C 80

60 6V 60

40 40

5V 100°C 25°C
20 20
TJ = – 55°C
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 2.8 3.6 4.4 5.2 6.0 6.8 7.6
VDS, DRAIN–TO–SOURCE VOLTAGE (Volts) VGS, GATE–TO–SOURCE VOLTAGE (Volts)

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)

RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)

0.020 0.0132
VGS = 10 V TJ = 25°C
0.018 0.0128
TJ = 100°C
0.0124
0.016
0.0120
0.014 VGS = 10 V
0.0116
0.012 25°C
0.0112
0.010
0.0108
– 55°C 15 V
0.008 0.0104

0.006 0.0100
0 10 20 30 40 50 60 70 80 90 100 110 120 0 10 20 30 40 50 60 70 80 90 100 110 120
ID, DRAIN CURRENT (Amps) ID, DRAIN CURRENT (Amps)

Figure 3. On–Resistance versus Drain Current Figure 4. On–Resistance versus Drain Current
and Temperature and Gate Voltage

1.8 1000
R DS(on) , DRAIN–TO–SOURCE RESISTANCE

VGS = 10 V VGS = 0 V
1.6 ID = 30 A
TJ = 125°C
I DSS, LEAKAGE (nA)
(NORMALIZED)

1.4 100

1.2 100°C
25°C
1.0 10

0.8

0.6 1
– 50 – 25 0 25 50 75 100 125 150 0 10 20 30 40 50 60
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (Volts)

Figure 5. On–Resistance Variation with Figure 6. Drain–To–Source Leakage

Temperature Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data 3

MTP60N06HD
POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.

5000
VDS = 0 V VGS = 0 V
Ciss TJ = 25°C
4000
C, CAPACITANCE (pF)

3000
Crss
Ciss
2000

Coss
1000
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

4 Motorola TMOS Power MOSFET Transistor Device Data

 MTP60N06HD

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

12 60 1000

VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)

QT VDD = 30 V
10 50 ID = 60 A
VGS VGS = 10 V
TJ = 25°C
8 40 tr
Q1 Q2

t, TIME (ns)
tf
6 30 100

4 ID = 60 A 20 td(off)
TJ = 25°C
2 10
Q3
VDS td(on)
0 0 10
0 8 16 24 32 40 48 56 1 10 100
QT, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (Ohms)

Figure 8. Gate–To–Source and Drain–To–Source Figure 9. Resistive Switching Time

Voltage versus Total Charge Variation versus Gate Resistance

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode di/dts. The diode’s negative di/dt during ta is directly con-
are very important in systems using it as a freewheeling or trolled by the device clearing the stored charge. However,
commutating diode. Of particular interest are the reverse re- the positive di/dt during tb is an uncontrollable diode charac-
covery characteristics which play a major role in determining teristic and is usually the culprit that induces current ringing.
switching losses, radiated noise, EMI and RFI. Therefore, when comparing diodes, the ratio of tb/ta serves
System switching losses are largely due to the nature of as a good indicator of recovery abruptness and thus gives a
the body diode itself. The body diode is a minority carrier de- comparative estimate of probable noise generated. A ratio of
vice, therefore it has a finite reverse recovery time, trr, due to 1 is considered ideal and values less than 0.5 are considered
the storage of minority carrier charge, QRR, as shown in the
snappy.
typical reverse recovery wave form of Figure 12. It is this
Compared to Motorola standard cell density low voltage
stored charge that, when cleared from the diode, passes
MOSFETs, high cell density MOSFET diodes are faster
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further (shorter trr), have less stored charge and a softer reverse re-
increases switching losses. Therefore, one would like a covery characteristic. The softness advantage of the high
diode with short t rr and low QRR specifications to minimize cell density diode means they can be forced through reverse
these losses. recovery at a higher di/dt than a standard cell MOSFET
The abruptness of diode reverse recovery effects the diode without increasing the current ringing or the noise gen-
amount of radiated noise, voltage spikes, and current ring- erated. In addition, power dissipation incurred from switching
ing. The mechanisms at work are finite irremovable circuit the diode will be less due to the shorter recovery time and
parasitic inductances and capacitances acted upon by high lower switching losses.

60
VGS = 0 V
I S , SOURCE CURRENT (AMPS)

50 TJ = 25°C

40

30

20

10

0
0.5 0.6 0.7 0.8 0.9 1.0
VSD, SOURCE–TO–DRAIN VOLTAGE (Volts)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data 5

 MTP60N06HD
di/dt = 300 A/µs Standard Cell Density
trr

I S , SOURCE CURRENT
High Cell Density
trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define able operation, the stored energy from circuit inductance dis-
the maximum simultaneous drain–to–source voltage and sipated in the transistor while in avalanche must be less than
drain current that a transistor can handle safely when it is for- the rated limit and must be adjusted for operating conditions
ward biased. Curves are based upon maximum peak junc- differing from those specified. Although industry practice is to
tion temperature and a case temperature (TC) of 25°C. Peak rate in terms of energy, avalanche energy capability is not a
repetitive pulsed power limits are determined by using the constant. The energy rating decreases non–linearly with an
thermal response data in conjunction with the procedures increase of peak current in avalanche and peak junction tem-
discussed in AN569, “Transient Thermal Resistance –
perature.
General Data and Its Use.”
Although many E–FETs can withstand the stress of drain–
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM) to–source avalanche at currents up to rated pulsed current
nor rated voltage (VDSS) is exceeded, and that the transition (IDM), the energy rating is specified at rated continuous cur-
time (tr, tf) does not exceed 10 µs. In addition the total power rent (ID), in accordance with industry custom. The energy rat-
averaged over a complete switching cycle must not exceed ing must be derated for temperature as shown in the
(TJ(MAX) – TC)/(RθJC). accompanying graph (Figure 13). Maximum energy at cur-
A power MOSFET designated E–FET can be safely used rents below rated continuous ID can safely be assumed to
in switching circuits with unclamped inductive loads. For reli- equal the values indicated.

1000 600
EAS, SINGLE PULSE DRAIN–TO–SOURCE

VGS = 20 V ID = 60 A
SINGLE PULSE
500
AVALANCHE ENERGY (mJ)

TC = 25°C
I D , DRAIN CURRENT (AMPS)

100 10 µs 400

300
100 µs
10 200
1 ms
RDS(on) LIMIT 10 ms
THERMAL LIMIT 100
PACKAGE LIMIT dc
1 0
0.1 1.0 10 100 25 50 75 100 125 150
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Rated Forward Biased Figure 13. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature

6 Motorola TMOS Power MOSFET Transistor Device Data

 MTP60N06HD

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5

(NORMALIZED) 0.2

0.1
0.1 P(pk)
0.05 RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
0.02 PULSE TRAIN SHOWN
t1 READ TIME AT t1
0.01
t2 TJ(pk) – TC = P(pk) RθJC(t)
SINGLE PULSE DUTY CYCLE, D = t1/t2
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)

Figure 14. Thermal Response

di/dt
IS
trr
ta tb
TIME

tp 0.25 IS

IS

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data 7

MTP60N06HD
PACKAGE DIMENSIONS

NOTES:
SEATING 1. DIMENSIONING AND TOLERANCING PER ANSI
–T– PLANE
Y14.5M, 1982.
B F C 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
T S BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
4
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
Q A 0.570 0.620 14.48 15.75
1 2 3 B 0.380 0.405 9.66 10.28
U STYLE 5:
C 0.160 0.190 4.07 4.82
PIN 1. GATE
H 2. DRAIN D 0.025 0.035 0.64 0.88
3. SOURCE F 0.142 0.147 3.61 3.73
K 4. DRAIN G 0.095 0.105 2.42 2.66
Z H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
L R N 0.190 0.210 4.83 5.33
V Q 0.100 0.120 2.54 3.04
J R 0.080 0.110 2.04 2.79
G S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
D U 0.000 0.050 0.00 1.27
N V 0.045 ––– 1.15 –––
CASE 221A–06 Z ––– 0.080 ––– 2.04
ISSUE Y

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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*MTP60N06HD/D*
8 ◊ Motorola TMOS Power MOSFET Transistor Device Data
MTP60N06HD/D