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 KAD RESEARCH LABORATORY

TECHNICAL REPORT

A Hand-held Electronic Still Camera and its Playback System

S. J. Sasson
A HAND-HELD ELECTRONIC STILL CAMERA AND ITS PLAYBACK SYSTEM

H-001478-WU
January 12, 1977
Author:

SJS/gl

S. J. Sasson
Applied Electronics Research

G. A. Lloyd, Supervisor
Applied Electronics Research

W. Feldman
Signed for Kodak Apparatus Division
Research Laboratory
 ABSTRACT

A hand-held camera is described which captures black and white

still pictures electronically and records them on an
inexpensive, audio grade (magnetic tape) cassette. The
cassette may he removed from the camera and inserted into a
playback unit for viewing on a television monitor.
 TABLE OF CONTENTS

INTRODUCTION...............................................1

RESULTS....................................................1

CONCLUSIONS................................................5

NEEDED DEVELOPMENTS........................................6

PATENT STATUS..............................................8

CAMERA DESCRIPTION.........................................8

PLAYBACK UNIT.............................................14

APPENDIX A................................................26

(Camera Construction)
Technical Report ---1

INTRODUCTION
The creation of a latent image in a phototsenstive emulsion by
exposure to a scene's reflected light has been the basis for
still photography from its inception. The second major required
step has been the development of the latent image in order to
make it visible. The job of the camera has been to hold the
film, to focus the scene onto the film and to provide a means
of controlling the exposure. The film is usually removed from
the camera for the development step. After development, the
pictures are stored in the form of prints or slides.

Trends in several areas of electronic technology have shown

that a practical alternative method of capturing and displaying
still pictures may be possible in the near future. In this
alternative camera, the scene would be imaged onto the surface
of a photosensitive integrated circuit that would convert the
optical image to an electronic signal pattern which would be
stored on magnetic tape. To view the image, the tape would be
played back on a unit which would convert the signal pattern to
a repeating television signal which could be sent to a TV
monitor for viewing.

In order to develop an understanding of this technology and to

demonstrate the feasibility of the concept, an electronic
camera and playback system was designed and built using 1975
technology.

RESULTS
The camera that was built is shown in Figure 1. It is
completely self-contained and is easily portable. The black and
white images are stored in a cassette (see Figure 1) which is
removable for playback on the playback unit shown in Figure 2.
The physical and performance characteristics are listed below.

Physical Characteristics

Size: 8¼" wide x 6" deep x 9" high

Weight: 8½ pounds
2
3
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Cassette: standard 300 foot Phillips digital cassette

Power source: sixteen size AA 450 ma-hr batteries
Image sensor: Fairchild type 201 100x100 CCD array
Digital Memory: Twelve 4096 bit dynamic memory chips
Control logic CMOS integrated circuitry

Optics: XL 55 movie camera optics, exposure control and

viewfinder.
Cassette Recorder: Memodyne low power digital cassette recorder.

Performance Characteristics

Exposure time: 50 msec

Minimum scene
brightness: 2 ft-lamberts
Digitization: 4 bits/pixel
Record time: 23 seconds to record one picture (2275 bits/sec)
Tape speed: 5¼ ips
Recording Density: 433 bits/in
No. of Pictures
per cassette: 30
Power consumption: 750 ma. peak (while recording)
Spectral response: 500 to 740 nm
Dynamic Range: 100:1

The playback unit, shown in Figure 2, has as its controlling element a

microcomputer. This computer brings the picture information into its
memory system and rearranges it to be compatible with the conventional
television format. The computer then enters a Direct Memory Access (DMA)
mode in which the information is repeatedly taken from the computer memory
and formed into a "National Television Standards Committee" (NTSC)
standard signal. It takes 30 seconds to read in one picture and to
rearrange the information for display. The picture can then be displayed
on the TV as long as desired with no degradation in picture quality.
Technical Report ---5

CONCLUSIONS
This electronic camera concept has several outstanding advantages for use
in still photography. Pictures are taken by the camera under existing
light conditions and viewed immediately on a television set without any
chemical processing steps. Unwanted pictures can be erased and the tape
reused. The desired pictures may be transferred to master magnetic tape,
film or video disk. The camera could be built without the need for
mechanical exposure control and shuttering mechanisms. These functions
could be implemented electronically.

The laboratory model of the electronic camera and playback unit

demonstrate within the limits of present technology what an
electronically-based, still photographic system would be like. The
construction and operation of this camera highlighted some of the major
problems that have to be solved before a system of this kind can be
practical as a consumer product.

The practical implementation of this system requires that a significant amount

of progress be made in the areas of charge coupled device (CCD) image
sensors, digital memory, integrated circuits and microcomputer technology. The
most significant needs are as follows: Higher resolution, broader spectral
response and increased dynamic range. A practical means of color
separation must be developed. Digital memory density and speed must be
increased and power requirements must be decreased. Microcomputers will have
to provide increased speed of operation. Material cost must be reduced in all
these areas.

These developments will be implemented, as they become available, into

future cameras being developed in KADRL as part of an ongoing effort in fully
electronic still photography.

THE CAMERA OF THE FUTURE

The camera described in this report represents a first attempt at
demonstrating a photographic system which may, with improvements in
technology, substantially impact the way pictures will be taken in the future. A
future camera for the consumer may be envisioned as a small device capable of
taking color pictures under very low light conditions. The pictures will be
stored in a magnetic medium on a nonvolatile solid state memory which will be
removable from the camera for playback. The picture will have a resolution at
least comparable to today's 110 film. Sound will be recorded along with the
image to aid in a picture's description. The picture, existing in electronic
Technical Report ---6
form, could be sent over conventional communication channels with little or no
modification. Infrared, as well as visible photography would be possible
with the same camera by changing optical filters. The pictures will be saved on
film, tape or video disk and the camera storage medium will be reused.

NEEDED DEVELOPMENTS
There is a great deal of effort being put into those areas of electronic
technology that will affect the future development of the electronic
camera. CCDs have been the subject of an intense development effort since
their invention in 1969. The 100 x 100 element imaging array was the largest
available in 1975. This 10,000 pixel resolution provides an inferior picture
when compared to a standard television scene which is represented by
approximately 215,000 pixels. A larger area array is presently available (RCA
SID 52501) with an active area made up of 320 x 512 elements. This array will
be utilized in the camera presently under development in this laboratory. The
spectral response of a CCD is closely related to the electroptical
properties of the semiconductor. The blue light response of the CCDs is poor
due to a high absorption of this portion of spectrum by the polysilicon
electrodes. The poor blue response makes the arrays available today unsuitable
for available light color imaging.1 Changes in device construction can improve
this characteristic.2 Improvements in the materials and processing involved
in the fabrication of CCDs will allow these devices to work at lower light
levels by reducing the shot noise of the dark current (the main component
of noise in uncooled devices used in low light imaging).3 Cooled operation of
CCD's results in improved low light performance and increased dynamic range.5
Technical Report ---7

The rate at which the camera electronics must process the picture
information is determined by the CCD scan rate. A slow scan rate will
allow inexpensive electronic circuits for processing data. For example,
the operation of the 512 x 320 element array can currently be varied from
1 picture every 33 msec to one every 10 seconds by cooling the device to -
6°C.4 This reduces the data rate from 6.1 MHz to l6 KHz. A slower rate
would require less bandwidth of the analog and digital circuitry allowing
the power consumption and the cost of the camera to be substantially
reduced.

A straightforward means of providing color separation is required. CCD's

used in color photography might be modified so that individual
photoelements were sensitive to either the red, green, or blue portions of
the spectrum. This would be accomplished by placing a grid of spectral
filters over the array. Work of this type is presently underway at KRL.

Digital memory is an important part of the camera and playback unit. MOS
integrated circuit technology has allowed memory bit density to double
every year since 1969. The l6K memory chip was made commercially available
in 1976, providing l6,384 bits of digital storage in one 1.6 pin DIP
package. A 64 K Bit chip is likely by 1980.6 The cost per bit has gone
from 2 cents in 1970 to .3 cents in 1974 and is expected to drop below .1
cent by 1979. MOS memory provides the fastest access speed at these high
densities. However, other technologies hold the promise of high densities
with lower speed. CCD technology has produced a 16K serial shift register
with a price of .013 cents per bit with an average latency time of 100
µsec (INTEL 24l6 CCD shift register). Future use of CCD's for digital
storage will be in the medium speed buffer memory because of the
inherently long access time due to the shift register nature of the
device. Magnetic bubble technology holds the promise of extremely dense
(10 to 10 bits/in) non-volatile digital storage.7,8 The first commercially
available devices will be introduced in 1977 (l00KHz shift rate).
Expectations are for data rates reaching 10MHz for future devices.7 The
relative simplicity required for their construction (only 1 masking step
for bubbles versus 5 for MOS memory) promises that magnetic bubbles will
offer a very low cost means of digital storage.

Microcomputer technology has matured to the point where fast (1

µsec/machine cycle) and powerful central processing units are commercially
available for under $20.00. The immediate future promises to produce a
host of sophisticated peripheral chips that will allow the manipulation of
digital data at a much lower cost than before. There is an unprecedented
Technical Report ---8
effort on the part of the electronics industry to develop microcomputer
technology and this effort is expected to continue as more applications
for this inexpensive computing power is found.

PATENT STATUS
An invention report covering the concept of an electronic still camera has
been written (202114) and a patent application is expected in the near
future. Texas Instruments has patented an electronic still picture system
(BP l440 791) of a similar type. The TI inventors project that their
concept will allow the consumer to take snapshots for less than .5 cent
per picture.

THE CAMERA
The electronic camera pictured in Figure 1 is diagramed in Figure 3 and
some of the operational timing waveforms are shown in Figure 4.

The sequence of events for taking a picture starts with the operator
framing the scene he wants to photograph in the viewfinder. The button for
making an exposure has two detents. When the first detent is reached, the
power is turned on in the camera, at which point the clocking circuits
begin to clock out information from one CCD. The CCD must be cleared of
the excess charge it contains after first being energized. This takes
about 2 seconds at the 200 KHz horizontal clocking frequency. Also, during
this initial interval, the exposure control stabilizes to a setting
determined by the ambient light level. Two seconds after the first detent
is reached, the button is pushed to the second detent causing a picture to
be taken.
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The control circuits monitor the clocking signals going to the CCD and
determine when the beginning of the next frame occurs. Then, the control
circuits gate the sample and hold circuit to capture each pixel output from
the CCD (Figure 5). This extends the amount of time each pixel is available
for processing from 2.5 µsec to 5 µsec. The analog to digital (A/D)
converter using a successive approximation technique, converts the analog
voltage level to a 4 bit digital word 2.5 µsec after the control circuits
give a start of conversion signal. The 4 bit word is latched by the end of
conversion signal (EOC) coming from the A/D converter. The 4 bit word is
now available to the buffer memory for a full 5 µsec.

The word is written into memory immediately after the EOC signal is
received by the memory control circuits. The EOC is also used to advance
the address counter to point to the next 4 bit word memory location. The
write cycle takes 2.5 µsec to complete and begins following an EOC signal
unless a refresh memory cycle is being executed. Since the buffer memory is
dynamic, it must be refreshed periodically. This refresh operation, which
takes 2.5 µsec, occurs once every l6 µsec. Since the refresh operation is
controlled by a separate clock, the refresh request signal, coming from the
refresh control circuit, is asynchronous with the EOC signals from the A/D
converter. Therefore, the longest the digital word must be present on the
latch is one refresh cycle time (2.5 µsec), and one write cycle time (2.5
µsec) or 5 µsec.
Technical Report ---12

The camera control circuits will detect when the CCD has transferred out
the last pixel of the desired picture. At this point, the picture has been
captured and resides in the buffer memory as 10,000 4 bit digital words
arranged in sequence from the top of field 1 to the bottom of field 2.

The camera control circuit now is ready to record the contents of the
buffer memory onto the cassette tape. At this point, the Read/Write line
to the memory control circuit goes high. The recording sequence is
initiated by a signal from the tape deck motor speed control circuit which
occurs after the motor has achieved steady state speed.

The motor in the tape deck is a stepping motor whose speed is determined
by the clocking signal applied to it. In order to record the picture onto
the tape in the shortest time possible, the tape must be moving at as high
a speed as possible. This speed is 5¼ inches per second, corresponding to
a motor stepping rate of 625Hz. In order to reach this speed, the motor
begins at a lower speed of 2½. inches per second (300Hz) and ramps up to
the final speed over a period of approximately ½ second. The increase of
the motor clock frequency begins as the camera first begins to capture a
picture (when second detent on button is reached). The signal which
indicates achievement of steady state speed causes the first word in the
buffer memory to appear in parallel at the memory's output. This word is
converted into a serial bit stream by the tape control circuit. The serial
bits are sent to the recording circuit at a rate determined by the tape
clock (2275 Hz). The 4 bits followed by a synchronization bit are recorded
on the cassette tape using a 2-track Non-Return to Zero Intermediate
(NRZI) format. A flux reversal on track 1 is a logic 1 and a flux reversal
on track 2 is a logic zero. Therefore, the two tracks together carry the
tape clock rate information. A flux reversal appearing on both tracks
simultaneously is a synchronization bit. After each synchronization bit is
recorded, the tape control circuit generates a request for the next word
from the buffer memory. The tape control circuit waits until the next 4
bit word appears on the memory's data lines and then records it in exactly
the same
Technical Report ---13

as
Technical Report ---14
manner as the first word. This process repeats until the memory control
section detects an address of 10,002 which indicates that the entire
picture has been recorded. The recording process takes about 23 seconds.
The camera power is then turned off by a signal from the memory control
circuit. The camera is now ready to take another picture.

PLAYBACK UNIT

Since a microcomputer controls the playback unit a flow chart describes its
operation (Figure 6). The computer (a Motorola Mc6800) incorporated into an
EXORciser development system, begins its data acquisition from the tape by
responding to a restart command from the front panel of the EXORciser
system. The tape deck is turned on and ramped up to a speed of 600Hz in
much the same manner that the deck in the camera was started. The computer
looks at the output from the two tape tracks (Figure 7). If one of the two
lines has a flux reversal, a one or a zero, as appropriate, is put in a
known bit position. If both lines have flux reversals (the synchronization
signal) the 4 bit word just assembled from the tape is put into the
computer's memory buffer. In this manner, the 50,000 serial bits on the
tape are assembled into 10,000 4 bit words and arranged sequentially in
memory. This is done under the control of a program called TAPEIN whose
listing appears in Figure 8. If the computer, during the execution of
TAPEIN, fails to see a rising edge of the tape clock for a period of time
exceeding 30 msec and the computer buffer has not been filled beyond 8000
words, the buffer is eased and filled starting at location zero with the
next set of data read from the type. In this way gaps between pictures can
be recognized and random noise recorded on the tape during start up are
ignored. The tape deck motor is shut off after the picture is in the
memory.
Technical Report ---15

The picture is
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originally arranged with CCD field 1 starting at location 0000 and ending
5000 words later at address 138l (HEX). CCD field 2, also 5000 words long,
begins here and ends at 2710 (HEX). These 100 lines must be used to fill
400 interlaced lines on a television monitor. This is accomplished by
rearranging the lines in memory so that the first line of the CCD
information is available to fill the first lines of each field on the
monitor. The first line in the second field is then available to fill the
next two lines of each field the monitor, etc. This rearrangement is
accomplished by a program called INTLAC whose listing is shown in Figure
9.

With the picture suitably arranged in memory, the computer automatically

goes to a Direct Memory Access mode (DMA) of operation in which the
central processing unit (CPU) releases control of the computer memory bus.
A set of DMA circuits now begins to present the picture to the TV monitor.

The 400 lines fill a little over 80% of the screen in the vertical
direction. The presentation in the horizontal direction is sized so that
the aspect ratio of the image is correct.

The DMA board (Figure 10) has two independent banks of fast bipolar RAM.
While a line of the picture (100 4 bit words) is being read from the
computer memory buffer into one of the fast RAM banks, the other will be
reading out its contents to the TV at a rate of 1 pixel per 430 msec. The
line is read out twice allowing 126 µsec for the other bank to be filled
with its line of information The 100 words are brought to this fast buffer
from the computer memory in 86.8 µsec. This insures that one buffer is
always filled before the other has finished presenting its line of
information twice. The roles are then reversed with the new line being
sent out to the TV and the other buffer being filled with a line of
information. This process repeats until the end of monitor field 1, when
the computer address counters are reset and the picture is repeated for
monitor field 2. Exactly the same information is sent out during each
field.

The D/A converter output is combined with video timing waveforms to

produce a composite video signal which can be applied to a TV monitor. The
presentation can be continued indefinitely with no degradation of the
image.
Technical Report ---20
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To display the next picture on the tape, the computer is given a restart
command and the previously described sequences begin again. Each picture
replaces the previous one in the computer buffer memory.

Figure 11 shows the television display of a picture taken by the

electronic camera of the back-lit transparency shown at the left. The
contouring of the background is due to representing the picture with only
4 bits (l6 gray levels). The white specks appearing on the boy's face
result from certain photosites having a much greater dark current than the
rest of the photosites.
Technical Report ---26

APPENDIX A

CAMERA CONSTRUCTION
The camera was constructed so as to allow easy disassembly while also
allowing portability. The camera is shown partially disassembled in Figure
12. The circuits used for the implementation of the functional blocks
shown in Figure 3. were built on 5 circuit boards in the camera body and 2
in the camera head (see Figure 12). The design of the blocks shown in
Figure 3. will be described.

BOARD 1
CCD - (Figure A1)

The Fairchild CCD 201 area array was placed in the film plane of an
optical assembly from an XL55 movie camera. The active area of the
CCD(ll9.6 mils vertical, 159.1 horizontal) easily fits in the window
provided for the super 8 format (165.3 mils vertical, 248.2 mils
horizontal). Immediately in front of the CCD, an infrared filter was
placed to restrict the systems response only to light of a wavelength less
than 800 nm. The differential amplifier, constructed on a small board
behind the rest of the circuits shown in Figure Al, eliminates some of the
clocking noise while providing some voltage gain to the signal. The output
is connected to the sample and hold circuit which gives an output voltage
of 0 volts for no light and 2 volts for saturation.

BOARD 1
CCD clocking circuits (Figure A2)

These circuits generate the appropriate timing waveforms to be applied to

the CCD for proper operation (Figure A3). The main clock is set to give a
horizontal clocking frequency of 200 KHz. The clocking waveforms are sent
to level shifting driver circuits located on the power supply board to
make the high and low levels of the clocks compatible with the particular
CCD.
Technical Report ---27
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Camera Control

The rising edge of So indicates the start of field one and is used to
start picture acquisition. Qvl and Qv2. determine the start of each line of
information. This circuit ignores the first line of data from each field,
the first horizontal period and the last 4 horizontal periods from each
line. These time periods contain no valid picture data. Qn is used also by
these circuits to synchronize the sample and hold with each pixel voltage
at the output of the CCD.

Signals Rl and R2 indicate the state of the camera. After the first detent
has been reached on the switch (SWl) and before the 2nd detent (SW2) both
Rl and R2 are high. This resets most of the circuits in the camera to an
initial setting. The 2nd detent (SW2 high) causes Rl to go low and R2 to
go high. This indicates to the camera that the picture is being read from
the CCD to the memory. This state lasts for 50 milliseconds. After the
picture is placed in memory, the camera control circuits drive Rl high and
R2 low to start the recording of the picture data onto the tape. When the
motor clock reaches final speed, recording will begin.

BOARD 3
A/D Converter (Figure A4)

A series of monostable multivibrators create the sample and hold control

pulse, the delay for settling and the start conversion pulse for the A/D
Converter.

The A/D converter is a successive approximation type with 4 bit

resolution. It was constructed using a CMOS successive approximation
register, a 6 bit D/A converter and a comparator. The conversion will
start from zero to 500 nsec after the start conversion pulse is received
and the EOC appears 2 µsec later. The rising edge of the EOC signal is
converted into a pulse which latches the 4 bits and creates a Write
Request signal to the memory control logic.

Tape Control Circuits

The Transmit Buffer Register Load (TBRL) signal comes from the memory
control logic when the s bits coming from the memory are stable and is
used to latch these bits into a parallel-to-serial converter. The tape

clock begins to clock out these bits at 2275 bits/sec. The synchronization
bit is generated and sent after the fourth bit and a Read Request is sent
to the memory control logic for the next word.
Technical Report ---33
Motor Clock

The motor clock is started, by the exclusive-or between Rl and R2. When it
reaches final running speed, a Schmitt. trigger circuit is activated and
gives the first Read Request signal to the memory control logic for the
first word to be recorded.

BOARD 4
Memory Control (Figure A5)

The transitions of Rl are used to reset the memory address counters to

zero. Rl is also used to determine whether the memory request signal is
for a Read or Write operation (low is Write, high is Read). The memory
requests and refresh requests are latched and operated on by the memory
request having the highest priority. The appropriate waveforms are applied
to the memory circuits (board 5) to accomplish the actual Read or Write
operation.

The End of Recording signal is generated by monitoring the address of the

memory. When it reaches 10,002 a signal is generated which is sent to the
power supply board to shut off the camera power.

Refresh Control These circuits contain the address counters for the
refreshing operation. Every 16 µsec a Refresh request is generated and the
Refresh address counters are incremented. This is constantly repeated
through the 32 subdivisions in the memory that need to be refreshed.

BOARD 5

This board contains 12 4K dynamic memory chips (Motorola 6605).

Technical Report ---34
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BOARD 6
Power Supply Board (Figure A6)

The camera is powered from size AA 450 ma-hr nickel-cadmium batteries

wired in series to give a positive 19.2 volt supply. An inverter circuit
creates a -19.2 volt supply capable of an output current of 100 ma.
Regulators produces +15, +12, and +5 volt supplies from the +19.2 volts
and -12 and -5 volt supplies from the -19.2 volt inverter output.

This board also contains the driver/level shifting transistors for the CCD
voltages. Each one of these CCD voltages must be adjustable so that the
best performance can be obtained from any CCD 201 used in the camera.
Technical Report ---36
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R E F E R E N C E S

(1) J. R. Horak, "Color Sensitivity of Charge-Coupled Imaging Devices,'

Technical Memorandum #62672, Eastman Kodak Co., Kodak Research
Laboratories, May 1975.
(2) "High Performance Image Density with Charge-Coupled Devices," G. F.
Amelio, L. Walsh and R. H. Dyck, Fairchild Semiconductor
(3) "Charge Transfer Devices," C. H. Sequin and M. F. Tompsett, Bell
Laboratories, Academic Pres. IMC.
(4) "Cooled Slow Scan Performance of a 512 x 320 Element Charge-Coupled
Image., R. L. RodgerIII and D. L. Giorachino, RCA Corp.
(5) "Low Light Level Performance of the CCD-201," R. H. Dych and M. D.
Jack, Fairchild Semiconductor.
(6) "A Review and Projection of Semiconductor Components for Digital
Storage. D. Hodges, Proceedings I.E.E.E., Vol 63, No.8; Aug. 1975.
(7) "Magnetic Bubble Technology Integrated-Circuit Magnetics for Digital
Storage and Processing." Edited by HSU Chang, I.E.E.E. Press, p 217.
(8) "Bubbles Rise from the Lab," E. A. Torrero, I.E.E.E. Spectrum, Sept.
1976
Technical Report ---38
D I S T R I B U T I O N

C. R. Adler
C. Altmann
D. E. Beach
R. P. Crandall/E. V. Ince
P. J. Dygert/B. S. Bonino
D. J. DeMarle/J. L. Bachman
E. A. Edwards/P. L. Dillon
B. L. Elle
W. Feldman/G. A. Lloyd
W. H. Haynie
M. L. Kerney
J. L. Quigley
R. J. Roman/R. A. Spaulding
S. J. Sasson
J. M. Streh
R. S. VanHeyningen
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KADRL Library
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