Ina 823

INA823
SBOSA75B – JULY 2021 – REVISED NOVEMBER 2021
INA823 Precision, Low-Power, Wide-Supply (2.7-V to 36-V) Instrumentation Amplifier
1 Features 3 Description
• Input overvoltage protection up to ±60 V The INA823 is an integrated instrumentation amplifier
• Input voltage extends 150 mV below negative that offers low power consumption and operates
supply over a wide, single-supply or dual-supply range.
• Low power supply current: 180 µA (typ) A single external resistor sets any gain from 1
• Precision performance: to 10,000. The device provides low input offset
– Low offset voltage: 20 µV (typ), 100 µV (max) voltage, low offset voltage drift, low input bias
– Low input bias current: 8nA (max) current, and low current noise while remaining
– Common-mode rejection: cost-effective. Additional circuitry protects the inputs
• 84 dB, G = 1 (min) against overvoltage up to ±60 V.
• 104 dB, G = 10 (min) The INA823 is optimized to provide a high common-
• 120 dB, G ≥ 100 (min) mode rejection ratio. At G = 1, the common-mode
– Power supply rejection: 100 dB, G = 1 (min) rejection ratio exceeds 84 dB across the full input
• Input voltage noise: 21 nV/√Hz common-mode range. The INA823 has a wide
• Bandwidth: 1.9 MHz (G = 1), 60 kHz (G = 100) common-mode voltage range as low as 150-mV
• Stable with 1-nF capacitive loads below negative supply. The device is designed for
• Supply range: low-voltage operation from a 2.7-V single supply, and
– Single-supply: 2.7 V to 36 V dual supplies up to ±18 V. The low power and single
– Dual-supply: ±1.35 V to ±18 V supply operation enable hand-held, battery-operated
• Specified temperature range: –40°C to +125°C systems.
• Packages: 8-pin SOIC and 8-pin VSSOP
Device Information
2 Applications PART NUMBER PACKAGE(1) BODY SIZE (NOM)
• Flow transmitter SOIC (8) 4.90 mm × 3.91 mm
INA823
• Wearable fitness and activity monitor VSSOP (8) 3.00 mm x 3.00 mm
• Infusion pump
(1) For all available packages, see the package option
• Blood glucose monitor addendum at the end of the data sheet.
• Electrocardiogram (ECG)
• Surgical equipment
• Weigh scale
• Analog input module
• Process analytics (pH, gas, concentration, force
and humidity)
• Battery test
7
+VS
2 IN Overvoltage
+ 50 k 50 k
Protection
1 RG
–
50 k –
6
50 k + OUT
8 RG
–
REF 5
50 k 50 k
3 +IN Overvoltage +
Protection
VS
4
INA823 Simplified Internal Schematic
Typical Distribution of
Input Stage Offset Voltage Drift
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA823
SBOSA75B – JULY 2021 – REVISED NOVEMBER 2021 www.ti.com
Table of Contents
1 Features............................................................................1 9 Application and Implementation.................................. 23
2 Applications..................................................................... 1 9.1 Application Information............................................. 23
3 Description.......................................................................1 9.2 Typical Applications.................................................. 24
4 Revision History.............................................................. 2 10 Power Supply Recommendations..............................29
5 Device Comparison Table...............................................3 11 Layout........................................................................... 29
6 Pin Configuration and Functions...................................3 11.1 Layout Guidelines................................................... 29
7 Specifications.................................................................. 4 11.2 Layout Example...................................................... 30
7.1 Absolute Maximum Ratings........................................ 4 12 Device and Documentation Support..........................31
7.2 ESD Ratings .............................................................. 4 12.1 Device Support....................................................... 31
7.3 Recommended Operating Conditions.........................4 12.2 Documentation Support.......................................... 31
7.4 Thermal Information....................................................4 12.3 Receiving Notification of Documentation Updates..31
7.5 Electrical Characteristics.............................................5 12.4 Support Resources................................................. 31
7.6 Typical Characteristics................................................ 7 12.5 Trademarks............................................................. 31
8 Detailed Description......................................................19 12.6 Electrostatic Discharge Caution..............................31
8.1 Overview................................................................... 19 12.7 Glossary..................................................................31
8.2 Functional Block Diagram......................................... 19 13 Mechanical, Packaging, and Orderable
8.3 Feature Description...................................................20 Information.................................................................... 31
8.4 Device Functional Modes..........................................22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2019) to Revision B (November 2021) Page
• Changed device from advanced information (preview) to production data (active) ...........................................1
2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: INA823

INA823
www.ti.com SBOSA75B – JULY 2021 – REVISED NOVEMBER 2021
5 Device Comparison Table

DEVICE DESCRIPTION GAIN EQUATION RG AT PINS
1-nV/√Hz Noise, 35-µV Offset, 0.4 µV/°C VOS Drift, 28-MHz Bandwidth,
INA849 G = 1 + 6 kΩ / RG 2, 3
Precision Instrumentation Amplifier
35-µV Offset, 0.4 µV/°C VOS Drift, 7-nV/√Hz Noise, High-Bandwidth,
INA821 G = 1 + 49.4 kΩ / RG 2, 3
35-µV Offset, 0.4 µV/°C VOS Drift, 8-nV/√Hz Noise, Low-Power,
INA819 G = 1 + 50 kΩ / RG 2, 3
200-μA Supply Current, 3-V to 36-V Supply Instrumentation Amplifier
INA826 G = 1 + 49.4 kΩ / RG 2, 3
With Rail-to-Rail Output
INA818 G = 1 + 50 kΩ / RG 1, 8
INA828 G = 1 + 50 kΩ / RG 1, 8
25-µV VOS, 0.1 µV/°C VOS Drift, 1.8-V to 5-V, RRO, 50-µA IQ, Chopper-
INA333 G = 1 + 100 kΩ / RG 1, 8
Stabilized INA
1/8 V/V to 128 V/V Programmable Gain Instrumentation Amplifier With
PGA280 Digital programmable N/A
3-V or 5-V Differential Output; Analog Supply up to ±18 V
INA159 G = 0.2 V Differential Amplifier for ±10-V to 3-V and 5-V Conversion G = 0.2 V/V N/A
PGA112 Precision Programmable Gain Op Amp With SPI Digital programmable N/A
6 Pin Configuration and Functions
RG 1 8 RG
–IN 2 7 +VS
+IN 3 6 OUT
–VS 4 5 REF
Not to scale
Figure 6-1. D (8-Pin SOIC) and DGK (8-Pin VSSOP) Packages, Top View
Table 6-1. Pin Functions

PIN
TYPE DESCRIPTION
NAME NO.
–IN 2 Input Negative (inverting) input
+IN 3 Input Positive (noninverting) input
OUT 6 Output Output
REF 5 Input Reference input. This pin must be driven by a low impedance source.
RG 1, 8 — Gain setting pin. Place a gain resistor between pin 1 and pin 8.
–VS 4 Power Negative supply
+VS 7 Power Positive supply
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3

INA823
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Dual supply, VS = (+VS) – (–VS) ± 20
VS –VS, +VS pins voltage V
Single supply, VS = (+VS) 40
IN pins voltage (–VS) – 60 (+VS) + 60 V
RG, REF, OUT pins voltage (–VS) – 0.5 (+VS) + 0.5 V
RG pins current –10 10 mA
OUT pin current –50 50 mA
ISC Output short-circuit current(2) Continuous
TA Operating temperature –50 150 °C
TJ Junction temperature 175 °C
Tstg Storage temperature –65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Short-circuit to VS / 2.
7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Single supply, VS = (+VS) 2.7 36
VS Supply voltage V
Dual supply, VS = (+VS) – (–VS) ±1.35 ±18
TA Specified temperature –40 125 °C
7.4 Thermal Information

INA823
THERMAL METRIC(1) D (SOIC) DGK (VSSOP) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 126.7 167.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 67.0 60.3 °C/W
RθJB Junction-to-board thermal resistance 70.1 88.7 °C/W
ψJT Junction-to-top characterization parameter 18.6 7.9 °C/W
ψJB Junction-to-board characterization parameter 69.4 87.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

INA823
7.5 Electrical Characteristics

at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
20 100
µV
VOSI Input stage offset voltage(1) (3) 190
TA = –40°C to +125°C(2)
0.2 1.2 µV/°C
140 450
µV
VOSO Output stage offset voltage(1) (3) 850
TA = –40°C to +125°C(2)
1 5 µV/°C
G = 1, RTI 100 130
G = 10, RTI 115 148
PSRR Power-supply rejection ratio VS = ±1.35 V to ±18 V dB
G = 100, RTI 120 148
G = 1000, RTI 120 148
ZIN Input impedance 12 || 8.5 GΩ || pF
RFI filter, –3-dB frequency 20 MHz
(–VS) – 0.15 (+VS) – 1
VCM Operating input voltage(4) VS = ±1.35 V to ±18 V V
TA = –40°C to +125°C See Figure 7-53
Input overvoltage TA = –40°C to +125°C(2) ±60 V
At dc to 60 Hz, RTI, VCM = (V–) –0.15 V to (V+) – 1 V,
84 110
G=1
CMRR Common-mode rejection ratio 104 136 dB
G = 10
120 149
G ≥ 100
BIAS CURRENT
1.2 8
nA
IB Input bias current 2.4
TA = –40°C to +125°C
15 pA/°C
0.4 4
nA
IOS Input offset current 0.8
TA = –40°C to +125°C
4 pA/°C
NOISE VOLTAGE
Input stage voltage noise
f = 1 kHz, G = 1000, RS = 0 Ω 21 nV/√Hz
eNI density(6)
Input stage voltage noise(6) fB = 0.1 Hz to 10 Hz, G = 1000, RS = 0 Ω 0.4 µVPP
Output stage voltage noise
f = 1 kHz, RS = 0 Ω 120 nV/√Hz
eNO density(6)
Output stage voltage noise(6) fB = 0.1 Hz to 10 Hz, RS = 0 Ω 5 µVPP
Current noise density f = 1 kHz 160 fA/√Hz
in
Current noise fB = 0.1 Hz to 10 Hz, G = 100 5 pAPP

INA823
7.5 Electrical Characteristics (continued)

at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GAIN
Gain equation 1 + (100 kΩ / RG) V/V
G Gain 1 10000 V/V
G=1 ±0.01 ±0.04
G = 10 ±0.025 ±0.2
GE Gain error(5) VO = ±10 V %
G = 100 ±0.025 ±0.2
G = 1000 ±0.05 ±0.2
G=1 ±0.2 ±5
Gain drift(5) TA = –40°C to +125°C ppm/°C
G>1 ±12 ±35
G = 1 to 10 2 10
Gain nonlinearity G > 10 5 ppm
G = 1 to 100, RL = 2 kΩ 15
OUTPUT
Output voltage swing (–VS) + 0.15 (+VS) – 0.15 V
Load capacitance Stable operation 1000 pF
ZOUT Closed-loop output impedance See Figure 7-37 Ω
ISC Short-circuit current Continuous to VS / 2 ±20 mA
FREQUENCY RESPONSE
G=1 1.9 MHz
G = 10 350
BW Bandwidth, –3 dB
G = 100 60 kHz
G = 1000 6
SR Slew rate G = 1, VO = ±10 V 0.9 V/µs
G = 1 to 10, VSTEP = 10 V 12
To 0.01% G = 100, VSTEP = 10 V 28
G = 1000, VSTEP = 10 V 260
tS Settling time µs
G = 1 to 10, VSTEP = 10 V 14
To 0.001% G = 100, VSTEP = 10 V 33
G = 1000, VSTEP = 10 V 290
REFERENCE INPUT
RIN Input impedance 100 kΩ
Reference input voltage (–VS) (+VS) V
Gain to output 1 V/V
Reference gain error inside the output voltage swing 0.01 0.05 %
POWER SUPPLY
180 250
IQ Quiescent current VIN = 0 V µA
TA = –40°C to +125°C 300
(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).

(2) Specified by characterization.
(3) Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔVOS(RTI) = √[ΔVOSI 2 + (ΔVOSO / G)2].
(4) Input voltage range of the instrumentation amplifier input stage. The input range depends on the common-mode voltage, differential
voltage, gain, and reference voltage. See Typical Characteristic curves for more information.
(5) The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
(6) Total RTI voltage noise is equal to: eN(RTI) = √[eNI 2 + (eNO / G)2].

INA823
7.6 Typical Characteristics

at TA = 25°C, VS = ±15 V, RL = 10 kΩ, CL = 0 pF, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)
Table 7-1. Table of Graphs

FIGURE TITLE FIGURE NUMBER
Typical Distribution Graphs
Typical Distribution of Input Stage Offset Voltage Figure 7-1
Typical Distribution of Input Stage Offset Voltage Drift Figure 7-2
Typical Distribution of Output Stage Offset Voltage Figure 7-3
Typical Distribution of Output Stage Offset Voltage Drift Figure 7-4
Typical Distribution of Inverting Input Bias Current Figure 7-5
Typical Distribution of Noninverting Input Bias Current Figure 7-6
Typical Distribution of Input Offset Current Figure 7-7
Typical CMRR Distribution, G = 1 Figure 7-8
Typical CMRR Distribution, G = 10 Figure 7-9
Typical Gain Error Distribution Figure 7-10
vs Temperature Graphs
Input Stage Offset Voltage vs Temperature Figure 7-11
Output Stage Offset Voltage vs Temperature Figure 7-12
Input Bias Current vs Temperature Figure 7-13
Input Offset Current vs Temperature Figure 7-14
CMRR vs Temperature, G = 1 Figure 7-15
CMRR vs Temperature, G = 10 Figure 7-16
Gain Error vs Temperature, G = 1 Figure 7-17
Gain Error vs Temperature, G = 100 Figure 7-18
Supply Current vs Temperature Figure 7-19
AC Performance Graphs
Closed-Loop Gain vs Frequency Figure 7-20
CMRR vs Frequency (RTI) Figure 7-21
CMRR vs Frequency (RTI, 1-kΩ source imbalance) Figure 7-22
Positive PSRR vs Frequency (RTI) Figure 7-23
Negative PSRR vs Frequency (RTI) Figure 7-24
Voltage Noise Spectral Density vs Frequency (RTI) Figure 7-25
Current Noise Spectral Density vs Frequency (RTI) Figure 7-26
0.1-Hz to 10-Hz RTI Voltage Noise Figure 7-27
0.1-Hz to 10-Hz RTI Voltage Noise, G = 1000 Figure 7-28
Small-Signal Response, G = 1 Figure 7-29
Overshoot vs Capacitive Loads Figure 7-33
Large-Signal Step Response Figure 7-34
Settling Time vs Step Size Figure 7-35
Large-Signal Frequency Response Figure 7-36
Closed-Loop Output Impedance vs Frequency Figure 7-37

INA823

Table 7-1. Table of Graphs (continued)

FIGURE TITLE FIGURE NUMBER
Input and Output Voltage Graphs
Input Current vs Input Overvoltage Figure 7-38
Gain Nonlinearity, G = 1 Figure 7-39
Positive Input Bias Current vs Common‑Mode Voltage (VS–) Figure 7-43
Positive Input Bias Current vs Common‑Mode Voltage (VS+) Figure 7-44
Negative Input Bias Current vs Common‑Mode Voltage (VS–) Figure 7-45
Negative Input Bias Current vs Common‑Mode Voltage (VS+) Figure 7-46
Offset Voltage vs Common-Mode Voltage, VS = 30 V Figure 7-47
Offset Voltage vs Common-Mode Voltage, VS = 2.7 V Figure 7-48
Positive Output Voltage Swing vs Output Current, VS = 30 V Figure 7-49
Negative Output Voltage Swing vs Output Current, VS = 30 V Figure 7-50
Positive Output Voltage Swing vs Output Current, VS = 2.7 V Figure 7-51
Negative Output Voltage Swing vs Output Current, VS = 2.7 V Figure 7-52
Input Common-Mode Voltage vs Output Voltage, VS = 2.7 V, G = 1 Figure 7-53
Input Common-Mode Voltage vs Output Voltage, VS = 2.7 V, G = 1 Figure 7-54
Input Common-Mode Voltage vs Output Voltage, VS = 5 V, G = 1 Figure 7-55
Input Common-Mode Voltage vs Output Voltage, VS = 5 V, G = 100 Figure 7-56
Input Common-Mode Voltage vs Output Voltage, VS = 24 V and VS = 30 V, G = 1 Figure 7-57
Input Common-Mode Voltage vs Output Voltage, VS = 24 V and VS = 30 V, G = 10 Figure 7-58

INA823

N = 1225 Mean = 3.63 μV Std Dev = 18.0 μV N = 30 Mean = –0.024 μV/ºC Std Dev = 0.177 μV//ºC
Figure 7-1. Typical Distribution of Input Stage Offset Voltage Figure 7-2. Typical Distribution of Input Stage Offset Voltage
Drift
N = 1225 Mean = 48.0 μV Std Dev = 92.4 μV N = 30 Mean = 0.17 μV/ºC Std Dev = 0.795 μV/ºC
Figure 7-3. Typical Distribution of Output Stage Offset Voltage Figure 7-4. Typical Distribution of Output Stage Offset Voltage
Drift
30 30
20 20
Amplifiers (%)
Amplifiers (%)
10 10
0 0
-2 -1 0 1 2 3 4 5 -2 -1 0 1 2 3 4 5
Input Bias Current (nA) Input Bias Current (nA)
N = 1200 Mean = 1.21 nA Std Dev = 0.384 nA N = 1200 Mean = 1.11 nA Std Dev = 0.368 nA
Figure 7-5. Typical Distribution of Inverting Input Bias Current Figure 7-6. Typical Distribution of Noninverting Input Bias
Current

INA823
7.6 Typical Characteristics (continued)

30
20
Amplifiers (%)
10
0
-2 -1 0 1 2
Input Offset Current (nA)
N = 1170 Mean = –0.092 nA Std Dev = 0.35 nA N = 1225 Mean = –0.22 μV/V Std Dev = 6.95 μV/V
Figure 7-7. Typical Distribution of Input Offset Current Figure 7-8. Typical CMRR Distribution
15
10
Amplifiers (%)
0
-0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2
Gain Error (%)
N = 1225 Mean = –0.0599 μV/V Std. Dev = 0.710 μV/V N = 550 Mean = –0.0334 % Std. Dev = 0.0433 %
G = 10 G = 10
Figure 7-9. Typical CMRR Distribution Figure 7-10. Typical Gain Error Distribution
100 1000
80 800
Input-Referred Offset Voltage ( V)
Output Stage Offset Voltage ( V)
60 600
40 400
20 200
0 0
-20 -200
-40 -400
-60 Mean -600 Mean
-80 +3 -800 +3
-3 -3
-100 -1000
-60 -40 -20 0 20 40 60 80 100 120 140 -50 -25 0 25 50 75 100 125 150
Temperature ( C) Temperature ( C)
Figure 7-11. Input Stage Offset Voltage vs Temperature Figure 7-12. Output Stage Offset Voltage vs Temperature

INA823

4.5 2
4
1.5
3.5
1
Input Offset Current (nA)

3
Input Bias Current (nA)
2.5 0.5
2
1.5 0
1 -0.5
0.5
0 -1
-0.5 -1.5
-1 Mean Mean
+3 -2 +3
-1.5 -3 -3
-2 -2.5
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Figure 7-13. Input Bias Current vs Temperature Figure 7-14. Input Offset Current vs Temperature
140 160
Unit 1 Unit 1
Common-Mode Rejection Ratio (dB)

Unit 2 Unit 2
Unit 3 Unit 3
130 Unit 4 150 Unit 4
Unit 5 Unit 5
120 140
110 130
100 120
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
G=1 G = 10
Figure 7-15. CMRR vs Temperature Figure 7-16. CMRR vs Temperature
0.03 0.4
0.02 0.3
Normalized Gain Error (%)
Normalized Gain Error (%)
0.01 0.2
0 0.1
-0.01 0
-0.02 -0.1
-0.03 -0.2
Mean Mean
-0.04 +3 -0.3 +3
-3 -3
-0.05 -0.4
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
G=1 Average of 120 units Normalized at +25°C G = 100 Average of 120 units Normalized at +25°C
Figure 7-17. Gain Error vs Temperature Figure 7-18. Gain Error vs Temperature

INA823

240 80
G=1
230 70
G = 10
220 60 G = 100
G = 1000
50
Supply Current (A)
210
40
200
Gain (dB)
30
190
20
180
10
170 0
160 -10
150 VS =  2.7 V -20
VS =  15 V
140 -30
-50 -30 -10 10 30 50 70 90 110 130 150 10 100 1k 10k 100k 1M
Temperature (C) Frequency (Hz)
Figure 7-19. Supply Current vs Temperature Figure 7-20. Closed-Loop Gain vs Frequency
160 160
G=1 G=1

140 G = 10 140 G = 10
G = 100 G = 100
120 120 G = 1000
100 100
80 80
60 60
40 40
20 20
0 0
1 10 100 1k 10k 100k 1 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)
Figure 7-21. CMRR vs Frequency (RTI) Figure 7-22. CMRR vs Frequency (RTI, 1-kΩ source imbalance)
160 160
Negative Power Supply Rejection Ratio (dB)
Positive Power Supply Rejection Ratio (dB)
140 140
120 120
100 100
80 80
60 60
40 G=1 40 G=1
G = 10 G = 10
20 G = 100 20 G = 100
G = 1000 G = 1000
0 0
100m 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k
Figure 7-23. Positive PSRR vs Frequency (RTI) Figure 7-24. Negative PSRR vs Frequency (RTI)

INA823

1000 1000
Spectral Density (nV/ Hz)
Spectral Density (fA/ Hz)

100
Voltage Noise
Current Noise
10
1 G=1
G = 10
G = 100
G = 1000
0.1 100
100m 1 10 100 1k 10k 100k 100m 1 10 100 1k 10k
Figure 7-25. Voltage Noise Spectral Density vs Frequency (RTI) Figure 7-26. Current Noise Spectral Density vs Frequency (RTI)
Figure 7-27. 0.1-Hz to 10-Hz RTI Voltage Noise Figure 7-28. 0.1-Hz to 10-Hz RTI Voltage Noise
100 100
80 80
60 60
Output Amlitude (mV)
40 40
20 20
0 0
-20 -20
-40 -40
-60 -60
-80 -80
-100 -100
0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
Time ( s) Time ( s)
G=1 RL = 10 kΩ CL = 100 pF G = 10 RL = 10 kΩ CL = 100 pF
Figure 7-29. Small-Signal Response Figure 7-30. Small-Signal Response

INA823

100 100
80 80
60 60

40 40
20 20
0 0
-20 -20
-40 -40
-60 -60
-80 -80
-100 -100
0 10 20 30 40 50 60 70 80 90 100 0 100 200 300 400 500 600 700 800 900 1000
Time ( s) Time ( s)
G = 100 RL = 10 kΩ CL = 100 pF G = 1000 RL = 10 kΩ CL = 100 pF
Figure 7-31. Small-Signal Response Figure 7-32. Small-Signal Response
12
G=1
9 G = 10
G = 100
6 G = 1000
Output Amlitude (V)
-3
-6
-9
-12
0 100 200 300 400 500 600 700 800 900 1000
Time ( s)
Figure 7-33. Overshoot vs Capacitive Loads Figure 7-34. Large-Signal Step Response
39 20
0.01% VS = 15 V
36 0.001% 18 VS = 2.7 V
33 16
Output Amplitude (V)
30 14
Settling Time (µs)
27 12
24 10
21 8
18 6
15 4
12 2
9 0
2 4 6 8 10 12 14 16 18 20 100 1k 10k 100k 1M
Step Size (V) Frequency (Hz)
Figure 7-35. Settling Time vs Step Size Figure 7-36. Large-Signal Frequency Response

INA823

1000
100
Output Impedance ( )
10
0.1
1 10 100 1k 10k 100k 1M 10M
Frequency (Hz)
VS = ±15 V
Figure 7-37. Closed-Loop Output Impedance vs Frequency Figure 7-38. Input Current vs Input Overvoltage
1.5
1
Nonlinearity (ppm)
0.5
-0.5
-1
-1.5
G=1
-2
-12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12
Output Voltage (V)
Figure 7-39. Gain Nonlinearity Figure 7-40. Gain Nonlinearity

4 14
12
3 10
8
2
6
Nonlinearity (ppm)
Nonlinearity (ppm)
1 4
2
0 0
-2
-1 -4
-6
-2
-8
-3 -10
G = 100 -12 G = 1000
-4 -14
-12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12
Output Voltage (V) Output Voltage (V)
Figure 7-41. Gain Nonlinearity Figure 7-42. Gain Nonlinearity

INA823

0 2
Normalized Positive Input Bias Current (nA)
Normalized Positive Input Bias Current (nA)

IBP Avg
-10 IBP +3
IBP −3
-20 1.5 VCM Range
-30
-40 1
-50
-60 IBP Avg 0.5

IBP +3
-70 IBP −3
VCM Range
-80 0
-16 -15 -14 -13 -12 -11 -10 10 11 12 13 14 15
Common-Mode Voltage (V) Common-Mode Voltage (V)
Figure 7-43. Positive Input Bias Current vs Common‑Mode Figure 7-44. Positive Input Bias Current vs Common‑Mode
Voltage (VS–) Voltage (VS+)
10 2
Normalized Negative Input Bias Current (nA)
Normalized Negative Input Bias Current (nA)

IBN Avg
0 IBN +3
IBN −3
-10 VCM Range
1.5
-20
-30
1
-40
-50
IBN Avg 0.5
-60
IBN +3
-70 IBN −3
VCM Range
-80 0
-16 -15 -14 -13 -12 -11 -10 10 11 12 13 14 15
Common-Mode Voltage (V) Common-Mode Voltage (V)
Figure 7-45. Negative Input Bias Current vs Common‑Mode Figure 7-46. Negative Input Bias Current vs Common‑Mode
Voltage (VS–) Voltage (VS+)
50
-45 C
40 -20 C
25 C
Input Offset Voltage ( V)
85 C
30 125 C
VCM Range
20
10
-10
-20
-16 -12 -8 -4 0 4 8 12 16
Common-Mode Voltage (V)
VS = ±15 V VS = ±1.35 V
Figure 7-47. Offset Voltage vs Common-Mode Voltage Figure 7-48. Offset Voltage vs Common-Mode Voltage

INA823

15 -14
-40 C
14.9 -14.1 25 C
14.8 -14.2 85 C
125 C
14.7 -14.3
Output Voltage (V)

Output Voltage (V)
14.6 -14.4
14.5 -14.5
14.4 -14.6
14.3 -14.7
-40 C
14.2 -14.8
25 C
14.1 85 C -14.9
125 C
14 -15
0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
Output Current (A) Output Current (A)
VS = ±15 V VS = ±15 V
Figure 7-49. Positive Output Voltage Swing vs Output Current Figure 7-50. Negative Output Voltage Swing vs Output Current
2.7 -1.7
-40 C
2.6 -1.8 25 C
2.5 -1.9 85 C
125 C
2.4 -2
Output Voltage (V)
Output Voltage (V)
2.3 -2.1
2.2 -2.2
2.1 -2.3
2 -2.4
-40 C
1.9 25 C -2.5
1.8 85 C -2.6
125 C
1.7 -2.7
0 0.005 0.01 0.015 0.02 0.025 0 0.005 0.01 0.015 0.02 0.025
Output Current (A) Output Current (A)
VS = ±1.35 V VS = ±1.35 V
Figure 7-51. Positive Output Voltage Swing vs Output Current Figure 7-52. Negative Output Voltage Swing vs Output Current
1.8 2.25
2.1 VREF = 0 V
1.6 1.95 VREF = 1.35 V
1.8
1.4
1.65
1.2 1.5
1.35
1 1.2
0.8 1.05
0.9
0.6 0.75
0.6
0.4 0.45
0.2 VREF = 0 V 0.3
VREF = 1.35 V 0.15
0 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75
VS = 2.7 V G=1 VS = 2.7 V G = 100
Figure 7-53. Input Common-Mode Voltage vs Output Voltage Figure 7-54. Input Common-Mode Voltage vs Output Voltage

INA823

5 5
VREF = 0 V VREF = 0 V
4.5 VREF = 2.5 V 4.5 VREF = 2.5 V
4 4

3.5 3.5
3 3
2.5 2.5
2 2
1.5 1.5
1 1
0.5 0.5
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VS = 5 V G=1 VS = 5 V G = 100
G=1 G > 10

INA823
8 Detailed Description
8.1 Overview
The INA823 is a monolithic precision instrumentation amplifier that incorporates a current-feedback input stage
and a four-resistor difference-amplifier output stage. One of the features of an instrumentation amplifier (IA)
is that the gain is set by placing an external resistor across the RG pins, as described in Section 8.3.1. The
three-op-amp IA topology in the INA823 limits the maximum input voltage applied to the input terminal. The
maximum input voltage depends on the common-mode voltage, differential voltage, gain, and the reference
voltage; for more information, see Section 8.3.2. The INA823 also features protection at each input by two
junction field-effect transistors (JFETs) that provide a low series resistance under normal signal conditions,
and preserve excellent noise performance. When excessive voltage is applied, these transistors limit the input
current, as described in Section 8.3.3.
The INA823 is developed for medical-sector applications such as infusion pumps (see Section 9.2.1), and
industrial applications such as programmable logic controllers (see Section 9.2.2)
The schematic in Figure 8-1 shows how the INA823 operates. A differential input voltage is buffered by the input
transistors, Q1 and Q2, and is forced across RG. This causes a signal current through RG, R1, and R2. The output
difference amplifier, A3, removes the common-mode component of the input signal and refers the output signal
to the REF pin. The threshold voltage of Q1 and Q2 (defined as VBE) along with the voltage drop across R1 and
R2 produce output voltages on A1 and A2, respectively, that are approximately 0.8 V less than the input voltages.
V+ V+
Optional RG
(External)
50 k
A1 Out = VCM + VBE + 0.125 V + VD /2 G R1 R2
A2 Out = VCM + VBE + 0.125 V VD /2 G 50 k 50 k V+
V V
50 k
Output Swing Range A1, A2, (V+) 0.1 V to (V ) + 0.1 V
50 k A OUT
VO = G (VIN+ VIN ) + VREF 3
Linear Input Range A 3 = (V+) 0.9 V to (V ) + 0.1 V V+
V
50 k
REF
V+ V+
V
+IN
Q1 Q2
VD /2 C1 C2
Overvoltage V A1 A2 V Overvoltage
Protection Protection
IB Cancellation IB Cancellation
RB VB RB
VCM
VD /2
V
IN
Figure 8-1. Detailed Schematic
8.2 Functional Block Diagram

External Gain Set
REF
Resistor (Optional)
Input Bias Current-

Overvoltage
─IN Current Feedback
Protection
Cancellation Input Stage
Difference
OUT
Amplifier
Input Bias Current-
Overvoltage
+IN Current Feedback
Protection
Cancellation Input Stage

INA823
8.3 Feature Description

8.3.1 Gain-Setting Function
Figure 8-2 shows that the gain of the INA823 is set by a single external resistor (RG) connected between the RG
pins (pins 1 and 8).
+VS
VIN / 2
IN +VS
50 k 50 k
Overvoltage
+
+ Protection
–
RG
50 k – OUT
RG
50 k +
+
VCM RL
– RG
VIN / 2 –
50 k 50 k
Overvoltage + REF
+ +IN Protection
VS
VS
Figure 8-2. Simplified Schematic of the INA823 With Gain and Output Equations
The gain of the INA823 can be calculated with Equation 1:
G = 1+ 100 kΩ
R (1)
G
The value of the external gain resistor RG is then derived from the gain equation:
RG = 100 kΩ
G − 1 (2)
Table 8-1 lists several commonly used gains and resistor values. The 100-kΩ term in Equation 1 is a result of the
sum of the two internal 50-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate absolute
values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift
specifications of the Section 7.5. As shown in Figure 8-2 and explained in more details in Section 11, make sure
to connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground that are placed as
close to the device as possible.
Table 8-1. Commonly Used Gains and Resistor Values
DESIRED GAIN NEAREST 1% RG (Ω) CALCULATED GAIN ERROR (%)
1 Not connected Not connected
2 100 k 0
5 24.9 k 0.321
10 11 k 0.909
20 5.23 k 0.602
33 3.09 k 1.098
50 2.05 k 0.439
65 1.58 k 1.091
100 1.02 k 0.961
200 499 0.700
500 200 0.200
1000 100 0.100

INA823
8.3.1.1 Gain Drift

The stability and temperature drift of the external gain setting resistor (RG) also affects gain. The contribution of
RG to gain accuracy and drift is determined from Equation 2.
The best gain drift of 5 ppm/℃ (maximum) is achieved when the INA823 uses G = 1 V/V without RG connected.
In this case, gain drift is limited by the slight mismatch of the temperature coefficient of the integrated 50-kΩ
resistors in the differential amplifier (A3).
At gains greater than 1 V/V, gain drift increases as a result of the individual drift of the 50-kΩ resistors in the
feedback of A1 and A2 relative to the drift of the external gain resistor (RG.) The low temperature coefficient of
the internal feedback resistors significantly improves the overall temperature stability of applications using gains
greater than 1 V/V over alternate options.
8.3.2 Input Common-Mode Voltage Range
The INA823 linear input voltage range extends from 1 V less than the positive supply to 0.15 V less than the
negative supply, and maintains excellent common-mode rejection throughout this range. The common-mode
range for the most common operating conditions are shown in Figure 8-3. While there are other methods to
calculate the common-mode voltage range, the suggested tool is the Analog Engineers Calculator.
5 5
VREF = 0 V VREF = 0 V
4.5 VREF = 2.5 V 4.5 VREF = 2.5 V
4 4
3.5 Common-Mode Voltage (V) 3.5

3 3
2.5 2.5
2 2
1.5 1.5
1 1
0.5 0.5
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VS = 5 V, G = 1 VS = 5 V, G = 100
Figure 8-3. Input Common-Mode Voltage Figure 8-4. Input Common-Mode Voltage
vs Output Voltage vs Output Voltage
G = 1, VREF = 0 V G > 10, VREF = 0 V
Figure 8-5. Input Common-Mode Voltage Figure 8-6. Input Common-Mode Voltage
vs Output Voltage vs Output Voltage
A single-supply instrumentation amplifier has special design considerations. To achieve a common-mode

range that extends to single-supply ground, the INA823 employs a current-feedback topology with PNP input

INA823
transistors. The matched PNP transistors, Q1 and Q2, shift the input voltages of both inputs up by a diode drop,
and (through the feedback network) shift the output of A1 and A2 by approximately 0.6 V. The output of A1 and
A2 is well within the linear range when the inputs are within the single-supply ground. When inputs are within the
supply ground, differential measurements can be made at the ground level. As a result of this input level-shifting,
the voltages at pin 1 and pin 8 are not equal to the respective input pin voltages. For most applications, this
inequality is not important because only the gain-setting resistor connects to these pins.
8.3.3 Input Protection
The inputs of the INA823 device are individually protected for voltages up to ±60 V and for short transients up
to ±80 V. For example, a condition of –60 V on one input and +60 V on the other input does not cause damage.
Internal circuitry on each input provides low series impedance under normal signal conditions. If the input is
overloaded, the protection circuitry limits the input current to a value of approximately 4 mA.
+V
ZD1
+VS
IN Overvoltage
Input Voltage +
Protection
Source – Input Transistor
-VS
ZD2
-V
Figure 8-7. Input Current Path During an Overvoltage Condition
During an input overvoltage condition, current flows through the input protection diodes into the power supplies,
as shown in Figure 8-7. If the power supplies are unable to sink current, then Zener diode clamps (ZD1 and ZD2
in Figure 8-7) must be placed on the power supplies to provide a current pathway to ground. Figure 8-8 shows
the input current for input voltages from –80 V to +80 V when the INA823 is powered by ±15-V supplies.
Figure 8-8. Input Current vs Input Overvoltage
8.4 Device Functional Modes

The INA823 has a single functional mode and is operational when the power supply voltage is greater than 2.7 V
(±1.35 V). The maximum power-supply voltage for the INA823 is 36 V (±18 V).

INA823
9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information

9.1.1 Input Bias Current Return Path
The input impedance of the INA823 is extremely high, but a path must be provided for the input bias current of
both inputs. This input bias current is typically 1.2 nA. High input impedance means that this input bias current
changes little with varying input voltage.
For proper operation, input circuitry must provide a path for this input bias current. Figure 9-1 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range of the INA823, and the input amplifiers saturate. If the differential source resistance
is low, the bias current return path connects to one input (as shown in the thermocouple example in Figure
9-1). With a higher source impedance, use two equal resistors to provide a balanced input, with the possible
advantages of a lower input offset voltage as a result of bias current, and better high-frequency common-mode
rejection. Furthermore, matched input impedances generally minimize the impact to performance in cases where
the input common-mode voltage is very low and input bias current can increase as the IB cancellation circuity
runs out of headroom. The input offset current typically remains low; therefore, well-matched input impedances
reduce the differential error voltage that would otherwise arise.
For more details about why a valid input bias current return path is necessary, see the Importance of Input Bias
Current Return Paths in Instrumentation Amplifier Applications application note.
Microphone,
Hydrophone, TI Device
and So Forth
47 kW 47 kW
Thermocouple TI Device
10 kW
TI Device
Center tap provides

bias current return.
Copyright © 2017, Texas Instruments Incorporated
Figure 9-1. Providing an Input Common-Mode Current Path

INA823
9.2 Typical Applications

9.2.1 Resistive-Bridge Pressure Sensor
The INA823 is an integrated instrumentation amplifier that measures small differential voltages while
simultaneously rejecting larger common-mode voltages. The device offers a low power consumption of 250
µA (max) and high precision, thus minimizing errors with voltage offset, offset drift and gain error.
The device is designed for portable applications where sensors measure physical parameters, such as changes
in fluid, pressure, temperature, or humidity. An example of a pressure sensor used in the medical sector is in
portable infusion pumps or dialysis machines.
The pressure sensor is made of a piezo-resistive element that can be derived as a classical 4-resistor
Wheatstone bridge. Occlusion (infusion of fluids, medication, or nutrients) happens only in one direction, and
therefore, can only cause the resistive element (R) to expand. This expansion causes a change in voltage on
one leg of the Wheatstone bridge, which induces a differential voltage VDIFF.
Figure 9-2 showcases an exemplary circuit for an occlusion pressure sensor application, as required in infusion
pumps. When blockage (occlusion) occurs against a set-point value, the tubing depresses, thus causing the
piezo-resistive element to expand (Node AD: R + ΔR). The signal chain connected to the bridge downstream
processes the pressure change and can trigger an alarm.
VSS = 5 V
VEXT = 2.5 V
1 F 1 F
REF5025
A

R

k
+
99
0.1 F
R
4.
D
Pressure B –
Occlusion
Sensor VOUT
VDIFF RG INA823 ADC µC
C VREF
+
R1
GND
Figure 9-2. Resistive-Bridge Pressure Sensor
Low-tolerance bridge resistors must be used to minimize the offset and gain errors.
Given that there is only a positive differential voltage applied, this circuit is laid out in single-ended supply
mode. The excitation voltage, VEXT, to the bridge must be precise and stable; otherwise, measurement error is
introduced.
The REF5025 is a low-noise, low-drift (3 ppm/C), and high-precision (0.05%) voltage reference that is an
excellent option to generate the excitation voltage VEXT.
The following subsections give the design requirements and detailed design procedure for an application with a
occlusion pressure sensor.
For more information and design tips to consider when using a resistive-bride pressure sensor, see the Design
tips for a resistive-bridge pressure sensor in industrial process-control systems analog applications journal.

INA823
9.2.1.1 Design Requirements

For this application, the design requirements are as shown in Table 9-1.
Table 9-1. Design Requirements
DESCRIPTION VALUE
Single supply voltage VS= 5 V
Excitation voltage VEXT = 2.5 V
Occlusion pressure range P = 1...10 psi, increments of p = 0.5 psi
Occlusion pressure sensitivity S = 2 ± 0.5 (25%) mV/V/psi
Occlusion pressure impedance (R) R = 4.99 kΩ ± 50 Ω (0.1%)
Total pressure sampling rate Sr = 20 Hz
Full-scale range of ADC VADC(fs) = VOUT = 4.5 V
9.2.1.2 Detailed Design Procedure

This section provides basic calculations to lay out the instrumentation amplifier with respect to the given design
requirements.
One of the key considerations in resistive-bridge sensors is the common-mode voltage, VCM. If the bridge is
balanced (no pressure, thus no voltage change), VCM(MAX) is half of the bridge excitation (VEXT). As the pressure
increases to the maximum value, the common-mode voltage decreases to VCM(MIN).
To achieve the output voltage of VOUT = 4.5 V with the INA823, the limitation for the common-mode voltage is at
VCM(INA823max) = 1.8 V, as shown in Figure 7-56 and Figure 9-3 (where an initial gain value of 100 V/V is used
as an approximation). An additional series resistor in the Wheatstone bridge string (R1) is required to shift the
common-mode voltage to this value. However, be aware that shifting the common-mode voltage also changes
the effective excitation voltage VEXT across the bridge.
Figure 9-3. Screen Shot From Analog Engineer's Calculator
Calculate the new effective excitation voltage VEXT(NOM) associated with a desired VCM(MIN) value by solving the
following:
VEXT − VCM MIN 2.5 − 1.8

VEXT NOM = 2* = 2* = 1.366 V (3)
1 + SMAX*PMAX 1 + 2.5 mV V*psi*10 psi

INA823
VEXT(NOM) can in turn be used to calculate the desired value of R1:
V
R1 = R V EXT 2.5 V
− 1 = 4.99 kΩ 1.366 V − 1 = 4.144 kΩ (4)
EXT NOM
Use a standard 0.1% resistor value of 4.12 kΩ.

Calculate the maximum value of VDIFF by solving the following equation for the maximum pressure of 10 psi:
VDIFF = SMAX*PMAX *VEXT NOM = 2.5 mV V*psi*10 psi *1.366 V = 34.15 mV (5)
Use the resulting value to verify that the minimum bridge common-mode voltage, VCM(MIN), is within the limits of
the INA823 by solving the following:
V
VCM MAX = VCM MIN + DIFF
2 = 1.8 V +
34.15 mV
2 = 1.817 V (6)
Next, use Equation 7 to calculate the required gain for the given maximum sensor output voltage span, VDIFF,
with respect to the required VOUT, which is the full-scale range of the ADC.
VOUT
G = V = 4.5 V = 131.77 V/V (7)
DIFF(MAX) 34.15 mV
Equation 8 calculates the gain-setting resistor value using the INA823 gain equation shown in Equation 2:
RG = 100 kΩ
G − 1 =
100 kΩ
= 764.69 Ω (8)
131.77 V V − 1
Use a standard 0.1% resistor value of 768 Ω, so as not to exceed the full-scale range of the ADC.
9.2.1.3 Application Curves
The following typical characteristic curve is for the circuit in Figure 9-2.
0.05 5
VDIFF
0.045 VOUT 4.5
Differential Input Voltage VDIFF (V)
0.04 4
Output Voltage VOUT (V)
0.035 3.5
0.03 3
0.025 2.5
0.02 2
0.015 1.5
0.01 1
0.005 0.5
0 0
4950 5050 5150 5250 5350 5450 5550
Bridge Resistance R+R ()
Figure 9-4. Input Differential Voltage, Output Voltage vs Bridge Resistance

INA823
9.2.2 Supporting High Common-Mode Voltage in PLC Input Modules

Figure 9-5 showcases a high common-mode voltage circuit that is commonly required for programmable logic
controller (PLC) analog input modules. This circuit uses a resistive scaling network in front of the IA.
Ri
750 k
15 V
+ Rf Cf 5V
0.1 μF
VDIFF / 2 249 k 47 nF
+
RG VOUT
33.2 k INA823 ADC
+ +
VCM VREF
– –
VDIFF / 2 Rf' Cf'
R i' 249 k 47 nF
750 k
─ 15 V
0.1 μF
Figure 9-5. High Common-Mode Voltage PLC Input Module
For a detailed description of the passive scaling approach and more, see the Supporting High-Voltage Common
Mode Using Instrumentation Amplifier application brief.
9.2.2.1 Design Requirements
Table 9-2 lists the requirements for this design example.

Table 9-2. Design Parameters
PARAMETER VALUE
Supply voltage ±15 V
Common-mode voltage +36 V / –43 V
Input differential signal 1V
Gain VOUT/VDIFF 1 V/V
Minimum dc CMRR 65 dB
9.2.2.2 Detailed Design Procedure
The gain of the IA is calculated so that the circuit operates at unity gain, where VOUT = VDIFF.
The single-ended input impedance, Rin(SE), of the circuit is the sum of the scaling resistors (Rf + Ri). To
minimize the error that is caused by the tolerance of the scaling resistors, keep Rin > 1 MΩ.
Ideally, choose the resistors so that Rf / Ri = Rf' / Ri'. In the real world, designers have to trade off between
the mismatch of ratios that degrades the common-mode rejection ratio (CMRR) and the acceptable cost for the
design.
The following text describe how to estimate the CMRR performance of the external resistor scaling approach. In
the calculation of CMRR, the following factors are considered:
• Take into account the number of resistors, which is estimated by √n, where n is the number of resistors
applied. In this case, this estimation results in a factor of 2.
• ΔR / R is the resistor matching ratio. The resistor tolerance for all four resistors is 0.1%.
• Take into account that a normal production distribution of the resistor value with a standard deviation of ±3 σ
(99.7%). In this case, the assumption results in a factor σ = 1/3 = 0.33 into the equation.

INA823
Equation 9 calculates the common-mode rejection ratio with given factors:
CMRRdB = G1
ΔR
+1
(9)
α∙ R ∙ n
0.25 +1
CMRRdB = = 65.5 dB (10)
0.33∙0.1%∙√4
The scaling ratio G1 is calculated by:
R
G1 = R +f R (11)
f i
where
• Rf is variable
• Ri is fixed at 750 kΩ.
Figure 9-6 shows a comparison between the CMRR performance at worst-case (α neglected) and considering
normal distribution for different gain settings of G1.
For more details about the calculation of CMRR, see the Difference amplifier (subtractor) circuit analog
engineer's circuit.
9.2.2.3 Application Curves
Figure 9-6. Common-mode Rejection Ratio of External Resistor Network for Different Scaling Ratios

INA823
10 Power Supply Recommendations

The nominal performance of the INA823 is specified with a supply voltage of ±15 V and midsupply reference
voltage. The device also operates using power supplies from ±1.35 V (2.7 V) to ±18 V (36 V) and non-midsupply
reference voltages with excellent performance. Parameters that can vary significantly with operating voltage and
reference voltage are shown in Section 7.6.
CAUTION
Supply voltages higher than 40 V (±20 V) can permanently damage the device.
11 Layout
11.1 Layout Guidelines
Attention to good layout practices is always recommended. For best operational performance of the device, use
the following PCB layout practices:
• Make sure that both input paths are well-matched for source impedance and capacitance to avoid converting
common-mode signals into differential signals.
• Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources local to the
analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Route the input traces as far away from the supply or output traces as possible to reduce parasitic coupling. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than crossing
in parallel with the noisy trace.
• Place the external components as close to the device as possible.
• Use short, symmetric, and wide traces to connect the external gain resistor to minimize capacitance
mismatch between the RG pins.
• Keep the traces as short as possible.

INA823
11.2 Layout Example

+V
C2
R2
+VS
+IN
RG
R3 INA823 OUT
REF
RG
–VS
–IN
R1
C1
Ground plane
–V
removed at gain
resistor to minimize
parasitic capacitance
Use ground pours for

shielding the input
signal pairs R3
GND +V
GND
R1 1 RG RG 8 C2
–IN 2 –IN +VS 7

Input traces routed
adjacent to each other +IN 3 +IN OUT 6 OUT
R2 4 –VS REF 5
Low-impedance
connection for
GND
reference pin
C1
Place bypass
capacitors as close to
IC as possible
–V
Figure 11-1. Example Schematic and Associated PCB Layout

INA823
12 Device and Documentation Support

12.1 Device Support
12.1.1 Development Support
• SPICE-based analog simulation program — TINA-TI software folder
• Analog Engineer's Calculator
12.1.1.1 PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Comprehensive Error Calculation for Instrumentation Amplifiers application note
• Texas Instruments, Importance of Input Bias Current Return Paths in Instrumentation Amplifier Applications
application note
• Texas Instruments, REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference data sheet
• Texas Instruments, OPAx191 36-V, Low Power, Precision, CMOS, Rail-to-Rail Input/Output, Low Offset
Voltage, Low Input Bias Current Op Amp data sheet
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 25-Jun-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
INA823DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2IVJ Samples
INA823DGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2IVJ Samples
INA823DR ACTIVE SOIC D 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 INA823 Samples
INA823DT ACTIVE SOIC D 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 INA823 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA823DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
INA823DGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
INA823DR SOIC D 8 3000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
INA823DT SOIC D 8 250 180.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
INA823DGKR VSSOP DGK 8 2500 356.0 356.0 35.0
INA823DGKT VSSOP DGK 8 250 210.0 185.0 35.0
INA823DR SOIC D 8 3000 356.0 356.0 35.0
INA823DT SOIC D 8 250 210.0 185.0 35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated

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INA823

SBOSA75B – JULY 2021 – REVISED NOVEMBER 2021

INA823 Precision, Low-Power, Wide-Supply (2.7-V to 36-V) Instrumentation Amplifier

INA823 Simplified Internal Schematic

2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: INA823

5 Device Comparison Table

6 Pin Configuration and Functions

Table 6-1. Pin Functions

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

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7.5 Electrical Characteristics

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5

7.5 Electrical Characteristics (continued)

(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).

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7.6 Typical Characteristics

Table 7-1. Table of Graphs

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7.6 Typical Characteristics

Table 7-1. Table of Graphs (continued)

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7.6 Typical Characteristics

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9

7.6 Typical Characteristics (continued)

Output Stage Offset Voltage ( V)

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7.6 Typical Characteristics (continued)

Input Offset Current (nA)

Common-Mode Rejection Ratio (dB)

Normalized Gain Error (%)

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7.6 Typical Characteristics (continued)

Common-Mode Rejection Ratio (dB)

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7.6 Typical Characteristics (continued)

Spectral Density (fA/ Hz)

Output Amlitude (mV)

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7.6 Typical Characteristics (continued)

Output Amlitude (mV)

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7.6 Typical Characteristics (continued)

Figure 7-39. Gain Nonlinearity Figure 7-40. Gain Nonlinearity

Figure 7-41. Gain Nonlinearity Figure 7-42. Gain Nonlinearity

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15

7.6 Typical Characteristics (continued)

Normalized Positive Input Bias Current (nA)

-60 IBP Avg 0.5

Normalized Negative Input Bias Current (nA)

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7.6 Typical Characteristics (continued)

Output Voltage (V)

VDIFF = SMAXPMAX VEXT NOM = 2.5 mV Vpsi10 psi *1.366 V = 34.15 mV (5)