SN 65 HVD 1781

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SN65HVD1780, SN65HVD1781, SN65HVD1782

SLLS877H – DECEMBER 2007 – REVISED MARCH 2017
SN65HVD178x Fault-Protected RS-485 Transceivers With 3.3-V to 5-V Operation

1 Features 3 Description
1• Bus-Pin Fault Protection to: The SN65HVD178x devices are designed to survive
overvoltage faults such as direct shorts to power
– > ±70 V (SN65HVD1780, SN65HVD1781) supplies, mis-wiring faults, connector failures, cable
– > ±30 V (SN65HVD1782) crushes, and tool mis-applications. The devices are
• Operation With 3.3-V to 5-V Supply Range also robust to ESD events with high levels of
protection to the human-body-model specification.
• ±16-kV HBM Protection on Bus Pins
• Reduced Unit Load for Up to 320 Nodes The SN65HVD178x devices combine a differential
driver and a differential receiver, which operate from
• Failsafe Receiver for Open-Circuit, Short-Circuit,
a single power supply. In the SN65HVD1782, the
and Idle-Bus Conditions driver differential outputs and the receiver differential
• Low Power Consumption inputs are connected internally to form a bus port
– Low Standby Supply Current, 1 µA Maximum suitable for half-duplex (two-wire bus)
communication. This port features a wide common-
– ICC 4-mA Quiescent Current During Operation
mode voltage range, making the devices suitable for
• Pin-Compatible With Industry-Standard SN75176 multipoint applications over long cable runs. These
• Signaling Rates of 115 kbps, 1 Mbps, and up to devices are characterized from –40°C to 125°C.
10 Mbps These devices are pin-compatible with the industry-
standard SN75176 transceiver, making them drop-in
• Create a Custom Design using the SN65HVD178x
upgrades in most systems.
with the WEBENCH® Power Designer
These devices are fully compliant with ANSI TIA/EIA
2 Applications 485-A with a 5-V supply and can operate with a 3.3-V
supply with reduced driver output voltage for low-
• HVAC Networks power applications. For applications where operation
• Security Electronics is required over an extended common-mode voltage
• Building Automation range, see the SN65HVD1785 (SLLS872) data sheet.
• Telecommunication Equipment Device Information(1)
• Motion Control PART NUMBER PACKAGE BODY SIZE (NOM)
• Industrial Networks SOIC (8) 4.90 mm × 3.91 mm
SN65HVD178x
PDIP (8) 9.81 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Protection Against Bus Shorts
VFAULT up to 70 V
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLLS877H – DECEMBER 2007 – REVISED MARCH 2017 www.ti.com
Table of Contents
1 Features .................................................................. 1 9.2 Functional Block Diagram ....................................... 15
2 Applications ........................................................... 1 9.3 Feature Description................................................. 15
3 Description ............................................................. 1 9.4 Device Functional Modes........................................ 16
4 Revision History..................................................... 2 10 Application and Implementation........................ 18
10.1 Application Information.......................................... 18
5 Device Comparison Table..................................... 4
10.2 Typical Application ............................................... 18
6 Pin Configuration and Functions ......................... 4
11 Power Supply Recommendations ..................... 22
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ..................................... 4 12 Layout................................................................... 22
12.1 Layout Guidelines ................................................. 22
7.2 ESD Ratings: JEDEC................................................ 5
12.2 Layout Example .................................................... 22
7.3 ESD Ratings: IEC ..................................................... 5
7.4 Recommended Operating Conditions....................... 5 13 Device and Documentation Support ................. 23
7.5 Thermal Information .................................................. 5 13.1 Device Support...................................................... 23
7.6 Electrical Characteristics........................................... 6 13.2 Documentation Support ........................................ 23
7.7 Power Dissipation Characteristics ............................ 7 13.3 Related Links ........................................................ 23
7.8 Switching Characteristics .......................................... 7 13.4 Receiving Notification of Documentation Updates 23
7.9 Typical Characteristics .............................................. 9 13.5 Community Resources.......................................... 24
13.6 Trademarks ........................................................... 24
8 Parameter Measurement Information ................ 10
13.7 Electrostatic Discharge Caution ............................ 24
8.1 Equivalent Input Schematic .................................... 14
13.8 Glossary ................................................................ 24
9 Detailed Description ............................................ 15
9.1 Overview ................................................................. 15 14 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (August 2015) to Revision H Page
• Added WEBENCH information to the Features, Detailed Design Procedure, and Device Support sections ........................ 1
• Added values to the Storage temperature in the Absolute Maximum Ratings table.............................................................. 4
• Added the Equivalent Input Schematic section .................................................................................................................... 14
Changes from Revision F (August 2012) to Revision G Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision E (September 2008) to Revision F Page
• Deleted text from the first Description paragraph - The internal current-limit circuits allow fault survivability without
causing the high bus currents that otherwise might damage external components or power supplies. ............................... 1
• Changed From: Voltage input range, transient pulse, A and B, through 100 Ω in the Absolute Maximum Ratings
table To: Transient overvoltage pulse through 100 Ω per TIA-485 ........................................................................................ 4
• Changed Figure 13 title From: Measurement of Receiver Enable Times With Driver Disabled To: Measurement of
Receiver Enable Times With Driver Disabled ...................................................................................................................... 13
Changes from Revision D (August 2008) to Revision E Page
• Changed Bus input current (disabled driver), separating the condition for the different devices........................................... 6
2 Submit Documentation Feedback Copyright © 2007–2017, Texas Instruments Incorporated
Product Folder Links: SN65HVD1780 SN65HVD1781 SN65HVD1782

www.ti.com SLLS877H – DECEMBER 2007 – REVISED MARCH 2017
Changes from Revision C (July 2008) to Revision D Page
• Changed Receiver propagation delay max value From: 70 ns To: 80 ns. ............................................................................. 8
Changes from Revision B (April 2008) to Revision C Page
• Added two new part numbers 1780 and 1782 ....................................................................................................................... 1

• Deleted Features Bullet: Designed for RS-485 and RS-422 Networks.................................................................................. 1
• Changed making it a drop-in upgrade for most devices -to- making them drop-in upgrades in most systems. .................... 1
Changes from Revision A (January 2008) to Revision B Page
• Changed the IOS Min value From: -150 To: -200 and Max value From: 150 To: 200 ............................................................ 6
Changes from Original (December 2007) to Revision A Page
• Changed Receiver propagation delay max value From: 50 ns To: 70 ns. ............................................................................. 8
• Changed tPLZ, tPHZ Receiver disable time From 3000 ns To 100 ns....................................................................................... 8
Copyright © 2007–2017, Texas Instruments Incorporated Submit Documentation Feedback 3

5 Device Comparison Table
TRANSCEIVER SIGNALING RATE NUMBER OF NODES

SN65HVD1780 Up to 115 kbps Up to 320
SN65HVD1781 Up to 1 Mbps Up to 320
SN65HVD1782 Up to 10 Mbps Up to 64
6 Pin Configuration and Functions
D Package and P Package

8-Pin SOIC and 8-Pin PDIP
Top View
R 1 8 VCC
RE 2 7 B
DE 3 6 A
D 4 5 GND
Pin Functions
PIN
I/O DESCRIPTION
NAME NUMBER
Bus
A 6 Driver output or receiver input (complimentary to B)
input/output
Bus
B 7 Driver output or receiver input (complimentary to A)
input/output
D 4 Digital input Driver data input
DE 3 Digital input Driver enable high
Reference
GND 5 Local device ground
potential
R 1 Digital output Receive data output
RE 2 Digital input Receiver enable low
VCC 8 Supply 4.5-V to 5.5-V supply
7 Specifications
7.1 Absolute Maximum Ratings (1)
MIN MAX UNIT
Supply voltage, VCC –0.5 7 V
SN65HVD1780, SN65HVD1781 A, B pins –70 70
Voltage at bus pin V
SN65HVD1782 A, B pins –70 30
Input voltage at any logic pin –0.3 VCC + 0.3 V
Transient overvoltage pulse through 100 Ω per TIA-485 –70 70 V
Receiver output current –24 24 mA
Junction temperature, TJ 170 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings: JEDEC

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all Bus pins and GND ±16000
pins (1)
Electrostatic All pins ±4000 V
V(ESD)
discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±2000
Machine model JEDEC Standard 22, Test Method A115, all pins ±400 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 ESD Ratings: IEC

VALUE UNIT
IEC 60749-26 ESD (human body model), bus terminals and
V(ESD) Electrostatic discharge ±16000 V
GND
7.4 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Supply voltage 3.15 5 5.5 V
VI Input voltage at any bus terminal (separately or common mode) (1) –7 12 V
VIH High-level input voltage (driver, driver enable, and receiver enable inputs) 2 VCC V
VIL Low-level input voltage (driver, driver enable, and receiver enable inputs) 0 0.8 V
VID Differential input voltage –12 12 V
Output current, driver –60 60 mA
IO
Output current, receiver –8 8 mA
RL Differential load resistance 54 60 Ω
CL Differential load capacitance 50 pF
SN65HVD1780 115 kbps
1/tUI Signaling rate SN65HVD1781 1
Mbps
SN65HVD1782 10
Operating free-air temperature (See Power 5-V supply –40 105
TA °C
Dissipation Characteristics) 3.3-V supply –40 125
TJ Junction temperature –40 150 °C
(1) By convention, the least positive (most negative) limit is designated as minimum in this data sheet.
7.5 Thermal Information

SN65HVD178x
(1)
THERMAL METRIC D (SOIC) P (PDIP) UNIT
8 PINS 8 PINS
JEDEC high-K model 138 59
RθJA Junction-to-ambient thermal resistance °C/W
JEDEC low-K model 242 128
RθJC(top) Junction-to-case (top) thermal resistance 61 61 °C/W
RθJB Junction-to-board thermal resistance 62 39 °C/W
ψJT Junction-to-top characterization parameter 3.4 17.6 °C/W
ψJB Junction-to-board characterization parameter 33.4 28.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

7.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 60 Ω, 4.75 V ≤ VCC 375 Ω on each output TA < 85°C 1.5
to –7 V to 12 V
Figure 6 TA < 125°C 1.4
RL = 54 Ω, TA < 85°C 1.7 2

Driver differential output 4.75 V ≤ VCC ≤ 5.25 V TA < 125°C 1.5
|VOD| V
voltage magnitude
RL = 54 Ω,
0.8 1
3.15 V ≤ VCC ≤ 3.45 V
RL = 100 Ω, TA < 85°C 2.2 2.5

4.75 V ≤ VCC ≤ 5.25 V TA < 125°C 2
Change in magnitude of driver
Δ|VOD| RL = 54 Ω –50 0 50 mV
differential output voltage
VOC(SS) Steady-state common-mode
1 VCC/2 3 V
output voltage
Change in differential driver
ΔVOC –50 0 50 mV
output common-mode voltage
Peak-to-peak driver common- Center of two 27-Ω load resistors
VOC(PP) 500 mV
mode output voltage See Figure 7
COD Differential output capacitance 23 pF
Positive-going receiver
VIT+ differential input voltage –100 –35 mV
threshold
Negative-going receiver
VIT– differential input voltage –180 –150 mV
threshold
Receiver differential input
VHYS voltage threshold hysteresis 30 50 mV
(VIT+ – VIT–)
Receiver high-level output
VOH IOH = –8 mA 2.4 VCC – 0.3 V
voltage
Receiver low-level output TA < 85°C 0.2 0.4

VOL IOL = 8 mA V
voltage TA < 125°C 0.5
Driver input, driver enable, and
II(LOGIC) –50 50 μA
receiver enable input current
IOZ Receiver output high- VO = 0 V or VCC, RE at VCC μA
–1 1
impedance current
Driver short-circuit output
IOS –200 200 mA
current
1780, 1781 75 100
VI = 12 V
Bus input current (disabled VCC = 3.15 to 5.5 V or 1782 400 500
II(BUS) μA
driver) VCC = 0 V, DE at 0 V 1780, 1781 –60 –40
VI = –7 V
1782 –400 –300
DE = VCC,
Driver and receiver enabled RE = GND, 4 6
no load
DE = VCC,
Driver enabled, receiver disabled RE = VCC, 3 5 mA
no load
DE = GND,
Driver disabled, receiver enabled RE = GND, 2 4
no load
ICC Supply current (quiescent)
DE = GND,
D = open,
RE = VCC, 0.15 1
no load,
TA < 85°C
Drive and receiver disabled (standby mode) µA
DE = GND,
D = open,
RE = VCC, 12
no load,
TA < 125°C
Supply current (dynamic) See Typical Characteristics

7.7 Power Dissipation Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MAX UNIT
VCC = 5.5 V, TJ = 150°C, RL = 300 Ω,
CL = 50 pF (driver),
290
CL = 15 pF (receiver)
5-V supply, unterminated (1)
VCC = 5.5 V, TJ = 150°C, RL = 100 Ω,
PD Power dissipation 320 mW
5-V supply, RS-422 load (1)
VCC = 5.5 V, TJ = 150°C, RL = 54 Ω,
400
5-V supply, RS-485 load (1)
TSD Thermal-shutdown junction temperature 170 °C
(1) Driver and receiver enabled, 50% duty cycle square-wave signal at signaling rate: 1 Mbps.
7.8 Switching Characteristics

over recommended operating conditions (unless otherwise noted)
DRIVER (SN65HVD1780)
RL = 54 Ω, 3.15 V < VCC < 3.45 V 0.4 1.4 1.8
Driver differential output rise or fall
tr, tf CL = 50 pF, µs
time 3.15 V < VCC < 5.5 V 0.4 1.7 2.6
See Figure 8
RL = 54 Ω,
tPHL, tPLH Driver propagation delay CL = 50 pF, 0.8 2 µs
See Figure 8
RL = 54 Ω,
Driver differential output pulse skew,
tSK(P) CL = 50 pF, 20 250 ns
|tPHL – tPLH|
See Figure 8
tPHZ, tPLZ Driver disable time See Figure 9 and Figure 10 0.1 5 µs
See Figure 9 and
Receiver enabled 0.2 3
Figure 10
tPZH, tPZL Driver enable time µs
See Figure 9 and
Receiver disabled 3 12
Figure 10
Driver differential output rise or fall
tr, tf RL = 54 Ω, CL = 50 pF, See Figure 8 50 300 ns
time
tPHL, tPLH Driver propagation delay RL = 54 Ω, CL = 50 pF, See Figure 8 200 ns
Driver differential output pulse skew,
tSK(P) RL = 54 Ω, CL = 50 pF, See Figure 8 25 ns
|tPHL – tPLH|
tPHZ, tPLZ Driver disable time See Figure 9 and Figure 10 3 µs
See Figure 9 and
Receiver enabled 300 ns
Figure 10
tPZH, tPZL Driver enable time
See Figure 9 and
Receiver disabled 10 µs
Figure 10
All VCC and
50
Driver differential output rise or fall RL = 54 Ω, Temperature
tr, tf ns
time CL = 50 pF VCC > 4.5 V and
16
T < 105°C
RL = 54 Ω,
tPHL, tPLH Driver propagation delay See Figure 8 55 ns
CL = 50 pF
Driver differential output pulse skew, RL = 54 Ω,
tSK(P) See Figure 8 10 ns
|tPHL – tPLH| CL = 50 pF
tPHZ, tPLZ Driver disable time See Figure 9 and Figure 10 3 µs

Switching Characteristics (continued)

over recommended operating conditions (unless otherwise noted)
See Figure 9 and
Receiver enabled 300 ns
Figure 10
tPZH, tPZL Driver enable time
See Figure 9 and
Receiver disabled 9 µs
Figure 10
RECEIVER
tr, tf Receiver output rise or fall time CL = 15 pF, 4 15
All devices ns
See Figure 11
SN65HVD1780,
CL = 15 pF, 100 200
tPHL, tPLH Receiver propagation delay time SN65HVD1781 ns
See Figure 11
SN65HVD1782 80
SN65HVD1780,
Receiver output pulse skew, CL = 15 pF, 6 20
tSK(P) SN65HVD1781 ns
|tPHL – tPLH| See Figure 11
SN65HVD1782 5
tPLZ, tPHZ Receiver disable time Driver enabled, See Figure 12 15 100 ns
tPZL(1), tPZH(1) Driver enabled, See Figure 12 80 300 ns
tPZL(2), tPZH(2) Receiver enable time
Driver disabled, See Figure 13 3 9 μs

7.9 Typical Characteristics
10 80
TA = 25°C
RE at VCC
0 70 DE at VCC VCC = 5 V
ICC − RMS Supply Current − mA

IO − Driver Output Current − mA
RL = 54 W
CL = 50 pF
−10 60
−20 50
−30 40
TA = 25°C VCC = 3.3 V

−40 DE at VCC 30
D at VCC
RL = 54 W
−50 20
0 1 2 3 4 5 6 0 100 200 300 400 500 600 700 800 900 1000
VCC − Supply Voltage − V Signaling Rate − kbps
G001 G002
Figure 1. Driver Output Current vs Supply Voltage Figure 2. RMS Supply Current vs Signaling Rate
4.4 35
4.0
30
VCC = 5.5 V
VOD − Differential Output Voltage − V
3.6
VCC = 3.3 V
3.2 25
Load = 300 W
Rise\Fall Time - (ns)
2.8
20
2.4
Load = 100 W
2.0
15
Load = 60 W VCC = 5 V
1.6
1.2 10
VCC = 3.3 V
0.8
5
0.4
VCC = 3.15 V
0.0 0
0 5 10 15 20 25 30 35 40 45 50 -50 0 50 100 150
I(diff) − Differential Load Current − mA Temperature - (°C)
G003
Figure 3. Differential Output Voltage vs Differential Load Figure 4. SN65HVD1782 Rise or Fall Time
Current
2.5
RL = 50 W, VCC = 5.5 V
2.3
CL = 50 pF
2.1
VCC = 5 V
VOD − Differential Output − V
1.9
1.7
VCC = 4.5 V
1.5
1.3
VCC = 4 V
VCC = 3.6 V
1.1
0.9 VCC = 3.3 V

VCC = 3 V
0.7
0.5
500
700
900
1300
1500
1700
1900
2100
2300
2500
2700
1100
Transition Time − ns
Figure 5. SN65HVD1780 Differential Output Amplitude and Transition Time vs Supply Voltage

8 Parameter Measurement Information

Input generator rate is 100 kbps, 50% duty cycle, rise or fall time is less than 6 ns, output impedance is 50 Ω.
VCC 375 W ±1%
DE
A
D
0 V or 3 V VOD 60 W ±1%
+ –7 V < V(test) < 12 V
B _
375 W ±1%
Copyright © 2016, Texas Instruments Incorporated
Figure 6. Measurement of Driver Differential Output Voltage With Common-Mode Load
VCC
A VA
27 W ±1%
DE
A
D B VB
Input
VOC VOC(PP) DVOC(SS)
B
27 W ±1% CL = 50 pF ±20%
VOC
CL Includes Fixture and
Instrumentation Capacitance
Figure 7. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
VCC 3V
VI 50% 50%
DE CL = 50 pF ±20%
A
D tPLH tPHL
VOD CL Includes Fixture
and Instrumentation »2V
Input B RL = 54 W 90% 90%
VI 50 W Capacitance VOD
Generator ±1% 0V 0V
10% 10%
» –2 V
tr tf
Figure 8. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
3V
A S1
D VO VI
3V 50% 50%
B 0V
DE RL = 110 W 0.5 V
CL = 50 pF ±20% tPZH
Input ± 1% VOH
VI 50 W CL Includes Fixture 90%
Generator
and Instrumentation VO
Capacitance 50%
»0V
tPHZ
NOTE: D at 3 V to test non-inverting output, D at 0 V to test inverting output.
Figure 9. Measurement of Driver Enable and Disable Times With Active High Output and Pulldown Load

Parameter Measurement Information (continued)

3V
RL = 110 W »3V
A ±1%
S1 VI 50% 50%
D VO
3V
0V
B tPZL tPLZ
DE
CL = 50 pF ±20% »3V
Input
Generator VI 50 W CL Includes Fixture VO
and Instrumentation 50%
10%
Capacitance VOL
NOTE: D at 0 V to test non-inverting output, D at 3 V to test inverting output.
Figure 10. Measurement of Driver Enable and Disable Times With Active-Low Output and Pullup Load
A
R VO
Input
VI 50 W
Generator B
1.5 V CL = 15 pF ±20%
RE
0V CL Includes Fixture
and Instrumentation
Capacitance
3V
VI 50% 50%
0V
tPLH tPHL
VOH
90% 90%
VO 50% 50%
10% 10% VOL
tr tf
Figure 11. Measurement of Receiver Output Rise and Fall Times and Propagation Delays


3V VCC
DE A
R VO 1 kW ± 1%
0 V or 3 V D S1
B
CL = 15 pF ±20%
RE
CL Includes Fixture
and Instrumentation
Input Capacitance
Generator VI 50 W
3V
VI 50% 50%
0V
tPZH(1) tPHZ
VOH
D at 3 V
90% S1 to GND
VO 50%
»0V
tPZL(1) tPLZ
VCC
D at 0 V
VO 50% S1 to VCC
10%
VOL
Figure 12. Measurement of Receiver Enable and Disable Times With Driver Enabled


VCC
A
0 V or 1.5 V R VO 1 kW ± 1%
S1
B
1.5 V or 0 V CL = 15 pF ±20%
RE
CL Includes Fixture
and Instrumentation
Input Capacitance
Generator VI 50 W
3V
VI 50%
0V
tPZH(2)
VOH
A at 1.5 V
VO 50% B at 0 V
S1 to GND
GND
tPZL(2)
VCC
A at 0 V
VO 50% B at 1.5 V
S1 to VCC
VOL
Figure 13. SN65HVD1781 Measurement of Receiver Enable Times With Driver Disabled


8.1 Equivalent Input Schematic
When the input digital pins float, internal high value resistors pull D/REB pins to VCC and DE pin to GND to place
the device into known states. If the voltage level of D/REB input pins is higher than that of power rail, input
current can flow through the input resistor and pull up resistor to VCC.
D and RE Inputs DE Input

VCC VCC
100 kΩ
1 kΩ 1 kΩ
Input Input
100 kΩ
Figure 14. Equivalent Input Schematic Diagrams

9 Detailed Description
9.1 Overview
The SN65HVD178x devices are half-duplex RS-485 transceivers available in three speed grades suitable for
data transmission up to 115 kbps, 1 Mbps, and 10 Mbps.
These devices feature a wide common-mode operating range and bus-pin fault protection up to ±70 V. Each
device has an active-HIGH driver enable and active-LOW receiver enable. A standby current of less than 1 µA
can be achieved by disabling both driver and receiver.
9.2 Functional Block Diagram
VCC
R
RE A
DE B
GND
9.3 Feature Description

Internal ESD protection circuits protect the transceiver bus terminals against ±16 kV human body model (HBM)
electrostatic discharges.
Device operation is specified over a wide temperature range from –40°C to 125°C.
9.3.1 70-V Fault Protection

The SN65HVD178x family of RS-485 transceivers is designed to survive bus pin faults up to ±70 V. The
SN65HVD1782 will not survive a bus pin fault with a direct short to voltages above 30 V when:
• The device is powered on, AND
• The driver is enabled (DE = HIGH), AND
– D = HIGH AND the bus fault is applied to the A pin, OR
– D = LOW AND the bus fault is applied to the B pin
Under other conditions, the device will survive shorts to bus pin faults up to ±70 V. Table 1 summarizes the
conditions under which the device may be damaged, and the conditions under which the device will not be
damaged.
Table 1. Device Conditions

POWER DE D A B RESULTS
OFF X X –70 V < VA < 70 V –70 V < VB < 70 V Device survives
ON L X –70 V < VA < 70 V –70 V < VB < 70 V Device survives
ON H L –70 V < VA < 70 V –70 V < VB < 30 V Device survives
ON H L –70 V < VA < 70 V 30 V < VB Damage may occur
ON H H –70 V < VA < 30 V –70 V < VB < 30 V Device survives
ON H H 30 V < VA –70 V < VB < 30 V Damage may occur

9.3.2 Receiver Failsafe

The SN65HVD178x family of half-duplex transceivers provides internal biasing of the receiver input thresholds in
combination with large input-threshold hysteresis. At a positive input threshold of VIT+ = –35 mV and an input
hysteresis of VHYS = 30 mV, the receiver output remains logic high under bus-idle, bus-short, or open bus
conditions in the presence of up to 130 mVPP differential noise without the need for external failsafe biasing
resistors.
9.3.3 Hot-Plugging
These devices are designed to operate in "hot swap" or "hot pluggable" applications. Key features for hot-
pluggable applications are power-up and power-down glitch-free operation, default disabled input and output
pins, and receiver failsafe.
As shown in Figure 1, an internal power-on reset circuit keeps the driver outputs in a high-impedance state until
the supply voltage has reached a level at which the device will reliably operate. This ensures that no problems
will occur on the bus pin outputs as the power supply turns on or turns off.
As shown in Device Functional Modes, the enable inputs have the feature of default disable on both the driver
enable and receiver enable. This ensures that the device will neither drive the bus nor report data on the R pin
until the associated controller actively drives the enable pins.
9.4 Device Functional Modes

When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as
VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pulldown resistor to ground, thus, when left open, the driver is disabled (high-impedance) by
default. The D pin has an internal pullup resistor to VCC, thus, when left open while the driver is enabled, output A
turns high and B turns low.
Table 2. Driver Function Table

INPUT ENABLE OUTPUTS
FUNCTION
D DE A B
H H H L Actively drive bus high
L H L H Actively drive bus low
(1)
X L Z Z Driver disabled
(1)
X OPEN Z Z Driver disabled by default
OPEN H H L Actively drive bus high by default
(1) When both the driver and receiver are disabled, the device enters a low-power standby mode.
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and lower than the negative input threshold, VIT-, the receiver output, R, turns
low. If VID is between VIT+ and VIT- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven
(idle bus).

Table 3. Receiver Function Table

DIFFERENTIAL INPUT ENABLE OUTPUT
FUNCTION
VID = VA – VB RE R
VIT+ < VID L H Receive valid bus high
VIT– < VID < VIT+ L ? Indeterminate bus state
VID < VIT– L L Receive valid bus low
(1)
X H Z Receiver disabled
(1)
X OPEN Z Receiver disabled by default
Open-circuit bus L H Fail-safe high output
Short-circuit bus L H Fail-safe high output
Idle (terminated) bus L H Fail-safe high output
(1) When both the driver and receiver are disabled, the device enters a low-power standby mode.

10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information

The SN65HVD178x devices are half-duplex RS-485 transceivers commonly used for asynchronous data
transmissions. The driver and receiver enable pins allow for the configuration of different operating modes.
R R R
R R R
RE A RE A RE A
DE B DE B DE B
D D D
D D D
Figure 15. Half-Duplex Transceiver Configurations
Using independent enable lines provides the most flexible control as it allows for the driver and the receiver to be
turned on and off individually. While this configuration requires two control lines, it allows for selective listening
into the bus traffic, whether the driver is transmitting data or not.
Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal.
In this configuration, the transceiver operates as a driver when the direction-control line is high, and as a receiver
when the direction-control line is low.
Additionally, only one line is required when connecting the receiver-enable input to ground and controlling only
the driver-enable input. In this configuration, a node not only receives the data from the bus, but also the data it
sends and can verify that the correct data have been transmitted.
10.2 Typical Application

An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer
cable length.
R R R R
A A
RE RE
RT RT
B B
DE DE
D D D D
A B A B
R R
D D
R RE DE D R RE DE D
Figure 16. Typical RS-485 Network With Half-Duplex Transceivers


Typical Application (continued)

10.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
10.2.1.1 Data Rate and Bus Length

There is an inverse relationship between data rate and bus length, meaning the higher the data rate, the shorter
the cable length; and conversely, the lower the data rate, the longer the cable may be without introducing data
errors. While most RS-485 systems use data rates from 10 kbps to 100 kbps, some applications require data
rates up to 250 kbps at distances of 4000 feet and longer. Longer distances are possible by allowing for small
signal jitter of up to 5% or 10%.
10000
5%, 10%, and 20% Jitter
Cable Length (ft)
1000
Conservative
Characteristics
100
10
100 1k 10k 100k 1M 10M 100M
Data Rate (bps)
Figure 17. Cable Length vs Data Rate Characteristic
Even higher data rates are achievable (for example, 10 Mbps for the SN65HVD1782) in cases where the
interconnect is short enough (or has suitably low attenuation at signal frequencies) to not degrade the data.
10.2.1.2 Stub Length

When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in Equation 1.
Lstub ≤ 0.1 × tr × v × c
where
• tr is the 10/90 rise time of the driver
• c is the speed of light (3 × 108 m/s)
• v is the signal velocity of the cable or trace as a factor of c (1)
10.2.1.3 Bus Loading

The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. The SN65HVD1780 and SN65HVD1781 are 1/10 unit
load transceivers, and so up to 320 can be placed on a common bus. The SN65HVD1782 is a 1/2 unit load
transceiver, so up to 64 can share a bus.


10.2.1.4 Receiver Failsafe
The differential receivers of the SN65HVD178x family are “failsafe” to invalid bus states caused by:
• Open bus conditions, such as a disconnected connector
• Shorted bus conditions, such as cable damage shorting the twisted-pair together
• Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic High state so that the output of the
receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the “input indeterminate” range
does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output
must output a High when the differential input VID is more positive than +200 mV, and must output a Low when
VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are VIT(+),
VIT(-), and VHYS (the separation between VIT(+) and VIT(-)). As shown in the Electrical Characteristics, differential
signals more negative than –200 mV will always cause a Low receiver output, and differential signals more
positive than +200 mV will always cause a High receiver output.
When the differential input signal is close to zero, it is still above the maximum VIT(+) threshold of –35 mV, and
the receiver output will be High. Only when the differential input is more than VHYS below VIT(+) will the receiver
output transition to a Low state. Therefore, the noise immunity of the receiver inputs during a bus fault condition
includes the receiver hysteresis value, VHYS, as well as the value of VIT(+).
R
Vhys (min)
30 mV
VID (mV)
-65 -35 0 +65
Vn max = 130 mVpp
Figure 18. SN65HVD178x Noise Immunity Under Bus Fault Conditions
10.2.2 Detailed Design Procedure
10.2.2.1 Custom Design with WEBENCH® Tools

Click here to create a custom design using the SN65HVD178x device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance
– Run thermal simulations to understand the thermal performance of your board
– Export your customized schematic and layout into popular CAD formats
– Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
Although the SN65HVD178x family is internally protected against human-body-model ESD strikes up to 16 kV,
additional protection against higher-energy transients can be provided at the application level by implementing
external protection devices.

3.3V
100nF 100nF
10k VCC
R1
R
RxD
MCU/ RE A TVS
UART
DE B
DIR
D
TxD
R2
10k GND
Figure 19. RS-485 Transceiver With External Transient Protection
Figure 19 shows a protection circuit intended to withstand 8-kV IEC ESD (per IEC 61000-4-2) as well as 4-kV
EFT (per IEC 61000-4-4).
Table 4. Bill of Materials

DEVICE FUNCTION ORDER NUMBER MANUFACTURER
XCVR RS-485 Transceiver SN65HVD1781 TI
R1,R2 10 Ω, Pulse-Proof Thick-Film CRCW0603010RJNEAHP Vishay
Resistor
TVS Bidirectional 600-W Transient SMBJ43CA Littelfuse
Suppressor
10.2.3 Application Curve
Figure 20. SN65HVD1780 Differential Output at 115 kbps

11 Power Supply Recommendations

To assure reliable operation at all data rates and supply voltages, each supply should be buffered with a 100-nF
ceramic capacitor located as close to the supply pins as possible. The TPS76350 is a linear voltage regulator
suitable for the 5-V supply.
12 Layout
12.1 Layout Guidelines

On-chip IEC-ESD protection is good for laboratory and portable equipment but often insufficient for EFT and
surge transients occurring in industrial environments. Therefore robust and reliable bus node design requires the
use of external transient protection devices.
Because ESD and EFT transients have a wide-frequency bandwidth from approximately 3 MHz to 3 GHz, high-
frequency layout techniques must be applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.
2. Use VCC and ground planes to provide low-inductance. Note that high-frequency currents follow the path of
least inductance and not the path of least impedance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of the transceiver, UART, or
controller ICs on the board.
5. Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance.
6. Use 1-kΩ to 10-kΩ pullup and pulldown resistors for enable lines to limit noise currents in these lines during
transient events.
7. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
12.2 Layout Example
5
Via to ground
C 4 Via to VCC
R
6 R
1
JMP
MCU R
5
TVS
6 R
SN65HVD178x 5
Figure 21. SN65HVD178x Half-Duplex Layout Example

13 Device and Documentation Support
13.1 Device Support

13.1.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the SN65HVD178x device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance
– Run thermal simulations to understand the thermal performance of your board
– Export your customized schematic and layout into popular CAD formats
– Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
13.1.2 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support

13.2.1 Related Documentation
For related documentation, see the following:
SN65HVD17xx Fault-Protected RS-485 Transceivers With Extended Common-Mode Range, SLLS872
13.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links

TECHNICAL TOOLS & SUPPORT &
PART PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
SN65HVD1780 Click here Click here Click here Click here Click here
13.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

13.5 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.6 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 8-Dec-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
SN65HVD1780D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 VP1780 Samples
SN65HVD1780DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 VP1780 Samples
SN65HVD1780DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 VP1780 Samples
SN65HVD1780DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 VP1780 Samples
SN65HVD1780P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 105 65HVD1780 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 8-Dec-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD1780, SN65HVD1781, SN65HVD1782 :
• Automotive : SN65HVD1780-Q1, SN65HVD1781-Q1, SN65HVD1782-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 1-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65HVD1780DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD1781DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD1782DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD1780DR SOIC D 8 2500 356.0 356.0 35.0
SN65HVD1781DR SOIC D 8 2500 356.0 356.0 35.0
SN65HVD1782DR SOIC D 8 2500 356.0 356.0 35.0
TUBE
T - Tube
height L - Tube length
W - Tube
width
B - Alignment groove width

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN65HVD1780D D SOIC 8 75 506.6 8 3940 4.32
SN65HVD1780DG4 D SOIC 8 75 506.6 8 3940 4.32
SN65HVD1780P P PDIP 8 50 506 13.97 11230 4.32
SN65HVD1781D D SOIC 8 75 506.6 8 3940 4.32
SN65HVD1781DG4 D SOIC 8 75 506.6 8 3940 4.32
SN65HVD1781P P PDIP 8 50 506 13.97 11230 4.32
SN65HVD1782D D SOIC 8 75 506.6 8 3940 4.32
SN65HVD1782DG4 D SOIC 8 75 506.6 8 3940 4.32
SN65HVD1782P P PDIP 8 50 506 13.97 11230 4.32
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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SN65HVD1780, SN65HVD1781, SN65HVD1782

SN65HVD178x Fault-Protected RS-485 Transceivers With 3.3-V to 5-V Operation

Protection Against Bus Shorts

Changes from Revision G (August 2015) to Revision H Page

Changes from Revision F (August 2012) to Revision G Page

Changes from Revision E (September 2008) to Revision F Page

Changes from Revision D (August 2008) to Revision E Page

2 Submit Documentation Feedback Copyright © 2007–2017, Texas Instruments Incorporated

Product Folder Links: SN65HVD1780 SN65HVD1781 SN65HVD1782

Changes from Revision C (July 2008) to Revision D Page

Changes from Revision B (April 2008) to Revision C Page

• Added two new part numbers 1780 and 1782 ....................................................................................................................... 1

Changes from Revision A (January 2008) to Revision B Page

Changes from Original (December 2007) to Revision A Page

Copyright © 2007–2017, Texas Instruments Incorporated Submit Documentation Feedback 3

5 Device Comparison Table

TRANSCEIVER SIGNALING RATE NUMBER OF NODES

6 Pin Configuration and Functions

D Package and P Package

4 Submit Documentation Feedback Copyright © 2007–2017, Texas Instruments Incorporated

Product Folder Links: SN65HVD1780 SN65HVD1781 SN65HVD1782

7.2 ESD Ratings: JEDEC

7.3 ESD Ratings: IEC

7.4 Recommended Operating Conditions

7.5 Thermal Information

Copyright © 2007–2017, Texas Instruments Incorporated Submit Documentation Feedback 5

7.6 Electrical Characteristics

RL = 54 Ω, TA < 85°C 1.7 2

RL = 100 Ω, TA < 85°C 2.2 2.5

Receiver low-level output TA < 85°C 0.2 0.4

6 Submit Documentation Feedback Copyright © 2007–2017, Texas Instruments Incorporated

Product Folder Links: SN65HVD1780 SN65HVD1781 SN65HVD1782

7.7 Power Dissipation Characteristics

7.8 Switching Characteristics

Copyright © 2007–2017, Texas Instruments Incorporated Submit Documentation Feedback 7

Switching Characteristics (continued)

8 Submit Documentation Feedback Copyright © 2007–2017, Texas Instruments Incorporated

Product Folder Links: SN65HVD1780 SN65HVD1781 SN65HVD1782

7.9 Typical Characteristics

ICC − RMS Supply Current − mA

TA = 25°C VCC = 3.3 V

0.9 VCC = 3.3 V

Copyright © 2007–2017, Texas Instruments Incorporated Submit Documentation Feedback 9

8 Parameter Measurement Information

Figure 6. Measurement of Driver Differential Output Voltage With Common-Mode Load

NOTE: D at 3 V to test non-inverting output, D at 0 V to test inverting output.

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Parameter Measurement Information (continued)

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NOTE: D at 0 V to test non-inverting output, D at 3 V to test inverting output.

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Parameter Measurement Information (continued)

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Parameter Measurement Information (continued)

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Parameter Measurement Information (continued)

D and RE Inputs DE Input

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Figure 14. Equivalent Input Schematic Diagrams