DESIGN OF BOOTH MULTIPLIER

1)Overview

rst
clk output
start
t Booth Multiplier
sn
finish
sbn

Name Bit Description

rst 1 reset signal
clk 1 clock impulse
start 1 begin of process
sbn M multiplier
sn N multiplied number
output M+N result
finish 1 end of process

*State of the art:

- Parallel Binary Multiplier Circuit
- Serial Multiplier
- Shift and Add Multiplier
2)Architecture
Start

Load Cnt = n
A <= {sn,0...0,0}
S <= {-sn,0...0,0}
P <= {0..0,sbn,0}
Sn min
A <= {1,sn,0...0,0}
S <= {0,-sn,0...0,0}
P <= {0,0..0,sbn,0}

Yes
P[1:0] = 01 Yes P = P+A

No

Yes
P[1:0] = 10 P = P+S

No
No
Shift-left P,
Cnt = cnt - 1

Cnt=0?

Yes
Yes

Stop

Algorithm of Booth Multiplier

 Idle

ASMD of Booth Multiplier

 Structure of Booth Multiplier

RTL view of Booth Multiplier

 Coverage of test plan for simulation

*Simulation result: