Embedded Analog-to-Digital Converters
Klaas Bult
Broadcom Corporation
Bunnik, The Netherlands
bult@broadcom .com
Abstract - Systems-on-Chips (SoCs) have
become a reality in the past decade. Several dozens
of different functional blocks are being integrated on
a single die, reaching transistor counts of up to half a
billion. From the Analog portion of an SoC the Data
Converters are probably among the most challeng-
ing blocks, often limiting system performance and
dominating power dissipation. However, require-
ments regarding yield, die-size, scalability, noise
immunity, power and the fact that logic is almost for
free, cause distinct differences between embedded
Data Converters and their stand-alone, usually gen-
eral purpose, counterparts. This paper describes
these differences and provides an overview of the
state-of-the art in Analog-to-Digital Conversion.
I. INTRODUCTION
In a world "going digital" one of the dominant
remaining Analog blocks is the Data Converter. With
the cost of digital functionality going down exponen-
tially along the path of technology scaling, trading ana-
log circuitry for digital becomes more and more
attractive. The Data Converter is the minimum required
Analog function, often limiting overall system perfor-
mance. Within Analog Front-Ends (AFE) or RF-Receiv-
ers (RF-RX) the Analog-to-Digital Converter is one of
the hardest blocks to design as well. Being embedded
imposes extra problems on top of that. Limiting the
scope of the discussion to Nyquist-Rate (High Speed)
Analog-to-Digital Converters, this paper discusses what
it means to be "embedded" (section II, III and IV), the
difference between embedded and stand-alone data con-
verters from a system perspective (section V), the state-
of-the-art in Analog-to-Digital Conversion (section VI,
VII and VIII), how to choose an optimal architecture
(section IX) as well as the future of embedded design
(section X).
II. SYSTEM-ON-A-CHIP (SoC)
A. A typical SoC
Nowadays complete and very complex systems
are integrated on one single die and for the larger sys-
tems the number of transistors is approaching a billion.
By far the largest portion of that is in the digital part of
the system, which usually contains Multi-core GHz Pro-
cessors, multiple Mbytes of memory, various Media
Access Controllers (MAC) and several dedicated Digital
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Signal Processors (DSP). Examples can be found in
consumer applications like Cellular phones, DVD play-
ers, Multi-media players and Set-Top boxes.
As shown in the typical example of fig. 1, these
systems usually also contain multiple Analog Front-
Ends (AFE), Analog Back-Ends (ABE), as well as RF
Receive and Transmit functions. It is not uncommon
that the number of Analog/RF functions exceeds a
dozen or more.
B. A typical Analog Front-End (AFE)
Fig. 2 shows a typical AFE. With the idea in
mind that digital is (almost) for free, the trend is to keep
the analog circuitry to a minimum, pushing to the digital
domain whatever is possible. Starting from the back, the
minimum required function is the ADC. Usually a
Track& Hold or a Sample & Hold Amplifier (SHA) is
preceding the ADC. For anti-aliasing or noise reduction
purposes some form of Low-Pass Filtering (LPF) is
implemented , although often just the natural poles of the
other blocks are deemed sufficient. Active filtering is
usually avoided as it is often simpler (as well as lower
power and cost) to increase the sampling speed a bit to
allow simple first-order filtering. A Programmable-Gain
Amplifier (PGA) adjusts the incoming signal to opti-
mally fit to the reference voltage of the ADC. Omitting
this function and absorbing this in the dynamic range of
the ADC is usually too costly in terms of power dissipa-
tion.
I
processor
.-
,
II.
•
Fig. 1. A typical System-on-a-Chip (SoC). Often multiple
Analog Front-Ends (AFE), Analog Back-Ends (ABE), RF-
Receive (RF-RX) and RF-Transmit (RF-TX) blocks are
integrated along with multiple DSPs, memory and proces-
sor blocks .
 Fig. 2. A typical Analog Front-End (AFE) of an
SoC: Programmable Gain Amplifier (PGA), Low-
Pass Filter (LPF), Sample & Hold Amplifier
(SHA) and Analog-to-Digital Converter (ADC).
~~
Fig. 3. A typical SoC RF Front-End (RFFE). Most Radio/Tuner
architectures are either Direct-Conversion or Low-IF.
C. A typical RF Receiver (RF-RX)
Similarly to AFE blocks, a typical RF Receiver
(RF-RX), as shown in fig. 3, is also kept as simple as
possible. Whether Narrowband Radio or Wideband
Tuner, the architecture of choice is either Direct Conver-
sion or Low-IF, with significant support of digital func-
tionality to reduce the effect of circuit imperfections in
the Analog/RF domain. The huge gain necessary in the
receive chain is obtained through Variable Gain Ampli-
fiers (VGA) distributed along the signal path to opti-
mize dynamic Range of the receiver and the ADC.
III. WHAT DOES "EMBEDDED" MEAN?
A. Process-choice and Process-Options
As pointed out in the previous section, nowadays
complete systems are integrated on one single die occu-
pying as much as hundreds of square millimeters . By far
the largest portion of that is in the digital part of the sys-
tem. Although it's hard to give a generic number for the
percentage that Analog circuitry occupies in an SoC, it
is fair to say that in the vast majority of SoC chips the
area is dominated by digital circuitry. Therefore the pro-
cess-choice of an SoC is usually completely dominated
by digital requirements and the requirements for Analog
design playa very small role. This makes perfect sense
since with a billion digital transistors on a chip, the pro-
cess should be optimized for digital design to optimize
the overall yield and cost.
For the same reason, "Analog process options",
like MiM caps or double poly are not allowed. It cannot
be justified to increase the total chip-cost by 5% for an
Analog option that is not being used by say 95% of the
chip area. Analog designers just have to live with that
environment and have to make their circuits work with
what the digitally optimized process offers them.
B. Yield
In order to achieve a good overall chip yield,
Analog circuitry needs to have a very high yield as well.
The large ratio between Analog and Digital area ampli-
fies the significance of Analog yield: it is very costly if a
150mm2 die has to be thrown away because a O.2mm2
analog function has a yield problem. In fact, Analog cir-
cuitry needs to yield close to defect-density to be
acceptable. This is quite different from the situation for
stand-alone designs.
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TUNER
C. Cross- Talk
For a long time cross-talk was believed to be a
major road-block towards the realization of SoCs: a bil-
lion digital transistors generate a lot of noise through the
substrate and pin-connections, forcing Analog designers
to design very cross-talk insensitive circuits. But as was
pointed out in [I] , separating the analog functions on a
different die also suffers from X-talk problems, in that
case primarily from the digital output pins that form the
interface with the fully digital die. Over time however,
analog designers have developed a way to cope with
that, by choosing high-Ohmic substrates, using guard-
rings, using distance, choosing fully differential circuits
and choosing pin-positions very carefully. At this
moment, although care is always needed, cross-talk is
no longer in the top-three list-of-problems of embedded
Data Converter design.
D. Testing
As opposed to their Stand-Alone counterparts,
embedded Data Converters normally don't have their
digital I/O's connected to external pins. Digital signals
either come from (in the case of the DAC) or go to (in
the case of the ADC) the digital part on the same die.
This not only saves significant amounts of power, but
also relieves the design from the burden of bringing pos-
sibly very high-frequency digital signals on or off the
chip, along with the associated problems of cross-talk .
For a 12-bit ADC or DAC, the isolation between the
Most Significant Bit (MSB) and the analog signal has to
be better than SOdB, especially at high frequencies a
very difficult task indeed.
For testing purposes however, the digital signals
have to be routable to test pins and the problem could
rise again if the sampling speed is high enough. But suit-
able solutions have been found to address that problem.
In the case of the ADC, memory can be placed
on chip to capture a certain amount of data, that subse-
quently can be read out at a much slower pace, through
test-pins . This can reduce the problem to levels below
the noise-floor of the design. The required digital mem-
ory usually is available in the digital system anyway.
For DACs the situation is even nicer. In many
cases a Direct Digital Frequency Synthesizer (DDFS) is
available to generate the tones needed for testing. Often
even a dual DDFS is used to generate the tones for two-
 tone testing. The only interfaces with the outside world
are the test-pins to select the exact frequency (often with
24-bit accuracy), the test-pins to select the amplitude of
the digital signals and the Analog output signal. All that
is needed is a Spectrum Analyzer to analyze the output
signal. In the case a DDFS is not already available in the
digital system, that function is often integrated addition-
ally for test-purposes only. In modem CMOS processes
the size of a DDFS is so small that cost is no longer a
reason not to do this.
Most SoCs incorporate a receive- as well as a
transmit-function, which means that both a DAC as well
as an ADC are present. This enables Analog loop-back
in which the DAC drives the ADC, allowing the imple-
mentation of a fully digital test as a very powerful and
cost-effective test-scenario. Examples can be found in
Ethernet, DSL and SerDes.
E. Digital Signal Processing Power
So far in this section mostly additional demands
on Analog circuit design imposed by the integration
onto an SoC have been discussed. However, being
embedded within large amounts of digital circuitry also
means that a lot of digital processing power is available,
which can be used to the advantage of the Analog
design. Even complex functions like FFTs are available.
The general trend towards digitally aided Analog design
(where techniques like digital calibration and error-cor-
rection techniques are fully exploited) allows for better
Analog performance or for reduced power, while main-
taining the same performance.
IV. DEMANDS ON THE ORGANIZATION
As stated previously, large SoC's contain dozens
of sub-systems each requiring their own Analog/RF
blocks. Systems of this size always require the latest
CMOS node in order to hit the cost-target for the end-
applications. Often the integration-level of these sys-
tems are limited by yield issues and higher integration-
levels require the higher packing density of the next
technology-node. Supporting the Analog and RF
requirements of these systems puts very specific
demands on the organization.
A. Size ofthe Portfolio
Dozens of systems cannot be designed from
scratch and expected to be successfully integrated on an
SoC. Typically 90% - 95% of the blocks have to be
ready on the shelf and tested in previous systems. Only a
few blocks per generation can be added if any reason-
able rate of success is expected. This requires a very
large portfolio of sub-systems, including their Analogi
RF blocks, to be production-tested and ready. For that
reason it has become very hard for smaller companies to
enter this business space.
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B. Fast Porting and size ofAnalog Organization
Unfortunately, the huge portfolio of IP-blocks
becomes obsolete every 18 to 24 month, when the next
CMOS-node is becoming economically viable. So,
being embedded not only means that you need to be able
to port a single design quickly and often from one prod-
uct generation to another (with often increased specs),
but you actually need to port the entire portfolio from
one technology to the next every 18 to 24 month. As a
result it is prudent to look ahead to whatever the next
technology looks like and check whether your design
will also work (with possibly some minor changes) in
the next process node. Doing something that only works
in the current technology means postponing challenges
to the future. Because digital circuits are easily ported
from one technology to the next, to be able to keep up
with their Tape-Out schedules, a significant size of orga-
nization supporting the Analog/RF circuits is needed.
c. System Knowledge
A lot of system knowledge usually is available in
an SoC design environment. Dedicated Analog design
can take advantage of this specific system knowledge.
This also means that in most cases the Analog design
will not be general purpose but specifically tailored to
the system at hand. This can easily lead to seemingly
unbalanced designs where for instance the equivalent
ENOB from a noise point of view is 1 or 2 bits higher
than the equivalent ENOB for distortion, simply
because that is the best choice from a system perspec-
tive (see section V.G).
Contrary to what might be expected, the vast
amount of system knowledge usually leads to continu-
ously changing analog specs. The constant quest for the
optimal system performance includes the optimization
of the specifications for the Analog blocks, making
Analog design specifications a constantly moving tar-
get. A significant amount of systems knowledge is
therefore needed from Analog designers in order to be
able to negotiate the most appropriate target specifica-
tions for the Analog blocks.
D. Programmable Design and Design for Bug-Fixing
Modem CMOS processes are extremely expen-
sive and dedicated test-chips are often very hard to jus-
tify. Even Multi-Project Wafers (MPW) are becoming
scarce. New designs are often expected to go in produc-
tion in one single pass with only metal-spins to solve
occasional bugs. This requires not only very careful
design, but it is also prudent to add a significant amount
of dummy transistors (fingers) and route all the connec-
tions in metal. On top of that, many bias-currents, refer-
ence-voltages, load-resistors, filtering-capacitors, etc.
can be made programmable, to accommodate unex-
pected parameter skews.
 V SYSTEM ASPECTS
One of the more subtle differences between
Stand-Alone and Embedded Data Converters is that the
latter can be even more specifically tailored to the needs
of the system, as is shown below.
A. SNR versus THD
SNR and THD both have an equal effect on the
ENOB of a Data Converter. For that reason Stand-Alone
ADCs usually have balanced specification with respects
to noise and distortion. Some systems however, are
more sensitive to nonlinearities, like narrow-band RF-
systems, where strong blockers in adjacent channels can
leak in to the wanted channel through inter-modulation
distortion and wipe out the wanted channel.
Other systems are often more sensitive to noise.
An example is the quantization of a wide-band signal.
Due to the broadband nature of the signal, the statistical
properties start resembling that of a Gaussian-distrib-
uted signal. A well known aspect of that is that,
although So events do happen, the signal spends most of
its time between +/- 2a. In systems with some amount
of error-correction, the influence of errors caused by
rare So events is so small that the Data Converter does
not have to be able to handle such large signals without
some form of performance degradation. That means that
at full-scale, the THD does not necessarily have to meet
the same value as the SNR. In fact the "imbalance" can
be significant, like 1 or 2 bits.
Data Converters with more stringent specifica-
tions on SNR than on THD may seem unbalanced (and
are much harder to publish for sure). But on the other
hand, that might be exactly what the system is asking for
and the Converter design should take advantage of that.
B. Quantization Noise
Quantization noise seems like a straightforward
aspect of a converter and often does not get much atten-
tion. If one needs 9.5 ENOB, then a 10-bit should do the
job. However, an ideal10-bit (without any noise, distor-
tion or jitter) is already limited to 10.0 ENOB. In order
to achieve the required 9.5 ENOB all the other effects
together (noise, jitter and distortion) should also achieve
10.0 ENOB in order to obtain 9.5 ENOB for the total
design. By deciding to go to 11 or 12 bits somewhat
more room for the other effects is obtained in a fairly
cheap way (see section V.I). Adding an additional least-
significant bit is not costly at all, although the digital
needs to be able to process this. This is a degree of free-
dom in embedded design that general purpose convert-
ers cannot benefit from.
c. Frequency Response
General purpose ADCs usually are expected to
have a flat (or nearly flat) performance up to the Nyquist
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frequency. For reasons like anti-aliasing or noise sub-
sampling and down-folding it is often preferable to have
some margin between the highest signal frequency and
the Nyquist frequency. That means that often the perfor-
mance of the data converter does not have to be flat up
to Nyquist. If that is the case it would be overkill and a
waste of power not to take advantage of that in the
design.
D. Latency
Latency can be a problem in some systems. Usu-
ally that depends on whether or not a loop is fed back
around the data converter. If there is, then the stability of
the loop will be negatively influenced by an increase in
latency. Often the latency in the digital domain is much
bigger than the latency of the data converter and this
becomes part of the negotiation with the system/digital
designers. For this reason, pipeline converters may have
to be excluded as a result of a strong restriction on
latency.
E. Bit Error Rate Performance
Bit Error Rate (BER) is a design parameter which
is often not discussed in ADC presentations or papers. It
is not simple to deal with in simulation and very time-
consuming during characterization. However, especially
in fast-sampling data converters, BER can be a very
dominant factor in design, dependent on the system
requirements. As an example, Cable applications like
Set-Top Boxes or Cable Modems require BERs in the
order of 10-12 and Ethernet applications require even
lower BERs of around 10-15 . Such demanding specifica-
tions can have a strong effect on the choice of architec-
ture. Fast sampling applications with stringent
requirements on BER may require either Flash- or Fold-
ing-architectures to meet the BER specifications (see
also sections VI.A and VI.F). However, BER specifica-
tions can vary widely from system to system. Measure-
ment systems, in which the final result may be averaged
over time can be more relaxed in their BER-require-
ments. A BER of 10-6 will not seriously degrade the
SNR of oscilloscope front-ends, even if every single bit-
error is a full-scale error. Many wireless systems aren't
even requiring anything more stringent than a BER of
10-4 .
F Accuracy ofReferences and Offsets
The accuracy requirement with respect to refer-
ences and offsets can also be very different between
embedded converters and their stand-alone counterparts.
The stand-alone version usually has tight specification
on the accuracy and spread of the reference voltage. The
embedded version has very relaxed specifications for
the reference voltages because it is usually preceded by
a Programmable Gain Amplifier (PGA) that is automati-
 cally adjusted to allow optimal use of the converters The embedded version uses 45-nm CMOS,
dynamic range. which is required to meet the level of integration and
On the other hand, in the embedded version usu- cost target for the system. The design is operated from a
ally no pins are available for the references, neither to 1.0-V supply but uses thick-oxide (this option is free
use external (precision) components nor for de-cou- because it is required by the digital I/O) for switches,
pling. The problem needs to be solved completely on- allowing rail-to-rail operation. The stand-alone version
chip, whereas the stand-alone version easily can use uses a 250-nm technology because it's less expensive
some pins for this purpose. and uses a 2.5-V supply, the regular supply voltage in
this technology. The MiM-option is used to reduce area
G Embedded versus Stand-Alone ADC for the capacitors used in this design.
To exemplify the differences between embedded The embedded version is realized in 0.5-mm2 .
and stand-alone ADCs discussed in the above, this sec- Area is important because it immediately impacts the
tion compares a typical (but imaginary) stand-alone cost of the SoC. The small feature size and improved
general purpose ADC to a typical (but imaginary) matching of this technology are full exploited. The
embedded ADC. Table 1 shows the specifications of stand-alone version has an area of 8.0-mm 2 . Area is not
both example ADCs. extremely important because the design is pad-limited
Table 1: A typical embedded vs. stand-alone ADC (and the cost per mm 2 is much lower in this relatively
old technology anyway).
Specification Embedded Stand-alone
The embedded version is packaged in a 776-pin
NOB 12 10 BGA which was necessary for the SoC. Pins for the ana-
SQR [dB] 74.0 61.9 log part of the chip (12) are kept to a minimum to reduce
Thermal Noise [dB] 65.1 65.1 the cost. For testing, an additional set of test-pins can be
SNR [dB] 64.6 60.2 configured to allow separate testing of the data con-
THD [dB] 61.1 68.0 verter. The stand-alone version is packaged in a 128-pin
SNDR [dB] 59.5 59.5 EPQFP, where all pins are used for the converter.
ENOB 9.6 9.6
VI. ADC TECHNIQUES
INL(lOb) [lsb] 0.6 0.4
DNL(lOb) [Isb] 0.3 0.3 This section gives an overview of Analog-to-
ERBW[MHz] 80 100 Digital Converter techniques and the state-of-the-art in
Fsamp [MS/s] 320 200 Analog-to-Digital Converters.
CMOS [nm] 45 250 A. Flash-Converters [8-11]
Options Thick-Oxide (free) MiM The Flash-architecture is probably the most
Vsupply [V] 1.0/2.5 2.5 straightforward ADC architecture known. It is widely
Area [mm/] 0.5 8.0 known that Flash-architectures are good for high speed.
Package 776 pin BGA 128-pin EPQFP Partly this is because there is often very little circuitry
Power [mW] 19.6 33.5 between the input signal and the comparator (often just
a simple pre-amp), but probably even more important
In this example, although the total resulting because the comparator decision can be followed by
ENOB is the same, the number of bits in both designs is several digital latches, increasing the BER (see section
different. The embedded design is taking advantage of V.G) dramatically. Architectures that require a decision
the freedom to choose a few more bits to lower the in one or even in half a clock-cycle, like any subranging
quantization noise. As the application happens to allow architecture (including most Two-Step and Pipeline
lower THD (because the input is a broadband signal architectures) do not have this option (see section VI.B).
with an amplitude distribution close to Gaussian) the The Flash-architecture remains the architecture of
extra headroom is used for lowering the THD which in choice for the fastest low resolution type of applications
tum allows for lower power, specifically in the continu- [9, 11], often with averaging and interpolation [8, 10]
ous-time part of the AFE. The result of this is an INL/
DNL that is significantly higher in the embedded ver- B. Sub-ranging [12-15]
sion (but on an 12-bit resolution compared to a 10-bit Although the Flash-architecture is the most
resolution of the stand-alone version). In the same way, straightforward and simplest architecture, the number of
the embedded version takes advantage of the fact that comparators and their accuracy in terms of offset grow
only 80-MHz of bandwidth is required, but at the same exponentially with the number of bits required in the
time pushes the clock-frequency to give more headroom converter. The subranging architecture solves that prob-
to filtering. lem by taking a Two-Step or Multi-Step (Pipeline or

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 AiD D/A AiD
Coarse-bits Fine-bits
Fig. 4. Subranging architecture. Usually there is 1 bit of
overlap between Coarse and Fine ADC to allow correc-
tion of errors of the Coarse-ADC (see fig. 5).
SAR) approach (Fig . 4) . First a Coarse-ADC makes a
rough estimate where the input signal is. Then the archi-
tecture zooms in on that estimate, by subtracting the
coarse-estimate from the input signal (through the
DAC) and subsequently magnifying the residue-signal
with an amplifier. In a second step a Fine-ADC deter-
mines the value of the input signal more accurately. This
idea forms the core of most of the known data-converter
architectures, including Two-Step, Subranging, Pipelin-
ing and Successive Approximation Registers (SAR)
based ADCs .
The action of subranging requires that in one
clock-cycle the Coarse comparators take a decision ,
subsequently drive the DAC to subtract the coarse-esti-
mate from the input sif,rnal and feed the residue-signal to
an amplifier, which then amplifies the difference and
supplies the result to the Fine-ADC. This requires care-
ful timing and precludes the use of digital latches fol-
lowing the comparators to improve the BER. Running
such an architecture at high clock-speeds requires very
good comparators (very low BERs) or the system
should allow moderate to bad ADC-BERs.
C. Error-Correction using Overrange [16]
If the signal is close to the boundary between two
adjacent sub-ranges, it is possible that the coarse esti-
mate selects the wrong sub-range. However, this prob-
lem can be easily solved by reducing the gain of the
residue amplifier and mapping the subranging on a
smaller portion of the input range of the Fine-ADC (fig.
5a). The additional part of the Fine-ADC range is called
overrange. If the input signal is close to an edge of the
subrange and by mistake selects the wrong subrange
(fig. 5b), then the residue-signal does not fall in to the
intended range of the Fine-ADC, but in the overrange.
However, since the Fine-ADC can still perform well in
the overrange, the error can be recovered and the Coarse
bits can be corrected.
In essence, this technique is possible because the
next stage can look more accurately as a result of the
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Q) Q)
0)
c
0)
c
~ ~
Q; Q;
a > b >
0 0
Fig. 5. The use of overrange for error correction, a) the
regular situation, b) the signal goes in overrange.
extra gain between the stages and in tum the extra gain
is possible because the next stage does not have to han-
dle the entire range as a result of the zooming-action.
Almost all architectures using subranging, like Two-
Step, Subrange, Pipeline and SAR make use of this cor-
rection technique.
D. Pipeline Architecture [16-26]
Of coarse the principle of sub-ranging can be
repeated in the Fine-ADC. If we cascade several of
those stages , we can perform one sub-range conversion
per clock-cycle and each clock-cycle the signal ripples
through this cascade of sub-range blocks . This architec-
ture is called a Pipeline ADC and is shown in fig. 6a.
The Pipeline ADC is one of the most popular
ADC architectures. Extracting only 1 or a few bits per
stage (and then passing it on to the next stage, the real
pipelining) keeps the problem per stage simple, the
throughput high (because only 1 or a few bits are
resolved per clock-cycle the clock-speed can be rela-
tively high) and still reduces the problem for the next
stage by the number of bits resolved in the stage (2
times simpler in a l-bit-pcr-stagc architecture). This
architecture lends itself well to several forms of error-
correction, of which using overrange as discussed above
is the simplest one. But in the past decade many more
elaborate error-correction techniques have been devel-
oped, allowing either better performance or lower power
for the same performance (see section VII).
E. Succ essive Approximation Register ADC [27-32]
The SAR-ADC uses the idea of subranging in a
slightly different way and is shown in fig. 7. Instead of
using multiple stages, all the bits get resolved in 1 single
stage, but at a rate of 1 bit per clock-cycle. The DAC in
the feedback-loop slowly approaches the value of the
input signal. To that purpose, the comparator decides
each clock-cycle whether the approximation of the DAC
needs to be corrected up or down and the SAR-Iogic
 a)
AID D/A AID
Stage 1
b)
1 Digital Domain
Fig. 6. A Pipeline Converter with a) the first 3 stages and b) gain-calibration in the digital domain.
keeps track of all the decisions and drives the DAC
through a binary-search algorithm . The strong points of
this architecture are it's simplicity, the total omission of
gain-elements (amplifiers), and the insensitivity to off-
sets. This allows for very low power implementations.
However, it needs N clock-cycles for N bits of resolu-
tion, which limits the maximum achievable conversion
rate. Although this architecture has been around for
quite a long time, the low conversion speed has pushed
it's use to the background for a significant amount of
time. Recently, interleav ing (section VI.G) has been
used to solve this issue [27-32], with very good results.
Because of it's inherent low-power features and
progress in interleaving techniques, SAR-ADCs have
become very popular again [27-32].
F. Folding and Interpolating ADC [33-38J
Folding is a technique that has been around for a
long time and has becom e popular in Bipolar technol-
ogy [33]. It is a form of Analog pre-processing that aims
to reduce the number of comparators by using the same
comparator for more than one decision . In fact, Folding
is an implementation of subranging without making usc
of a coarse ADC to determine the subrange and not nec-
essarily using clocked-clements like comparators.
o times the overall intended speed. When combined in the
J (1)'-
>0)
.- 0
f/)...J
:g .
o ><
o ~
~c..
cnc..
« connecting the SHA to each of the N slices are needed .
Fig. 7. Successive Approximation Register (SAR) ADC.
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D/A AID D/A
Stage 2 Stage 3
Contains
Error-Signal
A significant advantage of Folding is that it does
not use comparators for the folding-action. As opposed
to other subranging architectures the clock-speed does
not get limited by the fact that comparator decisions
have to be used to select the next subrange . In that
respect the Folding-architecture falls in the category of
Flash-type architectures that in principle can have
extremely good BER by adding latches at the end. This
does increase the latency, but one or two clock-cycles
does not necessarily have to be a problem .
Folding is still being used today in fast sampling
ADCs with moderate resolution [34-38]. In [38], folding
is pushed to another level again, showing a pipelined
folding implementation of 729-times folds, with coarse-
comparators in every folding-block, making the distinc-
tion between Folding and Pipelining even more subtle .
G Interleaving [29-32, 37-39J
Every ADC-architecture has a certain maximum
conversion speed in a certain process technology. When
pushed to this limit, the efficiency in terms of perfor-
mance-per-mW power-dissipation will go down. If
either a conversion speed exceeding what was deemed
feasible in a particular technology, or improved effi-
ciency is needed, parallelism in the form of interleaving
can be used. The effect of this is an exchange of hard-
ware for speed. Interleaving [39] is implemented with N
slices of the same ADC in parallel, each running at lIN
digital domain, the overall intended conversion speed
can be obtained .
There are however, a few problems in this
approach that have to be dealt with. When only the ADC
is interleaved and is driven by a single SHA, N switches
The SHA supplies each of the slices with samples at the
 rate of that individual slice and is rotating through the N
slices. In that case the SHA itself needs to run at the
overall conversion speed. That makes the SHA the hard-
est block to design and also limiting the conversion
speed.
There are also errors introduced by the interleav-
ing technique itself. Mismatch between the slices will
cause offsets and gain-errors for each slice. If N slices
are interleaved and Fsamp is the overall sampling speed,
offsets between the individual slices will cause tones at
multiples of FsamplN. If the input frequency equals Fin'
Gain-errors between the slices will cause tones of Fin
around the same multiples of FsamplN (at nFsamplN +/-
Fin' with 0 < n < N). Generally speaking, these tones
will fall in the signal band-of-interest and need to be
kept to a minimum. Offset and Gain-calibration tech-
niques [37] or redundancy [30] have been proposed to
deal with these problems.
If the SHA cannot meet the required sampling
speed, it can be built of interleaved slices as well. This
however, introduces additional errors, usually even
harder to deal with. Now, due to mismatches, the sam-
pling moments might deviate from the ideal uniform
sampling grid. This also causes tones of Fin around mul-
tiples of FsamplN. These tones however, cannot be can-
celled by the gain-calibration techniques because of
phase-differences.
Differences in bandwidth also generates tones at
the same spot in the spectrum, but now the magnitude of
the tones are signal-frequency dependent. This compli-
cates the problem very substantially and requires very
significant signal processing to be solved. In [61] an
embedded solution is shown where all lanes are kept
separate in the Analog domain and in the digital domain
the lanes are combined using a MIMO-FFE (Multiple-
Input Multiple-Output Feed Forward Equalizer), allow-
ing the lanes to be equalized individually. This is a per-
fect example allowed by an embedded environment,
impossible for stand-alone solutions.
Table 2: Interleaved ADCs pushing the sampling speed
Ref NOB ENOB ERBW F samp
[58] 8 6.5 2.0 20 80
[59] 11 8.8 0.4 1.0 8 problematic indeed.
[60] 11 9.2 0.4 0.8 4
[29] 10 7.9 1.0 1.35 16
In the past decade interleaving of pipeline ADCs
has been pushing the conversion speed in to the GHz
range. Table 2 gives an overview. Due to the above men-
tioned additional problems of the interleaving technique
itself, the overall ENOB never reaches the ENOB of a
single slice. Note that in table 2 on average the ENOB is
almost 2 bits lower than the NOB.
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VII. ADVANCED CALIBRATION TECHNIQUES
As stated before, the embedded environment is
ideally suited for digital-aided analog design, allowing
better performance at lower power-dissipation levels.
New advances in Error-Correction and Calibration are
being discussed in the following paragraphs.
A. Gain Calibration Techniques [17-26]
One of the main sources of errors in Pipeline
converters is a deviation of the amplifier gain from the
ideal value of 2m (see fig. 4). As a result the transition
from one subrange to another will show a sudden jump,
resulting in a spike in the DNL-curve. Many papers
have been published to correct these errors [17-26].
If an estimate could be made of the actual ampli-
fier-gain' then these errors could be corrected in the dig-
ital domain by changing the radix accordingly. The
principle of estimating the amplifier gain is depicted in
fig. 6b. A small pseudo-random signal is injected at the
input of the DAC in Stage 1 and gets subsequently con-
verted to the Analog domain. It then goes through the
analog "2x" amplifier and is fed to Stage 2. Simulta-
neously, in the digital domain, the pseudo-random signal
is passed through an ideal "2x" amplifier and fed to the
DAC of Stage 2. If both path match (i.e. if the Analog
"2x" amplifier has a gain of exactly 2), then the two sig-
nals cancel at the input of the "2x" amplifier in stage 2.
Any deviation from the ideal value of 2 will result in a
finite "error" signal that can be detected in the digital
domain at the output of the ADC of Stage 3 by correlat-
ing that signal with the pseudo-random signal. This can
be used to slowly adapt the radix in the digital domain to
match the Analog gain.
This technique could be implemented in the fore-
ground during start-up, using substantial calibration sig-
nal-levels, but it is also often done in the back-ground
(during normal operation). The disadvantage is that the
pseudo-random signals needed for the training have to
be small with respect to the regular signal and a correla-
tion techniques with long averaging is needed to extract
the error signals correctly, taking a long time to con-
N
verge. While during normal operation this might not be
a problem, during production testing this can be very
B. Amplifier Nonlinearity Calibration [22,26,53]
Gain-errors are not the only artifacts being cali-
brated in Pipeline ADCs. Recently papers have been
published that go much further [22,26, 53].
In [53] a converter is proposed that also cali-
brates for 3rd-order amplifier distortion. The principle is
rather simple. Instead of a single pseudo-random signal,
a sum of 3 uncorrected pseudo-random signals is
injected at the input of the DAC in the sub-range block
of a Pipeline ADC. If the amplifier has a 3rd order dis-
 tortion component with coefficient u3' then in the output
signal of the amplifier a component will be present
equal to the product of the 3 pseudo-random signals and
u3. This component is then digitized again by the next
stage ADC. Correlating the signal at the output of the
ADC with the product of the pseudo-random signals
yields an estimate of u3. This estimate can be used to
cancel the 3rd-order distortion terms in the digital
domain. The same paper [53] also shows an implemen-
tation of their previously published DAC-DNL cancel-
lation. Although active area is relatively high, very good
results have been obtained indeed.
C. Split-ADC Calibration Technique [54-57]
To tackle the problem of long convergence times,
techniques have been investigated that make use of
deterministic methods as opposed to the statistical meth-
ods described in the previous section. Recently a very
elegant method for Pipeline-calibration has been pro-
posed [54 - 57]. The technique is based on the simple
idea of splitting an ADC in two half-circuits, each con-
suming exactly 50% of the power, with devices exactly
50% of the original size (in width) and each functioning
as a complete ADC. If both circuit halves are being
operated simultaneously on the same input signal, and if
in the digital domain the resulting converted signals are
added, the overall performance should be exactly equal
to the performance of the ADC before it was split in to
two half-circuits. However, due to random mismatches
and spreads, each half ADC will have a different offset
and gain-blocks will have slightly different gains. This
can be detected by looking at the differences between
the two circuit halves, any difference between the two
halves has to be an error. The technique is based on
using the difference between the two halves as an input
to the calibration engine to correct the errors in each of
the circuit halves. Since taking the difference between
the two halves cancels the regular signal, the calibration
engine only operates on error signals and converges
much faster.
Systematic errors present in both circuit halves
are not automatically cancelled this way, but with proper
knowledge of the error-mechanisms of a certain archi-
tecture, this may be solved as well. For instance, if this
technique is applied to a Pipeline ADC, each half will
produce a typical error plot with jumps at the transition
from one subrange to the next. If the two circuit halves
are deliberately given different coarse decision points,
then those jumps will appear at different spots for each
half-ADC. The result is that one half-ADC is generating
significant errors at a location where the other half-ADC
is hardly making any error at all and vice versa. By
looking at the difference between the two circuit halves
these errors can be detected and fed to the error-correc-
tion block [57].
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There are a few great advantages of this tech-
nique. First of all, from an Analog perspective, no extra
circuitry and no extra power dissipation is needed, the
two halves dissipate exactly 50% of the original power
dissipation. By combining (adding) the signals in the
digital domain, the original SNR is not degraded as
well. The second great feature of this technique is that
no calibration signal (like a small pseudo-random sig-
nal) is needed, the circuit can converge during regular
operation and uses the difference between the two
halve-circuits. The problem has become deterministic
and can converge orders-of-magnitude faster than the
techniques discussed in the previous sections.
D. Future Calibration Techniques
In principle, with the vast amounts of signal pro-
cessing power available around embedded Data Con-
verter, even more elaborate techniques could be
considered, for example techniques making use of FFT-
functions. Of special interest are techniques that make
use of advanced system information like the decision-
point (slicer) SNR. This would allow Data Converter
designs tailored exactly to the needs of the system at
hand.
Currently, most of the advanced calibration tech-
niques are still under investigation at Universities only
and implemented in Matlab. It will take a while before
these techniques end up in actual products. But undoubt-
edly techniques like these will be used in the future,
allowing even better performance at a lower power
level.
VIII. LOW POWER TECHNIQUES
Apart from calibration techniques to lower
power dissipation (and interleaving which indirectly can
have the same effect), other techniques that aim to
reduce power dissipation have been proposed recently.
Most of them try to either reduce the number of
OpAmps or substantially simplify them.
A. OpAmp sharing [41-43]
A straightforward implementation of a Pipeline
ADC uses one OpAmp per stage. Each OpAmp is oper-
ated in 2 phases, a reset-phase and an amplify-phase.
This means that only 50% of the time the OpAmp is
actively doing something and the other 50% is wasted.
The OpAmp-sharing technique makes use of this situa-
tion by using the OpAmp actively in both phases.
This was first done in Switched-Capacitor cir-
cuits [40] by sharing the OpAmps between two parallel
circuits that were operated out-of-phase and was called
double-sampling. In Pipeline-ADCs this can be done if
there are multiple ADCs in parallel, like for instance in
an I-and Q-path of an IF-section of a receiver, or when
multiple ADCs are interleaved. When this is not the
 case, then OpAmp-sharing can also be implemented
between successive stages of a pipeline [41-43].
Normally, a factor of two in power dissipation
reduction can be obtained. However, in the case of suc-
cessive stages, the stages are usually scaled down in
power to take advantage of reduced SNR requirements
of the following stage. In that case less than a factor of
two can be gained by this technique.
B. SHA-Iess ADCs [48-52]
The Sample & Hold Amplifier (SHA) preceding
most ADCs, has to be able to track the input signal with
sufficient linearity (similar to the entire ADC) and also
show the same SNR. The OpAmp used in the first pipe-
line-stage has to handle the same signal swing and has
similar noise requirements. These blocks are the two
most dominant blocks in linearity and noise and are
therefore consuming most power.
For that reason, several proposals have been
made to share the OpAmp between these two blocks,
which can lead to significant power-savings.
C. Openloop Residue Amplifier and Calibration [22]
With the idea in mind that errors caused by the
residue-amplifier can be corrected by digital calibration
(section VII), [22] have shown that it is feasible to use
openloop amplifiers in stead of closed-loop amplifiers
for this purpose. In this particular case a gain of 8x was
sufficient and, as a result of the absence of a loop, the
design is completely freed of any stability requirements.
That simplifies the amplifier design to a cascoded differ-
ential pair with resistive loads. An ENOB of 10.7 is
achieved while sampling at 75MS/s.
D. Incomplete Settling and Calibration [44]
Along the same lines, [44] proposes to allow
incomplete settling of its residu amplifiers to obtain
higher conversion speeds. Errors caused by this design
are calibrated again. Even lower power than [22] is
shown at similar performance.
E. Comparator-based ADCs [45-47]
OpAmps are among the most complicated analog
sub-blocks in data converters. They have to supply suf-
ficient gain to suppress any distortion to a low enough
level, they have to show low enough noise to support the
dynamic range of the converter and they also have to be
stable in feedback with sometimes varying load-condi-
tions. The main task of the OpAmp is to make sure the
feedback-capacitors see a sufficiently complete charge-
transfer by ensuring a very low virtual ground level at
the end of the clock-period.
Comparator-based ADCs accomplish the same
by using a comparator to switch off a current-source
when the charge-transfer is complete. To this purpose
the comparator checks the virtual ground for a zero-
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crossing. Comparators are simpler than OpAmps
because stability as well as linearity is no issue. This can
not only save a significant amount of power, but may
also enable even lower voltage operation than what is
possible for OpAmps. In [47] a lOb 26MS/s pipelined
ADC is realized in 65nm CMOS, operating from a 1.2V
supply and a power-dissipation of 5.5mW.
IX. OPTIMAL ARCHITECTURE?
A. No Real Favorite
Architectural choices can have a major impact on
the design of circuits. However, many of the architec-
tures discussed above have common properties and dif-
ferences are not always that obvious. Over the years
almost all architectures have retained their valid spot in
the spectrum of Data Converters and there are no obvi-
ous winners. Similarly, there are no obvious architec-
tural choices for embedded converters.
When decisions have to be made about architec-
tural choices, comparisons between architectures are
unavoidable. If data-points are available close to the tar-
get specifications, the comparison is easy. However,
often data points are available from (previous) designs
that are somewhat further away from the target specifi-
cations and sometime even further away. In those cases
a fair and relevant comparison can only be made
through extrapolation or interpolation. The question that
needs to be answered is then: given this performance,
what does it take to get to the desired performance?
Usually the primary aspects being considered are power
and sometimes area. Figures-of-Merit are exactly doing
that, they try to give an answer to the question: which
architecture can do the job for the lowest cost?
B. Figures-of-Merit (FOMs)
Popular FOMs [2] are trying to calculate the
power it takes per conversion-cycle per lsb and are cal-
culated as:
FOM = P / (2 ENOB 2F ERBW) (1)
in which P = Power Dissipation, ENOB Effective
Number of Bits and FERBW = Error Resolution Band-
width, which is the frequency at which the performance
has dropped by 0.5 ENOB. Usually the minimum of
FERBW and Nyquist-frequency (F clk/2) is used in (1) to
avoid the inclusion of subsampling.
Sometimes, instead of the Effective Number Of
Bits (ENOB), only the number of bits (NOB) are taken,
ignoring any lack in performance drop versus frequency,
which is less useful. Sometimes simply the Nyquist-fre-
quency is taken instead of FERBW. This ignores any
reduced performance below Nyquist. In that case, when
applied to oversampling ADCs, FNyquist is normally
substituted by 2 times the input bandwidth of the ADC.
 c. The use ofFOMs
Even though these FOMs are derived from vast
amounts of published data [2, 6], one has to be very
careful to apply this to individual architectures. The data
that was used to derive these FOMs ranged over many
different architectures, exhibiting vastly different values
for ENOB, Fclk , FERBW and Power. On top of that, only
the best performing converters were used to do the
curve- fitting.
The problem may be best shown using the fol-
lowing example. Ifa 4-bit Flash ADC (16 pre-amps and
16 comparators) needs to be improved to a 5-bit Flash,
the power would have to go up 2x for doubling the num-
ber of pre-amps and comparators and another 4x for
lowering the noise by 1 bit. This would cost 8x in
power, far more than the 2x predicted by the FOM of
equation (1). However, if a designer would keep doing
this to extend the number of bits to for instance 8, the
power dissipation would be horribly high and he would
be forced to go to another architecture (probably already
going from 4 to 5 bits).
For individual blocks, power estimates always are
proportional to the Dynamic Range squared (equivalent
to 22ENOB, instead of 2ENOB) [5]. However, the overall
power dissipation from ADCs built from those individ-
ual blocks, seems to fit better to the Dynamic Range to
the power of one [2, 6]. This has to be because generally
speaking adding one bit of resolution to the ADC
involves changing the architecture. That emphasizes the
fact that the design landscape for ADCs is far from
being smooth and is characterized by sharp transitions
going from one architecture to the next.
In practice this often means that in order to find
the best suitable architecture, different designs have to
be worked out to a reasonable level of detail before an
appropriate decision can be made.
Special care should be taken when considering
published FOMs. In the last couple of years there has
been a clear tendency to produce papers that can boast
of a very good FOM. For that reason often certain parts
of the power-dissipation are left out (like the SHA or
any form of input-buffer, the clock-drivers and the refer-
ences). However, what matters to the system is the total
power-dissipation and a well optimized AFE design.
X. TECHNOLOGY SCALING [1-7]
Many papers have been written about the effect
of technology scaling on Analog circuits [1 - 3, 5, 7] in
general and on Data Converters in particular [4, 6]. Up
until about 0.8um technology, the supply voltage had
been 5V for a long time. When it went down to 3.3V
many people were afraid that would be the end of the
dream of integrating analog with digital circuitry and
SoCs would never really happen. This discussion started
in the '90s and never really stopped. Every new drop in
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the supply voltage (2.5V, 1.8V, 1.2V, 1.0V, 0.9V) was
claimed again as the end of the road for SoCs and some
companies changed their focus to Multi-Chip Modules
(MCM) for that reason only. In the newest technologies
(90nm, 65nm, 45nm) the supply voltage hasn't scaled
down nearly as much as was originally predicted [7], but
new problems came to light, like gate-leakage or low
intrinsic gain. Nevertheless, non of these effects so far
stopped the progress on SoCs and in the past decade
SoCs have been shipping in all these technologies in
many millions per month. It doesn't look like that is
going to change for the next technology nodes either.
It can been shown that technology scaling has a
strong effect on power dissipation in analog circuits. In
[5] 24 different situations in Analog design have been
studied and categorized. But contrary to popular
believe, it is not only getting worse with lower supply
voltages. Dependent on the what dominates the lower
end of the dynamic range (noise or matching) and
dependent on whether the specifications are dominated
by small signal, large signal or feedback requirements,
the power can also go down with the scaling of the tech-
nology, especially in matching dominated situations.
Fact is that data converter performance has been dra-
matically improving over the past decade, especially in
the newer technologies. Many designs have taken
advantage of the higher speed, the higher density and
the better matching that each step in the progress of
technology scaling brings us.
Generally speaking, as a result of the large num-
ber of transistors (approaching a billion) integrated in
large SoCs, typical "Analog" problems like matching,
gate-leakage, subthreshold leakage and reduced intrinsic
gain, are becoming equally problematic for the digital
part of the chip. These problem will have to be and are
currently being solved, mostly in the technology
domain. Analog circuits will benefit from those solu-
tions equally, or even more than digital circuits [5].
XI. CONCLUSIONS
Designing embedded data converter entails dif-
ferent degrees of freedom compared to designing their
stand-alone counterparts: logic is for free, speed and
matching are great, but on the other hand supply volt-
ages are low, process options are too costly and the
design has to yield at defect density. The constant fear
that embedding analog circuits in large digital circuits
will become impossible started two decades ago, and is
still alive but is not supported by evidence. Some of the
fears have been put to rest (like cross-talk, which in the
'90s was believed to kill the path to SoCs, is not even in
the top 3 of current day embedded ADC designer prob-
lem-list anymore), but are being replaced by new fears
(like low intrinsic gain and gate-leakage). But fact is
that many extremely large SoCs (more than 200mm 2
 nd almost reaching a billion transistors) have been and
still are in very large volume production (many millions [21]
per month) and there is no sign this will stop in the near
future.
The effect this has on the design of data convert- [22]
ers is clear. More and more, "digital assisted" analog
design will become mainstream. The effect this has on
[23]
the choice of data converter architecture is less obvious.
Although pipeline converters have become very popular
in Nyquist-rate ADCs, almost all other architectures are [24]
still alive and it does not look like anyone of them will
win and obsolete the other architectures. Personal pref-
erences of and familiarity with certain architectures still [25]
have a very strong influence on what choices designers
make.
[26]
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