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Lab Report #02 (1737)
Lab Report #02 (1737)
Fall 2021
Control Signal
Registration No : 18 PWCSE1737
Class Section: B
“On my honor, as student of University of Engineering and Technology, I have neither given
nor received unauthorized assistance on this academic work.”
Submitted to:
G(s) = 10/s2+2s+20
Impulse Response:
Matlab:
Code:
clc
clear all
close all
num=[10];
denum=[1 2 20];
Sys=tf(num, denum);
plot(diff(step(Sys)));
title('Impulse Response');
Output:
Simulink:
Design:
Output:
Step Response:
Matlab:
Code:
clc
clear all
close all
num=[10];
denum=[1 2 20];
Sys=tf(num, denum);
figure
step(Sys);
title('Step Response');
Output:
Simulink:
Design:
Output:
Task#02:
Apply the sinusoidal input to the System G(s) = 10/s2+2s+10 in both Matlab and Simulink.
Compare both the results too. Also plot output vs input in both. (Hint: lsim)
Sol:
Matlab:
Code:
clc
clear all
close all
num=[10];
denum=[1 2 20];
t=1:0.01:10;
Sys=tf(num, denum);
figure
plot(sin(t));
title('input sinosoidal signal');
u=sin(t);
figure
lsim(Sys,u,t);
Output:
Simulink:
Design:
Output:
Task#03:
Apply the following input to the system in both Simulink and Matlab.
Sin(2 π t)+u(t)+2u(t-5)
Square input with amplitude equal to 1 and time period equal to 10 seconds. Simulate
the System for at least 40 seconds.
Combine both of the above inputs.
sin(2 π t)+u(t)+2u(t-5)
Matlab:
Code:
num= [10];
denum=[1 2 20];
t = 0:0.01:10;
Sys=tf(num,denum);
u=sin(2*pi*t);
y1=lsim(Sys, u, t);
y2=step(Sys, 0:0.01:10);
y3=step(Sys, 5:0.01:10);
temp=zeros(500, 1);
y3= [temp;y3];
y=y1+y2+y3;
plot (t,y)
Output:
Simulink:
Design:
Output:
Square input with amplitude equal to 1 and time period equal to 10 seconds. Simulate the
System for at least 40 seconds
Matlab:
Code:
Output:
Simulink:
Design:
Output:
Combine both of the above inputs.
Matlab:
Code:
num= [10];
denum=[1 2 20];
t = 0:0.01:10;
Sys=tf(num,denum);
u=sin(t);
y1=lsim(Sys, u, t);
y2=step(Sys, 0:0.01:10);
y3=step(Sys, 5:0.01:10);
temp=zeros(500,1);
y3= [temp;y3];
y4=square(t);
y4';
y=y1+y2+y3+y4';
plot (t,y)
Output:
Simulink:
Design:
Output: