IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO.

6, JUNE 2016 1385

A 2.2 GHz −242 dB-FOM 4.2 mW ADC-PLL

Using Digital Sub-Sampling Architecture
Teerachot Siriburanon, Student Member, IEEE, Satoshi Kondo, Member, IEEE, Kento Kimura, Tomohiro Ueno,
Satoshi Kawashima, Tohru Kaneko, Wei Deng, Member, IEEE, Masaya Miyahara, Member, IEEE,
Kenichi Okada, Senior Member, IEEE, and Akira Matsuzawa, Fellow, IEEE

Abstract—This paper presents an all-digital phase-locked loop
(AD-PLL) using a voltage-domain digitization realized by an
analog-to-digital converter (ADC) instead of adopting a tradi-
tional time-to-digital converter (TDC) which usually suffers from
a tradeoff in resolution and power consumption. It consists of an
18 bit class-C digitally controlled oscillator (DCO), a 4 bit com-
parator, a digital loop filter (DLF), and a frequency-locked loop
(FLL). Implemented in 65 nm CMOS technology, the proposed
PLL reaches an in-band phase noise of −112 dBc/Hz and an RMS
jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit
(FoM) of −242 dB was achieved with a power consumption of
only 4.2 mW.
Index Terms—All-digital phase-locked loop (AD-PLL),
analog-to-digital converter (ADC), CMOS, frequency synthesizer,
low-power, sub-sampling, voltage-domain.
I. I NTRODUCTION
T O SEAMLESSLY connect a billion devices in the Internet
of Things (IoTs), high-performance clocks with low jit-
ter are essential to synchronize their operation at high speed
with a large amount of data. This requires clock and fre-
quency synthesizers that exhibit low integrated phase noise or
jitter with low power consumption [1]. Conventionally, precise
clock generation can be achieved by using analog charge-pump
phase-locked loops (PLLs) [1]–[4]. Due to high gain in phase
detection, a sub-sampling PLL achieves lower jitter perfor-
mance with low power consumption [2]–[4]. Unfortunately, the
analog PLL loop filter occupies large area and it is difficult
to reconfigure. Moreover, in highly scaled CMOS technol-
ogy, the performance of analog PLLs tends to be limited by
Manuscript received September 20, 2015; revised December 26, 2015 and
March 01, 2016; accepted March 12, 2016. Date of publication May 02, 2016;
date of current version June 09, 2016. This paper was approved by Associate
Editor Pavan Kumar Hanumolu. This work was supported in part by MIC,
SCOPE, STARC, STAR, and VDEC in collaboration with Synopsys, Inc.,
Cadence Design Systems, Inc., Agilent Technologies Japan, Ltd, and Mentor
Graphics, Inc.
T. Siriburanon, T. Kaneko, M. Miyahara, K. Okada, and A. Matsuzawa are
with the Department of Physical Electronics, Tokyo Institute of Technology,
Tokyo 152–8552, Japan (e-mail: tee@ssc.pe.titech.ac.jp).
S. Kondo is with the Corporate Research and Development Center, Toshiba
Corporation, Kawasaki, Kanagawa 212–8582, Japan.
K. Kimura is with Fujitsu Limited, Kawasaki, Kanagawa 213–0012, Japan.
T. Ueno is with ADVANTEST Corporation, Gunma R&D Center, Gunma
370–0718, Japan.
S. Kawashima is with Toyota Motor Corporation, Toyota 471–8571, Japan.
W. Deng is with Apple Inc., Cupertino, CA 95014 USA.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2016.2546304
0018-9200 © 2016 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution
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device leakage and low supply voltages, causing degradation in
integrated phase noise and spur performance [5].
To operate a PLL in the digital domain through a scalable
digital loop filter, several architectures have been proposed,
e.g., a phase-domain AD-PLL which directly measures output
phase of a digitally controlled oscillator (DCO) with reference
clock through a counter and a time-to-digital converter (TDC)
for coarse and fine phase detection, respectively [6]–[10].
Alternatively, phase error from the divided feedback signal and
reference clock can be measured by means of a TDC as shown
in Fig. 1(a) [11]–[14]. For fractional operation, both architec-
tures require fine TDC resolution with at least one oscillator
period of dynamic range, which results in high power consump-
tion and area. On the other hand, in an integer-N AD-PLL, the
reference clock edge and feedback clock edges always align
and a wide dynamic range TDC is not necessary. This allows
the use of a simple 1 bit or bang-bang phase detector (BBPD).
However, to achieve wide bandwidth, a 1 bit TDC may suffer
from limit cycle behavior which results in jitter performance
degradation [15].
This work focuses on the development of a low-power
low-jitter AD-PLL in digital sub-sampling architecture which
enables multi-bit phase digitization with fine resolution that
does not exhibit a strict requirement on its dynamic range
for an integer-N operation [14], [16]. Fine resolution phase
digitization is developed by exploiting high detection gain of
time-to-voltage conversion using a sub-sampling phase detec-
tor which samples DCO waveforms by a reference clock [2]
and converts the voltage difference into the digital domain by
an analog-to-digital converter (ADC) as shown in Fig. 1(b) [17].
Without requirements for high resolution ADC, this approach
can result in high resolution in phase digitization with low
power consumption. The fractional operation can also be imple-
mented by dithering the reference clock edge or feedback signal
[18], [19], or digitizing the input waveform [20]. Moreover,
an energy-efficient class-C push-pull DCO is adopted with an
assistance from an adaptive bias scheme that provides robust
startup oscillation and enhancement in phase noise performance
at steady state.
This paper is organized as follows. Section II discusses phase
digitization in conventional time domain and proposed voltage
domain in its fundamental level. Section III describes the pro-
posed architecture using voltage-domain digital sub-sampling
architecture. Moreover, theoretical resolutions of the proposed
phase digitization and phase noise modelling of ADC-PLL are
1386
Fig. 1. Simplified diagram of PLLs and timing diagram of (a) conventional
time-domain approach using TDC and (b) proposed voltage-domain approach
using ADC.
analyzed. Section IV presents details of the important build-
ing blocks. Section V demonstrates the experimental results of
the proposed ADC-PLL. Finally, conclusions are summarized
in Section VI.
II. P HASE D IGITIZATION IN A LL -D IGITAL
P HASE -L OCKED L OOP (AD-PLL)
Typically, due to limited resolution of the phase digitization
in the traditional TDC, in-band phase noise is limited by the
quantization noise of TDC [6]–[13]. For a uniform phase noise
power spanned from dc to the Nyquist frequency, the close-in
phase noise due to TDC quantization noise is estimated as [21]
2 2
(2π) Δt 1
Lin−band = (1)
12 Tv fREF
where Δt is the resolution of the phase digitization and Tv is
the period of DCO output frequency. Therefore, to lower the
in-band phase noise, resolution of phase digitization should be
minimized.
A TDC can be implemented based on a delay line as shown
in Fig. 2. A high-speed signal is input to a delay line which
generates multiple references in time. Differential flip-flops are
usually utilized to compare each time reference with the rising
edge of the reference clock. Thus, the phase difference of the
high-speed signal and reference clock can be determined but
limited by a resolution of one inverter delay (td ). As technol-
ogy advances, the length of CMOS transistor becomes smaller
and results in higher speed [5]. Unfortunately, even in the cur-
rent advanced technology of 65 nm or 28 nm, the resolution is
limited to approximately 20 ps and 10 ps, respectively. From
(1), for 2 GHz carrier frequency, this refers to a limitation of an
in-band phase noise of approximately −97 and −105, respec-
tively. However, for highly precise clock or higher data-rates
application with high modulation scheme, the in-band phase
noise of the synthesizer should be lowered. To further improve
resolution, a number of techniques have been proposed, e.g.,
Vernier delay line [9], [22], [23], ring-oscillator-based [11],
[24], and time amplifier [10]. Fine resolution TDC usually
suffers from process-voltage-temperature (PVT) variation that
results in ambiguity in its full range as shown in Fig. 4(a) or an
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 6, JUNE 2016
Fig. 2. (a) Simplified diagram of traditional TDC and (b) timing diagram of
TDC.
Fig. 3. Full range of (a) time and (b) voltage domains.
uncertainty in propagation delay of each inverter which results
in an integral nonlinearity (INL) as shown in Fig. 5(b). For very
fine resolution TDC, jitter from delay elements could limit its
effective resolution. Timing uncertainty in each inverter can be
analyzed by assuming a rising edge is input to an inverter which
outputs a falling edge signal with a time delay of td as shown in
Fig. 5(a). Due to random voltage noise with a variance (σt2dN ),
an instant of threshold crossing away from an ideal slope of
IN /C, where IN is a discharged current of NMOS and C is
a load capacitance, generates timing uncertainty or jitter. This
originally derives from two uncorrelated white noise sources,
i.e., current noise integrating on load capacitance seen at the
output of each inverter and an initial noise on the load capaci-
tance as shown in Fig. 6(a). This variance can be expressed as
follows [25]:
2kTγN CVDD kTC
σt2dN = 2 + 2 (2)
IN (VDD − VtN ) IN
where k is Boltzmann constant, T is temperature, VDD is sup-
ply voltage, and VtN is threshold voltage of NMOS. It can
be observed that to lower the internal jitter in delay line,
higher current or larger inverter size is required. Unfortunately,
increasing the size of the transistors would result in larger
load capacitance. This results in high power consumption in a
fractional-N AD-PLL when fine resolution and wide dynamic
range is required. For an integer-N PLL, power consumption
can be relaxed since high resolution TDC with only a few
picoseconds dynamic range is required [14], [16].
In this work, operating in voltage domain, the input wave-
form from a DCO is first sampled by a sample-and-hold circuit.
Then, it is quantized into digital domain by an ADC. For an
ADC, precise voltage references can be generated which accu-
rately define its dynamic range as shown in Fig. 3(b). Second,
a linear voltage division from a simple resistive ladder can pro-
vide linear and accurate reference voltage for an ADC as shown
in Fig. 4(b). However, the input waveform may suffer from
SIRIBURANON et al.: A 2.2 GHz –242 DB-FOM 4.2 MW ADC-PLL USING DIGITAL SUB-SAMPLING ARCHITECTURE
(a) (b)
Fig. 4. Local mismatch of each reference point in its dynamic range (a) time
and (b) voltage domains.
Fig. 5. Resolution enhancement using amplifier in (a) time and (b) voltage
domains.
Fig. 6. Noise source that fundamentally sets the limits on phase variance in a
phase digitization of (a) conventional time domain and (b) proposed voltage
domain.
PVT variation which requires calibration when wide dynamic
range is required [20]. In this work, even though a linear con-
version from phase to voltage domain can only cover a few
picoseconds near zero crossing point, it is not an issue for an
integer-N operation as described earlier [14], [16]. Third, to fur-
ther improve resolution, a voltage amplifier can be used with
reasonable accuracy, good linearity, and small power consump-
tion. One of the most important noise sources in voltage domain
is from voltage noise on capacitors in a sampling process. The
variance of an equivalent time uncertainty can be derived by
normalizing the voltage noise to the slope of the input signal as
shown in Fig. 6(b).
kT/C
σt2samp = 2 (3)
(VDCO 2πfDCO )
where VDCO is the amplitude of input signal, and fDCO is the
oscillation frequency of input signal. It can be observed that
jitter is no longer a factor of current but kT/C noise. Higher
capacitance can be used to lower the noise from the sampler
1387
TABLE I
S UMMARY OF T IME VS . VOLTAGE D OMAIN P HASE D IGITIZATION
with a constraint in the dynamic range and ADC resolution.
This could result in excessively large power consumption and
area if the size of the sampling capacitor is not optimized. On
the other hand, in voltage domain, the voltage difference can
be amplified and resolution can be improved, e.g., considering
a voltage gain of 8 with a 4 bit ADC, the equivalent time reso-
lution can be less than 1 ps while consuming power of 2 mW.
Detailed consideration for all noise sources will be discussed in
the next section. As summarized in Table I, a voltage-domain
approach using an ADC has advantages in terms of capability
to generate stable and accurate references and achieve fine reso-
lution without tradeoff in drawing large current. This results in a
multi-bit phase digitization with fine resolution. Therefore, low
noise performance in an integer-N AD-PLL can be achieved in
voltage domain with low power consumption.
III. P ROPOSED A RCHITECTURE OF ADC-PLL
IN A S UB -S AMPLING A RCHITECTURE
A. Basic Operation
Instead of relying on phase detection in pure time domain,
voltage domain digitization is proposed by means of an ADC
that translates a sampled voltage from the input waveform of
the DCO into digital codes. Digital outputs are input to the
digital loop filter to control the DCO as shown in Fig. 7(a).
A reference clock is used to sample the waveform into voltage
domain, i.e., the phase difference is converted into voltage dif-
ference [2]. An ADC is used to convert voltage difference into
digital domain. In the case of a 3 bit ADC, 8 levels of volt-
age references are used to convert sampled voltage into digital
codes as shown in Fig. 7(b). It can be observed that higher res-
olution of the ADC would improve the resolution in voltage
and, consequently, improve the equivalent resolution in time
(Δt). An alternative approach is to amplify the sampled voltage
so that a simple ADC can be used to achieve higher resolu-
tion. Moreover, directly amplifying DCO waveforms requires a
high-speed amplifier with precise gain, which is not desirable.
In this work, the operation of the proposed ADC-based phase
digitization is illustrated in Fig. 8(a). The DCO signal is first
sampled by a sample-and-hold circuit as shown in Fig. 8(b).
After that, small voltage is amplified by a variable gain differen-
tial amplifier with gain G. Since it operates at reference clock,
this amplifier consumes much less power and can operate with
precision as shown in the hold part of Fig. 8(c). Note that the
1388 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 6, JUNE 2016

Fig. 7. (a) Simplified diagram of the proposed voltage-domain phase digitiza-

tion. (b) Time resolution with gain enhancement.

Fig. 9. Operation of the ADC-PD when reference (a) phase leading and
(b) phase lagging.

Fig. 8. Operation of the ADC-PD. (a) Overall simplified circuits and its
waveforms after (b) sample-and-hold and (c) amplification.

tracking part is also amplified but only the sampled voltage in

the hold part is input to an ADC. As discussed in the previ-
ous section, sampling noise on the loading capacitor acts as a
noise source in the ADC-based phase digitization (ADC-PD).
This will be discussed in detail in Section III-C. The amplified
voltage is input to an ADC and converted into digital domain.
For example, if the reference phase is leading the zero-crossing
point, an ADC generates more zeros than ones, as shown in
Fig. 9(a). On the other hand, if the reference phase is lagging,
there would be more ones than zeros as shown in Fig. 9(b). To
estimate an equivalent time resolution of the proposed ADC-
PD, sinusoidal input waveform from the DCO is quantized
Fig. 10. Equivalent resolution (a) without and (b) with effect of the resolution
from voltage domain to digital domain by an ADC as shown enhancement.
in Fig. 10(a). The resolution in voltage can be expressed as
where Vrange is dynamic range of an ADC, and N is the res-
Vrange olution of the ADC. An equivalent resolution in time can be
Δv = N (4)
2 derived from (4) with the slope of the input signal as follows:
SIRIBURANON et al.: A 2.2 GHz –242 DB-FOM 4.2 MW ADC-PLL USING DIGITAL SUB-SAMPLING ARCHITECTURE
Fig. 11. Conceptual diagram of adaptive gain and resolution enhancement
when N = 4, Vrange = 1 V, VDCO = 0.6 V, and fDCO is 2.2 GHz.
Δv
Δt ≈
{VDCO .sin (2πfDCO t)}
d
dt
Δv
= (5)
VDCO .2πfDCO .cos (2πfDCO t)
where VDCO is the voltage swing of the input signal, and
fDCO is the input frequency. From (4) and (5), the equiva-
lent time resolution when the input signal crosses t = 0 can be
expressed as
Vrange
Δt ≈ . (6)
2N .VDCO .2πfDCO
To further improve the resolution of the ADC-based phase
detector, a final equivalent time resolution can be approxi-
mated as
1 Vrange
Δt ≈ · N
G 2 · VDCO · 2πfDCO
where G is the gain of the variable gain amplifier. It can be
observed that the gain enhancement can improve an equivalent
resolution in time while operating at reference clock. Therefore,
fine resolution can be achieved without consuming large power
and area.
The conceptual diagram of the effect of resolution enhance-
ment is illustrated in Fig. 11. From (6), it can be observed that
an equivalent time resolution of ADC-PD with a unity gain is
7.5 ps. To avoid bang-bang settling behavior, this can allow a
larger dynamic range of 120 ps from 4 bit level of ADC in order
to bring the DCO phase into locked as shown in Fig. 11. Once
the phase has been captured, the gain of the variable ampli-
fier can be increased to improve jitter performance as a gain
of 10 would allow us to achieve 0.75 ps resolution in time
from (7). This allows a dynamic range of 12 ps, which is suffi-
cient to capture the phase of the ADC-PLL with a peak-to-peak
jitter of 2.3 ps.
B. Detailed Architecture
Fig. 12 shows the detailed block diagram of the proposed
ADC-PLL. It is composed of a frequency-locked loop (FLL)
1389
for frequency acquisition [26] and a core phase-locking loop
using ADC-PD in a digital sub-sampling architecture which
directly samples the output from the DCO without any divider
in the feedback path. The frequency of the DCO is digitized by
a 12 bit counter clocked by a slow reference clock. The digital
adder/subtractor compares the digitized frequency with a pre-
defined frequency controlled word (FCW) and feeds an 8 bit
frequency difference into a digital loop filter. The output of this
digital filter coarsely controls the oscillation frequency of the
DCO through 8 bit codes as shown in the upper part of Fig. 12.
The resolution of coarse tuning in an FLL is 1 MHz. Through
8 bit coarse tuning, it can cover the whole tuning range of the
DCO. For the phase locking path, the output of the DCO is
sampled by a bootstrapped sample-and-hold circuit in order to
reduce charge injection. Sampled values are input to a variable
gain amplifier which controls the gain of the phase detection
path. It initially achieves phase capturing with relatively smaller
gain and shifts to higher gain for lower jitter performance. The
outputs of the amplifier are input to a 4 bit flash ADC for con-
verting voltage signals into digital domains. The ADC clocks
are generated from the input reference clock, which will be
discussed in Section IV-C. The 4 bit output of the ADC is con-
trolled by the digital loop filter (DLF) consisting of proportional
and integral paths. This digital filter output determines whether
to increase, decrease, or hold the oscillation frequency of the
DCO. The first 7 bit output code of the DLF controls medium
capacitor bank of the DCO with resolution of 80 kHz, whereas
its fine bits achieve a resolution of 11.5 kHz which is further
dithered through a third-order delta-sigma modulator (DSM) to
increase the effective resolution of the DCO.
C. Phase Noise Modelling
(7)
In order to determine the characteristic of the proposed ADC-
PLL, the s-domain transfer function of the proposed ADC-PLL
is shown in Fig. 13. From the continuous approximation of the
z-domain model [21], the s-domain open-loop transfer function
of the proposed ADC-PLL at steady state can be derived as
 
KI fREF KDCO
Hopen (s) = GADC KP + (8)
s s
where GADC is the gain of the ADC phase detector, KP and
KI are the proportional and integral gain of the digital loop fil-
ter, and KDCO is the gain of the DCO. GADC can be expressed
as GADCO 2N /Vrange . The closed loop transfer function can,
therefore, be derived as follows:
Hopen (s)
Hclose (s) =
1 + Hopen (s)
GADC KDCO (KP s + KI fREF )
= 2 .
s + GADC KDCO KP s + GADC KDCO KI fREF )
(9)
It can be observed that the loop bandwidth of the PLL can
be controlled by adjusting gain G of the variable gain amplifier,
and the proportional and integral gain of digital loop filter.
1390
Fig. 12. Detailed block diagram of the proposed ADC-PLL.
Fig. 13. S-domain model of the ADC-based AD-PLL with noise sources added.
From Fig. 13, there are three main noise sources, i.e., noises
from the reference clock (φn,R ), the ADC phase detector,
and the DCO (φn,v ). The main noise contributors for the in-
band region are from the reference clock and phase detector
which includes quantization noise from the ADC-PD (φn,res ),
sampling noise (φn,samp ), input-referred noise of VGA noise
(φn,VGA ), and noise from the comparator (φn,comp ). Even though
there is no divider in the feedback path, the reference noise is
still multiplied by (fDCO /fREF )2 [2]. As discussed earlier, the
resolution of the conventional TDC is limited by an inverter
delay. In this work, instead of relying on pure time-domain
approach, sampling of the input signal helps in achieving
fine phase digitization. From Fig. 13 and (8), the closed-loop
transfer function of φn,res can be derived as
φv 1 Hopen (s)
Hn,res (s) = = · . (10)
φn,res G 1 + Hopen (s)
Equation (10) shows that the quantization noise from the
ADC-PD is reduced by a factor of gain G which is similar
to the discussion in Section III-A. Since the standard devia-
tion in time (σt ) can be found by normalizing the standard
deviation of phase (σφ ) to the angular frequency of the input
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 6, JUNE 2016
Fig. 14. Resolution in time of ADC-PD, and jitter from offset voltage of
comparator when N = 4, VDCO = 0.6 V, Vrange = 1 V, fDCO = 2.2 GHz and
offset voltage of comparator is 2.5 mVrms .
signal [21]. From (6) and (10), the in-band phase noise from
the quantization noise of the ADC-PD can be estimated as
2  2
1 σφ,n,res 1 Vrange 1
LADC−PD = 2 · = .
G fREF 12 G · VDCO · 2N fREF
(11)
Substituting equivalent time resolution of the ADC-PD in
(7) into (1) can yield the same result as (11). From Fig. 3,
it can be observed that the noises from comparator (φn,comp ),
which includes its input-referred noise and offset voltage, are
also suppressed by gain G from the same loop characteris-
tics. Therefore, both quantization noise from the ADC-PD
and jitter from comparator noises can be suppressed by G as
shown in Fig. 14. Moreover, phase noise contribution from the
SIRIBURANON et al.: A 2.2 GHz –242 DB-FOM 4.2 MW ADC-PLL USING DIGITAL SUB-SAMPLING ARCHITECTURE
Fig. 15. Theoretical limit of in-band phase noise in a digital sub-sampling
architecture considering noises from the sampler, VGA, comparator, quanti-
zation noise of ADC-PD, and reference clock.
quantization noise of the ADC-PD and offset voltage of the
comparator can also be lower as G increases.
To quantify other noise sources, let us consider the noise
from sample-and-hold circuits. It can be observed that the
closed-loop characteristic of φn,samp is simply the AD-PLL
closed-loop transfer function (Hclose (s)). Therefore, from (3),
the in-band phase noise contributed by the sampling noise can
be expressed as [2]
2
σφ,samp kT 1 is less than −140 dBc/Hz at 1 MHz offset. The total phase noise
Lsamp = = 2 . (12)
fREF CVDCO fREF
Considering a sampling capacitor of 40 fF and VDCO of 0.6 V,
the phase noise from sampling jitter would be −145 dBc/Hz
which is relatively lower than the quantization noise of the
ADC-PD and noise from the reference clock. Similar to sam-
pling jitter, input-referred noise of the VGA also passes through
the low-pass characteristics of the AD-PLL and the same analy-
sis can be applied. Fig. 15 shows the theoretical limit of in-band
phase noise of the proposed ADC-PLL when all the noise
sources in the phase detection are considered with 100 MHz
reference clock. This includes the input-referred noise of VGA,
input-referred noise and offset voltages of the comparator in the
ADC, quantization noise of the ADC-PD and reference clock.
In the case of using sampling capacitance of 40 fF, VDCO of
0.6 V, input-referred noise of VGA of 0.34 Vrms , and offset
voltage of comparator of 2.5 mVrms , and gain of more than 4,
in-band phase noise would be limited by phase noise from the
reference clock instead of other noise sources.
Another important noise source is the DCO which is high-
pass filtered by the loop as shown in Fig. 13. The resolution of
the DCO can set limits to the phase noise performance. In this
work, the resolution of the DCO is further dithered by the third-
order delta-sigma modulator (MASH1-1-1). The DCO phase
noise can be estimated as follows [21]:
 2  2n
1 Δfres 1 πΔf
LDCO = 2sin (13)
12 Δf fdth fdth
where Δfres is the frequency resolution of the DCO, Δf is off-
set frequency, fdth is the dithering frequency, and n is an order
of DSM. In this work, LDCO after dithering with 550 MHz clock
1391
Fig. 16. Detailed schematics of (a) DCO buffer and sample-and-hold circuit
and (b) its bootstrapping circuit.
of the proposed PLL is a combination of all the noise sources
above after being filtered by its loop transfer function. The
phase noise estimation of the proposed AD-PLL is determined
and compared with the experimental result in Section V.
IV. C IRCUIT I MPLEMENTATION
A. Sample-and-Hold Circuit
Fig. 16(a) and (b) shows the schematics of the VCO buffer
and sample-and-hold circuit and its bootstrapped circuit [27],
respectively. Even though a bootstrapped switch is used in this
work, a typical NMOS switch and sampling capacitance can
also be used since an integer-N AD-PLL does not require wide
dynamic range as discussed in Section II. A source follower
is used as a DCO buffer to provide linear conversion near the
zero crossing point similar to the approaches in [18] and [28].
The amplitude of the waveform is approximately 0.6 V after the
sample-and-hold circuit. A sampling capacitor (Csamp ) of 40fF
is chosen to provide good dynamic range and small area, and
bring noise contribution low compared to other noise sources as
discussed in Section III-C. Moreover, the sampling input wave-
form could cause charge injection from the sampling switches
to the DCO. However, the DCO buffer is used as an isolation
that alleviates its effect to the oscillator as explained in [28].
As a result, a reference spur of less than −70 dBc has been
achieved.
B. Variable Gain Amplifier (VGA)
Fig. 17 shows the schematic of the variable gain amplifier
(VGA) which is a source-degenerated amplifier [29]. Its gain
1392
Fig. 17. (a) Schematic of variable gain amplifier (VGA) and (b) its gain
characteristics over VGC .
control G is done by varying the source resistance from bias
voltage (VGC ). Common-mode feedback (CMFB) is employed
in order to stabilize the common-mode voltage. The gain of the
VGA can be varied from 1 to 20 dB as shown in Fig. 17(b)
with a 3 dB bandwidth of approximately 400 MHz in the worst
corner. From simulation, gain variation over process variation
requires pre-calibration as the gain could be doubled or halved.
Supply variation from 0.9 to 1.0 V does not affect the gain
significantly. For temperature variation, calibration circuitry
may be necessary when operating across −20 to 100◦ C since
normalized gain could vary from −20 to 50%. The input capac-
itance of the VGA is approximately 7fF. Combined with the
capacitance on the sample-and-hold circuit, the loading capaci-
tance is approximately 50 fF. From post-layout simulation, the
input-referred noise of the VGA is 0.34 mVrms . Following the
analysis in Section III-C, this is equivalent to −143 dBc/Hz.
From a 1 V supply, the VGA consumes 0.5 mW.
C. Four Bit Flash Analog-to-Digital Converter (ADC)
In this implementation, a 4 bit flash ADC with resistively
averaged voltage-to-time amplifiers is used to quantize the input
signal from VGA into digital domain. As shown in Fig. 18(a),
an array of 21 comparators is adopted where each of the com-
parators is composed of a voltage-to-time amplifier followed by
a two-stage SR latch [30]. The schematic of the voltage-to-time
amplifier, which is based on dynamic preamp of double-latch-
type comparator with a positive feedback circuit, is shown in
Fig. 18(b). Fig. 18(c) shows the corresponding output wave-
forms of voltage–time amplifier, the first-stage SR latch and the
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 6, JUNE 2016
second-stage SR latch, respectively. Finally, Fig. 18(d) shows
the timing diagram of associated clocks in an ADC which are
generated from the input reference clock. During the reset phase
(φL = 0), M5 and M6 pre-charge the DP and DN nodes to the
supply voltage. After the reset phase, φL turns to high, M5
and M6 are turned off, and M7 and M8 are turned on. At DP
and DN nodes, the voltage drops with a rate determined by
the input differential voltage and an input-dependent time dif-
ference will build up. M3 and M4 form a positive feedback
circuit to enhance the gain of the voltage-to-time conversion.
Resistors averagely stabilize the slope of the output from the
dynamic amplifier in order to reduce the mismatch voltage [30],
[31]. After that, DP and DN are input to the first and second
stages of SR latches which determine zero/one decision (QA ,
QA B) and stabilize the digital output (Q, QB), respectively,
as shown in Fig. 18(c). Four dummy dynamic amplifiers and
latches are placed at the top and bottom of an array of com-
parators that gives 4 bit outputs to improve the linearity as
shown in Fig. 18(a). According to post-layout simulation, the
offset voltage by process variation and input-referred noise of
the dynamic amplifier are 2.5 mVrms and 0.39 mVrms , respec-
tively [30], which contribute to an in-band phase noise of less
than −145 dBc/Hz when G = 8 and negligibly smaller than the
other factor.
D. Push-Pull Class-C Digitally-Controlled Oscillator (DCO)
Similar to the conventional class of VCOs, the class-C
CMOS VCO has a theoretically 6 dB lower phase noise com-
pared to class-C NMOS VCO when operating in current-limited
region [32], [33]. If the operation of the push-pull VCO enters
the voltage-limited region, the conduction angle of the devices
increases and the drain current shapes are widened, which
degrades dc-to-RF current conversion efficiency [32]–[34]. To
avoid such issues, both NMOS and PMOS transistors should
remain in the active region. Thus, they should satisfy the
following conditions:
VCM + At < Vg,p − At + |Vth,p | < VDD (14)
VCM − At > Vg,n − Vth,n + At > 0. (15)
By assuming the same common-mode voltage, maximum
oscillation amplitude is limited by
At < (Vg,p − Vg,n + |Vth,p | + Vth,n )/4 (16)
where VCM is the common-mode voltage, Vg,p is the gate bias
voltage of the PMOS transistor, Vth,p is the threshold volt-
age of the PMOS transistor, Vg,n is the gate bias voltage of
the NMOS transistor, and Vth,n is the threshold voltage of the
NMOS transistor. According to (16), the maximum oscillation
swing can be enhanced by a larger difference between the gate
biases of PMOS and NMOS. However, an increase in Vg,p and
a decrease in Vg,n leads to maximum oscillation amplitude,
and their transconductance drops. To ensure their oscillation
start-up, relatively higher and lower gate biases for NMOS and
PMOS, respectively, are necessary at the initial state. Once
steady oscillation has been built, Vg,p and Vg,n can adaptively
SIRIBURANON et al.: A 2.2 GHz –242 DB-FOM 4.2 MW ADC-PLL USING DIGITAL SUB-SAMPLING ARCHITECTURE 1393

Fig. 18. (a) Schematic of 4 bit flash ADC with resistive averaging. (b) Schematic of voltage-to-time amplifier.(c) Output waveforms of each stage. (d) Timing of
associated clocks.

change their values to become higher and lower, respectively,
which in turn maximizes oscillation swing with better phase
noise performance at the steady state. However, if the common-
mode voltage of the tank is not centered between the oscillation
swings, the largest oscillation swing cannot be achieved with-
out pushing either NMOS or PMOS into triode region. In this
work, an automatic adjustment is guaranteed by an adaptive
bias for PMOS gate as shown in Fig. 19. The common-mode
voltage of oscillation is set by a reference branch on the top
left-hand corner of Fig. 19. Once an oscillation starts, Vbias_n
decreases so that the voltage at the source of the NMOS cross-
coupled pair reaches the reference value (Vref ) [35]. On the other
hand, Vbias_p also adaptively changes to a higher value at steady
state to maintain VCM in the reference value. Without a need for
additional reference bias, this reference voltage can be gener-
ated by a resistive divider from Vbias_n and Vbias_p . Fig. 20 shows
the simulated gate bias voltages for PMOS and NMOS cross-
coupled pairs that are both enhanced at the oscillation start-up
and adaptively changed as it enters the class-C operation for an
enhanced swing.
V. E XPERIMENTAL R ESULTS
The ADC-PLL is fabricated in 65 nm CMOS technology.
Fig. 21 shows the chip microphotograph. The areas for DCO,
ADC-PD, and digital blocks are 0.13 mm2 , 0.01 mm2 , and
0.01 mm2 , respectively. Fig. 22 and Fig. 23 show the frequency
spectrum and the measured phase noise plots at 2.2 GHz
1394
Fig. 19. Class-C push-pull VCO with adaptive bias circuitry.
Fig. 20. Simulated adaptive biases for gate bias of PMOS (Vbias_p ), NMOS
(Vbias_n ) and common-mode voltage of tank (VCM).
Fig. 21. Chip microphotograph.
evaluated by a spectrum analyzer (Agilent E4407B), and a sig-
nal source analyzer (Agilent E5052B), respectively. When the
bias of the VGA (VGC ) is 300 mV with an approximated gain of
2, the PLL bandwidth is approximately 600 kHz which results
to an in-band phase noise of −100 dBc/Hz. By increasing VGC
to 420 mV with an approximated gain of 8, the PLL band-
width extends to 3 MHz and the measured in-band phase noise
is −112 dBc/Hz at 300 kHz offset, while the integrated jit-
ter (10 kHz–40 MHz) is 0.38 ps. Fig. 24 shows the measured
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 6, JUNE 2016
Fig. 22. Measured frequency spectrum at a carrier frequency of 2.2 GHz.
Fig. 23. Measured phase noise characteristic at 2.2 GHz with VGC of 0.30 V,
0.35 V, and 0.42 V.
Fig. 24. Measured and simulated phase noise characteristic at 2.2 GHz.
phase noise in comparison with simulated phase noise derived
in Section III-C with consideration of measured DCO and ref-
erence phase noises that are shaped by the loop characteristics
when G is equal to 8. The frequency tuning range of the DCO
is 2.15 to 2.35 GHz. The reference clock is 100 MHz, and the
reference spur is −74 dBc. From 1.0 V supply, the power con-
sumption of DCO and its buffer is 1.5 mW, pre-amplifier (VGA)
consumes 0.5 mW, and the 4 bit flash ADC consumes 1.2 mW.
SIRIBURANON et al.: A 2.2 GHz –242 DB-FOM 4.2 MW ADC-PLL USING DIGITAL SUB-SAMPLING ARCHITECTURE
TABLE II
P ERFORMANCE C OMPARISON WITH S TATE - OF - THE -A RT I NTEGER -N D IGITAL PLL S
∗ PLL FoM is calculated from Eq. (17)
∗∗ Estimatedfrom figure
∗∗∗ Normalized In-band phase noise = In-band PN − 20 log(f
The digital blocks consume 1.0 mW, including the digital loop
filters, delta-sigma modulator, and its FLL.
Table II shows a performance comparison with the state-of-
the-art integer-N AD-PLLs. The proposed ADC-PLL achieves
competitively low in-band phase noise when compared with
[14], [26], [36], [37] while consuming 4.2 mW. Unlike BB-
based AD-PLLs which usually suffer from limited bandwidth
to avoid limit cycle, the proposed ADC-PLL achieves low
in-band phase noise performance exploiting the sub-sampling
phase detector for multi-bit high resolution with low power con-
sumption. Comparing the measured results with the analysis
in Section III-C shown in Fig. 24, it can be observed that the
noises from ADC-PD are below phase noise contribution from
reference clock which is the major noise source that limits the
in-band phase noise performance. In this work, the phase-noise
figure of merit (FoM) is −242 dB at 2.2 GHz output frequency,
where the FoM is defined as follows [38]:
 
σ  PDC
t
FoM = 20log + 10 log (17)
1s 1 mW
where σt is the integrated jitter, and PDC is the power consump-
tion. The proposed PLL achieves an FoM that is comparable
with the state-of-the-art work [14], [26], [36], [37] as shown in
Table II.
VI. C ONCLUSION
The ADC-based AD-PLL (ADC-PLL) is proposed using
voltage-domain digitization in sub-sampling architecture.
Resolution of phase detection in digital domain can be
1395
DCO /fREF ) − 10 log(fREF ) [11]
enhanced by voltage amplification. The voltage domain
approach shows the possibility of achieving high resolution in
phase digitalization which helps in achieving low in-band phase
noise in an AD-PLL.
ACKNOWLEDGMENT
The authors would like to thank Professor Robert Bogdan
Staszewski, Dr. Guanzhong Huang, and Yizhe Hu for their
technical discussions.
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Teerachot Siriburanon (S’10) received the B.E.
degree in telecommunications engineering from
Sirindhorn International Institute of Technology
(SIIT), Thammasat University, Pathumthani,
Thailand, in 2010, the M.E. and Ph.D. degrees
in physical electronics from the Tokyo Institute
of Technology, Tokyo, Japan, in 2012 and 2016,
respectively.
He is currently working as a postdoctoral
researcher at University College Dublin (UCD),
Dublin, Ireland. His research interests are CMOS
wireless transceiver systems and clock/frequency generations for wireless and
wireline communications.
Dr. Siriburanon was the recipient of the Japanese Government (MEXT)
Scholarship, the Young Researcher Best Presentation Award at Thailand–Japan
Microwave in 2013, the ASP-DAC Best Design Award in 2014 and 2015, the
IEEE SSCS Student Travel Grant Award in 2014, the IEEE SSCS Predoctoral
Achievement Award in 2016, and the Tejima Research Award in 2016.
Satoshi Kondo (S’10–M’14) received the B.E.
degree in electrical engineering from Gunma
National College of Technology, Gunma, Japan, in
2012, and the M.E. degree in physical electronics
from the Tokyo Institute of Technology, Tokyo,
Japan, in 2014.
He joined the Corporate Research and
Development Center, Toshiba Corporation,
Kawasaki, Japan, in 2014. His current research
includes CMOS RF circuit design and analog/digital
PLL frequency synthesizers.
Kento Kimura received the B.E. degree in electri-
cal and electronics engineering and the M.E. degree
in physical electronics from the Tokyo Institute
of Technology, Tokyo, Japan, in 2013 and 2015,
respectively.
He is currently with Fujitsu Limited, Kawasaki,
Japan. His research interests include RF/millimeter-
wave transceiver systems and clock/frequency
generation systems for high data-rate wireless
communications.
Tomohiro Ueno received the B.E. and M.E. degrees
in physical electronics from the Tokyo Institute
of Technology, Tokyo, Japan, in 2012 and 2014,
respectively.
He is currently working for ADVANTEST
Corporation, Gunma, Japan.
SIRIBURANON et al.: A 2.2 GHz –242 DB-FOM 4.2 MW ADC-PLL USING DIGITAL SUB-SAMPLING ARCHITECTURE
Satoshi Kawashima received the B.E. degree in elec-
trical and electronics engineering and the M.E. degree
in physical electronics from the Tokyo Institute
of Technology, Tokyo, Japan, in 2013 and 2015,
respectively.
He is currently with Toyota Motor Corporation,
Toyota, Japan.
Tohru Kaneko received the B.E. degree in electri-
cal and electronic engineering and the M.E. degree
in physical electronics from the Tokyo Institute of
Technology, Tokyo, Japan, in 2013 and 2015, respec-
tively. He is currently pursuing the Ph.D. degree in
physical electronics at Tokyo Institute of Technology.
His current research includes wide bandwidth
amplifiers and filters.
Wei Deng (S’08–M’13) received the B.S. and M.S.
degrees from the University of Electronic Science and
Technology of China (UESTC), Chengdu, China, in
2006 and 2009, respectively, and the Ph.D. degree
from the Tokyo Institute of Technology, Tokyo,
Japan, in 2013, all in electronic engineering.
He is currently with Apple Inc., Cupertino, CA,
USA, working on mixed-signal, analog, and RF IC
design for Apple A-series processors. During 2013 to
2014, he was a postdoctoral researcher at the Tokyo
Institute of Technology, leading a team for mixed-
signal, RF, and mm-wave IC design. He has authored and co-authored 50
journals and conference papers. His research interests include wireless/wireline
transceivers, clock/frequency generation systems, and data converters.
Dr. Deng has been the recipient of several national and international awards,
including the China Youth Science and Technology Innovation Award in
2011, the IEEE SSCS Predoctoral Achievement Award in 2012, the Chinese
Government Award for Outstanding Self-financed (non-government sponsored)
Students Abroad in 2013, the Tejima Research Award in 2013, and the
ASP-DAC Best Design Award in 2014 and 2015.
Masaya Miyahara (M’09) received the B.E. degree
in mechanical and electrical engineering from
Kisarazu National College of Technology, Kisarazu,
Japan, in 2004, and the M.E. and Ph.D. degree
in physical electronics from the Tokyo Institute
of Technology, Tokyo, Japan, in 2006 and 2009,
respectively.
Since 2009, he has been an Assistant Professor
in the Department of Physical Electronics, Tokyo
Institute of Technology. His research interests are RF
CMOS and mixed-signal circuits.
1397
Kenichi Okada (S’99–M’03–SM’16) received the
B.E., M.E., and Ph.D. degrees in communications and
computer engineering from Kyoto University, Kyoto,
Japan, in 1998, 2000, and 2003, respectively.
From 2000 to 2003, he was a Research Fellow
of the Japan Society for the Promotion of Science
in Kyoto University. From 2003 to 2007, he was an
Assistant Professor at the Precision and Intelligence
Laboratory, Tokyo Institute of Technology,
Yokohama, Japan. Since 2007, he has been an
Associate Professor in the Department of Physical
Electronics, Tokyo Institute of Technology, Tokyo, Japan. He has authored or
co-authored more than 300 journal and conference papers. His current research
interests include millimeter-wave CMOS wireless transceiver, digital PLL, 5G
mobile system, and ultra-low-power RF circuits.
Dr. Okada is a member of the Institute of Electronics, Information and
Communication Engineers (IEICE), the Information Processing Society of
Japan (IPSJ), and the Japan Society of Applied Physics (JSAP). He received
the Ericsson Young Scientist Award in 2004, the A-SSCC Outstanding Design
Award in 2006 and 2011, the ASP-DAC Special Feature Award in 2011
and Best Design Award in 2014 and 2015, JSPS Prize in 2014, Suematsu
Yasuharu Award in 2015, and 36 other international and domestic awards. He
is a member of the technical program committees of ISSCC, VLSI Circuits,
and ESSCIRC, and serves as an Associate Editor of IEEE J OURNAL OF
S OLID -S TATE C IRCUITS.
Akira Matsuzawa (M’88–SM’01–F’02) received
the B.S., M.S., and Ph. D. degrees in electronics engi-
neering from Tohoku University, Sendai, Japan, in
1976, 1978, and 1997, respectively.
In 1978, he joined Matsushita Electric Industrial
Co., Ltd (Panasonic). Since then, he has been work-
ing on research and development of analog and Mixed
Signal LSI technologies, ultra-high speed ADCs,
intelligent CMOS sensors, RF CMOS circuits, and
digital read-channel technologies for DVD systems.
From 1997 to 2003, he was a general manager in the
Advanced LSI Technology Development Center. In April 2003, he joined the
Tokyo Institute of Technology, Tokyo, Japan, where he is a Professor in physical
electronics. Currently, he is researching mixed-signal technologies, RF CMOS
circuit design for SDR, and high speed data converters.
Dr. Matsuzawa served as guest editor-in-chief for the special issue on analog
LSI technology of IEICE T RANSACTIONS ON E LECTRONICS in 1992, 1997,
and 2003, Vice-Program Chairman for the International Conference on Solid
State Devices and Materials (SSDM) in 1999 and 2000, guest editor for special
issues of IEEE T RANSACTIONS ON E LECTRON D EVICES, committee mem-
ber for analog technology in ISSCC, educational session chair of A-SSCC,
executive committee member of VLSI symposia, IEEE SSCS elected Adcom,
IEEE SSCS Distinguished Lecturer, Chair of IEEE SSCS Japan Chapter, and
Vice President of the Japan Institution of Electronics Packaging. He received
the IR100 Award in 1983, the R&D100 Award and the Remarkable Invention
Award in 1994, and the ISSCC Evening Panel Award in 2003, 2005, and 2015.
He has been an IEICE Fellow since 2010.