ICTON 2018 Tu.D1.

FPGA Implementation of Real-Time Secure OFDM Transmission

Using Digital Chaos
Ying Wang, Xuelin Yang*, and Weisheng Hu
State Key Lab of Advanced Optical Communication Systems and Networks,
Shanghai Jiao Tong University, Shanghai 200240, China
Tel: (+8621) 34204596, E-mail: x.yang@sjtu.edu.cn
ABSTRACT
The real-time implementation is demonstrated using Field-Programmable Gate Array (FPGA) hardware with
Xilinx System Generator (XSG), for secure orthogonal frequency division multiplexing (OFDM) transmission.
Vivado software and Verilog programming language are used for the purpose of the real-time system design and
the OFDM data transmission. An encrypted 16-QAM OFDM data transmission and recovery are successfully
carried out using FPGA. The multi-fold data encryption is achieved via the input data encryption using XOR,
real and imaginary parts of QAM symbols encryption, where the chaotic sequences are generated by a hyper
digital chaos. As a result, it provides a key space of ~1022 to enhance the confidentiality of OFDM data
transmission.
Keywords: orthogonal frequency division multiplexing (OFDM), digital chaos, field-programmable gate array
(FPGA), Xilinx system generator (XSG), Verilog programming language.

1. INTRODUCTION
With the exponential increase of optical data traffic driven by the advancement of the broadband services,
passive optical networks (PONs) have emerged as a promising candidate to cope with these requirements. As it
offers a number of advantages, such as high capacity, low cost, and energy efficiently [1]. Besides, adopting
orthogonal frequency division multiplexing (OFDM) as modulation technique in PONs inherits further benefits,
such as tolerance to fiber dispersion, high spectrum efficiency and cost-effectiveness [2]. However, with respect
to the fact that the downstream traffic in PONs has broadcasting nature, the transmitted data becomes more
vulnerable to the eavesdropping by illegal optical network units (ONUs). Therefore, secure OFDM transmission
is extremely necessary in PONs. To deal with this issue, many schemes have been proposed recently [3]. Among
these approaches, chaos-based schemes have acquired much attention due to the unique properties of the chaotic
system, such as the ergodicity, the pseudo randomness and the high sensitivity to the initial values [4]. However,
all of these methods are implemented through the offline digital signal processing (DSP), and the feasibility of
these approaches in the real-time implementation needs to be explored.
FPGA (Field Programmable Gate Array) has been widely applied in modern digital hardware circuit design,
because it offers a hardware platform that can provide high speed, flexibility, performance, efficiency and
reliability. It also can be found widespread in many applications, such as military radios and backbone
infrastructure of cellular networks. For FPGA based OFDM transmission, a number of approaches have been
introduced, however all of these schemes focus on the conventional OFDM transmission rather than secure
OFDM transmission.
In this paper, we propose for the first time a real-time secure OFDM transmission implemented on FPGA.
A multi-fold OFDM data encryption and transmission are performed using a hyper digital chaos [5], where the
chaotic sequences are used to encrypt the real and the imaginary part of the QAM symbols, as well as the input
data itself. A key space of 1022 is provided in the proposed scheme, to guarantee the physical layer
confidentiality. All of the hardware interfaces and modules are designed, implanted and verified through Vivado
using Verilog programming language. As a proof of concept, an encrypted 16-QAM OFDM signal is
successfully demonstrated using Xilinx System Generator (XSG).
DeQAM Mapper
QAM Mapper

I
Remove CP

I
Decryption
Encryption

Add CP

PRBS
PRBS

XOR

XOR
IFFT

FFT
S/P

P/S

S/P

P/S

Q Q
z
y

y
z

Synchronization
X

Binary Digital Chaos Binary

Keys

Figure 1. Schematic diagram of secure OFDM transmission.

978-1-5386-6605-0/18/$31.00 ©2018 IEEE 1

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ICTON 2018 Tu.D1.4

2. PRINCIPLE
The schematic setup of the proposed scheme is depicted in Fig. 1, where the chaotic encryption is implemented by
the means of XOR operation on the following parts: pseudo-random binary sequence, real part and imaginary part
of QAM symbol. In order to generate the chaotic sequences, a 3-dimensional (3D) digital chaos is deployed,
 x = -a ( x - y )

 y = bx - xz - y (1)
 z = xy - cz

The system enters in the chaotic regime, when the constants are set: 𝑎𝑎 = 35, 𝑏𝑏 = 8/3, 𝑐𝑐 = 25. According to
the literature [6], selecting 𝑥𝑥 = 0.1, 𝑦𝑦 = 0.1, 𝑧𝑧 = 0.15 as the initial value and setting a sufficient number of
initial iterations. For FPGA implementation of 3D chaotic system, the continuous system should be discretized,
as well as using of fixed-point data format is necessary. In this work, Q25 format with 128-bits fixed-point data
is used, i.e. decimal digits are 25 bits. To obtain the chaotic sequences of {𝑥𝑥}, {𝑦𝑦} and {𝑧𝑧} in FPGA, Eq. (1)
can be discretized and solved using Euler method, which can be expressed as
 x(n + 1) = (1 − Ta ) x(n) + Tay (n)

 y (n +=1) Tbx(n) − Tx(n) z (n) + (1 − T ) y (n) (2)
 z (n + 1) = (1 − Tc) z (n) + Tx(n) y (n)

where the parameter T represents the step size, and the smaller its value is, the more accurate the calculated
result of the discrete system state equation will be. T is set to 0.001 in this paper.
Based on Eq. (2) and with assist of Verilog hardware description language (HDL), the 3D chaotic system can
be directly implemented via Vivado design tool. Figure 2 shows the solution of Eq. (2), where xn, yn, and zn
represent three individual chaotic sequences.

Figure 2. Waveforms of chaotic sequences.

To verify the design of 3D hyper chaotic system on FPGA, XSG is used, in which 3D hyper chaotic system
module is implemented as a black box. We can verify whether the design and implementation of the chaotic
system in the FPGA are correct by analysing the timing diagram and phase diagram of the XSG.
The details of the proposed multi-fold data encryption is given as follows. The PRBS is applied as the input
data. The XOR operation is performed on the data and the digital chaotic sequence {𝑥𝑥} with 18-bits after the
decimal point. These operations can be expressed as
din = sx0 ⊕ sx1 ⊕ sx2 ⊕  ⊕ sx17 ⊕ data (3)
where 𝑑𝑑𝑖𝑖𝑖𝑖 denotes the result of the first XOR encryption, 𝑠𝑠𝑥𝑥0 , 𝑠𝑠𝑥𝑥1 , …, 𝑠𝑠𝑥𝑥17 are binary bits extracted from
chaotic sequence {𝑥𝑥} in the order from low bits to high bits. Before 16-QAM mapper, every encrypted 4-bits
are concatenated. For 16-QAM symbol encryption, the real and imaginary parts are encrypted separately using
the two digitized chaotic sequences {𝑦𝑦} and {𝑧𝑧}. The 16-QAM OFDM symbol is represented by 64-bits data,
where the real part takes the first 32-bits while the last 32-bits represent the imaginary part. Meanwhile, Q25
fixed-point data format is used to guarantee the data accuracy. The encryption process can be illustrated as
=QEn 
AA
 A B 00...0
... ⊕Q 63 Q 62 ...Q50 Q49 Q48 Q47 ...Q32

14 17

14 17

=I En CC
...C D 00...0
⊕ I 31 I 30 ...I18 I17 I16 I15 ...I 0 (4)

14
 
17
 
14 17

A=
S y0 ⊕ S z0 , B =
S y1 ⊕ S z1 , C =
S y2 ⊕ S z2 , D =
S y3 ⊕ S z3
where 𝑄𝑄𝐸𝐸𝐸𝐸 and 𝐼𝐼𝐸𝐸𝐸𝐸 represent the encrypted imaginary part and real part respectively, 𝑄𝑄32 , 𝑄𝑄33 , …, 𝑄𝑄63
represent the 1th bit to 32th bit in the binary sequence of the imaginary part, 𝐼𝐼0 , 𝐼𝐼1 , …, 𝐼𝐼31 represent the 1th bit to
32th bit in the binary sequence of the real part. Similar to 𝑠𝑠𝑥𝑥𝑖𝑖 (i = 1, 2, … , 17), 𝑠𝑠𝑦𝑦 and 𝑠𝑠𝑧𝑧𝑖𝑖 are also the binary
𝑖𝑖
bits extracted from the chaotic sequence {𝑦𝑦} and {𝑧𝑧} respectively. For those bits which need to remain their
original value we set 0 in the corresponding positions to operate XOR encryption.

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ICTON 2018 Tu.D1.4

From Eq. (4) it clear that, after the XOR encryption, each symbol will be scrambled into another point on the
constellation diagram. For example, the symbol with 𝑄𝑄 = 1 and 𝐼𝐼 = −1, will be scramble into another symbol
with 𝑄𝑄 = −3 and 𝐼𝐼 = 3 by assuming 𝐴𝐴 = 1, 𝐵𝐵 = 0, 𝐶𝐶 = 1 and 𝐷𝐷 = 0. For decryption, the same chaotic
sequences will be used to perform the XOR operation again.

3. SYSTEM IMPLEMENT ON FPGA

The design of the hardware model is built by using Xilinx Vivado, and the equivalent validation model is
implemented through XSG. The data rate is set at 100 Mb/s for each parallel channel. Unlike those modules in
the XSG by Verilog code, FFT and IFFT modules are obtained by calling Vivado IP core. In addition, the
communication of all modules is on the basis of handshake communication. As for the synchronization of
chaotic sequence, for the encryption and decryption of QAM module, the following scheme is adopted in this
paper.

Figure 3. Waveforms of the OFDM transmission encrypted with digital chaos.

First of all, two independent chaotic sequence generators are set in digital chaos module, one for encryption
and the other for decryption. Secondly, the chaotic sequence is stored using a buffer with first in first out (FIFO)
queuing method. In order to obtain the synchronous chaotic sequence, the valid signal from the output of QAM
mapper and FFT module is used to control the write and read operation of the buffer respectively. Similar to the
above procedure, the encryption and decryption of PRBS also need synchronous modules to get the same chaotic
sequence.
The complete simulation waveforms of the OFDM chaotic system in Vivado is shown in Fig. 3, where data
indicates the input PRBS, data_in is encypted input data by lorenz_data_3 before QAM mapper. dout is output
QAM, which will be encrypted by lorenz_data_1 to obtain encrypt_out. The decrypt_out is decryption result of
the output of FFT (yn) by lorenz_data_2. result is output of DeQAM, which is decrypted using lorenz_dtat_4 to
obtain the final output data (result_2). It can be noted that regardless of the delay introduced by the modules, the
two waveforms are totally similar. This implies that the encryption and the decryption process are preformed
probably.

4. SYSTEM VERIFICATION WITH XSG

The XSG constructs the algorithm of the digital signal processing system, which is the bridge of digital signal
processing high-level system design and Xilinx FPGA implementation. Every module in Vivado can be imported
into XSG in the form of black box. Then each module can be connected to build a circuit diagram. Running the
simulation, we can obtain the constellations before and after the 16-QAM module encryption. By importing
a picture into the work space of XSG through MATLAB as the original input data, then the recovered data after
transmission and decryption can be obtained, as shown in Fig.4.
Apparently, the Fig. 4(a) is the original image. Using the proposed algorithm to encrypt the input digital image,
the encrypted image is plotted in Fig. 4(b). At the receiving end, the encrypted image can be decrypted correctly
using the right chaotic keys, as shown in Fig. 4(c).

Figure 4. Simulation results of image encryption, (a). Original image; (b). Encrypted image; (c). Correctly
decrypted image; (d) Decrypted image with a wrong key (a tiny change the initial value).

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ICTON 2018 Tu.D1.4

Moreover, the sensitivity of the initial value of the digital chaos on the data recovery is evaluated during the
data decryption. Specifically, if adding 1 to the last bit of the binary number stored in the synchronization module,
it increases ~3×10-8 in decimal from the original number. By running the simulation in XSG, the decrypted image
in the case of a slightly different chaotic initial value is shown in Fig. 4(d). Obviously, the decryption of the image
is completely incorrect and cannot be recovered whenever the correct initial values are not available. Generally,
the bit error rate (BER) is ~0.5 if any of the initial values is changed ~10-15, which implies the robust security
using digital chaos in OFDM data encryption. For the proposed secure scheme as shown in Fig. 1, the overall
key space after the data encryption is 275 (~3.8 × 1022 ).

5. CONCLUSIONS
We propose a real-time secure data encryption for OFDM signal transmission based on FPGA hardware and XSG.
The hardware implementation includes the multi-fold OFDM data encryption on QAM symbols, as well as XOR
operation on the original data. After transmission, the encrypted OFDM signals are recovered using the correct
chaotic keys. Moreover, the multi-fold data encryption of OFDM signals provides a key space of 1022, which
guarantee the robust security during OFDM data transmission. This implementation is one step ahead towards the
real application for OFDM data encryption using digital chaos.

ACKNOWLEDGEMENTS
This work was supported in part by International S&T Cooperation Program of China, 2016YFE0104500,
Natural Science Foundation of China under Grants 61571291, 61431009 and 61221001.

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