VLSI Design : 2021-22

Lecture 8
CMOS Inverter Transient Response

By Dr. Sanjay Vidhyadharan

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 CMOS Inverter: Transient Response

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 CMOS Inverter: Transient Response

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 CMOS Inverter: Delay-Time Definitions

By definition, TPHL is the time delay between the V50 %-transition of the rising input voltage
and the V50%-transition of the falling output voltage. Similarly, TPLH is defined as the time
delay between the V50% -transition of the falling input voltage and the V50 %-transition of the
rising output voltage.

To simplify the analysis and the derivation of delay expressions, the input voltage waveform is
usually assumed to be an ideal step pulse with zero rise and fall times. Under this assumption,

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 CMOS Inverter: Transient Response

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 CMOS Inverter: Delay-Time Calculation
Three Methods

1. Average Current Model

2. Differential Equation Model
3. 1st Order RC delay Model

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 CMOS Inverter: Delay-Time Calculation
Average Current Model 𝑞 𝑑𝑞 𝑑𝑣
𝑐= ≫𝑖= =c
𝑣 𝑑𝑡 𝑑𝑡

Note that the average current during high-to-low transition can be calculated by using the
current values at the beginning and the end of the transition.

𝑉𝐷𝑆
𝑘𝑛′ 𝑊(𝑉𝑜𝑣 − 2 )𝑉𝐷𝑆
𝐼𝐷 =
𝑘𝑛′ 𝑊(𝑉𝐷𝐷 − 𝑉𝑇 )2 𝐿
𝐼𝐷 = 𝑉 𝑉𝐷𝐷
2𝐿 𝑘𝑛′ 𝑊(𝑉𝐷𝐷 −𝑉𝑇 − 𝐷𝐷 )
4 2
𝐼𝐷 =
𝐿
Similarly, the average capacitance current during low-to-high transition is

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 CMOS Inverter: Delay-Time Calculation
Differential Equation Model
𝑄
𝐶=
𝑉
𝑑𝑉
𝑖 =𝐶
𝑑𝑡
𝑑𝑉
𝑑𝑡 = 𝐶
𝑖

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 CMOS Inverter: Delay-Time Calculation
Differential Equation Model

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 CMOS Inverter: Delay-Time Calculation
Differential Equation Model
Approximate by assuming in saturation:

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 CMOS Inverter: Delay-Time Calculation
Differential Equation Model
Taking Velocity saturation into consideration

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 CMOS Inverter: Transient Response
1st Order RC delay Model

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 CMOS Inverter: Transient Response
1st Order RC delay Model

Furthermore, it has been found that these values apply for a number of CMOS fabrication
processes including 0.25 μm, 0.18 μm, and 0.13 μm (see Hodges et al., 2004).

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 Sizing of CMOS Inverter
Increase PMOS size -> improve tpLH but degrades tpHL !!

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 Sizing of CMOS Inverter

➢ The intrinsic delay of the inverter tp0 is independent of the sizing of the gate, and is
purely determined by technology and inverter layout.
➢ When no load is present, an increase in the drive of the gate is totally offset by the
increased capacitance.

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 Sizing of CMOS Inverter

𝐶𝑖𝑛𝑡 = 𝑆 𝐶𝑒𝑥𝑡

➢ Making S infinitely large yields the

maximum obtainable performance gain,
eliminating the impact of any external
load, and reducing the delay to the
intrinsic one.
➢ Yet, any sizing factor S that is
sufficiently larger than (Cext /Cint )
produces similar results at a substantial
gain in silicon area.

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 Sizing of CMOS Chain of Inverters

γ is a proportionality factor, which is only a function of technology and is close to 1 for

most sub-micron processes.

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 Sizing of CMOS Chain of Inverters

The optimum size of each inverter is the geometric mean of its neighbours – meaning that
if each inverter is sized up by the same factor f wrt the preceding gate, it will have the
same effective fan-out and the same delay

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 Sizing of CMOS Chain of Inverters

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 Sizing of CMOS Chain of Inverters

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 Sizing of CMOS Chain of Inverters

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 Short Circuit Loss

𝑉𝐷𝐷
➢ Use devices with Vth close to & steep switching characteristics
2
➢ Short Circuit loss reduces with Cload

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 Short Circuit Loss

➢ Short Circuit loss reduces with Cload

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 Switching Loss

𝑉 1 2
Energy stored in CLoad (𝐶𝐿)= ‫׬‬0 𝐷𝐷 𝑉𝐶 . 𝐶𝐿𝑑𝑉𝑐 = . 𝑉𝐷𝐷 ∗ 𝐶𝐿
2
𝑇 2
Energy consumed from power supply= 𝑉𝐷𝐷 ‫׬‬0 𝑖 𝑡 𝑑𝑡 = 𝑉𝐷𝐷 . 𝑄𝐶𝐿 = 𝑉𝐷𝐷 . 𝐶𝐿
21
Energy dissipated in pMOSFET during charging = . 𝑉𝐷𝐷 . 𝐶𝐿
2
2 1
Energy dissipated in nMOSFET during discharging = . 𝑉𝐷𝐷 . 𝐶𝐿
2
2
Power Consumption = Frequency. 𝑉𝐷𝐷 . 𝐶𝐿
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 Ring Oscillator Circuit

➢ The ring oscillator circuit can be used as a very simple pulse generator
➢ Utilized to characterize a particular design and/or a new fabrication process.
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 Thank you

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