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  • Lec 10 CMOS Static Logic Delays

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    Mainak Tarafdar
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    This document discusses delays in complex CMOS static logic circuits. It explains that delay has intrinsic and parasitic components. Intrinsic delay depends on factors like effective fanout, while parasitic delay depends on layout. Logical effort analysis allows estimating path delays by considering logical, electrical and branching efforts. An example shows determining gate sizes for minimum delay from input A to output B using logical effort calculations.

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    This document discusses delays in complex CMOS static logic circuits. It explains that delay has intrinsic and parasitic components. Intrinsic delay depends on factors like effective fanout, while parasitic delay depends on layout. Logical effort analysis allows estimating path delays by considering logical, electrical and branching efforts. An example shows determining gate sizes for minimum delay from input A to output B using logical effort calculations.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    10 views14 pages

    Lec 10 CMOS Static Logic Delays

    Uploaded by

    Mainak Tarafdar
    This document discusses delays in complex CMOS static logic circuits. It explains that delay has intrinsic and parasitic components. Intrinsic delay depends on factors like effective fanout, while parasitic delay depends on layout. Logical effort analysis allows estimating path delays by considering logical, electrical and branching efforts. An example shows determining gate sizes for minimum delay from input A to output B using logical effort calculations.

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    of 14

    VLSI Design : 2021-22

    Lecture 10
    Delays in
    Complex CMOS Static Logic Circuits

    By Dr. Sanjay Vidhyadharan

    ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION


    Logical Effort

    2/19/2022 2

    ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION


    Delay in a Logic Gates

    C int

    C interconnect
    2/19/2022 3

    ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION


    Delay in a Logic Gates
    For an Inverter

    f : effective fanout
    tp : Intrinsic Delay (Sizing Independent, Process Dependant)
    For a Complex gate
    f : Electrical effort = Cout / Cin

    tp0 : Remains Intrinsic Delay of inverter

    2/19/2022 4

    ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION


    Parasitic Delay
    p represents the ratio of the intrinsic (or unloaded) delays of the
    complex gate and the simple inverter.
    In multiples of pinv (1)

    Estimates of intrinsic delay factors of various logic types assuming simple


    layout styles, and a fixed PMOS/NMOS ratio.
    2/19/2022 5

    ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION


    Delay in a Logic Gates

    2/19/2022 6

    ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION


    Delay in a Logic Gates
    For a Complex gate

    h = fg the gate effort

    Path effective fanout

    Path Logical Effort

    Path Effort H = FG

    2/19/2022 7

    ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION


    Delay in a Logic Gates

    Digital Integrated Circuits By Jan M Rabaey


    2/19/2022 8

    ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION


    Logical Effort
    Paths that Branch

    G =1 15
    90
    F = 90 / 5 = 18 5
    GF = 18 15
    90
    f1 = (15 +15) / 5 = 6
    f2 = 90 / 15 = 6
    F <-> H
    H = g1g2f1f2 = 36 = 2GF (B=2)
    H = GBF
    2/19/2022

    ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION


    Logical Effort : Example

    • Select gate sizes x and y for least delay from A to B


    x

    y
    x
    Critical path
    45
    A 8
    x
    y B
    45

    2/19/2022

    ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION


    Logical Effort : Example
    x

    y
    x
    45
    A 8
    x
    y B
    45

    Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27


    Electrical Effort F = 45/8
    Branching Effort B=3*2=6
    Path Effort H = GBF = 125
    3
    Best Stage Effort ℎ= 𝐻=5
    Parasitic Delay P = 2 + 3 + 2 = 7
    Delay D = 3*5 + 7 = 22 = 4.4 FO4
    In multiples of pinv (1)
    2/19/2022

    ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION


    Logical Effort : Example
    • Delay of a fanout-of-4 (FO4) inverter
    d

    Logical Effort: G=1


    Electrical Effort: F=4
    H = FG = 4
    h=4
    Parasitic Delay: p=1
    Stage Delay: d=5

    ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION


    Logical Effort : Example

    • Work backward for sizes


    y = 45 * (5/3) / 5 = 15 h = 5 = fg the gate effort
    f = 5/g the gate effort
    x = (15*2) * (5/3) / 5 = 10

    45
    A P: 4
    P: 4
    N: 4 P: 12 B
    N: 6 45
    N: 3

    ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION


    Thank you

    2/19/2022 14

    ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

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